Further ppc & pseries updates

The CPU state contains two bitmaps, initialized from the CPU spec which describes which instructions are implemented on the CPU. A couple of bits are defined which cover instructions (VSX and DFP) which are not currently implemented in TCG. So far, these are only used to handle the case of -cpu host because a KVM guest can use the instructions when the host CPU supports them.

However, it's a mild layering violation to simply not include those bits in the CPU descriptions for those CPUs that do support them, just because we can't handle them in TCG. This patch corrects the situation, so that the instruction bits _are_ shown correctly in the cpu spec table, but are masked out from the cpu state in the non-KVM case.

Signed-off-by David Gibson <[email protected]>

This patch adds a PCI bus to the pseries machine. This instantiates the qemu generic PCI bus code, advertises a PCI host bridge in the guest's device tree and implements the RTAS methods specified by PAPR to access PCI config space. It also sets up the memory regions we need to provide windows into the PCI memory and IO space, and advertises those to the guest.

However, because qemu can't yet emulate an IOMMU, which is mandatory on pseries, PCI devices which use DMA (i.e. most of them) will not work with this code alone. Still, this is enough to support the virtio_pci device (which probably _should_ use emulated PCI DMA, but is specced to use direct hypervisor access to guest physical memory instead).

Signed-off-by Alexey Kardashevskiy <[email protected]>

Signed-off-by David Gibson <[email protected]>

From: Nishanth Aravamudan <[email protected]>

When run with a PPC Book3S (server) CPU Currently 'info tlb' in the qemu monitor reports "dump_mmu: unimplemented". However, during bringup work, it can be quite handy to have the SLB entries, which are available in the CPUPPCState. This patch adds an implementation of info tlb for book3s, which dumps the SLB.

Signed-off-by Nishanth Aravamudan <[email protected]>

Signed-off-by David Gibson <[email protected]>

---
target-ppc/helper.c | 32 +++++++++++++++++++++++++++-----

1 files changed, 27 insertions(+), 5 deletions(-)

target-ppc/helper.c +2 -0

index 137a494..29c7050 100644
@@ -1545,14 +1545,36 @@ static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
    }
 }
 
+static void mmubooks_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
+                              CPUState *env)

target-ppc/helper.c +8 -0

+        if (slbe == 0 && slbv == 0) {
+            continue;
+        }
+        cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
+                    i, slbe, slbv);
+    }
+}
+
 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)

Quoted 24 lines · David Gibson

From: Nishanth Aravamudan <[email protected]>

When run with a PPC Book3S (server) CPU Currently 'info tlb' in the qemu monitor reports "dump_mmu: unimplemented". However, during bringup work, it can be quite handy to have the SLB entries, which are available in the CPUPPCState. This patch adds an implementation of info tlb for book3s, which dumps the SLB.

Signed-off-by Nishanth Aravamudan <[email protected]>

Signed-off-by David Gibson <[email protected]>

---
target-ppc/helper.c | 32 +++++++++++++++++++++++++++-----

1 files changed, 27 insertions(+), 5 deletions(-)

target-ppc/helper.c +2 -0

index 137a494..29c7050 100644
@@ -1545,14 +1545,36 @@ static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
    }
 }
 
+static void mmubooks_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
+                              CPUState *env)

target-ppc/helper.c static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf, · line 1559

Quoted 10 lines

target-ppc/helper.c +10 -0

+{
+    int i;
+    uint64_t slbe, slbv;
+
+    cpu_synchronize_state(env);
+
+    cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
+    for (i = 0; i < env->slb_nr; i++) {
+        slbe = env->slb[i].esid;
+        slbv = env->slb[i].vsid;

From cpu.h:

#if defined(TARGET_PPC64)
    /* Address space register */
    target_ulong asr;
    /* PowerPC 64 SLB area */
    ppc_slb_t slb[64];
    int slb_nr;

#endif

Quoted 9 lines

target-ppc/helper.c +8 -0

+        if (slbe == 0 && slbv == 0) {
+            continue;
+        }
+        cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
+                    i, slbe, slbv);
+    }
+}
+
 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)

target-ppc/helper.c static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf, · line 1573

Quoted 10 lines

target-ppc/helper.c +3 -5

 {
-    switch (env->mmu_model) {
-    case POWERPC_MMU_BOOKE206:
+    if (env->mmu_model == POWERPC_MMU_BOOKE206) {
        mmubooke206_dump_mmu(f, cpu_fprintf, env);
-        break;
-    default:
-        cpu_fprintf(f, "%s: unimplemented\n", __func__);
+    } else {
+        if ((env->mmu_model & POWERPC_MMU_64B) != 0) {

I would actually prefer to explicitly keep the switch and match on all implementations explicitly. Also, have you verified this works without CONFIG_PPC64 set? In cpu.h I see the following:

#if defined(TARGET_PPC64)
#define POWERPC_MMU_64 0x00010000

#define POWERPC_MMU_1TSEG    0x00020000
    /* 64 bits PowerPC MMU                                     */
    POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,
    /* 620 variant (no segment exceptions)                     */
    POWERPC_MMU_620        = POWERPC_MMU_64 | 0x00000002,
    /* Architecture 2.06 variant                               */
    POWERPC_MMU_2_06       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003,

#endif /* defined(TARGET_PPC64) */

So POWERPC_MMU_64B shouldn't be defined for qemu-system-ppc.

Alex

Good points below. I forgot to CC Nish, the original patch author on my post, so I've added him to the list now.

Nish, can you correct these problems and resend the patch please?

Quoted 40 lines · David Gibson

Quoted 25 lines

From: Nishanth Aravamudan <[email protected]>

When run with a PPC Book3S (server) CPU Currently 'info tlb' in the qemu monitor reports "dump_mmu: unimplemented". However, during bringup work, it can be quite handy to have the SLB entries, which are available in the CPUPPCState. This patch adds an implementation of info tlb for book3s, which dumps the SLB.

Signed-off-by Nishanth Aravamudan <[email protected]>

Signed-off-by David Gibson <[email protected]>

---
target-ppc/helper.c | 32 +++++++++++++++++++++++++++-----

1 files changed, 27 insertions(+), 5 deletions(-)

target-ppc/helper.c +2 -0

index 137a494..29c7050 100644
@@ -1545,14 +1545,36 @@ static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
    }
 }
 
+static void mmubooks_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
+                              CPUState *env)

target-ppc/helper.c static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf, · line 1559

Quoted 10 lines

target-ppc/helper.c +10 -0

+{
+    int i;
+    uint64_t slbe, slbv;
+
+    cpu_synchronize_state(env);
+
+    cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
+    for (i = 0; i < env->slb_nr; i++) {
+        slbe = env->slb[i].esid;
+        slbv = env->slb[i].vsid;

From cpu.h:

Quoted 7 lines

#if defined(TARGET_PPC64)
    /* Address space register */
    target_ulong asr;
    /* PowerPC 64 SLB area */
    ppc_slb_t slb[64];
    int slb_nr;

#endif

Quoted 35 lines

Quoted 9 lines

target-ppc/helper.c +8 -0

+        if (slbe == 0 && slbv == 0) {
+            continue;
+        }
+        cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
+                    i, slbe, slbv);
+    }
+}
+
 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)

target-ppc/helper.c static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf, · line 1573

Quoted 10 lines

target-ppc/helper.c +3 -5

 {
-    switch (env->mmu_model) {
-    case POWERPC_MMU_BOOKE206:
+    if (env->mmu_model == POWERPC_MMU_BOOKE206) {
        mmubooke206_dump_mmu(f, cpu_fprintf, env);
-        break;
-    default:
-        cpu_fprintf(f, "%s: unimplemented\n", __func__);
+    } else {
+        if ((env->mmu_model & POWERPC_MMU_64B) != 0) {

I would actually prefer to explicitly keep the switch and match on all implementations explicitly. Also, have you verified this works without CONFIG_PPC64 set? In cpu.h I see the following:

#if defined(TARGET_PPC64)
#define POWERPC_MMU_64 0x00010000

#define POWERPC_MMU_1TSEG    0x00020000
    /* 64 bits PowerPC MMU                                     */
    POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,
    /* 620 variant (no segment exceptions)                     */
    POWERPC_MMU_620        = POWERPC_MMU_64 | 0x00000002,
    /* Architecture 2.06 variant                               */
    POWERPC_MMU_2_06       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003,

#endif /* defined(TARGET_PPC64) */

Quoted 1 line

So POWERPC_MMU_64B shouldn't be defined for qemu-system-ppc.

Quoted 4 lines · David Gibson

Good points below. I forgot to CC Nish, the original patch author on my post, so I've added him to the list now.

Nish, can you correct these problems and resend the patch please?

Yep, I'll work on this shortly.

Quoted 41 lines · Alexander Graf

Quoted 40 lines · David Gibson

Quoted 25 lines

From: Nishanth Aravamudan <[email protected]>

When run with a PPC Book3S (server) CPU Currently 'info tlb' in the qemu monitor reports "dump_mmu: unimplemented". However, during bringup work, it can be quite handy to have the SLB entries, which are available in the CPUPPCState. This patch adds an implementation of info tlb for book3s, which dumps the SLB.

Signed-off-by Nishanth Aravamudan <[email protected]>

Signed-off-by David Gibson <[email protected]>

---
target-ppc/helper.c | 32 +++++++++++++++++++++++++++-----

1 files changed, 27 insertions(+), 5 deletions(-)

target-ppc/helper.c +2 -0

index 137a494..29c7050 100644
@@ -1545,14 +1545,36 @@ static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
   }
 }
 
+static void mmubooks_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
+                              CPUState *env)

target-ppc/helper.c static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf, · line 1559

Quoted 10 lines

target-ppc/helper.c +10 -0

+{
+    int i;
+    uint64_t slbe, slbv;
+
+    cpu_synchronize_state(env);
+
+    cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
+    for (i = 0; i < env->slb_nr; i++) {
+        slbe = env->slb[i].esid;
+        slbv = env->slb[i].vsid;

From cpu.h:

Quoted 7 lines

Quoted 7 lines

#if defined(TARGET_PPC64)
   /* Address space register */
   target_ulong asr;
   /* PowerPC 64 SLB area */
   ppc_slb_t slb[64];
   int slb_nr;

#endif

Being unfamiliar with qemu's coding style (and not immediately seeing it in CODING_STYLE), would the right approach be to wrap this definition in an #if defined(TARGET_PPC64)?

Quoted 36 lines

Quoted 36 lines

Quoted 10 lines

target-ppc/helper.c +8 -0

+        if (slbe == 0 && slbv == 0) {
+            continue;
+        }
+        cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
+                    i, slbe, slbv);
+    }
+}
+
 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)

target-ppc/helper.c static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf, · line 1573

Quoted 10 lines

target-ppc/helper.c +3 -5

 {
-    switch (env->mmu_model) {
-    case POWERPC_MMU_BOOKE206:
+    if (env->mmu_model == POWERPC_MMU_BOOKE206) {
       mmubooke206_dump_mmu(f, cpu_fprintf, env);
-        break;
-    default:
-        cpu_fprintf(f, "%s: unimplemented\n", __func__);
+    } else {
+        if ((env->mmu_model & POWERPC_MMU_64B) != 0) {

I would actually prefer to explicitly keep the switch and match on all implementations explicitly. Also, have you verified this works without CONFIG_PPC64 set? In cpu.h I see the following:

#if defined(TARGET_PPC64)
#define POWERPC_MMU_64 0x00010000

#define POWERPC_MMU_1TSEG    0x00020000
   /* 64 bits PowerPC MMU                                     */
   POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,
   /* 620 variant (no segment exceptions)                     */
   POWERPC_MMU_620        = POWERPC_MMU_64 | 0x00000002,
   /* Architecture 2.06 variant                               */
   POWERPC_MMU_2_06       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003,

#endif /* defined(TARGET_PPC64) */

Quoted 1 line

Quoted 1 line

So POWERPC_MMU_64B shouldn't be defined for qemu-system-ppc.

And similarly here, only have the MMU_2_06 and MMU_64B cases in the switch be defined #if defined(TARGET_PPC64)?

Basically, asking if #ifdefs in the middle of functions are ok :)

Quoted 57 lines · Nishanth Aravamudan

Quoted 4 lines · David Gibson

Good points below. I forgot to CC Nish, the original patch author on my post, so I've added him to the list now.

Nish, can you correct these problems and resend the patch please?

Yep, I'll work on this shortly.

Quoted 41 lines · Alexander Graf

Quoted 40 lines · David Gibson

Quoted 25 lines

From: Nishanth Aravamudan <[email protected]>

When run with a PPC Book3S (server) CPU Currently 'info tlb' in the qemu monitor reports "dump_mmu: unimplemented". However, during bringup work, it can be quite handy to have the SLB entries, which are available in the CPUPPCState. This patch adds an implementation of info tlb for book3s, which dumps the SLB.

Signed-off-by Nishanth Aravamudan <[email protected]>

Signed-off-by David Gibson <[email protected]>

---
target-ppc/helper.c | 32 +++++++++++++++++++++++++++-----

1 files changed, 27 insertions(+), 5 deletions(-)

target-ppc/helper.c +2 -0

index 137a494..29c7050 100644
@@ -1545,14 +1545,36 @@ static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
   }
 }
 
+static void mmubooks_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
+                              CPUState *env)

target-ppc/helper.c static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf, · line 1559

Quoted 10 lines

target-ppc/helper.c +10 -0

+{
+    int i;
+    uint64_t slbe, slbv;
+
+    cpu_synchronize_state(env);
+
+    cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
+    for (i = 0; i < env->slb_nr; i++) {
+        slbe = env->slb[i].esid;
+        slbv = env->slb[i].vsid;

From cpu.h:

Quoted 7 lines

Quoted 7 lines

#if defined(TARGET_PPC64)
   /* Address space register */
   target_ulong asr;
   /* PowerPC 64 SLB area */
   ppc_slb_t slb[64];
   int slb_nr;

#endif

Quoted 3 lines

Being unfamiliar with qemu's coding style (and not immediately seeing it in CODING_STYLE), would the right approach be to wrap this definition in an #if defined(TARGET_PPC64)?

It's the only way to make it compile :)

Quoted 36 lines

Quoted 36 lines

Quoted 36 lines

Quoted 10 lines

target-ppc/helper.c +8 -0

+        if (slbe == 0 && slbv == 0) {
+            continue;
+        }
+        cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
+                    i, slbe, slbv);
+    }
+}
+
 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)

target-ppc/helper.c static void mmubooke206_dump_mmu(FILE *f, fprintf_function cpu_fprintf, · line 1573

Quoted 10 lines

target-ppc/helper.c +3 -5

 {
-    switch (env->mmu_model) {
-    case POWERPC_MMU_BOOKE206:
+    if (env->mmu_model == POWERPC_MMU_BOOKE206) {
       mmubooke206_dump_mmu(f, cpu_fprintf, env);
-        break;
-    default:
-        cpu_fprintf(f, "%s: unimplemented\n", __func__);
+    } else {
+        if ((env->mmu_model & POWERPC_MMU_64B) != 0) {

I would actually prefer to explicitly keep the switch and match on all implementations explicitly. Also, have you verified this works without CONFIG_PPC64 set? In cpu.h I see the following:

#if defined(TARGET_PPC64)
#define POWERPC_MMU_64 0x00010000

#define POWERPC_MMU_1TSEG    0x00020000
   /* 64 bits PowerPC MMU                                     */
   POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,
   /* 620 variant (no segment exceptions)                     */
   POWERPC_MMU_620        = POWERPC_MMU_64 | 0x00000002,
   /* Architecture 2.06 variant                               */
   POWERPC_MMU_2_06       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003,

#endif /* defined(TARGET_PPC64) */

Quoted 4 lines

Quoted 1 line

Quoted 1 line

So POWERPC_MMU_64B shouldn't be defined for qemu-system-ppc.

And similarly here, only have the MMU_2_06 and MMU_64B cases in the switch be defined #if defined(TARGET_PPC64)?

Yup :).

Quoted 1 line

Basically, asking if #ifdefs in the middle of functions are ok :)

It's the only valid way of making it work, yes. The alternative would be to drop all the TARGET_PPC64 ifdefery, but let's keep that for later.

Good points below. I forgot to CC Nish, the original patch author on my post, so I've added him to the list now.

Nish, can you correct these problems and resend the patch please?

Quoted 4 lines · David Gibson

Good points below. I forgot to CC Nish, the original patch author on my post, so I've added him to the list now.

Nish, can you correct these problems and resend the patch please?

When run with a PPC Book3S (server) CPU Currently 'info tlb' in the qemu monitor reports "dump_mmu: unimplemented". However, during bringup work, it can be quite handy to have the SLB entries, which are available in the CPUPPCState. This patch adds an implementation of info tlb for book3s, which dumps the SLB.

Signed-off-by Nishanth Aravamudan<[email protected]>

Signed-off-by David Gibson<[email protected]>

Quoted 11 lines · Nishanth Aravamudan

Quoted 4 lines · David Gibson

Good points below. I forgot to CC Nish, the original patch author on my post, so I've added him to the list now.

Nish, can you correct these problems and resend the patch please?

When run with a PPC Book3S (server) CPU Currently 'info tlb' in the qemu monitor reports "dump_mmu: unimplemented". However, during bringup work, it can be quite handy to have the SLB entries, which are available in the CPUPPCState. This patch adds an implementation of info tlb for book3s, which dumps the SLB.

Quoted 2 lines

Signed-off-by Nishanth Aravamudan<[email protected]>

Signed-off-by David Gibson<[email protected]>

Thanks, applied to ppc-next.

Quoted 12 lines · Alexander Graf

Quoted 11 lines · Nishanth Aravamudan

Quoted 4 lines · David Gibson

Good points below. I forgot to CC Nish, the original patch author on my post, so I've added him to the list now.

Nish, can you correct these problems and resend the patch please?

When run with a PPC Book3S (server) CPU Currently 'info tlb' in the qemu monitor reports "dump_mmu: unimplemented". However, during bringup work, it can be quite handy to have the SLB entries, which are available in the CPUPPCState. This patch adds an implementation of info tlb for book3s, which dumps the SLB.

Quoted 4 lines

Quoted 2 lines

Signed-off-by Nishanth Aravamudan<[email protected]>

Signed-off-by David Gibson<[email protected]>

Thanks, applied to ppc-next.

I'm guessing that ppc-next is now the branch destined for post 1.0. Is that right?

Signature · 5 lines

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David Gibson            | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au    | minimalist, thank you.  NOT _the_ _other_
               | _way_ _around_!
http://www.ozlabs.org/~dgibson