Add support for the OpenRISC architecture

Signed-off-by Stefan Kristiansson <[email protected]>

---
 common/image.c  |    1 +
 include/image.h |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)

common/image.c +1 -0

index 555d9d9..564dee1 100644
@@ -94,6 +94,7 @@ static const table_entry_t uimage_arch[] = {
 	{	IH_ARCH_BLACKFIN,	"blackfin",	"Blackfin",	},
 	{	IH_ARCH_AVR32,		"avr32",	"AVR32",	},
 	{	IH_ARCH_NDS32,		"nds32",	"NDS32",	},
+	{	IH_ARCH_OPENRISC,	"or1k",		"OpenRISC 1000",},
 	{	-1,			"",		"",		},
 };
 

include/image.h +0 -0

index c56a18d..dffa3cd 100644

??: [PATCH] Fix clash between IH_ARCH_NDS32 and IH_ARCH_SANDBOX

NDS32 and SANDBOX architecture were sharing the same IH_ARCH number

Signed-off-by Stefan Kristiansson <[email protected]>

architecture (test only) */
-#define IH_ARCH_NDS32 19 /* ANDES
Technology - NDS32 */
+#define IH_ARCH_NDS32 20 /* ANDES
Technology - NDS32 */

/*
* Image Types

Hi Stefan,

Quoted 5 lines

??: [PATCH] Fix clash between IH_ARCH_NDS32 and IH_ARCH_SANDBOX

NDS32 and SANDBOX architecture were sharing the same IH_ARCH number

Signed-off-by Stefan Kristiansson <[email protected]>

[snip]

Quoted 6 lines

architecture (test only) */
-#define IH_ARCH_NDS32 19 /* ANDES
Technology - NDS32 */
+#define IH_ARCH_NDS32 20 /* ANDES
Technology - NDS32 */

Quoted 3 lines

/*

* Image Types

Thanks!

Acked-by Macpaul Lin <[email protected]>

Hi Stefan,

Quoted 5 lines

??: [PATCH] Fix clash between IH_ARCH_NDS32 and IH_ARCH_SANDBOX

NDS32 and SANDBOX architecture were sharing the same IH_ARCH number

Signed-off-by Stefan Kristiansson <[email protected]>

arch/openrisc/config.mk new file +0 -0

\ No newline at end of file

arch/openrisc/cpu/cache.c new file +15 -0

+void dcache_enable(void)
+{
+	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);
+	asm("l.nop");
+	asm("l.nop");
+	asm("l.nop");
+	asm("l.nop");
+	asm("l.nop");
+	asm("l.nop");
+	asm("l.nop");
+	asm("l.nop");
+}
+
+void icache_enable(void)
+{

arch/openrisc/cpu/exceptions.c new file +40 -0

+static void exception_hang(int vect)
+{
+	printf("Unhandled exception at 0x%x ", vect & 0xff00);
+	switch (vect & 0xff00) {
+	case 0x100:
+		puts("(Reset)\n");
+		break;
+	case 0x200:
+		puts("(Bus Error)\n");
+		break;
+	case 0x300:
+		puts("(Data Page Fault)\n");
+		break;
+	case 0x400:
+		puts("(Instruction Page Fault)\n");
+		break;
+	case 0x500:
+		puts("(Tick Timer)\n");
+		break;
+	case 0x600:
+		puts("(Alignment)\n");
+		break;
+	case 0x700:
+		puts("(Illegal Instruction)\n");
+		break;
+	case 0x800:
+		puts("(External Interrupt)\n");
+		break;
+	case 0x900:
+		puts("(D-TLB Miss)\n");
+		break;
+	case 0xa00:
+		puts("(I-TLB Miss)\n");
+		break;
+	case 0xb00:
+		puts("(Range)\n");
+		break;
+	case 0xc00:
+		puts("(System Call)\n");
+		break;

arch/openrisc/cpu/cache.c line 91

Quoted 5 lines · On Saturday 19 November 2011 00:21:32 Stefan Kristiansson wrote:

arch/openrisc/cpu/cache.c new file +2 -0

 
+int checkicache(void)
+int checkdcache(void)

these should be static

arch/openrisc/cpu/cpu.c

Quoted 4 lines

arch/openrisc/cpu/cpu.c new file +1 -0

 
+int checkcpu(void)

looks like these should be static

Quoted 9 lines · Mike Frysinger

arch/openrisc/cpu/cache.c line 91

Quoted 5 lines · On Saturday 19 November 2011 00:21:32 Stefan Kristiansson wrote:

arch/openrisc/cpu/cache.c new file +2 -0

 
+int checkicache(void)
+int checkdcache(void)

these should be static

Quoted 6 lines

arch/openrisc/cpu/cpu.c

Quoted 4 lines

arch/openrisc/cpu/cpu.c new file +1 -0

 
+int checkcpu(void)

looks like these should be static

They are declared in common.h and are used outside their file scope.

Signed-off-by Stefan Kristiansson <[email protected]>

---
 arch/openrisc/config.mk        |   27 ++++
 arch/openrisc/cpu/Makefile     |   47 ++++++
 arch/openrisc/cpu/cache.c      |  157 +++++++++++++++++++
 arch/openrisc/cpu/cpu.c        |  157 +++++++++++++++++++
 arch/openrisc/cpu/exceptions.c |  109 +++++++++++++
 arch/openrisc/cpu/interrupts.c |  120 ++++++++++++++
 arch/openrisc/cpu/start.S      |  335
++++++++++++++++++++++++++++++++++++++++ 7 files changed, 952
insertions(+), 0 deletions(-)
 create mode 100644 arch/openrisc/config.mk
 create mode 100644 arch/openrisc/cpu/Makefile
 create mode 100644 arch/openrisc/cpu/cache.c
 create mode 100644 arch/openrisc/cpu/cpu.c
 create mode 100644 arch/openrisc/cpu/exceptions.c
 create mode 100644 arch/openrisc/cpu/interrupts.c
 create mode 100644 arch/openrisc/cpu/start.S

arch/openrisc/config.mk new file +23 -0

new file mode 100644
index 0000000..bea3d12
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2011
+# Julius Baxter <[email protected]>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CROSS_COMPILE ?= or32-elf-
+
+# r10 used for global object pointer, already set in OR32 GCC but just to

be +# clear

arch/openrisc/config.mk new file +3 -0

+PLATFORM_CPPFLAGS += -DCONFIG_OPENRISC -D__OR1K__ -ffixed-r10
+
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
\ No newline at end of file

arch/openrisc/cpu/Makefile new file +47 -0

new file mode 100644
index 0000000..b3b1a24
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2011
+# Julius Baxter <[email protected]>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).o
+
+START	= start.o
+COBJS-y	= cache.o cpu.o exceptions.o interrupts.o
+
+SRCS	:= $(START:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/openrisc/cpu/cache.c new file +2 -0

new file mode 100644
index 0000000..9dd627f
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2011, Stefan Kristiansson

<[email protected]> + * (C) Copyright 2011, Julius Baxter <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */

arch/openrisc/cpu/cache.c new file +23 -0

+}
+
+void flush_dcache_range(unsigned long addr, unsigned long stop)
+{
+	unsigned long linesize = get_linesize();
+
+	while (addr < stop) {
+		mtspr(SPR_DCBFR, addr);
+		addr += linesize;
+	}
+}
+
+void invalidate_dcache_range(unsigned long addr, unsigned long stop)
+{
+	unsigned long linesize = get_linesize();
+
+	while (addr < stop) {
+		mtspr(SPR_DCBIR, addr);
+		addr += linesize;
+	}
+}
+
+static void invalidate_icache_range(unsigned long addr, unsigned long

stop) +{

arch/openrisc/cpu/cache.c new file +73 -0

+	unsigned long linesize = get_linesize();
+
+	while (addr < stop) {
+		mtspr(SPR_ICBIR, addr);
+		addr += linesize;
+	}
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	flush_dcache_range(addr, addr + size);
+	invalidate_icache_range(addr, addr + size);
+}
+
+int icache_status(void)
+{
+	return mfspr(SPR_SR) & SPR_SR_ICE;
+}
+
+int checkicache(void)
+{
+	unsigned long iccfgr;
+	unsigned long cache_set_size;
+	unsigned long cache_ways;
+	unsigned long cache_block_size;
+
+	iccfgr = mfspr(SPR_ICCFGR);
+	cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
+	cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
+	cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
+
+	return cache_set_size * cache_ways * cache_block_size;
+}
+
+int dcache_status(void)
+{
+	return mfspr(SPR_SR) & SPR_SR_DCE;
+}
+
+int checkdcache(void)
+{
+	unsigned long dccfgr;
+	unsigned long cache_set_size;
+	unsigned long cache_ways;
+	unsigned long cache_block_size;
+
+	dccfgr = mfspr(SPR_DCCFGR);
+	cache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
+	cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
+	cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
+
+	return cache_set_size * cache_ways * cache_block_size;
+}
+
+void dcache_enable(void)
+{
+	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);
+	asm("l.nop");
+	asm("l.nop");
+	asm("l.nop");
+	asm("l.nop");
+	asm("l.nop");
+	asm("l.nop");
+	asm("l.nop");
+	asm("l.nop");
+}
+
+void dcache_disable(void)
+{
+	mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_DCE);
+}
+
+void icache_enable(void)

arch/openrisc/cpu/cache.c new file +23 -0

+}
+
+void icache_disable(void)
+{
+	mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_ICE);
+}
+
+int cache_init(void)
+{
+	if (mfspr(SPR_UPR) & SPR_UPR_ICP) {
+		icache_disable();
+		invalidate_icache_range(0, checkicache());
+		icache_enable();
+	}
+
+	if (mfspr(SPR_UPR) & SPR_UPR_DCP) {
+		dcache_disable();
+		invalidate_dcache_range(0, checkdcache());
+		dcache_enable();
+	}
+
+	return 0;
+}

arch/openrisc/cpu/cpu.c new file +2 -0

new file mode 100644
index 0000000..3b69285
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2011, Stefan Kristiansson

<[email protected]> + * (C) Copyright 2011, Julius Baxter <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */

arch/openrisc/cpu/cpu.c new file +44 -0

+
+#include <asm/system.h>
+#include <asm/openrisc_exc.h>
+#include <common.h>
+
+static volatile int illegal_instruction;
+
+void illegal_instruction_handler(void)
+{
+	ulong *epcr = (ulong *)mfspr(SPR_EPCR_BASE);
+
+	/* skip over the illegal instruction */
+	mtspr(SPR_EPCR_BASE, (ulong)(++epcr));
+	illegal_instruction = 1;
+}
+
+void checkinstructions(void)
+{
+	ulong ra = 1, rb = 1, rc;
+
+	exception_install_handler(EXC_ILLEGAL_INSTR,
+				illegal_instruction_handler);
+
+	illegal_instruction = 0;
+	asm volatile("l.mul %0,%1,%2" : "=r" (rc) : "r" (ra), "r" (rb));
+	printf("           Hardware multiplier: %s\n",
+		illegal_instruction ? "no" : "yes");
+
+	illegal_instruction = 0;
+	asm volatile("l.div %0,%1,%2" : "=r" (rc) : "r" (ra), "r" (rb));
+	printf("           Hardware divider: %s\n",
+		illegal_instruction ? "no" : "yes");
+
+	exception_free_handler(EXC_ILLEGAL_INSTR);
+
+}
+
+int checkcpu(void)
+{
+	ulong upr = mfspr(SPR_UPR);
+	ulong vr = mfspr(SPR_VR);
+	ulong iccfgr = mfspr(SPR_ICCFGR);
+	ulong dccfgr = mfspr(SPR_DCCFGR);
+	ulong immucfgr = mfspr(SPR_IMMUCFGR);

arch/openrisc/cpu/cpu.c new file +81 -0

+
+	if (upr & SPR_UPR_DCP) {
+		block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
+		ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
+		printf("       D-Cache: %d bytes, %d bytes/line, %d way(s)\n",
+		       checkdcache(), block_size, ways);
+	} else {
+		printf("       D-Cache: no\n");
+	}
+
+	if (upr & SPR_UPR_ICP) {
+		block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
+		ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
+		printf("       I-Cache: %d bytes, %d bytes/line, %d way(s)\n",
+		       checkicache(), block_size, ways);
+	} else {
+		printf("       I-Cache: no\n");
+	}
+
+	if (upr & SPR_UPR_DMP) {
+		sets = 1 << ((dmmucfgr & SPR_DMMUCFGR_NTS) >> 2);
+		ways = (dmmucfgr & SPR_DMMUCFGR_NTW) + 1;
+		printf("       DMMU: %d sets, %d way(s)\n",
+		       sets, ways);
+	} else {
+		printf("       DMMU: no\n");
+	}
+
+	if (upr & SPR_UPR_IMP) {
+		sets = 1 << ((immucfgr & SPR_IMMUCFGR_NTS) >> 2);
+		ways = (immucfgr & SPR_IMMUCFGR_NTW) + 1;
+		printf("       IMMU: %d sets, %d way(s)\n",
+		       sets, ways);
+	} else {
+		printf("       IMMU: no\n");
+	}
+
+	printf("       MAC unit: %s\n",
+		(upr & SPR_UPR_MP) ? "yes" : "no");
+	printf("       Debug unit: %s\n",
+		(upr & SPR_UPR_DUP) ? "yes" : "no");
+	printf("       Performance counters: %s\n",
+		(upr & SPR_UPR_PCUP) ? "yes" : "no");
+	printf("       Power management: %s\n",
+		(upr & SPR_UPR_PMP) ? "yes" : "no");
+	printf("       Interrupt controller: %s\n",
+		(upr & SPR_UPR_PICP) ? "yes" : "no");
+	printf("       Timer: %s\n",
+		(upr & SPR_UPR_TTP) ? "yes" : "no");
+	printf("       Custom unit(s): %s\n",
+		(upr & SPR_UPR_CUP) ? "yes" : "no");
+
+	printf("       Supported instructions:\n");
+	printf("           ORBIS32: %s\n",
+		(cpucfgr & SPR_CPUCFGR_OB32S) ? "yes" : "no");
+	printf("           ORBIS64: %s\n",
+		(cpucfgr & SPR_CPUCFGR_OB64S) ? "yes" : "no");
+	printf("           ORFPX32: %s\n",
+		(cpucfgr & SPR_CPUCFGR_OF32S) ? "yes" : "no");
+	printf("           ORFPX64: %s\n",
+		(cpucfgr & SPR_CPUCFGR_OF64S) ? "yes" : "no");
+
+	checkinstructions();
+
+	return 0;
+}
+
+int cleanup_before_linux(void)
+{
+	disable_interrupts();
+	return 0;
+}
+
+extern void __reset(void);
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	disable_interrupts();
+	__reset();
+	return 0;
+}

(quoted diff) +0 -0

b/arch/openrisc/cpu/exceptions.c new file mode 100644 index 0000000..06935be

arch/openrisc/cpu/exceptions.c new file +2 -0

@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2011, Stefan Kristiansson

<[email protected]> + * (C) Copyright 2011, Julius Baxter <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */

arch/openrisc/cpu/exceptions.c new file +90 -0

+
+#include <asm/system.h>
+#include <common.h>
+#include <stdio_dev.h>
+
+extern void hang(void);
+
+static void (*handlers[32])(void);
+
+void exception_install_handler(int exception, void (*handler)(void))
+{
+	if (exception < 0 || exception > 31)
+		return;
+
+	handlers[exception] = handler;
+}
+
+void exception_free_handler(int exception)
+{
+	if (exception < 0 || exception > 31)
+		return;
+
+	handlers[exception] = 0;
+}
+
+static void exception_hang(int vect)
+{
+	printf("Unhandled exception at 0x%x ", vect & 0xff00);
+	switch (vect & 0xff00) {
+	case 0x100:
+		puts("(Reset)\n");
+		break;
+	case 0x200:
+		puts("(Bus Error)\n");
+		break;
+	case 0x300:
+		puts("(Data Page Fault)\n");
+		break;
+	case 0x400:
+		puts("(Instruction Page Fault)\n");
+		break;
+	case 0x500:
+		puts("(Tick Timer)\n");
+		break;
+	case 0x600:
+		puts("(Alignment)\n");
+		break;
+	case 0x700:
+		puts("(Illegal Instruction)\n");
+		break;
+	case 0x800:
+		puts("(External Interrupt)\n");
+		break;
+	case 0x900:
+		puts("(D-TLB Miss)\n");
+		break;
+	case 0xa00:
+		puts("(I-TLB Miss)\n");
+		break;
+	case 0xb00:
+		puts("(Range)\n");
+		break;
+	case 0xc00:
+		puts("(System Call)\n");
+		break;
+	case 0xd00:
+		puts("(Floating Point)\n");
+		break;
+	case 0xe00:
+		puts("(Trap)\n");
+		break;
+	default:
+		puts("(Unknown exception)\n");
+		break;
+	}
+	printf("EPCR: 0x%08lx\n", mfspr(SPR_EPCR_BASE));
+	printf("EEAR: 0x%08lx\n", mfspr(SPR_EEAR_BASE));
+	printf("ESR:  0x%08lx\n", mfspr(SPR_ESR_BASE));
+	hang();
+}
+
+void exception_handler(int vect)
+{
+	int exception = vect >> 8;
+
+	if (handlers[exception])
+		handlers[exception]();
+	else
+		exception_hang(vect);
+}

(quoted diff) +0 -0

b/arch/openrisc/cpu/interrupts.c new file mode 100644 index 0000000..62d266a

arch/openrisc/cpu/interrupts.c new file +2 -0

@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2011, Stefan Kristiansson

<[email protected]> + * (C) Copyright 2011, Julius Baxter <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */

arch/openrisc/cpu/interrupts.c new file +101 -0

+
+#include <asm/types.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#include <asm/openrisc_exc.h>
+#include <common.h>
+
+struct irq_action {
+	interrupt_handler_t *handler;
+	void *arg;
+	int count;
+};
+
+static struct irq_action handlers[32];
+
+void interrupt_handler(void)
+{
+	int irq;
+
+	while ((irq = ffs(mfspr(SPR_PICSR)))) {
+		if (handlers[--irq].handler) {
+			handlers[irq].handler(handlers[irq].arg);
+			handlers[irq].count++;
+		} else {
+			/* disable the interrupt */
+			mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1 << irq));
+			printf("Unhandled interrupt: %d\n", irq);
+		}
+		/* clear the interrupt */
+		mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1 << irq));
+	}
+}
+
+int interrupt_init(void)
+{
+	/* install handler for external interrupt exception */
+	exception_install_handler(EXC_EXT_IRQ, interrupt_handler);
+	/* Enable interrupts in supervisor register */
+	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
+
+	return 0;
+}
+
+void enable_interrupts(void)
+{
+	/* Set interrupt enable bit in supervisor register */
+	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
+	/* Enable timer exception */
+	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_TEE);
+}
+
+int disable_interrupts(void)
+{
+	/* Clear interrupt enable bit in supervisor register */
+	mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE);
+	/* Disable timer exception */
+	mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_TEE);
+	return 0;
+}
+
+void irq_install_handler(int irq, interrupt_handler_t *handler, void *arg)
+{
+	if (irq < 0 || irq > 31)
+		return;
+
+	handlers[irq].handler = handler;
+	handlers[irq].arg = arg;
+}
+
+void irq_free_handler(int irq)
+{
+	if (irq < 0 || irq > 31)
+		return;
+
+	handlers[irq].handler = 0;
+	handlers[irq].arg = 0;
+}
+
+#if defined(CONFIG_CMD_IRQ)
+int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+
+	printf("\nInterrupt-Information:\n\n");
+	printf("Nr  Routine   Arg       Count\n");
+	printf("-----------------------------\n");
+
+	for (i = 0; i < 32; i++) {
+		if (handlers[i].handler) {
+			printf("%02d  %08lx  %08lx  %d\n",
+				i,
+				(ulong)handlers[i].handler,
+				(ulong)handlers[i].arg,
+				handlers[i].count);
+		}
+	}
+	printf("\n");
+
+	return 0;
+}
+#endif

arch/openrisc/cpu/start.S new file +2 -0

new file mode 100644
index 0000000..03e6a8e
@@ -0,0 +1,335 @@
+/*
+ * (C) Copyright 2011, Stefan Kristiansson

<[email protected]> + * (C) Copyright 2011, Julius Baxter <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */

arch/openrisc/cpu/start.S new file +38 -0

+
+#include <asm-offsets.h>
+#include <asm/spr-defs.h>
+#include <config.h>
+
+#define EXCEPTION_STACK_SIZE (128+128)
+
+#define HANDLE_EXCEPTION			\
+	l.addi	r1, r1, -EXCEPTION_STACK_SIZE	;\
+	l.sw	0x1c(r1), r9			;\
+	l.jal	_exception_handler		;\
+	 l.nop					;\
+	l.lwz 	r9, 0x1c(r1)			;\
+	l.addi	r1, r1, EXCEPTION_STACK_SIZE	;\
+	l.rfe					;\
+	 l.nop
+
+	.section .vectors, "ax"
+	.global __reset
+
+	/* reset */
+	.org	0x100
+__reset:
+	/* there is no guarantee r0 is hardwired to zero, clear it here */
+	l.andi	r0, r0, 0
+	/* reset stack and frame pointers */
+	l.andi	r1, r0, 0
+	l.andi	r2, r0, 0
+
+	/* set supervisor mode */
+	l.ori	r3,r0,SPR_SR_SM
+	l.mtspr	r0,r3,SPR_SR
+
+	/* Relocate u-boot */
+	l.movhi	r3,hi(__start)		/* source start address */
+	l.ori	r3,r3,lo(__start)
+	l.movhi	r4,hi(_stext)		/* dest start address */
+	l.ori	r4,r4,lo(_stext)

arch/openrisc/cpu/start.S new file +7 -0

+
+#ifdef CONFIG_SYS_RELOCATE_VECTORS
+	/* Relocate vectors from 0xf0000000 to 0x00000000 */
+	l.movhi r4, 0xf000 /* source */
+	l.movhi r5, 0      /* destination */
+	l.addi	r6, r5, CONFIG_SYS_VECTORS_LEN /* length */
+.L_relocvectors:

arch/openrisc/cpu/start.S new file +241 -0

+
+	/* bus error */
+	.org	0x200
+	HANDLE_EXCEPTION
+
+	/* data page fault */
+	.org	0x300
+	HANDLE_EXCEPTION
+
+	/* instruction page fault */
+	.org	0x400
+	HANDLE_EXCEPTION
+
+	/* tick timer */
+	.org	0x500
+	HANDLE_EXCEPTION
+
+	/* alignment */
+	.org	0x600
+	HANDLE_EXCEPTION
+
+	/* illegal instruction */
+	.org	0x700
+	HANDLE_EXCEPTION
+
+	/* external interrupt */
+	.org	0x800
+	HANDLE_EXCEPTION
+
+	/* D-TLB miss */
+	.org	0x900
+	HANDLE_EXCEPTION
+
+	/* I-TLB miss */
+	.org	0xa00
+	HANDLE_EXCEPTION
+
+	/* range */
+	.org	0xb00
+	HANDLE_EXCEPTION
+
+	/* system call */
+	.org	0xc00
+	HANDLE_EXCEPTION
+
+	/* floating point */
+	.org	0xd00
+	HANDLE_EXCEPTION
+
+	/* trap */
+	.org	0xe00
+	HANDLE_EXCEPTION
+
+	/* reserved */
+	.org	0xf00
+	HANDLE_EXCEPTION
+
+	/* reserved */
+	.org	0x1100
+	HANDLE_EXCEPTION
+
+	/* reserved */
+	.org	0x1200
+	HANDLE_EXCEPTION
+
+	/* reserved */
+	.org	0x1300
+	HANDLE_EXCEPTION
+
+	/* reserved */
+	.org	0x1400
+	HANDLE_EXCEPTION
+
+	/* reserved */
+	.org	0x1500
+	HANDLE_EXCEPTION
+
+	/* reserved */
+	.org	0x1600
+	HANDLE_EXCEPTION
+
+	/* reserved */
+	.org	0x1700
+	HANDLE_EXCEPTION
+
+	/* reserved */
+	.org	0x1800
+	HANDLE_EXCEPTION
+
+	/* reserved */
+	.org	0x1900
+	HANDLE_EXCEPTION
+
+	/* reserved */
+	.org	0x1a00
+	HANDLE_EXCEPTION
+
+	/* reserved */
+	.org	0x1b00
+	HANDLE_EXCEPTION
+
+	/* reserved */
+	.org	0x1c00
+	HANDLE_EXCEPTION
+
+	/* reserved */
+	.org	0x1d00
+	HANDLE_EXCEPTION
+
+	/* reserved */
+	.org	0x1e00
+	HANDLE_EXCEPTION
+
+	/* reserved */
+	.org	0x1f00
+	HANDLE_EXCEPTION
+
+	/* Startup routine */
+	.text
+	.global _start
+_start:
+	/* Init stack and frame pointers */
+	l.movhi	r1, hi(CONFIG_SYS_INIT_SP_ADDR)
+	l.ori	r1, r1, lo(CONFIG_SYS_INIT_SP_ADDR)
+	l.or	r2, r0, r1
+
+	/* clear BSS segments */
+	l.movhi	r4, hi(_bss_start)
+	l.ori	r4, r4, lo(_bss_start)
+	l.movhi	r5, hi(_bss_end)
+	l.ori	r5, r5, lo(_bss_end)
+.L_clear_bss:
+	l.sw	0(r4), r0
+	l.sfltu	r4,r5
+	l.bf	.L_clear_bss
+	 l.addi	r4,r4,4
+
+	/* Reset registers before jumping to board_init */
+	l.andi	r3, r0, 0
+	l.andi	r4, r0, 0
+	l.andi	r5, r0, 0
+	l.andi	r6, r0, 0
+	l.andi	r7, r0, 0
+	l.andi	r8, r0, 0
+	l.andi	r9, r0, 0
+	l.andi	r10, r0, 0
+	l.andi	r11, r0, 0
+	l.andi	r12, r0, 0
+	l.andi	r13, r0, 0
+	l.andi	r14, r0, 0
+	l.andi	r15, r0, 0
+	l.andi	r17, r0, 0
+	l.andi	r18, r0, 0
+	l.andi	r19, r0, 0
+	l.andi	r20, r0, 0
+	l.andi	r21, r0, 0
+	l.andi	r22, r0, 0
+	l.andi	r23, r0, 0
+	l.andi	r24, r0, 0
+	l.andi	r25, r0, 0
+	l.andi	r26, r0, 0
+	l.andi	r27, r0, 0
+	l.andi	r28, r0, 0
+	l.andi	r29, r0, 0
+	l.andi	r30, r0, 0
+	l.andi	r31, r0, 0
+
+	l.j	board_init
+	 l.nop
+
+	.size	_start, .-_start
+
+/*
+ * Store state onto stack and call the real exception handler
+ */
+	.section .text
+	.extern	exception_handler
+	.type	_exception_handler, at function
+
+_exception_handler:
+	/* Store state (r9 already saved)*/
+	l.sw	0x00(r1), r2
+	l.sw	0x04(r1), r3
+	l.sw	0x08(r1), r4
+	l.sw	0x0c(r1), r5
+	l.sw	0x10(r1), r6
+	l.sw	0x14(r1), r7
+	l.sw	0x18(r1), r8
+	l.sw	0x20(r1), r10
+	l.sw	0x24(r1), r11
+	l.sw	0x28(r1), r12
+	l.sw	0x2c(r1), r13
+	l.sw	0x30(r1), r14
+	l.sw	0x34(r1), r15
+	l.sw	0x38(r1), r16
+	l.sw	0x3c(r1), r17
+	l.sw	0x40(r1), r18
+	l.sw	0x44(r1), r19
+	l.sw	0x48(r1), r20
+	l.sw	0x4c(r1), r21
+	l.sw	0x50(r1), r22
+	l.sw	0x54(r1), r23
+	l.sw	0x58(r1), r24
+	l.sw	0x5c(r1), r25
+	l.sw	0x60(r1), r26
+	l.sw	0x64(r1), r27
+	l.sw	0x68(r1), r28
+	l.sw	0x6c(r1), r29
+	l.sw	0x70(r1), r30
+	l.sw	0x74(r1), r31
+
+	/* Save return address */
+	l.or	r14, r0, r9
+	/* Call exception handler with the link address as argument */
+	l.jal	exception_handler
+	 l.or	r3, r0, r14
+	/* Load return address */
+	l.or	r9, r0, r14
+
+	/* Restore state */
+	l.lwz	r2, 0x00(r1)
+	l.lwz	r3, 0x04(r1)
+	l.lwz	r4, 0x08(r1)
+	l.lwz	r5, 0x0c(r1)
+	l.lwz	r6, 0x10(r1)
+	l.lwz	r7, 0x14(r1)
+	l.lwz	r8, 0x18(r1)
+	l.lwz	r10, 0x20(r1)
+	l.lwz	r11, 0x24(r1)
+	l.lwz	r12, 0x28(r1)
+	l.lwz	r13, 0x2c(r1)
+	l.lwz	r14, 0x30(r1)
+	l.lwz	r15, 0x34(r1)
+	l.lwz	r16, 0x38(r1)
+	l.lwz	r17, 0x3c(r1)
+	l.lwz	r18, 0x40(r1)
+	l.lwz	r19, 0x44(r1)
+	l.lwz	r20, 0x48(r1)
+	l.lwz	r21, 0x4c(r1)
+	l.lwz	r22, 0x50(r1)
+	l.lwz	r23, 0x54(r1)

arch/openrisc/cpu/cache.c line 27

Quoted 1 line

arch/openrisc/cpu/cache.c new file +1 -0

+	return (mfspr(SPR_ICCFGR) & SPR_ICCFGR_CBS) ? 32 : 16;

What's mfspr ... if it's some register, then maybe mfspr_read() ?

arch/openrisc/cpu/cpu.c line 76

Quoted 2 lines

arch/openrisc/cpu/cpu.c new file +2 -0

+	printf("CPU:   OpenRISC-%x00 (rev %d) @ %d MHz\n",
+		ver, rev, (CONFIG_SYS_CLK_FREQ / 1000000));

The CPU won't tell you it's speed ?

arch/openrisc/cpu/start.S line 67

Quoted 4 lines

arch/openrisc/cpu/start.S new file +4 -0

+	l.addi	r3,r3,4
+	l.sfltu	r4,r5
+	l.bf	.L_reloc
+	 l.addi	r4,r4,4			/* delay slot */

The formating here doesn't seem right?

Quoted 3 lines

arch/openrisc/cpu/cache.c line 27

Quoted 1 line

arch/openrisc/cpu/cache.c new file +1 -0

+	return (mfspr(SPR_ICCFGR) & SPR_ICCFGR_CBS) ? 32 : 16;

What's mfspr ... if it's some register, then maybe mfspr_read() ?

It's an instruction, "move from special register", so I don't think the _read would be appropriate in this case.

Quoted 4 lines

arch/openrisc/cpu/cpu.c line 76

Quoted 2 lines

arch/openrisc/cpu/cpu.c new file +2 -0

+	printf("CPU:   OpenRISC-%x00 (rev %d) @ %d MHz\n",
+		ver, rev, (CONFIG_SYS_CLK_FREQ / 1000000));

The CPU won't tell you it's speed ?

Nope.

Quoted 7 lines

arch/openrisc/cpu/start.S line 67

Quoted 5 lines

arch/openrisc/cpu/start.S new file +4 -0

+	l.addi	r3,r3,4
+	l.sfltu	r4,r5
+	l.bf	.L_reloc
+	 l.addi	r4,r4,4			/* delay slot */

The formating here doesn't seem right?

The extra space there is to denote that the instruction is in a delay slot.
I think it brings more readability to the code, but if it meets too much resistance I'll remove them.

Stefan

Quoted 7 lines · Marek Vasut

Quoted 4 lines

arch/openrisc/cpu/cpu.c line 76

Quoted 2 lines

arch/openrisc/cpu/cpu.c new file +2 -0

+	printf("CPU:   OpenRISC-%x00 (rev %d) @ %d MHz\n",
+		ver, rev, (CONFIG_SYS_CLK_FREQ / 1000000));

The CPU won't tell you it's speed ?

Nope.

That's weird, how do you calibrate delay then, using static setup ?

Quoted 6 lines

Quoted 6 lines · Marek Vasut

Quoted 4 lines

arch/openrisc/cpu/cpu.c line 76

Quoted 2 lines

arch/openrisc/cpu/cpu.c new file +2 -0

+	printf("CPU:   OpenRISC-%x00 (rev %d) @ %d MHz\n",
+		ver, rev, (CONFIG_SYS_CLK_FREQ / 1000000));

The CPU won't tell you it's speed ?

Quoted 3 lines

Quoted 1 line

Nope.

That's weird, how do you calibrate delay then, using static setup ?

You mean in Linux? CPU freq is passed in via the device tree.

Quoted 7 lines · Marek Vasut

Quoted 6 lines

Quoted 6 lines · Marek Vasut

Quoted 4 lines

arch/openrisc/cpu/cpu.c line 76

Quoted 2 lines

arch/openrisc/cpu/cpu.c new file +2 -0

+	printf("CPU:   OpenRISC-%x00 (rev %d) @ %d MHz\n",
+		ver, rev, (CONFIG_SYS_CLK_FREQ / 1000000));

The CPU won't tell you it's speed ?

Quoted 5 lines

Quoted 3 lines

Quoted 1 line

Nope.

That's weird, how do you calibrate delay then, using static setup ?

You mean in Linux? CPU freq is passed in via the device tree.

I mean in u-boot, it seems weird for the CPU to be unable to tell you how fast it runs.

Quoted 8 lines · Marek Vasut

Quoted 6 lines

arch/openrisc/cpu/start.S line 67

Quoted 4 lines

arch/openrisc/cpu/start.S new file +4 -0

+	l.addi	r3,r3,4
+	l.sfltu	r4,r5
+	l.bf	.L_reloc
+	 l.addi	r4,r4,4			/* delay slot */

The formating here doesn't seem right?

Quoted 4 lines

The extra space there is to denote that the instruction is in a delay slot.
I think it brings more readability to the code, but if it meets too much resistance I'll remove them.

You already have comment there, but let's see what the others think.

+init_fnc_t *init_sequence[] = {

+#if defined(CONFIG_NET_MULTI)

Signed-off-by Stefan Kristiansson <[email protected]>

---
 arch/openrisc/lib/Makefile |   47 ++++++++++++
 arch/openrisc/lib/board.c  |  175
++++++++++++++++++++++++++++++++++++++++++++ arch/openrisc/lib/bootm.c  | 
 84 +++++++++++++++++++++
 arch/openrisc/lib/timer.c  |  104 ++++++++++++++++++++++++++
 4 files changed, 410 insertions(+), 0 deletions(-)
 create mode 100644 arch/openrisc/lib/Makefile
 create mode 100644 arch/openrisc/lib/board.c
 create mode 100644 arch/openrisc/lib/bootm.c
 create mode 100644 arch/openrisc/lib/timer.c

arch/openrisc/lib/Makefile new file +47 -0

new file mode 100644
index 0000000..db3c657
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(ARCH).o
+
+SOBJS-y	+=
+
+COBJS-y	+= board.o
+COBJS-y	+= bootm.o
+COBJS-y	+= timer.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/openrisc/lib/board.c new file +55 -0

new file mode 100644
index 0000000..b033031
@@ -0,0 +1,175 @@
+/*
+ * (C) Copyright 2011
+ * Julius Baxter, julius at opencores.org
+ *
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <[email protected]>
+ *
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <stdio_dev.h>
+#include <watchdog.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <net.h>
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+#endif
+#ifdef CONFIG_CMD_NAND
+#include <nand.h>	/* cannot even include nand.h if it isnt configured */
+#endif
+
+#include <timestamp.h>
+#include <version.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * All attempts to come up with a "common" initialization sequence
+ * that works for all boards and architectures failed: some of the
+ * requirements are just _too_ different. To get rid of the resulting
+ * mess of board dependend #ifdef'ed code we now make the whole
+ * initialization sequence configurable to the user.
+ *

arch/openrisc/lib/board.c new file +97 -0

+
+/*
+ * Initialization sequence
+ */
+
+init_fnc_t *init_sequence[] = {
+	cache_init,
+	timer_init,		/* initialize timer */
+	env_init,
+	serial_init,
+	console_init_f,
+	display_options,
+	checkcpu,
+	checkboard,
+	NULL,			/* Terminate this list */
+};
+
+
+/***********************************************************************/
+void board_init(void)
+{
+	bd_t *bd;
+	init_fnc_t **init_fnc_ptr;
+
+	gd = (gd_t *)CONFIG_SYS_GBL_DATA_ADDR;
+
+	memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
+
+	gd->bd = (bd_t *)(gd+1);	/* At end of global data */
+	gd->baudrate = CONFIG_BAUDRATE;
+	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
+
+	bd = gd->bd;
+	bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+#ifndef CONFIG_SYS_NO_FLASH
+	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+#endif
+#if	defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
+	bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
+	bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
+#endif
+	bd->bi_baudrate = CONFIG_BAUDRATE;
+
+	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
+		WATCHDOG_RESET();
+		if ((*init_fnc_ptr)() != 0)
+			hang();
+	}
+
+	WATCHDOG_RESET();
+
+	/* The Malloc area is immediately below the monitor copy in RAM */
+	mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
+
+#ifndef CONFIG_SYS_NO_FLASH
+	WATCHDOG_RESET();
+	bd->bi_flashsize = flash_init();
+#endif
+
+#ifdef CONFIG_CMD_NAND
+	puts("NAND:  ");
+	nand_init();
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+	puts("MMC:   ");
+	mmc_initialize(bd);
+#endif
+
+	WATCHDOG_RESET();
+	env_relocate();
+
+	WATCHDOG_RESET();
+	stdio_init();
+	jumptable_init();
+	console_init_r();
+
+	WATCHDOG_RESET();
+	interrupt_init();
+
+#if defined(CONFIG_BOARD_LATE_INIT)
+	board_late_init();
+#endif
+
+#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_NET_MULTI)
+	puts("NET:   ");
+#endif
+	eth_initialize(bd);
+#endif
+
+	/* main_loop */
+	for (;;) {
+		WATCHDOG_RESET();
+		main_loop();
+	}

arch/openrisc/lib/board.c new file +3 -0

+	for (;;)
+		;
+}

arch/openrisc/lib/bootm.c new file +2 -0

new file mode 100644
index 0000000..2c5d9ae
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2011 Stefan Kristiansson

<[email protected]> + *
+ * Based on microblaze implementation by:
+ * (C) Copyright 2007 Michal Simek
+ * (C) Copyright 2004 Atmark Techno, Inc.
+ *
+ * Michal SIMEK <[email protected]>
+ * Yasushi SHOJI <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */

arch/openrisc/lib/bootm.c new file +56 -0

+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <u-boot/zlib.h>
+#include <asm/byteorder.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int do_bootm_linux(int flag, int argc, char * const argv[],
+			bootm_headers_t *images)
+{
+	void	(*kernel) (unsigned int);
+	ulong	rd_data_start, rd_data_end;
+
+	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
+		return 1;
+
+	int	ret;
+
+	char	*of_flat_tree = NULL;
+#if defined(CONFIG_OF_LIBFDT)
+	/* did generic code already find a device tree? */
+	if (images->ft_len)
+		of_flat_tree = images->ft_addr;
+#endif
+
+	kernel = (void (*)(unsigned int))images->ep;
+
+	/* find ramdisk */
+	ret = boot_get_ramdisk(argc, argv, images, IH_ARCH_OPENRISC,
+			&rd_data_start, &rd_data_end);
+	if (ret)
+		return 1;
+
+	show_boot_progress(15);
+
+	if (!of_flat_tree && argc > 3)
+		of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16);
+#ifdef DEBUG
+	printf("## Transferring control to Linux (at address 0x%08lx) " \
+				"ramdisk 0x%08lx, FDT 0x%08lx...\n",
+		(ulong) kernel, rd_data_start, (ulong) of_flat_tree);
+#endif
+	if (dcache_status() || icache_status())
+		flush_cache((ulong)kernel, max(checkdcache(), checkicache()));
+
+	/*
+	 * Linux Kernel Parameters (passing device tree):
+	 * r3: pointer to the fdt, followed by the board info data
+	 */
+	kernel((unsigned int) of_flat_tree);
+	/* does not return */
+
+	return 1;
+}

arch/openrisc/lib/timer.c new file +2 -0

new file mode 100644
index 0000000..52d2be9
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2011, Stefan Kristiansson

<[email protected]> + * (C) Copyright 2011, Julius Baxter <[email protected]>
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */

arch/openrisc/lib/timer.c new file +9 -0

+
+#include <asm/system.h>
+#include <asm/openrisc_exc.h>
+#include <common.h>
+
+static ulong timestamp;
+
+/* how many counter cycles in a jiffy */
+#define TIMER_COUNTER_CYCLES 

(CONFIG_SYS_CLK_FREQ/CONFIG_SYS_OPENRISC_TMR_HZ) +/* how many ms elapses between each timer interrupt */

arch/openrisc/lib/timer.c new file +60 -0

+#define TIMER_TIMESTAMP_INC   (1000/CONFIG_SYS_OPENRISC_TMR_HZ)
+/* how many cycles per ms */
+#define TIMER_CYCLES_MS       (CONFIG_SYS_CLK_FREQ/1000)
+/* how many cycles per us */
+#define TIMER_CYCLES_US       (CONFIG_SYS_CLK_FREQ/1000000uL)
+
+void timer_isr(void)
+{
+	timestamp += TIMER_TIMESTAMP_INC;
+	mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
+		(TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
+}
+
+int timer_init(void)
+{
+	/* Install timer exception handler */
+	exception_install_handler(EXC_TIMER, timer_isr);
+
+	/* Set up the timer for the first expiration. */
+	timestamp = 0;
+
+	mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
+		(TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
+
+	/* Enable tick timer exception in supervisor register */
+	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_TEE);
+
+	return 0;
+}
+
+void reset_timer(void)
+{
+	timestamp = 0;
+
+	mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
+		(TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
+}
+
+/*
+ * The timer value in ms is calculated by taking the
+ * value accumulated by full timer revolutions plus the value
+ * accumulated in this period
+ */
+ulong get_timer(ulong base)
+{
+	return timestamp + mfspr(SPR_TTCR)/TIMER_CYCLES_MS - base;
+}
+
+void set_timer(ulong t)
+{
+	reset_timer();
+	timestamp = t;
+}
+
+void __udelay(ulong usec)
+{
+	ulong elapsed = 0;
+	ulong tick;
+	ulong last_tick;
+

Quoted 1 line

 create mode 100644 arch/openrisc/lib/timer.c

Timer support isn't a library function but a CPU function, so move it to 3/9.

arch/openrisc/lib/board.c line 172

Quoted 1 line

arch/openrisc/lib/board.c new file +1 -0

+	asm("l.nop 0x1"); /* Kill any simulation */

Simulation? Oh, it's an FPGA based CPU or what?

Quoted 52 lines

arch/openrisc/lib/timer.c new file +52 -0

+int timer_init(void)
+{
+	/* Install timer exception handler */
+	exception_install_handler(EXC_TIMER, timer_isr);
+
+	/* Set up the timer for the first expiration. */
+	timestamp = 0;
+
+	mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
+		(TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
+
+	/* Enable tick timer exception in supervisor register */
+	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_TEE);
+
+	return 0;
+}
+
+void reset_timer(void)
+{
+	timestamp = 0;
+
+	mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
+		(TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
+}
+
+/*
+ * The timer value in ms is calculated by taking the
+ * value accumulated by full timer revolutions plus the value
+ * accumulated in this period
+ */
+ulong get_timer(ulong base)
+{
+	return timestamp + mfspr(SPR_TTCR)/TIMER_CYCLES_MS - base;
+}
+
+void set_timer(ulong t)
+{
+	reset_timer();
+	timestamp = t;
+}
+
+void __udelay(ulong usec)
+{
+	ulong elapsed = 0;
+	ulong tick;
+	ulong last_tick;
+
+	last_tick = mfspr(SPR_TTCR);
+	while ((elapsed / TIMER_CYCLES_US) < usec) {
+		tick = mfspr(SPR_TTCR);
+		if (tick >= last_tick)
+			elapsed += (tick - last_tick);

arch/openrisc/lib/timer.c line 104

Quoted 5 lines

arch/openrisc/lib/timer.c new file +5 -0

+		else
+			elapsed += TIMER_COUNTER_CYCLES - (last_tick - tick);
+		last_tick = tick;
+	}
+}

I'm not sure if this conforms with current timer api, can you cross-check with arch/arm/arm926ejs/mx28/timer.c ? That's the latest addition and should conform.

Quoted 4 lines

Quoted 1 line

 create mode 100644 arch/openrisc/lib/timer.c

Timer support isn't a library function but a CPU function, so move it to 3/9.

I never quite worked out where the timer functions belongs, some have them in interupts.c and some in their own file. Some have them cpu/ and some in lib/

Quoted 3 lines

arch/openrisc/lib/board.c line 172

Quoted 1 line

arch/openrisc/lib/board.c new file +1 -0

+	asm("l.nop 0x1"); /* Kill any simulation */

Simulation? Oh, it's an FPGA based CPU or what?

Well, yes, FPGAs are probably the most common case, but also ASIC implementations exists.
The extra argument to the nop instruction is ignored by hardware, but have special meanings when ran in simulation.

Quoted 54 lines

Quoted 54 lines

arch/openrisc/lib/timer.c new file +53 -0

+int timer_init(void)
+{
+	/* Install timer exception handler */
+	exception_install_handler(EXC_TIMER, timer_isr);
+
+	/* Set up the timer for the first expiration. */
+	timestamp = 0;
+
+	mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
+		(TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
+
+	/* Enable tick timer exception in supervisor register */
+	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_TEE);
+
+	return 0;
+}
+
+void reset_timer(void)
+{
+	timestamp = 0;
+
+	mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT |
+		(TIMER_COUNTER_CYCLES & SPR_TTMR_TP));
+}
+
+/*
+ * The timer value in ms is calculated by taking the
+ * value accumulated by full timer revolutions plus the value
+ * accumulated in this period
+ */
+ulong get_timer(ulong base)
+{
+	return timestamp + mfspr(SPR_TTCR)/TIMER_CYCLES_MS - base;
+}
+
+void set_timer(ulong t)
+{
+	reset_timer();
+	timestamp = t;
+}
+
+void __udelay(ulong usec)
+{
+	ulong elapsed = 0;
+	ulong tick;
+	ulong last_tick;
+
+	last_tick = mfspr(SPR_TTCR);
+	while ((elapsed / TIMER_CYCLES_US) < usec) {
+		tick = mfspr(SPR_TTCR);
+		if (tick >= last_tick)
+			elapsed += (tick - last_tick);
+		else

Quoted 8 lines

arch/openrisc/lib/timer.c line 104

Quoted 4 lines

arch/openrisc/lib/timer.c new file +4 -0

+			elapsed += TIMER_COUNTER_CYCLES - (last_tick - tick);
+		last_tick = tick;
+	}
+}

I'm not sure if this conforms with current timer api, can you cross-check with arch/arm/arm926ejs/mx28/timer.c ? That's the latest addition and should conform.

In my opinion it seems to do the same thing as that, what exactly did you find non-conforming?

Stefan

Quoted 8 lines

Quoted 3 lines

arch/openrisc/lib/board.c line 172

Quoted 1 line

arch/openrisc/lib/board.c new file +1 -0

+	asm("l.nop 0x1"); /* Kill any simulation */

Simulation? Oh, it's an FPGA based CPU or what?

Well, yes, FPGAs are probably the most common case, but also ASIC implementations exists.
The extra argument to the nop instruction is ignored by hardware, but have special meanings when ran in simulation.

Hmm ... I'm not quite sure this is right.

Quoted 4 lines

Quoted 4 lines

Quoted 3 lines

arch/openrisc/lib/board.c line 172

Quoted 1 line

arch/openrisc/lib/board.c new file +1 -0

+	asm("l.nop 0x1"); /* Kill any simulation */

Simulation? Oh, it's an FPGA based CPU or what?

Quoted 6 lines

Quoted 4 lines

Well, yes, FPGAs are probably the most common case, but also ASIC implementations exists.
The extra argument to the nop instruction is ignored by hardware, but have special meanings when ran in simulation.

Hmm ... I'm not quite sure this is right.

It's not important to have there, I'll just remove it.

Signed-off-by Stefan Kristiansson <[email protected]>

---
 common/cmd_bdinfo.c |   22 ++++++++++++++++++++++
 1 files changed, 22 insertions(+), 0 deletions(-)

common/cmd_bdinfo.c +8 -0

index 688b238..1cd69b5 100644
@@ -460,6 +460,28 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc,
 char * const argv[]) return 0;
 }
 
+#elif defined(CONFIG_OPENRISC)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	bd_t *bd = gd->bd;
+
+	print_num("mem start",		(ulong)bd->bi_memstart);
+	print_lnum("mem size",		(u64)bd->bi_memsize);

common/cmd_bdinfo.c +4 -0

+
+	return 0;
+}
+
 #else
  #error "a case for this architecture does not exist!"
 #endif

Quoted 10 lines

common/cmd_bdinfo.c +10 -0

+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	bd_t *bd = gd->bd;
+
+	print_num("mem start",		(ulong)bd->bi_memstart);
+	print_lnum("mem size",		(u64)bd->bi_memsize);
+	print_num("flash start",	(ulong)bd->bi_flashstart);
+	print_num("flash size",		(ulong)bd->bi_flashsize);
+	print_num("flash offset",	(ulong)bd->bi_flashoffset);
+

common/cmd_bdinfo.c int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) · line 480

Quoted 6 lines

common/cmd_bdinfo.c +6 -0

+#if defined(CONFIG_CMD_NET)
+	print_eth(0);
+	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+#endif
+
+	printf("baudrate    = %ld bps\n", bd->bi_baudrate);

Would consistent format of the printed data be a problem ? ;-)

Quoted 10 lines

Quoted 10 lines

+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{

common/cmd_bdinfo.c +8 -0

+	bd_t *bd = gd->bd;
+
+	print_num("mem start",		(ulong)bd->bi_memstart);
+	print_lnum("mem size",		(u64)bd->bi_memsize);
+	print_num("flash start",	(ulong)bd->bi_flashstart);
+	print_num("flash size",		(ulong)bd->bi_flashsize);
+	print_num("flash offset",	(ulong)bd->bi_flashoffset);
+

Quoted 8 lines

common/cmd_bdinfo.c int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) · line 480

Quoted 6 lines

common/cmd_bdinfo.c +6 -0

+#if defined(CONFIG_CMD_NET)
+	print_eth(0);
+	printf("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+#endif
+
+	printf("baudrate    = %ld bps\n", bd->bi_baudrate);

Would consistent format of the printed data be a problem ? ;-)

I'm sorry, I don't think I understand what you are referring to here. When printed, they are all lined up.
If I haven't missed something, every arch does the printing like that.

Stefan

Signed-off-by Stefan Kristiansson <[email protected]>

---
 MAINTAINERS |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

MAINTAINERS +3 -0

index f6f6b72..bf144cc 100644
@@ -1147,5 +1147,16 @@ Macpaul Lin <[email protected]>
 	ADP-AG101P	N1213 (AG101P XC5 FPGA)
 
 #########################################################################
+# OpenRISC Systems:							#
+#									#
+# Maintainer Name, Email Address					#

Keep up the good work!

This patch series adds support for the OpenRISC 1000 architecture.

Quoted 1 line · On Saturday 19 November 2011 00:21:29 Stefan Kristiansson wrote:

This patch series adds support for the OpenRISC 1000 architecture.

do you have a toolchain we can use to build this ?