MIPS: fixes and updates

WARNING: line over 80 characters
WARNING: space prohibited between function name and open parenthesis '('
WARNING: braces {} are not necessary for single statement blocks
ERROR: return is not a function, parentheses are not required
ERROR: do not use assignment in if condition
ERROR: trailing statements should be on next line
ERROR: "foo * bar" should be "foo *bar"
ERROR: spaces required around that ':' (ctx:WxV)

Signed-off-by Daniel Schwierzeck <[email protected]>

---
 arch/mips/lib/board.c |  119

+++++++++++++++++++++++++------------------------ 1 files changed, 61 insertions(+), 58 deletions(-)

arch/mips/lib/board.c +14 -14

index 1274d63..9585db7 100644
@@ -64,42 +64,43 @@ int __board_early_init_f(void)
 	 */
 	return 0;
 }
-int board_early_init_f(void) __attribute__((weak,
 alias("__board_early_init_f"))); +int board_early_init_f(void)
+	__attribute__((weak, alias("__board_early_init_f")));
 
 
-static int init_func_ram (void)
+static int init_func_ram(void)
 {
 #ifdef	CONFIG_BOARD_TYPES
 	int board_type = gd->board_type;
 #else
 	int board_type = 0;	/* use dummy arg */
 #endif
-	puts ("DRAM:  ");
+	puts("DRAM:  ");
 
-	if ((gd->ram_size = initdram (board_type)) > 0) {
-		print_size (gd->ram_size, "\n");
-		return (0);
+	gd->ram_size = initdram(board_type);
+	if (gd->ram_size) {
+		print_size(gd->ram_size, "\n");
+		return 0;
 	}
-	puts (failed);
-	return (1);
+	puts(failed);
+	return 1;
 }
 
 static int display_banner(void)
 {
-
-	printf ("\n\n%s\n\n", version_string);
-	return (0);
+	printf("\n\n%s\n\n", version_string);
+	return 0;
 }
 
 #ifndef CONFIG_SYS_NO_FLASH
 static void display_flash_config(ulong size)
 {
-	puts ("Flash: ");
-	print_size (size, "\n");
+	puts("Flash: ");
+	print_size(size, "\n");
 }
 #endif
 
-static int init_baudrate (void)
+static int init_baudrate(void)
 {
 	gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
 	return 0;

arch/mips/lib/board.c +14 -12

+	/*
+	 * Pointer is writable since we allocated a register for it.
 	 */
 	gd = &gd_data;
+
 	/* compiler optimization barrier needed for GCC >= 3.4 */
-	__asm__ __volatile__("": : :"memory");
+	__asm__ __volatile__("" : : : "memory");
 
-	memset ((void *)gd, 0, sizeof (gd_t));
+	memset((void *)gd, 0, sizeof(gd_t));
 
 	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
-		if ((*init_fnc_ptr)() != 0) {
-			hang ();
-		}
+		if ((*init_fnc_ptr)() != 0)
+			hang();
 	}
 
 	/*

@@ -179,7 +182,7 @@ void board_init_f(ulong bootflag)
 	/* round down to next 4 kB limit.
 	 */
 	addr &= ~(4096 - 1);
-	debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
+	debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
 
 	/* Reserve memory for U-Boot code, data & bss
 	 * round down to next 16 kB limit

@@ -187,12 +190,12 @@ void board_init_f(ulong bootflag)
 	addr -= len;
 	addr &= ~(16 * 1024 - 1);
 
-	debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
+	debug("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
 
 	 /* Reserve memory for malloc() arena.
 	 */
 	addr_sp = addr - TOTAL_MALLOC_LEN;
-	debug ("Reserving %dk for malloc() at: %08lx\n",
+	debug("Reserving %dk for malloc() at: %08lx\n",
 			TOTAL_MALLOC_LEN >> 10, addr_sp);
 
 	/*

@@ -202,19 +205,19 @@ void board_init_f(ulong bootflag)
 	addr_sp -= sizeof(bd_t);
 	bd = (bd_t *)addr_sp;
 	gd->bd = bd;
-	debug ("Reserving %zu Bytes for Board Info at: %08lx\n",
+	debug("Reserving %zu Bytes for Board Info at: %08lx\n",
 			sizeof(bd_t), addr_sp);
 
 	addr_sp -= sizeof(gd_t);
 	id = (gd_t *)addr_sp;
-	debug ("Reserving %zu Bytes for Global Data at: %08lx\n",
-			sizeof (gd_t), addr_sp);
+	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
+			sizeof(gd_t), addr_sp);
 
 	/* Reserve memory for boot params.
 	 */
 	addr_sp -= CONFIG_SYS_BOOTPARAMS_LEN;
 	bd->bi_boot_params = addr_sp;
-	debug ("Reserving %dk for boot params() at: %08lx\n",
+	debug("Reserving %dk for boot params() at: %08lx\n",
 			CONFIG_SYS_BOOTPARAMS_LEN >> 10, addr_sp);
 
 	/*

arch/mips/lib/board.c +25 -24

-	bd->bi_baudrate	= gd->baudrate;		/* Console Baudrate */
+	bd->bi_memstart	= CONFIG_SYS_SDRAM_BASE;  /* start of DRAM memory */
+	bd->bi_memsize	= gd->ram_size;  /* size of DRAM memory in bytes */
+	bd->bi_baudrate	= gd->baudrate;  /* Console Baudrate */
 
-	memcpy (id, (void *)gd, sizeof (gd_t));
+	memcpy(id, (void *)gd, sizeof(gd_t));
 
-	relocate_code (addr_sp, id, addr);
+	relocate_code(addr_sp, id, addr);
 
 	/* NOTREACHED - relocate_code() does not return */
 }

@@ -254,14 +257,14 @@ void board_init_f(ulong bootflag)
  ************************************************************************
  */
 
-void board_init_r (gd_t *id, ulong dest_addr)
+void board_init_r(gd_t *id, ulong dest_addr)
 {
 #ifndef CONFIG_SYS_NO_FLASH
 	ulong size;
 #endif
-	extern void malloc_bin_reloc (void);
+	extern void malloc_bin_reloc(void);
 #ifndef CONFIG_ENV_IS_NOWHERE
-	extern char * env_name_spec;
+	extern char *env_name_spec;
 #endif
 	char *s;
 	bd_t *bd;

@@ -269,7 +272,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	gd = id;
 	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
 
-	debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
+	debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
 
 	gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE;
 

@@ -298,7 +301,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 #ifndef CONFIG_SYS_NO_FLASH
 	/* configure available FLASH banks */
 	size = flash_init();
-	display_flash_config (size);
+	display_flash_config(size);
 	bd->bi_flashsize = size;
 #endif
 

@@ -310,8 +313,8 @@ void board_init_r (gd_t *id, ulong dest_addr)
 #endif
 
 #ifdef CONFIG_CMD_NAND
-	puts ("NAND:  ");
-	nand_init ();		/* go init the NAND */
+	puts("NAND:  ");
+	nand_init();		/* go init the NAND */
 #endif
 
 #if defined(CONFIG_CMD_ONENAND)

@@ -333,51 +336,51 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
 /** leave this here (after malloc(), environment and PCI are working) **/
 	/* Initialize stdio devices */
-	stdio_init ();
+	stdio_init();
 
-	jumptable_init ();
+	jumptable_init();
 
 	/* Initialize the console (after the relocation and devices init) */
-	console_init_r ();
+	console_init_r();
 /** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **/
 
 	/* Initialize from environment */
 	load_addr = getenv_ulong("loadaddr", 16, load_addr);
 #if defined(CONFIG_CMD_NET)
-	if ((s = getenv ("bootfile")) != NULL) {
-		copy_filename (BootFile, s, sizeof (BootFile));
-	}
+	s = getenv("bootfile");
+	if (s)
+		copy_filename(BootFile, s, sizeof(BootFile));
 #endif
 
 #ifdef CONFIG_CMD_SPI
-	puts ("SPI:   ");
-	spi_init ();		/* go init the SPI */
-	puts ("ready\n");
+	puts("SPI:   ");
+	spi_init();		/* go init the SPI */
+	puts("ready\n");
 #endif
 
 #if defined(CONFIG_MISC_INIT_R)
 	/* miscellaneous platform dependent initialisations */
-	misc_init_r ();
+	misc_init_r();
 #endif
 
 #ifdef CONFIG_BITBANGMII
 	bb_miiphy_init();
 #endif
 #if defined(CONFIG_CMD_NET)
-	puts ("Net:   ");
+	puts("Net:   ");
 	eth_initialize(gd->bd);
 #endif
 
 	/* main_loop() can return to retry autoboot, if so just run it again. */
-	for (;;) {
-		main_loop ();
-	}
+	for (;;)
+		main_loop();
 
 	/* NOTREACHED - no way out of command loop except booting */
 }

WARNING: line over 80 characters
WARNING: space prohibited between function name and open parenthesis '('
WARNING: braces {} are not necessary for single statement blocks
ERROR: return is not a function, parentheses are not required
ERROR: do not use assignment in if condition
ERROR: trailing statements should be on next line
ERROR: "foo * bar" should be "foo *bar"
ERROR: spaces required around that ':' (ctx:WxV)

Signed-off-by Daniel Schwierzeck <[email protected]>

---
 arch/mips/lib/board.c |  119 +++++++++++++++++++++++++------------------------
 1 files changed, 61 insertions(+), 58 deletions(-)

board.c: In function 'board_init_r':
board.c:280:8: warning: unused variable 's'

Signed-off-by Daniel Schwierzeck <[email protected]>

---
 arch/mips/lib/board.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

arch/mips/lib/board.c +0 -1

index 9585db7..aac7690 100644
@@ -266,7 +266,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 #ifndef CONFIG_ENV_IS_NOWHERE
 	extern char *env_name_spec;
 #endif
-	char *s;
 	bd_t *bd;
 
 	gd = id;

Quoted 19 lines

board.c: In function 'board_init_r':
board.c:280:8: warning: unused variable 's'

Signed-off-by Daniel Schwierzeck <[email protected]>

---
?arch/mips/lib/board.c | ? ?3 +--
?1 files changed, 1 insertions(+), 2 deletions(-)

arch/mips/lib/board.c +0 -0

index 9585db7..aac7690 100644
@@ -266,7 +266,6 @@ void board_init_r(gd_t *id, ulong dest_addr)

?#ifndef CONFIG_ENV_IS_NOWHERE
? ? ? extern char *env_name_spec;
?#endif
- ? ? char *s;
? ? ? bd_t *bd;

Quoted 10 lines

? ? ? gd = id;

arch/mips/lib/board.c +0 -0

@@ -347,7 +346,7 @@ void board_init_r(gd_t *id, ulong dest_addr)

? ? ? /* Initialize from environment */
? ? ? load_addr = getenv_ulong("loadaddr", 16, load_addr); ?#if defined(CONFIG_CMD_NET)
- ? ? s = getenv("bootfile");
+ ? ? const char *s = getenv("bootfile");
? ? ? if (s)
? ? ? ? ? ? ? copy_filename(BootFile, s, sizeof(BootFile)); ?#endif

Are you sure about this "const" thing? Also, try compiling the stuff with gcc4.6, it'll reveal more errors.

Quoted 19 lines

Quoted 19 lines

board.c: In function 'board_init_r':
board.c:280:8: warning: unused variable 's'

Signed-off-by Daniel Schwierzeck <[email protected]>

---
 arch/mips/lib/board.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

arch/mips/lib/board.c +0 -1

index 9585db7..aac7690 100644
@@ -266,7 +266,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 #ifndef CONFIG_ENV_IS_NOWHERE
      extern char *env_name_spec;
 #endif
-     char *s;
      bd_t *bd;
 

Quoted 13 lines

arch/mips/lib/board.c void board_init_r(gd_t *id, ulong dest_addr) · line 352

Quoted 10 lines

arch/mips/lib/board.c +1 -1

      gd = id;

@@ -347,7 +346,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
      /* Initialize from environment */
      load_addr = getenv_ulong("loadaddr", 16, load_addr);
 #if defined(CONFIG_CMD_NET)
-     s = getenv("bootfile");
+     const char *s = getenv("bootfile");
      if (s)
              copy_filename(BootFile, s, sizeof(BootFile));
 #endif

Are you sure about this "const" thing? Also, try compiling the stuff with gcc4.6, it'll reveal more errors.

yes, s is only used in the if and as parameter for copy_filename. The function signature
also have const:

extern void copy_filename (char *dst, const char *src, int size);

And gcc-4.6.2 compiles that part without warnings.

board.c: In function 'board_init_r':
board.c:280:8: warning: unused variable 's'

Dear Daniel Schwierzeck,

Quoted 2 lines · In message <1322143076-20349-3-git-send-email-daniel.schwierzeck@googlemail.com…

board.c: In function 'board_init_r':
board.c:280:8: warning: unused variable 's'

...

Quoted 7 lines

? ? ? /* Initialize from environment */
? ? ? load_addr = getenv_ulong("loadaddr", 16, load_addr); ?#if defined(CONFIG_CMD_NET)
- ? ? s = getenv("bootfile");
+ ? ? const char *s = getenv("bootfile");
? ? ? if (s)
? ? ? ? ? ? ? copy_filename(BootFile, s, sizeof(BootFile));

We don't allow declarations in the middle of the code.

[This issue has also been fixed since, so no further actiuvity needed.]

Boards with CONFIG_SYS_NO_FLASH should not forced to define CONFIG_SYS_FLASH_BASE. In this case the flash data in bd_info should be initialized with 0 like the other archs do.

Signed-off-by Daniel Schwierzeck <[email protected]>

---
 arch/mips/lib/board.c |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

arch/mips/lib/board.c +1 -2

index aac7690..bcf12c5 100644
@@ -301,15 +301,19 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	/* configure available FLASH banks */
 	size = flash_init();
 	display_flash_config(size);
+	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
 	bd->bi_flashsize = size;
-#endif
 
-	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
 #if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
 	bd->bi_flashoffset = monitor_flash_len;	/* reserved area for U-Boot */
 #else

The CPUNum field in the Ebase register contains an unique identifier for each CPU. This helps to distinguish between CPU cores in multi-processor systems.

Signed-off-by Daniel Schwierzeck <[email protected]>

---
 arch/mips/include/asm/mipsregs.h |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

(quoted diff) +0 -0

b/arch/mips/include/asm/mipsregs.h index be7e5c6..15a9fd5 100644

arch/mips/include/asm/mipsregs.h +7 -0

@@ -89,6 +89,13 @@
 #define CP0_DWATCH $19
 
 /*
+ * Additional Coprocessor 0 register names.
+ * These registers are listed for completeness and are intended
+ * for usage in assembly code.
+ */
+#define CP0_EBASE $15,1
+
+/*
  * Coprocessor 0 Set 1 register names
  */
 #define CP0_S1_DERRADDR0  $26

Quoted 30 lines

The CPUNum field in the Ebase register contains an unique identifier for each CPU. This helps to distinguish between CPU cores in multi-processor systems.

Signed-off-by Daniel Schwierzeck <[email protected]>

---
?arch/mips/include/asm/mipsregs.h | ? 13 +++++++++++++ ?1 files changed, 13 insertions(+), 0 deletions(-)

(quoted diff) +0 -0

b/arch/mips/include/asm/mipsregs.h index be7e5c6..15a9fd5 100644

arch/mips/include/asm/mipsregs.h +0 -0

@@ -89,6 +89,13 @@

?#define CP0_DWATCH $19

?/*
+ * Additional Coprocessor 0 register names.
+ * These registers are listed for completeness and are intended
+ * for usage in assembly code.
+ */

arch/mips/include/asm/mipsregs.h +3 -0

+#define CP0_EBASE $15,1
+
+/*

? * Coprocessor 0 Set 1 register names
? */
?#define CP0_S1_DERRADDR0 ?$26

arch/mips/include/asm/mipsregs.h +0 -0

@@ -395,6 +402,12 @@
 ?#define ?CAUSEF_BD ? ? ? ? ? (_ULCAST_(1) ? << 31)
 

arch/mips/include/asm/mipsregs.h

Quoted 5 lines

?/*
+ * Bits in the coprocessor 0 EBase register.
+ */

arch/mips/include/asm/mipsregs.h +2 -0

+#define EBASEB_CPUNUM ? ? ? ? ? ? ? ?0
+#define EBASEF_CPUNUM ? ? ? ? ? ? ? ?(_ULCAST_(1023))

What's this? Isn't the maximum CPU number on MIPS 32 CPUs? Or maybe that's only 4kc limit?

This handler can be activated on multi-processor systems to boot only the master CPU. All slave CPUs are halted by executing the WAIT instruction. This is also useful to reduce the power consumption at boot time.

Signed-off-by Daniel Schwierzeck <[email protected]>

---
 arch/mips/cpu/mips32/start.S |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

arch/mips/cpu/mips32/start.S +8 -0

index 9c1b2f7..b6cb4be 100644
@@ -224,6 +224,14 @@ reset:
 
 	setup_c0_status_reset
 
+	/* Set all slave CPUs in sleep mode */
+#ifdef CONFIG_SYS_MPS_SLAVE_CPU_SLEEP
+	mfc0	k0, CP0_EBASE
+	and	k0, EBASEF_CPUNUM
+	bne	k0, zero, slave_cpu_sleep
+	 nop
+#endif
+
 	/* Init Timer */
 	mtc0	zero, CP0_COUNT
 	mtc0	zero, CP0_COMPARE

@@ -383,3 +391,11 @@ romReserved:
 

Quoted 33 lines

This handler can be activated on multi-processor systems to boot only the master CPU. All slave CPUs are halted by executing the WAIT instruction. This is also useful to reduce the power consumption at boot time.

Signed-off-by Daniel Schwierzeck <[email protected]>

---
?arch/mips/cpu/mips32/start.S | ? 16 ++++++++++++++++ ?1 files changed, 16 insertions(+), 0 deletions(-)

arch/mips/cpu/mips32/start.S +0 -0

index 9c1b2f7..b6cb4be 100644
@@ -224,6 +224,14 @@ reset:
 

? ? ? setup_c0_status_reset

+ ? ? /* Set all slave CPUs in sleep mode */

arch/mips/cpu/mips32/start.S +7 -0

+#ifdef CONFIG_SYS_MPS_SLAVE_CPU_SLEEP
+ ? ? mfc0 ? ?k0, CP0_EBASE
+ ? ? and ? ? k0, EBASEF_CPUNUM
+ ? ? bne ? ? k0, zero, slave_cpu_sleep
+ ? ? ?nop
+#endif
+

? ? ? /* Init Timer */
? ? ? mtc0 ? ?zero, CP0_COUNT
? ? ? mtc0 ? ?zero, CP0_COMPARE

arch/mips/cpu/mips32/start.S +0 -0

@@ -383,3 +391,11 @@ romReserved:
 

?romExcHandle:
? ? ? b ? ? ? romExcHandle

arch/mips/cpu/mips32/start.S romReserved: · line 401

Quoted 8 lines

arch/mips/cpu/mips32/start.S +8 -0

+
+ ? ? /* Additional handlers */
+#ifdef CONFIG_SYS_MPS_SLAVE_CPU_SLEEP
+slave_cpu_sleep:
+ ? ? wait
+ ? ? b ? ? ? slave_cpu_sleep
+ ? ? ?nop
+#endif

Can't you stall the CPU instead of letting it run in an empty loop? If not:

Acked-by Marek Vasut <[email protected]>

Quoted 45 lines

Quoted 31 lines

This handler can be activated on multi-processor systems to boot only the master CPU. All slave CPUs are halted by executing the WAIT instruction. This is also useful to reduce the power consumption at boot time.

Signed-off-by Daniel Schwierzeck <[email protected]>

---
 arch/mips/cpu/mips32/start.S |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

arch/mips/cpu/mips32/start.S +8 -0

index 9c1b2f7..b6cb4be 100644
@@ -224,6 +224,14 @@ reset:
 
      setup_c0_status_reset
 
+     /* Set all slave CPUs in sleep mode */
+#ifdef CONFIG_SYS_MPS_SLAVE_CPU_SLEEP
+     mfc0    k0, CP0_EBASE
+     and     k0, EBASEF_CPUNUM
+     bne     k0, zero, slave_cpu_sleep
+      nop
+#endif
+
      /* Init Timer */
      mtc0    zero, CP0_COUNT
      mtc0    zero, CP0_COMPARE

@@ -383,3 +391,11 @@ romReserved:
 

arch/mips/cpu/mips32/start.S romReserved: · line 401

Quoted 10 lines

arch/mips/cpu/mips32/start.S +8 -0

 romExcHandle:
      b       romExcHandle
+
+     /* Additional handlers */
+#ifdef CONFIG_SYS_MPS_SLAVE_CPU_SLEEP
+slave_cpu_sleep:
+     wait
+     b       slave_cpu_sleep
+      nop
+#endif

Can't you stall the CPU instead of letting it run in an empty loop? If not:

Quoted 1 line

Acked-by Marek Vasut <[email protected]>

the CPU is stalled with the wait instruction. The loop is actually paranoia ;)

From MIPS32 24KE Processor Core Family Software User's Manual:

The WAIT instruction forces the core into low power mode. The pipeline is stalled and when all external requests are
completed, the processor?s main clock is stopped. The processor will restart when reset (SI_Reset) is signaled, or a
non-masked interrupt is taken (SI_NMI, SI_Int, or EJ_DINT). Note that the core does not use the code field in this
instruction.

Quoted 16 lines

This handler can be activated on multi-processor systems to boot only the master CPU. All slave CPUs are halted by executing the WAIT instruction. This is also useful to reduce the power consumption at boot time.

Signed-off-by Daniel Schwierzeck <[email protected]>

---
 arch/mips/cpu/mips32/start.S |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

arch/mips/cpu/mips32/start.S +0 -0

index 9c1b2f7..b6cb4be 100644
@@ -224,6 +224,14 @@ reset:
 

arch/mips/cpu/mips32/start.S reset: · line 228

Quoted 4 lines

arch/mips/cpu/mips32/start.S +2 -0

      setup_c0_status_reset
 
+     /* Set all slave CPUs in sleep mode */
+#ifdef CONFIG_SYS_MPS_SLAVE_CPU_SLEEP

arch/mips/cpu/mips32/start.S +1 -0

index 9c1b2f7..b6cb4be 100644
@@ -224,6 +224,14 @@ reset:
 
  	setup_c0_status_reset
 
+	/* Set all slave CPUs in sleep mode */

Quoted 17 lines · Daniel Schwierzeck

arch/mips/cpu/mips32/start.S +0 -0

index 9c1b2f7..b6cb4be 100644
@@ -224,6 +224,14 @@ reset:
 

? ? ? ?setup_c0_status_reset

+ ? ? ? /* Set all slave CPUs in sleep mode */

arch/mips/cpu/mips32/start.S +7 -0

+#ifdef CONFIG_SYS_MPS_SLAVE_CPU_SLEEP
+ ? ? ? mfc0 ? ?k0, CP0_EBASE
+ ? ? ? and ? ? k0, EBASEF_CPUNUM
+ ? ? ? bne ? ? k0, zero, slave_cpu_sleep
+ ? ? ? ?nop
+#endif
+

Quoted 3 lines

? ? ? ?/* Init Timer */
? ? ? ?mtc0 ? ?zero, CP0_COUNT
? ? ? ?mtc0 ? ?zero, CP0_COMPARE

Just wondered, why is this conditionally selected? ?To save text size, or other reason?

The change looks Ok with s/MPS/MIPS/ typo fixed as pointed by Andrew.

Commit ab2a98b11716364bc5a8c43cdfa7fee176cda1d8 missed to use the new config option in dcache_enable().

Fix this to avoid inconsistencies if someone wants to disable and enable D-caches.

Signed-off-by Daniel Schwierzeck <[email protected]>

---
 arch/mips/cpu/mips32/cache.S |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

arch/mips/cpu/mips32/cache.S +4 -0

index 5ce0ec4..e683e8b 100644
@@ -30,6 +30,10 @@
 #include <asm/addrspace.h>
 #include <asm/cacheops.h>
 
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
 #define RA		t8
 
 /*

Signed-off-by Daniel Schwierzeck <[email protected]>

---
 arch/mips/cpu/mips32/cache.S     |   18 ++++++++++++++++++
 arch/mips/include/asm/mipsregs.h |    9 ++++++++-
 2 files changed, 26 insertions(+), 1 deletions(-)

arch/mips/cpu/mips32/cache.S +0 -0

index e683e8b..4801511 100644

arch/mips/cpu/mips32/cache.S +17 -0

+#define CONFIG_SYS_MIPS_CACHE_EXT_INIT
+#endif
+
+#ifdef CONFIG_SYS_CPU_MIPS34K
+#define CONFIG_SYS_MIPS_CACHE_EXT_INIT
+#endif
+
 #define RA		t8
 
 /*

@@ -81,7 +89,12 @@
  */
 LEAF(mips_init_icache)
 	blez		a1, 9f
+#ifdef CONFIG_SYS_MIPS_CACHE_EXT_INIT
+	mtc0		zero, CP0_ITAGLO
+	mtc0		zero, CP0_IDATALO
+#else
 	mtc0		zero, CP0_TAGLO
+#endif
 	/* clear tag to invalidate */
 	PTR_LI		t0, INDEX_BASE
 	PTR_ADDU	t1, t0, a1

@@ -106,7 +119,12 @@ LEAF(mips_init_icache)
  */
 LEAF(mips_init_dcache)
 	blez		a1, 9f
+#ifdef CONFIG_SYS_MIPS_CACHE_EXT_INIT
+	mtc0		zero, CP0_DTAGLO
+	mtc0		zero, CP0_DDATALO
+#else
 	mtc0		zero, CP0_TAGLO
+#endif
 	/* clear all tags */
 	PTR_LI		t0, INDEX_BASE
 	PTR_ADDU	t1, t0, a1

(quoted diff) +0 -0

b/arch/mips/include/asm/mipsregs.h index 15a9fd5..07a3cf6 100644

arch/mips/include/asm/mipsregs.h +1 -1

@@ -93,7 +93,14 @@
  * These registers are listed for completeness and are intended
  * for usage in assembly code.
  */
-#define CP0_EBASE $15,1
+#define CP0_EBASE	$15,1

Signed-off-by Daniel Schwierzeck <[email protected]>

---
 arch/mips/cpu/mips32/start.S |   21 +++++++++++++++++++--
 1 files changed, 19 insertions(+), 2 deletions(-)

arch/mips/cpu/mips32/start.S +7 -0

index b6cb4be..03cfd5a 100644
@@ -206,11 +206,28 @@ _start:
 	RVECENT(romReserved,125)
 	RVECENT(romReserved,126)
 	RVECENT(romReserved,127)
+	XVECENT(romExcHandle,0x400);
+	RVECENT(romReserved,129);
+	RVECENT(romReserved,130);
+	RVECENT(romReserved,131);
+	RVECENT(romReserved,132);
+	RVECENT(romReserved,133);
+	RVECENT(romReserved,134);

arch/mips/cpu/mips32/start.S +17 -0

@@ -206,11 +206,28 @@ _start:
  	RVECENT(romReserved,125)
  	RVECENT(romReserved,126)
  	RVECENT(romReserved,127)
+	XVECENT(romExcHandle,0x400);
+	RVECENT(romReserved,129);
+	RVECENT(romReserved,130);
+	RVECENT(romReserved,131);
+	RVECENT(romReserved,132);
+	RVECENT(romReserved,133);
+	RVECENT(romReserved,134);
+	RVECENT(romReserved,135);
+	RVECENT(romReserved,136);
+	RVECENT(romReserved,137);
+	RVECENT(romReserved,138);
+	RVECENT(romReserved,139);
+	RVECENT(romReserved,140);
+	RVECENT(romReserved,141);
+	RVECENT(romReserved,142);
+	RVECENT(romReserved,143);
+	XVECENT(romExcHandle,0x480);	# bfc00480: EJTAG debug exception

Quoted 23 lines · Daniel Schwierzeck

(quoted diff) +17 -0

@@ -206,11 +206,28 @@ _start:
 ? ? ? ?RVECENT(romReserved,125)
 ? ? ? ?RVECENT(romReserved,126)
 ? ? ? ?RVECENT(romReserved,127)
+ ? ? ? XVECENT(romExcHandle,0x400);
+ ? ? ? RVECENT(romReserved,129);
+ ? ? ? RVECENT(romReserved,130);
+ ? ? ? RVECENT(romReserved,131);
+ ? ? ? RVECENT(romReserved,132);
+ ? ? ? RVECENT(romReserved,133);
+ ? ? ? RVECENT(romReserved,134);
+ ? ? ? RVECENT(romReserved,135);
+ ? ? ? RVECENT(romReserved,136);
+ ? ? ? RVECENT(romReserved,137);
+ ? ? ? RVECENT(romReserved,138);
+ ? ? ? RVECENT(romReserved,139);
+ ? ? ? RVECENT(romReserved,140);
+ ? ? ? RVECENT(romReserved,141);
+ ? ? ? RVECENT(romReserved,142);
+ ? ? ? RVECENT(romReserved,143);
+ ? ? ? XVECENT(romExcHandle,0x480); ? ?# bfc00480: EJTAG debug exception
 

Quoted 9 lines

? ? ? ?/*
? ? ? ? * We hope there are no more reserved vectors!
- ? ? ? ?* 128 * 8 == 1024 == 0x400
- ? ? ? ?* so this is address R_VEC+0x400 == 0xbfc00400
+ ? ? ? ?* 144 * 8 == 1152 == 0x480
+ ? ? ? ?* so this is address R_VEC+0x480 == 0xbfc00480 ? ? ? ? */
? ? ? ?.align 4
?reset:

IIUC those exception vectors of +0x400/+0x480 have nothing to do with 24K processor core nor 34K either.

The change itself is Ok, and any other version taking Marek's comment into account is also welcome.

Signed-off-by Daniel Schwierzeck <[email protected]>

---
 arch/mips/include/asm/gpio.h |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/include/asm/gpio.h

arch/mips/include/asm/gpio.h new file +3 -0

new file mode 100644
index 0000000..04a98ad
@@ -0,0 +1,13 @@
+/*
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for

details. + *
+ * Copyright (C) 2011 Daniel Schwierzeck,
daniel.schwierzeck at googlemail.com + */

Signed-off-by Daniel Schwierzeck <[email protected]>

---
 arch/mips/lib/board.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

arch/mips/lib/board.c +10 -0

index bcf12c5..27c2cfe 100644
@@ -57,6 +57,16 @@ static char *failed = "*** failed ***\n";
  */
 unsigned long mips_io_port_base = -1;
 
+int __arch_cpu_init(void)
+{
+	/*
+	 * Nothing to do in this dummy implementation
+	 */
+	return 0;
+}
+int arch_cpu_init(void)
+	__attribute__((weak, alias("__arch_cpu_init")));
+
 int __board_early_init_f(void)
 {
 	/*

Quoted 40 lines

Signed-off-by Daniel Schwierzeck <[email protected]>

---

 arch/mips/lib/board.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

arch/mips/lib/board.c +10 -0

index bcf12c5..27c2cfe 100644
@@ -57,6 +57,16 @@ static char *failed = "*** failed ***\n";
 
  */
 
 unsigned long mips_io_port_base = -1;
 
+int __arch_cpu_init(void)
+{
+	/*
+	 * Nothing to do in this dummy implementation
+	 */
+	return 0;
+}
+int arch_cpu_init(void)
+	__attribute__((weak, alias("__arch_cpu_init")));
+
 

int __board_early_init_f(void)
{

arch/mips/lib/board.c +1 -0

 	/*

@@ -130,6 +140,7 @@ static int init_baudrate(void)
 
 typedef int (init_fnc_t) (void);
 
 init_fnc_t *init_sequence[] = {
 
+	arch_cpu_init,
 

arch/mips/lib/board.c static int init_baudrate(void) · line 146

Quoted 3 lines

arch/mips/lib/board.c +0 -0

 	board_early_init_f,
 	timer_init,
 	env_init,		/* initialize environment */

Maybe do it the same way it's done on ARM.

M

Build dbau1550_el only in LIST_au1xx0_el and LIST_mips_el. Also remove obsolete lists for mips5kc.

Quoted 2 lines

Build dbau1550_el only in LIST_au1xx0_el and LIST_mips_el. Also remove obsolete lists for mips5kc.

if possible, i'd really like to kill off all the specialized mips lists and do selection purely based on fields in boards.cfg.
-mike

Quoted 7 lines · On Thursday 24 November 2011 08:57:56 Daniel Schwierzeck wrote:

Quoted 2 lines

Build dbau1550_el only in LIST_au1xx0_el and LIST_mips_el. Also remove obsolete lists for mips5kc.

if possible, i'd really like to kill off all the specialized mips lists and do selection purely based on fields in boards.cfg.
-mike

I have to agree here.
M

Quoted 7 lines · Marek Vasut

Quoted 6 lines · On Thursday 24 November 2011 08:57:56 Daniel Schwierzeck wrote:

Quoted 2 lines

Build dbau1550_el only in LIST_au1xx0_el and LIST_mips_el. Also remove obsolete lists for mips5kc.

if possible, i'd really like to kill off all the specialized mips lists and do selection purely based on fields in boards.cfg. -mike

Quoted 3 lines

I have to agree here.
M

that is currently not possible because -EB and -EL are not properly handled in CFLAGS and LDFLAGS.
Until this is fixed we have to run MAKEALL twice with mips and mipsel and different toolchains.

Quoted 4 lines · Marek Vasut

Quoted 4 lines · On Thursday 24 November 2011 08:57:56 Daniel Schwierzeck wrote:

Quoted 2 lines

Build dbau1550_el only in LIST_au1xx0_el and LIST_mips_el. Also remove obsolete lists for mips5kc.

Quoted 4 lines

Quoted 2 lines

if possible, i'd really like to kill off all the specialized mips lists and do selection purely based on fields in boards.cfg.

I have to agree here.

that is currently not possible because -EB and -EL are not properly handled in CFLAGS and LDFLAGS.

Build dbau1550_el only in LIST_au1xx0_el and LIST_mips_el. Also remove obsolete lists for mips5kc.

Signed-off-by Daniel Schwierzeck <[email protected]>

Cc Thomas Lange <[email protected]>

---
 MAKEALL |   11 ++---------
 1 files changed, 2 insertions(+), 9 deletions(-)

This series contains bugfixes and coding style cleanups. Furthermore it contains some extensions for MIPS24k and MIPS34k cores as preparation for merging the support for various Lantiq SoCs.

Daniel Schwierzeck (11):
MIPS: board.c: make checkpatch.pl clean
MIPS: board.c: fix warning if CONFIG_CMD_NET is not defined
MIPS: board.c: fix init of flash data in bd_info
MIPS: add register definition for EBase register
MIPS: add sleep handler for slave CPUs in multi-processor systems
MIPS: make cache operation mode configurable in dcache_enable()
MIPS: extend cache initialization for MIPS24K and MIPS34K cores
MIPS: add additional reserved vectors for MIPS24K and MIPS34K cores
MIPS: add header file for generic GPIO API
MIPS: add init hook for CPU specific initialization
MIPS: MAKEALL: fix lists for MIPSel and MIPS boards

 MAKEALL                          |   11 +---
 arch/mips/cpu/mips32/cache.S     |   24 ++++++-
 arch/mips/cpu/mips32/start.S     |   37 ++++++++++-
 arch/mips/include/asm/gpio.h     |   13 ++++
 arch/mips/include/asm/mipsregs.h |   20 ++++++
 arch/mips/lib/board.c            |  139
+++++++++++++++++++++----------------- 6 files changed, 171 insertions(+),
73 deletions(-)
 create mode 100644 arch/mips/include/asm/gpio.h

My apologies for picking the rest of this series so late. Looks like the MIPS maintainer is n/a so I'll pull these through my staging tree once we'll fix some issues.

Best regards,
Marek Vasut

Hi Marek,

Am 31.03.2012 22:49, schrieb Marek Vasut:
<snip>

Quoted 7 lines

My apologies for picking the rest of this series so late. Looks like the MIPS maintainer is n/a so I'll pull these through my staging tree once we'll fix some issues.

Best regards,
Marek Vasut

thanks for looking into this but parts of this series are either obsolete or already applied by Wolfgang.

I'll resend a new series with bugfixes only as soon as MAKEALL is working again. Currently the MIPS tree is completely broken. All boards fail with:

cmd_bootm.c: In function 'do_bootm_subcommand':
cmd_bootm.c:518:23: error: 'bootm_headers_t' has no member named 'lmb' cmd_bootm.c: In function 'do_bootm':
cmd_bootm.c:665:21: error: 'bootm_headers_t' has no member named 'lmb'

I'll try to find a suitable fix.

Hi Daniel,

On Mon, 2 Apr 2012 13:54:18 +0200
Daniel Schwierzeck <[email protected]> wrote:

Quoted 7 lines

I'll resend a new series with bugfixes only as soon as MAKEALL is working again. Currently the MIPS tree is completely broken. All boards fail with:

cmd_bootm.c: In function 'do_bootm_subcommand':
cmd_bootm.c:518:23: error: 'bootm_headers_t' has no member named 'lmb' cmd_bootm.c: In function 'do_bootm':
cmd_bootm.c:665:21: error: 'bootm_headers_t' has no member named 'lmb'

...

Quoted 1 line

I'll try to find a suitable fix.

This is already fixed by http://patchwork.ozlabs.org/patch/149924/
I think.

Hi Marek,

Am 31.03.2012 22:49, schrieb Marek Vasut:
<snip>

Quoted 6 lines

My apologies for picking the rest of this series so late. Looks like the MIPS maintainer is n/a so I'll pull these through my staging tree once we'll fix some issues.

Best regards,
Marek Vasut

thanks for looking into this but parts of this series are either obsolete or already applied by Wolfgang.

I'll resend a new series with bugfixes only as soon as MAKEALL is working again. Currently the MIPS tree is completely broken. All boards fail with:

cmd_bootm.c: In function 'do_bootm_subcommand':
cmd_bootm.c:518:23: error: 'bootm_headers_t' has no member named 'lmb' cmd_bootm.c: In function 'do_bootm':
cmd_bootm.c:665:21: error: 'bootm_headers_t' has no member named 'lmb'

git bisect says:

44f074c771c4b70d250b0d7ed2f7513488c678bb is the first bad commit commit 44f074c771c4b70d250b0d7ed2f7513488c678bb

Author: Marek Vasut <[email protected]>
Date:   Wed Mar 14 21:52:45 2012 +0000

BOOT: Add "bootz" command to boot Linux zImage on ARM

This command boots Linux zImage from where the zImage is loaded to.
Passing initrd and fdt is supported.

Tested on i.MX28 based DENX M28EVK
Tested on PXA270 based Voipac PXA270.

NOTE: This currently only supports ARM, but other architectures
can be easily
added by defining bootz_setup().

I'll try to find a suitable fix.