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x86, amd: Kill misleading message about enablement of IO access to PCI ECS]

PATCH Jesse Barnes 1 participant 1 message Dec 5, 2011 1 message not in the archive PCI

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A message that is not in the archive (sent off-list or not yet received): [email protected]

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Yep, thanks. Applied.

Jesse

Quoted 60 lines · On Mon, 5 Dec 2011 18:12:28 +0100 Ingo Molnar <[email protected]> wrote:

i think this would be yours? Wrong Cc:s it appears.

I suspect the original 24d9b70b commit should have gone via the PCI tree too ...

Thanks,

Ingo

----- Forwarded message from Andreas Herrmann <[email protected]> -----

Date: Fri, 2 Dec 2011 08:27:53 +0100
From: Andreas Herrmann <[email protected]>
To: Thomas Gleixner <[email protected]>, Ingo Molnar <[email protected]>, "H. Peter Anvin"

	<[email protected]>

Cc: [email protected], Robert Richter <[email protected]>, Jan Beulich
<[email protected]>, Borislav Petkov <[email protected]>, Frank Arnold <[email protected]>
Subject: [PATCH] x86, amd: Kill misleading message about enablement of IO access to PCI ECS

From: Andreas Herrmann <[email protected]>

Commit 24d9b70b8c679264756a6980e668b96b3f964826 (x86: Use PCI method for enabling AMD extended config space before MSR method) added a message when IO access to PCI ECS was enabled via access to the NB_CFG PCI register. This can lead to a bogus message like

[    0.365177] Extended Config Space enabled on 0 nodes

which is misleading because IO ECS access is subsequently enabled for AMD CPUs (that support this) by modifying the corresponding NB_CFG MSR.

Furthermore it's not "Extended Config Space" that is enabled by this register setting. It's the IO access that is enabled for extended configruation space.

IMHO the ambiguous message needs to be cancelled.

Cc Jan Beulich <[email protected]>
Cc Robert Richter <[email protected]>
---
 arch/x86/pci/amd_bus.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)
arch/x86/pci/amd_bus.c +0 -1
index 026e493..7b7a897 100644
@@ -403,7 +403,6 @@ static void __init pci_enable_pci_io_ecs(void)
 			++n;
 		}
 	}
-	pr_info("Extended Config Space enabled on %u nodes\n", n);
 #endif
 }
 
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Jesse Barnes, Intel Open Source Technology Center