ARM: make head.S register assignments more convenient
PATCH 1/1 ARM: make head.S register assignments more convenient
The r1 (machine ID) and r2 (boot data pointer) values are getting in the way of standard procedure calls as those registers are normally clobbered by function calls. This is especially obnoxious when using the printascii et cie debugging routines.. This non-standard register allocation is even leaking into code far away from head.S i.e. the *_setup routines in mm/proc-*.S.
Move the machine ID / boot data pointer to r6 and r7 respectively, and adjust the surrounding/affected code accordingly.
Minor fixes to some comments are also included.
--- arch/arm/kernel/head-common.S | 101 +++++++++--------- arch/arm/kernel/head-nommu.S | 4 +- arch/arm/kernel/head.S | 207 ++++++++++++++++++----------------- arch/arm/mm/proc-arm1020.S | 8 +- arch/arm/mm/proc-arm1020e.S | 8 +- arch/arm/mm/proc-arm1022.S | 8 +- arch/arm/mm/proc-arm1026.S | 8 +- arch/arm/mm/proc-arm720.S | 16 ++-- arch/arm/mm/proc-arm920.S | 8 +- arch/arm/mm/proc-arm922.S | 8 +- arch/arm/mm/proc-arm925.S | 8 +- arch/arm/mm/proc-arm926.S | 6 +- arch/arm/mm/proc-feroceon.S | 8 +- arch/arm/mm/proc-mohawk.S | 8 +- arch/arm/mm/proc-sa110.S | 16 ++-- arch/arm/mm/proc-sa1100.S | 8 +- arch/arm/mm/proc-v6.S | 22 ++-- arch/arm/mm/proc-v7.S | 130 +++++++++++----------- arch/arm/mm/proc-xsc3.S | 10 +- arch/arm/mm/proc-xscale.S | 8 +- 20 files changed, 302 insertions(+), 298 deletions(-)
arch/arm/kernel/head-common.S +50 -51
@@ -32,38 +32,38 @@ */ __HEAD -/* Determine validity of the r2 atags pointer. The heuristic requires - * that the pointer be aligned, in the first 16k of physical RAM and +/* Determine validity of the r2 (now in r7) atags pointer. The heuristic + * requires that the pointer be aligned, in the first 16k of physical RAM and * that the ATAG_CORE marker is first and present. If CONFIG_OF_FLATTREE * is selected, then it will also accept a dtb pointer. Future revisions * of this function may be more lenient with the physical address and * may also be able to move the ATAGS block if necessary. * * Returns: - * r2 either valid atags pointer, valid dtb pointer, or zero - * r5, r6 corrupted + * r7 either valid atags pointer, valid dtb pointer, or zero + * r1, r5 corrupted */ __vet_atags: - tst r2, #0x3 @ aligned? + tst r7, #0x3 @ aligned? bne 1f - ldr r5, [r2, #0] + ldr r5, [r7, #0] #ifdef CONFIG_OF_FLATTREE - ldr r6, =OF_DT_MAGIC @ is it a DTB? - cmp r5, r6 + ldr r1, =OF_DT_MAGIC @ is it a DTB? + cmp r5, r1 beq 2f #endif cmp r5, #ATAG_CORE_SIZE @ is first tag ATAG_CORE? cmpne r5, #ATAG_CORE_SIZE_EMPTY bne 1f - ldr r5, [r2, #4] - ldr r6, =ATAG_CORE - cmp r5, r6 + ldr r5, [r7, #4] + ldr r1, =ATAG_CORE + cmp r5, r1 bne 1f 2: mov pc, lr @ atag/dtb pointer is ok -1: mov r2, #0 +1: mov r7, #0 mov pc, lr ENDPROC(__vet_atags)
@@ -72,48 +72,48 @@ ENDPROC(__vet_atags) * and uses absolute addresses; this is not position independent. * * r0 = cp#15 control register - * r1 = machine ID - * r2 = atags/dtb pointer + * r6 = machine ID + * r7 = atags/dtb pointer * r9 = processor ID */ __INIT __mmap_switched: adr r3, __mmap_switched_data - ldmia r3!, {r4, r5, r6, r7} - cmp r4, r5 @ Copy data segment if needed -1: cmpne r5, r6 - ldrne fp, [r4], #4 - strne fp, [r5], #4 + ldmia r3!, {r1, r2, r4, r5} + cmp r1, r2 @ Copy data segment if needed +1: cmpne r2, r4 + ldrne fp, [r1], #4 + strne fp, [r2], #4 bne 1b mov fp, #0 @ Clear BSS (and zero fp) -1: cmp r6, r7 - strcc fp, [r6],#4 +1: cmp r4, r5 + strcc fp, [r4], #4 bcc 1b - ARM( ldmia r3, {r4, r5, r6, r7, sp}) - THUMB( ldmia r3, {r4, r5, r6, r7} ) + ARM( ldmia r3, {r1, r2, r4, r5, sp}) + THUMB( ldmia r3, {r1, r2, r4, r5} ) THUMB( ldr sp, [r3, #16] ) - str r9, [r4] @ Save processor ID - str r1, [r5] @ Save machine type - str r2, [r6] @ Save atags pointer - bic r4, r0, #CR_A @ Clear 'A' bit - stmia r7, {r0, r4} @ Save control register values + str r9, [r1] @ Save processor ID + str r6, [r2] @ Save machine type + str r7, [r4] @ Save atags pointer + bic r1, r0, #CR_A @ Clear 'A' bit + stmia r5, {r0, r1} @ Save control register values b start_kernel ENDPROC(__mmap_switched) .align 2 .type __mmap_switched_data, %object __mmap_switched_data: - .long __data_loc @ r4 - .long _sdata @ r5 - .long __bss_start @ r6 - .long _end @ r7 - .long processor_id @ r4 - .long __machine_arch_type @ r5 - .long __atags_pointer @ r6 - .long cr_alignment @ r7 + .long __data_loc @ r1 + .long _sdata @ r2 + .long __bss_start @ r4 + .long _end @ r5 + .long processor_id @ r1 + .long __machine_arch_type @ r2 + .long __atags_pointer @ r4 + .long cr_alignment @ r5 .long init_thread_union + THREAD_START_SP @ sp .size __mmap_switched_data, . - __mmap_switched_data
@@ -121,11 +121,10 @@ __mmap_switched_data: * This provides a C-API version of __lookup_processor_type */ ENTRY(lookup_processor_type) - stmfd sp!, {r4 - r6, r9, lr} + stmfd sp!, {r9, lr} mov r9, r0 bl __lookup_processor_type - mov r0, r5 - ldmfd sp!, {r4 - r6, r9, pc} + ldmfd sp!, {r9, pc} ENDPROC(lookup_processor_type) /*
@@ -137,25 +136,25 @@ ENDPROC(lookup_processor_type) * * r9 = cpuid * Returns: - * r3, r4, r6 corrupted - * r5 = proc_info pointer in physical address space + * r1, r2, r3 corrupted + * r0 = proc_info pointer in physical address space * r9 = cpuid (preserved) */ __CPUINIT __lookup_processor_type: adr r3, __lookup_processor_type_data - ldmia r3, {r4 - r6} - sub r3, r3, r4 @ get offset between virt&phys - add r5, r5, r3 @ convert virt addresses to - add r6, r6, r3 @ physical address space -1: ldmia r5, {r3, r4} @ value, mask - and r4, r4, r9 @ mask wanted bits - teq r3, r4 + ldmia r3, {r0 - r2} + sub r3, r3, r0 @ get offset between virt&phys + add r0, r1, r3 @ convert virt addresses to + add r1, r2, r3 @ physical address space +1: ldmia r0, {r2, r3} @ value, mask + and r3, r3, r9 @ mask wanted bits + teq r2, r3 beq 2f - add r5, r5, #PROC_INFO_SZ @ sizeof(proc_info_list) - cmp r5, r6 + add r0, r0, #PROC_INFO_SZ @ sizeof(proc_info_list) + cmp r0, r1 blo 1b - mov r5, #0 @ unknown processor + mov r0, #0 @ unknown processor 2: mov pc, lr ENDPROC(__lookup_processor_type)
arch/arm/kernel/head-nommu.S +3 -1
@@ -44,13 +44,15 @@ ENTRY(stext) setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode @ and irqs disabled + mov r6, r1 @ preserve machine ID + mov r7, r2 @ preserve boot data pointer #ifndef CONFIG_CPU_CP15 ldr r9, =CONFIG_PROCESSOR_ID #else mrc p15, 0, r9, c0, c0 @ get processor id #endif bl __lookup_processor_type @ r5=procinfo r9=cpuid - movs r10, r5 @ invalid processor (r5=0)? + movs r10, r0 @ invalid processor (r5=0)? beq __error_p @ yes, error 'p' adr lr, BSYM(__after_proc_init) @ return (PIC) address
arch/arm/kernel/head.S +105 -102
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arch/arm/mm/proc-arm1020.S +4 -4
@@ -447,11 +447,11 @@ __arm1020_setup: mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 #endif - adr r5, arm1020_crval - ldmia r5, {r5, r6} + adr r2, arm1020_crval + ldmia r2, {r2, r3} mrc p15, 0, r0, c1, c0 @ get control register v4 - bic r0, r0, r5 - orr r0, r0, r6 + bic r0, r0, r2 + orr r0, r0, r3 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN orr r0, r0, #0x4000 @ .R.. .... .... .... #endif
arch/arm/mm/proc-arm1020e.S +4 -4
@@ -428,11 +428,11 @@ __arm1020e_setup: #ifdef CONFIG_MMU mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 #endif - adr r5, arm1020e_crval - ldmia r5, {r5, r6} + adr r2, arm1020e_crval + ldmia r2, {r2, r3} mrc p15, 0, r0, c1, c0 @ get control register v4 - bic r0, r0, r5 - orr r0, r0, r6 + bic r0, r0, r2 + orr r0, r0, r3 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN orr r0, r0, #0x4000 @ .R.. .... .... .... #endif
arch/arm/mm/proc-arm1022.S +4 -4
@@ -410,11 +410,11 @@ __arm1022_setup: #ifdef CONFIG_MMU mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 #endif - adr r5, arm1022_crval - ldmia r5, {r5, r6} + adr r2, arm1022_crval + ldmia r2, {r2, r3} mrc p15, 0, r0, c1, c0 @ get control register v4 - bic r0, r0, r5 - orr r0, r0, r6 + bic r0, r0, r2 + orr r0, r0, r3 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN orr r0, r0, #0x4000 @ .R.............. #endif
arch/arm/mm/proc-arm1026.S +4 -4
@@ -405,11 +405,11 @@ __arm1026_setup: mov r0, #4 @ explicitly disable writeback mcr p15, 7, r0, c15, c0, 0 #endif - adr r5, arm1026_crval - ldmia r5, {r5, r6} + adr r2, arm1026_crval + ldmia r2, {r2, r3} mrc p15, 0, r0, c1, c0 @ get control register v4 - bic r0, r0, r5 - orr r0, r0, r6 + bic r0, r0, r2 + orr r0, r0, r3 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN orr r0, r0, #0x4000 @ .R.. .... .... .... #endif
arch/arm/mm/proc-arm720.S +8 -8
@@ -123,10 +123,10 @@ __arm710_setup: mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) #endif mrc p15, 0, r0, c1, c0 @ get control register - ldr r5, arm710_cr1_clear - bic r0, r0, r5 - ldr r5, arm710_cr1_set - orr r0, r0, r5 + ldr r2, arm710_cr1_clear + bic r0, r0, r2 + ldr r2, arm710_cr1_set + orr r0, r0, r2 mov pc, lr @ __ret (head.S) .size __arm710_setup, . - __arm710_setup
@@ -150,11 +150,11 @@ __arm720_setup: #ifdef CONFIG_MMU mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) #endif - adr r5, arm720_crval - ldmia r5, {r5, r6} + adr r2, arm720_crval + ldmia r2, {r2, r3} mrc p15, 0, r0, c1, c0 @ get control register - bic r0, r0, r5 - orr r0, r0, r6 + bic r0, r0, r2 + orr r0, r0, r3 mov pc, lr @ __ret (head.S) .size __arm720_setup, . - __arm720_setup
arch/arm/mm/proc-arm920.S +4 -4
@@ -413,11 +413,11 @@ __arm920_setup: #ifdef CONFIG_MMU mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 #endif - adr r5, arm920_crval - ldmia r5, {r5, r6} + adr r2, arm920_crval + ldmia r2, {r2, r3} mrc p15, 0, r0, c1, c0 @ get control register v4 - bic r0, r0, r5 - orr r0, r0, r6 + bic r0, r0, r2 + orr r0, r0, r3 mov pc, lr .size __arm920_setup, . - __arm920_setup
arch/arm/mm/proc-arm922.S +4 -4
@@ -391,11 +391,11 @@ __arm922_setup: #ifdef CONFIG_MMU mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 #endif - adr r5, arm922_crval - ldmia r5, {r5, r6} + adr r2, arm922_crval + ldmia r2, {r2, r3} mrc p15, 0, r0, c1, c0 @ get control register v4 - bic r0, r0, r5 - orr r0, r0, r6 + bic r0, r0, r2 + orr r0, r0, r3 mov pc, lr .size __arm922_setup, . - __arm922_setup
arch/arm/mm/proc-arm925.S +4 -4
@@ -456,11 +456,11 @@ __arm925_setup: mcr p15, 7, r0, c15, c0, 0 #endif - adr r5, arm925_crval - ldmia r5, {r5, r6} + adr r2, arm925_crval + ldmia r2, {r2, r3} mrc p15, 0, r0, c1, c0 @ get control register v4 - bic r0, r0, r5 - orr r0, r0, r6 + bic r0, r0, r2 + orr r0, r0, r3 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN orr r0, r0, #0x4000 @ .1.. .... .... .... #endif
arch/arm/mm/proc-arm926.S +3 -3
@@ -436,10 +436,10 @@ __arm926_setup: #endif adr r5, arm926_crval - ldmia r5, {r5, r6} + ldmia r2, {r2, r3} mrc p15, 0, r0, c1, c0 @ get control register v4 - bic r0, r0, r5 - orr r0, r0, r6 + bic r0, r0, r2 + orr r0, r0, r3 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN orr r0, r0, #0x4000 @ .1.. .... .... .... #endif
arch/arm/mm/proc-feroceon.S +4 -4
@@ -517,11 +517,11 @@ __feroceon_setup: mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 #endif - adr r5, feroceon_crval - ldmia r5, {r5, r6} + adr r2, feroceon_crval + ldmia r2, {r2, r3} mrc p15, 0, r0, c1, c0 @ get control register v4 - bic r0, r0, r5 - orr r0, r0, r6 + bic r0, r0, r2 + orr r0, r0, r3 mov pc, lr .size __feroceon_setup, . - __feroceon_setup
arch/arm/mm/proc-mohawk.S +4 -4
@@ -355,11 +355,11 @@ __mohawk_setup: mov r0, #0 @ don't allow CP access mcr p15, 0, r0, c15, c1, 0 @ write CP access register - adr r5, mohawk_crval - ldmia r5, {r5, r6} + adr r2, mohawk_crval + ldmia r2, {r2, r3} mrc p15, 0, r0, c1, c0 @ get control register - bic r0, r0, r5 - orr r0, r0, r6 + bic r0, r0, r2 + orr r0, r0, r3 mov pc, lr .size __mohawk_setup, . - __mohawk_setup
arch/arm/mm/proc-sa110.S +8 -8
@@ -160,18 +160,18 @@ ENTRY(cpu_sa110_set_pte_ext) .type __sa110_setup, #function __sa110_setup: - mov r10, #0 - mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4 - mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4 + mov r0, #0 + mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 + mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 #ifdef CONFIG_MMU - mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4 + mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 #endif - adr r5, sa110_crval - ldmia r5, {r5, r6} + adr r2, sa110_crval + ldmia r2, {r2, r3} mrc p15, 0, r0, c1, c0 @ get control register v4 - bic r0, r0, r5 - orr r0, r0, r6 + bic r0, r0, r2 + orr r0, r0, r3 mov pc, lr .size __sa110_setup, . - __sa110_setup
arch/arm/mm/proc-sa1100.S +4 -4
@@ -205,11 +205,11 @@ __sa1100_setup: #ifdef CONFIG_MMU mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 #endif - adr r5, sa1100_crval - ldmia r5, {r5, r6} + adr r2, sa1100_crval + ldmia r2, {r2, r3} mrc p15, 0, r0, c1, c0 @ get control register v4 - bic r0, r0, r5 - orr r0, r0, r6 + bic r0, r0, r2 + orr r0, r0, r3 mov pc, lr .size __sa1100_setup, . - __sa1100_setup
arch/arm/mm/proc-v6.S +11 -11
@@ -209,14 +209,14 @@ __v6_setup: ALT_UP(orr r8, r8, #TTB_FLAGS_UP) mcr p15, 0, r8, c2, c0, 1 @ load TTB1 #endif /* CONFIG_MMU */ - adr r5, v6_crval - ldmia r5, {r5, r6} + adr r2, v6_crval + ldmia r2, {r2, r3} #ifdef CONFIG_CPU_ENDIAN_BE8 - orr r6, r6, #1 << 25 @ big-endian page tables + orr r3, r3, #1 << 25 @ big-endian page tables #endif mrc p15, 0, r0, c1, c0, 0 @ read control register - bic r0, r0, r5 @ clear bits them - orr r0, r0, r6 @ set them + bic r0, r0, r2 @ clear bits them + orr r0, r0, r3 @ set them #ifdef CONFIG_ARM_ERRATA_364296 /* * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
@@ -225,12 +225,12 @@ __v6_setup: * and the FI bit in the control register) disables hit-under-miss * without putting the processor into full low interrupt latency mode. */ - ldr r6, =0x4107b362 @ id for ARM1136 r0p2 - mrc p15, 0, r5, c0, c0, 0 @ get processor id - teq r5, r6 @ check for the faulty core - mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg - orreq r5, r5, #(1 << 31) @ set the undocumented bit 31 - mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg + ldr r3, =0x4107b362 @ id for ARM1136 r0p2 + mrc p15, 0, r2, c0, c0, 0 @ get processor id + teq r2, r3 @ check for the faulty core + mrceq p15, 0, r2, c1, c0, 1 @ load aux control reg + orreq r2, r2, #(1 << 31) @ set the undocumented bit 31 + mcreq p15, 0, r2, c1, c0, 1 @ write aux control reg orreq r0, r0, #(1 << 21) @ low interrupt latency configuration #endif mov pc, lr @ return to head.S:__ret
arch/arm/mm/proc-v7.S +65 -65
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arch/arm/mm/proc-xsc3.S +5 -5
@@ -461,18 +461,18 @@ __xsc3_setup: orr r0, r0, #(1 << 10) @ enable L2 for LLR cache mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg - adr r5, xsc3_crval - ldmia r5, {r5, r6} + adr r2, xsc3_crval + ldmia r2, {r2, r3} #ifdef CONFIG_CACHE_XSC3L2 mrc p15, 1, r0, c0, c0, 1 @ get L2 present information ands r0, r0, #0xf8 - orrne r6, r6, #(1 << 26) @ enable L2 if present + orrne r3, r3, #(1 << 26) @ enable L2 if present #endif mrc p15, 0, r0, c1, c0, 0 @ get control register - bic r0, r0, r5 @ ..V. ..R. .... ..A. - orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu) + bic r0, r0, r2 @ ..V. ..R. .... ..A. + orr r0, r0, r3 @ ..VI Z..S .... .C.M (mmu) @ ...I Z..S .... .... (uc) mov pc, lr
arch/arm/mm/proc-xscale.S +4 -4
@@ -562,11 +562,11 @@ __xscale_setup: orr r0, r0, #1 << 13 @ Its undefined whether this mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes - adr r5, xscale_crval - ldmia r5, {r5, r6} + adr r2, xscale_crval + ldmia r2, {r2, r3} mrc p15, 0, r0, c1, c0, 0 @ get control register - bic r0, r0, r5 - orr r0, r0, r6 + bic r0, r0, r2 + orr r0, r0, r3 mov pc, lr .size __xscale_setup, . - __xscale_setup
PATCH 1/1 ARM: make head.S register assignments more convenient
Quoted 28 lines · Nicolas Pitre
The r1 (machine ID) and r2 (boot data pointer) values are getting in the way of standard procedure calls as those registers are normally clobbered by function calls. This is especially obnoxious when using the printascii et cie debugging routines.. This non-standard register allocation is even leaking into code far away from
head.Si.e. the*_setuproutines inmm/proc-*.S.Move the machine ID / boot data pointer to r6 and r7 respectively, and adjust the surrounding/affected code accordingly.
Minor fixes to some comments are also included.
Signed-off-by Nicolas Pitre <[email protected]>--- arch/arm/kernel/head-common.S | 101 +++++++++--------- arch/arm/kernel/head-nommu.S | 4 +- arch/arm/kernel/head.S | 207 ++++++++++++++++++----------------- arch/arm/mm/proc-arm1020.S | 8 +- arch/arm/mm/proc-arm1020e.S | 8 +- arch/arm/mm/proc-arm1022.S | 8 +- arch/arm/mm/proc-arm1026.S | 8 +- arch/arm/mm/proc-arm720.S | 16 ++-- arch/arm/mm/proc-arm920.S | 8 +- arch/arm/mm/proc-arm922.S | 8 +- arch/arm/mm/proc-arm925.S | 8 +- arch/arm/mm/proc-arm926.S | 6 +- arch/arm/mm/proc-feroceon.S | 8 +-
Quoted 8 lines
arch/arm/mm/proc-mohawk.S | 8 +- arch/arm/mm/proc-sa110.S | 16 ++-- arch/arm/mm/proc-sa1100.S | 8 +- arch/arm/mm/proc-v6.S | 22 ++-- arch/arm/mm/proc-v7.S | 130 +++++++++++----------- arch/arm/mm/proc-xsc3.S | 10 +- arch/arm/mm/proc-xscale.S | 8 +- 20 files changed, 302 insertions(+), 298 deletions(-)
Is it also worth changing the other proc-*.S setup rountines to be PCS compliant too? This would clean up the calling convention further, and help avoid future sutprises.
Cheers
---Dave
PATCH 1/1 ARM: make head.S register assignments more convenient
Quoted 3 lines · Dave Martin
Is it also worth changing the other proc-*.S setup rountines to be PCS compliant too? This would clean up the calling convention further, and help avoid future sutprises.
They _aren't_ PCS functions in any case. They don't have a stack available to them. So, having them as non-PCS functions reinforces the fact that they _are_ special.
PATCH 1/1 ARM: make head.S register assignments more convenient
Quoted 8 lines · Russell King - ARM Linux
Quoted 3 lines · Dave Martin
Is it also worth changing the other proc-*.S setup rountines to be PCS compliant too? This would clean up the calling convention further, and help avoid future sutprises.
They _aren't_ PCS functions in any case. They don't have a stack available to them. So, having them as non-PCS functions reinforces the fact that they _are_ special.
Fair point.
Maybe a brief note in the commit message explaining why only certain proc-*.S files are touched would be belpful. But it's not vital.
Cheers
---Dave
PATCH 1/1 ARM: make head.S register assignments more convenient
Quoted 6 lines · Dave Martin
Quoted 5 lines · Russell King - ARM Linux
Quoted 3 lines · Dave Martin
Is it also worth changing the other proc-*.S setup rountines to be PCS compliant too? This would clean up the calling convention further, and help avoid future sutprises.
Quoted 8 lines
Quoted 3 lines
They _aren't_ PCS functions in any case. They don't have a stack available to them. So, having them as non-PCS functions reinforces the fact that they _are_ special.
Fair point.
Maybe a brief note in the commit message explaining why only certain proc-*.S files are touched would be belpful. But it's not vital.
They are touched only because they were using registers where I moved the previous r1 and r2 values to. So I moved their usage of mainly r5-r6 to the normally callee clobbered registers. I don't think there is further changes that would be as badly needed as those I did.
Nicolas
PATCH 1/1 ARM: make head.S register assignments more convenient
Quoted 14 lines · Nicolas Pitre
Quoted 12 lines · Dave Martin
Quoted 8 lines · Russell King - ARM Linux
Quoted 3 lines · Dave Martin
Is it also worth changing the other proc-*.S setup rountines to be PCS compliant too? This would clean up the calling convention further, and help avoid future sutprises.
They _aren't_ PCS functions in any case. They don't have a stack available to them. So, having them as non-PCS functions reinforces the fact that they _are_ special.
Fair point.
Quoted 7 lines
Quoted 2 lines
Maybe a brief note in the commit message explaining why only certain proc-*.S files are touched would be belpful. But it's not vital.
They are touched only because they were using registers where I moved the previous r1 and r2 values to. So I moved their usage of mainly r5-r6 to the normally callee clobbered registers. I don't think there is further changes that would be as badly needed as those I did.
Fair enough
---Dave