ARM: pl2x0/pl310: Refactor Kconfig to be more maintainable

PATCH New Dave Martin 5 participants 14 messages Nov 29, 2011 – Dec 13, 2011

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Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape Arm Samsung Exynos +2 more subsystems

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Dave Martin

author

2011-11-29 16:32 UTC #0 lore raw

PATCH 1/1 ARM: pl2x0/pl310: Refactor Kconfig to be more maintainable

Making CACHE_L2X0 depends on (huge list of MACH_ and ARCH_ configs) is bothersome to maintain and likely to lead to merge conflicts.

This patch moves the knowledge of which platforms have a L2x0 or PL310 cache controller to the individual machines. To enable this, a new HAVE_L2X0_L2CC config option is introduced to allow machines to indicate that they have such a cache controller independently of each other.

Signed-off-by Dave Martin <[email protected]>

---
 arch/arm/Kconfig               |    8 ++++++++
 arch/arm/mach-exynos/Kconfig   |    1 +
 arch/arm/mach-omap2/Kconfig    |    1 +
 arch/arm/mach-realview/Kconfig |    5 +++++
 arch/arm/mach-vexpress/Kconfig |    1 +
 arch/arm/mm/Kconfig            |   13 ++++++++-----
 arch/arm/plat-mxc/Kconfig      |    1 +
 7 files changed, 25 insertions(+), 5 deletions(-)

arch/arm/Kconfig +8 -0

index 44789ef..4068fe5 100644
@@ -339,6 +339,7 @@ config ARCH_HIGHBANK
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_AMBA
 	select ARM_GIC
+	select HAVE_L2X0_L2CC
 	select ARM_TIMER_SP804
 	select CLKDEV_LOOKUP
 	select CPU_V7

@@ -359,6 +360,7 @@ config ARCH_CLPS711X
 config ARCH_CNS3XXX
 	bool "Cavium Networks CNS3XXX family"
 	select CPU_V6K
+	select HAVE_L2X0_L2CC
 	select GENERIC_CLOCKEVENTS
 	select ARM_GIC
 	select MIGHT_HAVE_PCI

@@ -377,6 +379,7 @@ config ARCH_GEMINI
 config ARCH_PRIMA2
 	bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
 	select CPU_V7
+	select HAVE_L2X0_L2CC
 	select NO_IOPORT
 	select GENERIC_CLOCKEVENTS
 	select CLKDEV_LOOKUP

@@ -627,6 +630,7 @@ config ARCH_W90X900
 
 config ARCH_TEGRA
 	bool "NVIDIA Tegra"
+	select HAVE_L2X0_L2CC
 	select CLKDEV_LOOKUP
 	select CLKSRC_MMIO
 	select GENERIC_CLOCKEVENTS

@@ -699,6 +703,7 @@ config ARCH_MSM
 
 config ARCH_SHMOBILE
 	bool "Renesas SH-Mobile / R-Mobile"
+	select HAVE_L2X0_L2CC
 	select HAVE_CLK
 	select CLKDEV_LOOKUP
 	select HAVE_MACH_CLKDEV

@@ -900,6 +905,7 @@ config ARCH_U8500
 	bool "ST-Ericsson U8500 Series"
 	select CPU_V7
 	select ARM_AMBA
+	select HAVE_L2X0_L2CC
 	select GENERIC_CLOCKEVENTS
 	select CLKDEV_LOOKUP
 	select ARCH_REQUIRE_GPIOLIB

@@ -912,6 +918,7 @@ config ARCH_NOMADIK
 	select ARM_AMBA
 	select ARM_VIC
 	select CPU_ARM926T
+	select HAVE_L2X0_L2CC
 	select CLKDEV_LOOKUP
 	select GENERIC_CLOCKEVENTS
 	select ARCH_REQUIRE_GPIOLIB

@@ -968,6 +975,7 @@ config ARCH_VT8500
 config ARCH_ZYNQ
 	bool "Xilinx Zynq ARM Cortex A9 Platform"
 	select CPU_V7
+	select HAVE_L2X0_L2CC
 	select GENERIC_CLOCKEVENTS
 	select CLKDEV_LOOKUP
 	select ARM_GIC

arch/arm/mach-exynos/Kconfig +1 -0

index 724ec0f..b3eb318 100644
@@ -17,6 +17,7 @@ choice
 
 config ARCH_EXYNOS4
 	bool "SAMSUNG EXYNOS4"
+	select HAVE_L2X0_L2CC
 	help
 	  Samsung EXYNOS4 SoCs based systems

arch/arm/mach-omap2/Kconfig +1 -0

index 5034147..f4e7e6a 100644
@@ -44,6 +44,7 @@ config ARCH_OMAP4
 	select CPU_V7
 	select ARM_GIC
 	select LOCAL_TIMERS if SMP
+	select HAVE_L2X0_L2CC
 	select PL310_ERRATA_588369
 	select PL310_ERRATA_727915
 	select ARM_ERRATA_720789

arch/arm/mach-realview/Kconfig +5 -0

index dba6d0c..3dfd6b8 100644
@@ -12,6 +12,7 @@ config REALVIEW_EB_A9MP
 	bool "Support Multicore Cortex-A9 Tile"
 	depends on MACH_REALVIEW_EB
 	select CPU_V7
+	select HAVE_L2X0_L2CC
 	help
 	  Enable support for the Cortex-A9MPCore tile fitted to the
 	  Realview(R) Emulation Baseboard platform.

@@ -20,6 +21,7 @@ config REALVIEW_EB_ARM11MP
 	bool "Support ARM11MPCore Tile"
 	depends on MACH_REALVIEW_EB
 	select CPU_V6K
+	select HAVE_L2X0_L2CC
 	select ARCH_HAS_BARRIERS if SMP
 	help
 	  Enable support for the ARM11MPCore tile fitted to the Realview(R)

@@ -38,6 +40,7 @@ config MACH_REALVIEW_PB11MP
 	bool "Support RealView(R) Platform Baseboard for ARM11MPCore"
 	select CPU_V6K
 	select ARM_GIC
+	select HAVE_L2X0_L2CC
 	select HAVE_PATA_PLATFORM
 	select ARCH_HAS_BARRIERS if SMP
 	help

@@ -50,6 +53,7 @@ config MACH_REALVIEW_PB1176
 	bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S"
 	select CPU_V6
 	select ARM_GIC
+	select HAVE_L2X0_L2CC
 	select HAVE_TCM
 	help
 	  Include support for the ARM(R) RealView(R) Platform Baseboard for

@@ -77,6 +81,7 @@ config MACH_REALVIEW_PBA8
 config MACH_REALVIEW_PBX
 	bool "Support RealView(R) Platform Baseboard Explore"
 	select ARM_GIC
+	select HAVE_L2X0_L2CC
 	select HAVE_PATA_PLATFORM
 	select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
 	select ZONE_DMA if SPARSEMEM

arch/arm/mach-vexpress/Kconfig +1 -0

index 9311484..78d4f28 100644
@@ -5,6 +5,7 @@ config ARCH_VEXPRESS_CA9X4
 	bool "Versatile Express Cortex-A9x4 tile"
 	select CPU_V7
 	select ARM_GIC
+	select HAVE_L2X0_L2CC
 	select ARM_ERRATA_720789
 	select ARM_ERRATA_751472
 	select ARM_ERRATA_753970

arch/arm/mm/Kconfig +8 -5

index 67f75a0..bb743df 100644
@@ -816,13 +816,16 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 	  Say Y here to use the Feroceon L2 cache in writethrough mode.
 	  Unless you specifically require this, say N for writeback mode.
 
+config HAVE_L2X0_L2CC
+	bool
+	default n
+	help
+	  This option should be selected by machines which have a L2x0
+	  or PL310 cache controller.
+
 config CACHE_L2X0
 	bool "Enable the L2x0 outer cache controller"
-	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-		   REALVIEW_EB_A9MP || ARCH_IMX_V6_V7 || MACH_REALVIEW_PBX || \
-		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
-		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
-		   ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_HIGHBANK
+	depends on HAVE_L2X0_L2CC
 	default y
 	select OUTER_CACHE
 	select OUTER_CACHE_SYNC

arch/arm/plat-mxc/Kconfig +1 -0

index b3a1f2b..6871ed7 100644
@@ -20,6 +20,7 @@ config ARCH_IMX_V6_V7
 	bool "i.MX3, i.MX6"
 	select AUTO_ZRELADDR if !ZBOOT_ROM
 	select ARM_PATCH_PHYS_VIRT
+	select HAVE_L2X0_L2CC
 	help
 	  This enables support for systems based on the Freescale i.MX3 and i.MX6
 	  family.

Signature · 1 line

1.7.4.1

Rob Herring

2011-11-29 19:25 UTC #1 lore raw

PATCH 1/1 ARM: pl2x0/pl310: Refactor Kconfig to be more maintainable

Quoted 25 lines · Dave Martin

Making CACHE_L2X0 depends on (huge list of MACH_ and ARCH_ configs) is bothersome to maintain and likely to lead to merge conflicts.
This patch moves the knowledge of which platforms have a L2x0 or PL310 cache controller to the individual machines. To enable this, a new HAVE_L2X0_L2CC config option is introduced to allow machines to indicate that they have such a cache controller independently of each other.
Signed-off-by Dave Martin <[email protected]>
---
 arch/arm/Kconfig               |    8 ++++++++
 arch/arm/mach-exynos/Kconfig   |    1 +
 arch/arm/mach-omap2/Kconfig    |    1 +
 arch/arm/mach-realview/Kconfig |    5 +++++
 arch/arm/mach-vexpress/Kconfig |    1 +
 arch/arm/mm/Kconfig            |   13 ++++++++-----
 arch/arm/plat-mxc/Kconfig      |    1 +
 7 files changed, 25 insertions(+), 5 deletions(-)
arch/arm/Kconfig +0 -0
index 44789ef..4068fe5 100644

arch/arm/Kconfig config ARCH_HIGHBANK · line 345

Quoted 7 lines

arch/arm/Kconfig +1 -0

@@ -339,6 +339,7 @@ config ARCH_HIGHBANK
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_AMBA
 	select ARM_GIC
+	select HAVE_L2X0_L2CC
 	select ARM_TIMER_SP804
 	select CLKDEV_LOOKUP
 	select CPU_V7

These entries are sorted per rmk's review, so please keep it that way.

arch/arm/Kconfig config ARCH_CLPS711X · line 366

Quoted 8 lines

arch/arm/Kconfig +1 -0

@@ -359,6 +360,7 @@ config ARCH_CLPS711X
 config ARCH_CNS3XXX
 	bool "Cavium Networks CNS3XXX family"
 	select CPU_V6K
+	select HAVE_L2X0_L2CC
 	select GENERIC_CLOCKEVENTS
 	select ARM_GIC
 	select MIGHT_HAVE_PCI

But as you can see, that's rarely the case...

Quoted 133 lines

arch/arm/Kconfig +6 -0

@@ -377,6 +379,7 @@ config ARCH_GEMINI
 config ARCH_PRIMA2
 	bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
 	select CPU_V7
+	select HAVE_L2X0_L2CC
 	select NO_IOPORT
 	select GENERIC_CLOCKEVENTS
 	select CLKDEV_LOOKUP

@@ -627,6 +630,7 @@ config ARCH_W90X900
 
 config ARCH_TEGRA
 	bool "NVIDIA Tegra"
+	select HAVE_L2X0_L2CC
 	select CLKDEV_LOOKUP
 	select CLKSRC_MMIO
 	select GENERIC_CLOCKEVENTS

@@ -699,6 +703,7 @@ config ARCH_MSM
 
 config ARCH_SHMOBILE
 	bool "Renesas SH-Mobile / R-Mobile"
+	select HAVE_L2X0_L2CC
 	select HAVE_CLK
 	select CLKDEV_LOOKUP
 	select HAVE_MACH_CLKDEV

@@ -900,6 +905,7 @@ config ARCH_U8500
 	bool "ST-Ericsson U8500 Series"
 	select CPU_V7
 	select ARM_AMBA
+	select HAVE_L2X0_L2CC
 	select GENERIC_CLOCKEVENTS
 	select CLKDEV_LOOKUP
 	select ARCH_REQUIRE_GPIOLIB

@@ -912,6 +918,7 @@ config ARCH_NOMADIK
 	select ARM_AMBA
 	select ARM_VIC
 	select CPU_ARM926T
+	select HAVE_L2X0_L2CC
 	select CLKDEV_LOOKUP
 	select GENERIC_CLOCKEVENTS
 	select ARCH_REQUIRE_GPIOLIB

@@ -968,6 +975,7 @@ config ARCH_VT8500
 config ARCH_ZYNQ
 	bool "Xilinx Zynq ARM Cortex A9 Platform"
 	select CPU_V7
+	select HAVE_L2X0_L2CC
 	select GENERIC_CLOCKEVENTS
 	select CLKDEV_LOOKUP
 	select ARM_GIC

arch/arm/mach-exynos/Kconfig +1 -0

index 724ec0f..b3eb318 100644
@@ -17,6 +17,7 @@ choice
 
 config ARCH_EXYNOS4
 	bool "SAMSUNG EXYNOS4"
+	select HAVE_L2X0_L2CC
 	help
 	  Samsung EXYNOS4 SoCs based systems

arch/arm/mach-omap2/Kconfig +1 -0

index 5034147..f4e7e6a 100644
@@ -44,6 +44,7 @@ config ARCH_OMAP4
 	select CPU_V7
 	select ARM_GIC
 	select LOCAL_TIMERS if SMP
+	select HAVE_L2X0_L2CC
 	select PL310_ERRATA_588369
 	select PL310_ERRATA_727915
 	select ARM_ERRATA_720789

arch/arm/mach-realview/Kconfig +5 -0

index dba6d0c..3dfd6b8 100644
@@ -12,6 +12,7 @@ config REALVIEW_EB_A9MP
 	bool "Support Multicore Cortex-A9 Tile"
 	depends on MACH_REALVIEW_EB
 	select CPU_V7
+	select HAVE_L2X0_L2CC
 	help
 	  Enable support for the Cortex-A9MPCore tile fitted to the
 	  Realview(R) Emulation Baseboard platform.

@@ -20,6 +21,7 @@ config REALVIEW_EB_ARM11MP
 	bool "Support ARM11MPCore Tile"
 	depends on MACH_REALVIEW_EB
 	select CPU_V6K
+	select HAVE_L2X0_L2CC
 	select ARCH_HAS_BARRIERS if SMP
 	help
 	  Enable support for the ARM11MPCore tile fitted to the Realview(R)

@@ -38,6 +40,7 @@ config MACH_REALVIEW_PB11MP
 	bool "Support RealView(R) Platform Baseboard for ARM11MPCore"
 	select CPU_V6K
 	select ARM_GIC
+	select HAVE_L2X0_L2CC
 	select HAVE_PATA_PLATFORM
 	select ARCH_HAS_BARRIERS if SMP
 	help

@@ -50,6 +53,7 @@ config MACH_REALVIEW_PB1176
 	bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S"
 	select CPU_V6
 	select ARM_GIC
+	select HAVE_L2X0_L2CC
 	select HAVE_TCM
 	help
 	  Include support for the ARM(R) RealView(R) Platform Baseboard for

@@ -77,6 +81,7 @@ config MACH_REALVIEW_PBA8
 config MACH_REALVIEW_PBX
 	bool "Support RealView(R) Platform Baseboard Explore"
 	select ARM_GIC
+	select HAVE_L2X0_L2CC
 	select HAVE_PATA_PLATFORM
 	select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
 	select ZONE_DMA if SPARSEMEM

arch/arm/mach-vexpress/Kconfig +1 -0

index 9311484..78d4f28 100644
@@ -5,6 +5,7 @@ config ARCH_VEXPRESS_CA9X4
 	bool "Versatile Express Cortex-A9x4 tile"
 	select CPU_V7
 	select ARM_GIC
+	select HAVE_L2X0_L2CC
 	select ARM_ERRATA_720789
 	select ARM_ERRATA_751472
 	select ARM_ERRATA_753970

arch/arm/mm/Kconfig +0 -0

index 67f75a0..bb743df 100644

arch/arm/mm/Kconfig config CACHE_FEROCEON_L2_WRITETHROUGH · line 821

Quoted 6 lines

arch/arm/mm/Kconfig +3 -0

@@ -816,13 +816,16 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 	  Say Y here to use the Feroceon L2 cache in writethrough mode.
 	  Unless you specifically require this, say N for writeback mode.
 
+config HAVE_L2X0_L2CC
+	bool
+	default n

n is the default already.

arch/arm/mm/Kconfig config CACHE_FEROCEON_L2_WRITETHROUGH · line 828

Quoted 12 lines

arch/arm/mm/Kconfig +5 -5

+	help
+	  This option should be selected by machines which have a L2x0
+	  or PL310 cache controller.
+
 config CACHE_L2X0
 	bool "Enable the L2x0 outer cache controller"
-	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-		   REALVIEW_EB_A9MP || ARCH_IMX_V6_V7 || MACH_REALVIEW_PBX || \
-		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
-		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
-		   ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_HIGHBANK
+	depends on HAVE_L2X0_L2CC

For platforms that run in non-secure mode, this shouldn't really be a user selectable option. Perhaps those should just select CACHE_L2X0 directly. I'm not sure which one's those are other than Highbank and OMAP4.

Rob

Russell King - ARM Linux

2011-11-29 22:18 UTC #2 lore raw

PATCH 1/1 ARM: pl2x0/pl310: Refactor Kconfig to be more maintainable

Quoted 1 line · Rob Herring

But as you can see, that's rarely the case...

That's because I don't always catch them anymore.

It's something that does need sorting out though, because it makes conflict resolution harder to just have people appending to the end. With a sorting order in place, it helps spread the additions and so reduce the conflicts.

Dave Martin

author

2011-12-06 16:26 UTC #3 lore raw

PATCH 1/1 ARM: pl2x0/pl310: Refactor Kconfig to be more maintainable

In reply to Rob Herring

Quoted 21 lines · Rob Herring

Quoted 20 lines · Dave Martin
Making CACHE_L2X0 depends on (huge list of MACH_ and ARCH_ configs) is bothersome to maintain and likely to lead to merge conflicts.
This patch moves the knowledge of which platforms have a L2x0 or PL310 cache controller to the individual machines. To enable this, a new HAVE_L2X0_L2CC config option is introduced to allow machines to indicate that they have such a cache controller independently of each other.
Signed-off-by Dave Martin <[email protected]>
---
 arch/arm/Kconfig               |    8 ++++++++
 arch/arm/mach-exynos/Kconfig   |    1 +
 arch/arm/mach-omap2/Kconfig    |    1 +
 arch/arm/mach-realview/Kconfig |    5 +++++
 arch/arm/mach-vexpress/Kconfig |    1 +
 arch/arm/mm/Kconfig            |   13 ++++++++-----
 arch/arm/plat-mxc/Kconfig      |    1 +
 7 files changed, 25 insertions(+), 5 deletions(-)

Quoted 14 lines

arch/arm/Kconfig config ARCH_HIGHBANK · line 345
Quoted 12 lines
arch/arm/Kconfig +1 -0
index 44789ef..4068fe5 100644
@@ -339,6 +339,7 @@ config ARCH_HIGHBANK
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_AMBA
 	select ARM_GIC
+	select HAVE_L2X0_L2CC
 	select ARM_TIMER_SP804
 	select CLKDEV_LOOKUP
 	select CPU_V7
These entries are sorted per rmk's review, so please keep it that way.

Can you explain what order they should be in? Alphabetical?

Quoted 11 lines

arch/arm/Kconfig config ARCH_CLPS711X · line 366
Quoted 9 lines
arch/arm/Kconfig +1 -0
@@ -359,6 +360,7 @@ config ARCH_CLPS711X
 config ARCH_CNS3XXX
 	bool "Cavium Networks CNS3XXX family"
 	select CPU_V6K
+	select HAVE_L2X0_L2CC
 	select GENERIC_CLOCKEVENTS
 	select ARM_GIC
 	select MIGHT_HAVE_PCI
But as you can see, that's rarely the case...

Do you mean "things are not always in alphabetical order?"

Apologies if I'm being obtuse -- your comments are rather terse for me.

[...]

Quoted 5 lines

arch/arm/Kconfig
Quoted 3 lines
arch/arm/Kconfig +3 -0
+config HAVE_L2X0_L2CC
+	bool
+	default n
n is the default already.

Good point -- I'll kill that.

Quoted 8 lines

arch/arm/Kconfig +4 -2

+	help
+	  This option should be selected by machines which have a L2x0
+	  or PL310 cache controller.
+
 config CACHE_L2X0
 	bool "Enable the L2x0 outer cache controller"
-	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-		   REALVIEW_EB_A9MP || ARCH_IMX_V6_V7 || MACH_REALVIEW_PBX || \

Quoted 8 lines

arch/arm/Kconfig
Quoted 4 lines
arch/arm/Kconfig +1 -3
-		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
-		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
-		   ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_HIGHBANK
+	depends on HAVE_L2X0_L2CC
For platforms that run in non-secure mode, this shouldn't really be a user selectable option. Perhaps those should just select CACHE_L2X0 directly. I'm not sure which one's those are other than Highbank and OMAP4.

The idea here is to make the option user-selectable on platforms where it makes sense (and only those platforms).

So yes, I think that platforms which require this option _should_ select it directly, rather than it being reverse-selected from arch/arm/mm/Kconfig. This puts the knowledge in the logical place. Does this apply to OMAP3? I think we're always running in the Normal World there too.

Cheers
---Dave

Rob Herring

2011-12-06 16:51 UTC #4 lore raw

PATCH 1/1 ARM: pl2x0/pl310: Refactor Kconfig to be more maintainable

Quoted 37 lines · Dave Martin

Quoted 21 lines · Rob Herring
Quoted 20 lines · Dave Martin
Making CACHE_L2X0 depends on (huge list of MACH_ and ARCH_ configs) is bothersome to maintain and likely to lead to merge conflicts.
This patch moves the knowledge of which platforms have a L2x0 or PL310 cache controller to the individual machines. To enable this, a new HAVE_L2X0_L2CC config option is introduced to allow machines to indicate that they have such a cache controller independently of each other.
Signed-off-by Dave Martin <[email protected]>
---
 arch/arm/Kconfig               |    8 ++++++++
 arch/arm/mach-exynos/Kconfig   |    1 +
 arch/arm/mach-omap2/Kconfig    |    1 +
 arch/arm/mach-realview/Kconfig |    5 +++++
 arch/arm/mach-vexpress/Kconfig |    1 +
 arch/arm/mm/Kconfig            |   13 ++++++++-----
 arch/arm/plat-mxc/Kconfig      |    1 +
 7 files changed, 25 insertions(+), 5 deletions(-)
Quoted 14 lines
arch/arm/Kconfig config ARCH_HIGHBANK · line 345
Quoted 12 lines
arch/arm/Kconfig +1 -0
index 44789ef..4068fe5 100644
@@ -339,6 +339,7 @@ config ARCH_HIGHBANK
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_AMBA
 	select ARM_GIC
+	select HAVE_L2X0_L2CC
 	select ARM_TIMER_SP804
 	select CLKDEV_LOOKUP
 	select CPU_V7
These entries are sorted per rmk's review, so please keep it that way.

Quoted 1 line

Can you explain what order they should be in? Alphabetical?

Yes, alphabetical.

Quoted 13 lines

Quoted 12 lines
arch/arm/Kconfig config ARCH_CLPS711X · line 366
Quoted 10 lines
arch/arm/Kconfig +1 -0
@@ -359,6 +360,7 @@ config ARCH_CLPS711X
 config ARCH_CNS3XXX
 	bool "Cavium Networks CNS3XXX family"
 	select CPU_V6K
+	select HAVE_L2X0_L2CC
 	select GENERIC_CLOCKEVENTS
 	select ARM_GIC
 	select MIGHT_HAVE_PCI
But as you can see, that's rarely the case...

Quoted 3 lines

Do you mean "things are not always in alphabetical order?"
Apologies if I'm being obtuse -- your comments are rather terse for me.

Yes.

Quoted 28 lines

[...]
Quoted 5 lines
arch/arm/Kconfig
Quoted 3 lines
arch/arm/Kconfig +3 -0
+config HAVE_L2X0_L2CC
+	bool
+	default n
n is the default already.
Good point -- I'll kill that.
Quoted 8 lines
Quoted 8 lines
arch/arm/Kconfig +4 -2
+	help
+	  This option should be selected by machines which have a L2x0
+	  or PL310 cache controller.
+
 config CACHE_L2X0
 	bool "Enable the L2x0 outer cache controller"
-	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-		   REALVIEW_EB_A9MP || ARCH_IMX_V6_V7 || MACH_REALVIEW_PBX || \
Quoted 8 lines
arch/arm/Kconfig
Quoted 4 lines
arch/arm/Kconfig +1 -3
-		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
-		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
-		   ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_HIGHBANK
+	depends on HAVE_L2X0_L2CC
For platforms that run in non-secure mode, this shouldn't really be a user selectable option. Perhaps those should just select CACHE_L2X0 directly. I'm not sure which one's those are other than Highbank and OMAP4.

Quoted 7 lines

The idea here is to make the option user-selectable on platforms where it makes sense (and only those platforms).
So yes, I think that platforms which require this option _should_ select it directly, rather than it being reverse-selected from arch/arm/mm/Kconfig. This puts the knowledge in the logical place. Does this apply to OMAP3? I think we're always running in the Normal World there too.

No, as OMAP3 has the integrated L2 of the Cortex-A8.

Rob

Dave Martin

author

2011-12-06 17:20 UTC #5 lore raw

PATCH 1/1 ARM: pl2x0/pl310: Refactor Kconfig to be more maintainable

Quoted 92 lines · Rob Herring

Quoted 37 lines · Dave Martin
Quoted 21 lines · Rob Herring
Quoted 20 lines · Dave Martin
Making CACHE_L2X0 depends on (huge list of MACH_ and ARCH_ configs) is bothersome to maintain and likely to lead to merge conflicts.
This patch moves the knowledge of which platforms have a L2x0 or PL310 cache controller to the individual machines. To enable this, a new HAVE_L2X0_L2CC config option is introduced to allow machines to indicate that they have such a cache controller independently of each other.
Signed-off-by Dave Martin <[email protected]>
---
 arch/arm/Kconfig               |    8 ++++++++
 arch/arm/mach-exynos/Kconfig   |    1 +
 arch/arm/mach-omap2/Kconfig    |    1 +
 arch/arm/mach-realview/Kconfig |    5 +++++
 arch/arm/mach-vexpress/Kconfig |    1 +
 arch/arm/mm/Kconfig            |   13 ++++++++-----
 arch/arm/plat-mxc/Kconfig      |    1 +
 7 files changed, 25 insertions(+), 5 deletions(-)
Quoted 14 lines
arch/arm/Kconfig config ARCH_HIGHBANK · line 345
Quoted 12 lines
arch/arm/Kconfig +1 -0
index 44789ef..4068fe5 100644
@@ -339,6 +339,7 @@ config ARCH_HIGHBANK
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_AMBA
 	select ARM_GIC
+	select HAVE_L2X0_L2CC
 	select ARM_TIMER_SP804
 	select CLKDEV_LOOKUP
 	select CPU_V7
These entries are sorted per rmk's review, so please keep it that way.
Quoted 1 line
Can you explain what order they should be in? Alphabetical?
Yes, alphabetical.
Quoted 13 lines
Quoted 12 lines
arch/arm/Kconfig config ARCH_CLPS711X · line 366
Quoted 10 lines
arch/arm/Kconfig +1 -0
@@ -359,6 +360,7 @@ config ARCH_CLPS711X
 config ARCH_CNS3XXX
 	bool "Cavium Networks CNS3XXX family"
 	select CPU_V6K
+	select HAVE_L2X0_L2CC
 	select GENERIC_CLOCKEVENTS
 	select ARM_GIC
 	select MIGHT_HAVE_PCI
But as you can see, that's rarely the case...
Quoted 3 lines
Do you mean "things are not always in alphabetical order?"
Apologies if I'm being obtuse -- your comments are rather terse for me.
Yes.
Quoted 31 lines
[...]
Quoted 5 lines
arch/arm/Kconfig
Quoted 3 lines
arch/arm/Kconfig +3 -0
+config HAVE_L2X0_L2CC
+	bool
+	default n
n is the default already.
Good point -- I'll kill that.
Quoted 8 lines
Quoted 8 lines
arch/arm/Kconfig +4 -2
+	help
+	  This option should be selected by machines which have a L2x0
+	  or PL310 cache controller.
+
 config CACHE_L2X0
 	bool "Enable the L2x0 outer cache controller"
-	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-		   REALVIEW_EB_A9MP || ARCH_IMX_V6_V7 || MACH_REALVIEW_PBX || \
Quoted 8 lines
arch/arm/Kconfig
Quoted 4 lines
arch/arm/Kconfig +1 -3
-		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
-		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
-		   ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_HIGHBANK
+	depends on HAVE_L2X0_L2CC
For platforms that run in non-secure mode, this shouldn't really be a user selectable option. Perhaps those should just select CACHE_L2X0 directly. I'm not sure which one's those are other than Highbank and OMAP4.
The idea here is to make the option user-selectable on platforms where it makes sense (and only those platforms).

Quoted 6 lines

Quoted 4 lines
So yes, I think that platforms which require this option _should_ select it directly, rather than it being reverse-selected from arch/arm/mm/Kconfig. This puts the knowledge in the logical place. Does this apply to OMAP3? I think we're always running in the Normal World there too.
No, as OMAP3 has the integrated L2 of the Cortex-A8.

Yes, I realised that after I'd posted ... I'll tweak the series and repost.

Thanks for the feedback

---Dave

Dave Martin

author

2011-12-12 15:14 UTC #6 lore raw

PATCH 1/1 ARM: pl2x0/pl310: Refactor Kconfig to be more maintainable

In reply to Rob Herring

Quoted 190 lines · Rob Herring

Quoted 25 lines · Dave Martin

Making CACHE_L2X0 depends on (huge list of MACH_ and ARCH_ configs) is bothersome to maintain and likely to lead to merge conflicts.
This patch moves the knowledge of which platforms have a L2x0 or PL310 cache controller to the individual machines. To enable this, a new HAVE_L2X0_L2CC config option is introduced to allow machines to indicate that they have such a cache controller independently of each other.
Signed-off-by Dave Martin <[email protected]>
---
 arch/arm/Kconfig               |    8 ++++++++
 arch/arm/mach-exynos/Kconfig   |    1 +
 arch/arm/mach-omap2/Kconfig    |    1 +
 arch/arm/mach-realview/Kconfig |    5 +++++
 arch/arm/mach-vexpress/Kconfig |    1 +
 arch/arm/mm/Kconfig            |   13 ++++++++-----
 arch/arm/plat-mxc/Kconfig      |    1 +
 7 files changed, 25 insertions(+), 5 deletions(-)
arch/arm/Kconfig +0 -0
index 44789ef..4068fe5 100644

arch/arm/Kconfig config ARCH_HIGHBANK · line 345

Quoted 7 lines

arch/arm/Kconfig +1 -0

@@ -339,6 +339,7 @@ config ARCH_HIGHBANK
 	select ARCH_WANT_OPTIONAL_GPIOLIB
 	select ARM_AMBA
 	select ARM_GIC
+	select HAVE_L2X0_L2CC
 	select ARM_TIMER_SP804
 	select CLKDEV_LOOKUP
 	select CPU_V7

These entries are sorted per rmk's review, so please keep it that way.

arch/arm/Kconfig config ARCH_CLPS711X · line 366

Quoted 8 lines

arch/arm/Kconfig +1 -0

@@ -359,6 +360,7 @@ config ARCH_CLPS711X
 config ARCH_CNS3XXX
 	bool "Cavium Networks CNS3XXX family"
 	select CPU_V6K
+	select HAVE_L2X0_L2CC
 	select GENERIC_CLOCKEVENTS
 	select ARM_GIC
 	select MIGHT_HAVE_PCI

But as you can see, that's rarely the case...

Quoted 133 lines

arch/arm/Kconfig +6 -0

@@ -377,6 +379,7 @@ config ARCH_GEMINI
 config ARCH_PRIMA2
 	bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
 	select CPU_V7
+	select HAVE_L2X0_L2CC
 	select NO_IOPORT
 	select GENERIC_CLOCKEVENTS
 	select CLKDEV_LOOKUP

@@ -627,6 +630,7 @@ config ARCH_W90X900
 
 config ARCH_TEGRA
 	bool "NVIDIA Tegra"
+	select HAVE_L2X0_L2CC
 	select CLKDEV_LOOKUP
 	select CLKSRC_MMIO
 	select GENERIC_CLOCKEVENTS

@@ -699,6 +703,7 @@ config ARCH_MSM
 
 config ARCH_SHMOBILE
 	bool "Renesas SH-Mobile / R-Mobile"
+	select HAVE_L2X0_L2CC
 	select HAVE_CLK
 	select CLKDEV_LOOKUP
 	select HAVE_MACH_CLKDEV

@@ -900,6 +905,7 @@ config ARCH_U8500
 	bool "ST-Ericsson U8500 Series"
 	select CPU_V7
 	select ARM_AMBA
+	select HAVE_L2X0_L2CC
 	select GENERIC_CLOCKEVENTS
 	select CLKDEV_LOOKUP
 	select ARCH_REQUIRE_GPIOLIB

@@ -912,6 +918,7 @@ config ARCH_NOMADIK
 	select ARM_AMBA
 	select ARM_VIC
 	select CPU_ARM926T
+	select HAVE_L2X0_L2CC
 	select CLKDEV_LOOKUP
 	select GENERIC_CLOCKEVENTS
 	select ARCH_REQUIRE_GPIOLIB

@@ -968,6 +975,7 @@ config ARCH_VT8500
 config ARCH_ZYNQ
 	bool "Xilinx Zynq ARM Cortex A9 Platform"
 	select CPU_V7
+	select HAVE_L2X0_L2CC
 	select GENERIC_CLOCKEVENTS
 	select CLKDEV_LOOKUP
 	select ARM_GIC

arch/arm/mach-exynos/Kconfig +1 -0

index 724ec0f..b3eb318 100644
@@ -17,6 +17,7 @@ choice
 
 config ARCH_EXYNOS4
 	bool "SAMSUNG EXYNOS4"
+	select HAVE_L2X0_L2CC
 	help
 	  Samsung EXYNOS4 SoCs based systems

arch/arm/mach-omap2/Kconfig +1 -0

index 5034147..f4e7e6a 100644
@@ -44,6 +44,7 @@ config ARCH_OMAP4
 	select CPU_V7
 	select ARM_GIC
 	select LOCAL_TIMERS if SMP
+	select HAVE_L2X0_L2CC
 	select PL310_ERRATA_588369
 	select PL310_ERRATA_727915
 	select ARM_ERRATA_720789

arch/arm/mach-realview/Kconfig +5 -0

index dba6d0c..3dfd6b8 100644
@@ -12,6 +12,7 @@ config REALVIEW_EB_A9MP
 	bool "Support Multicore Cortex-A9 Tile"
 	depends on MACH_REALVIEW_EB
 	select CPU_V7
+	select HAVE_L2X0_L2CC
 	help
 	  Enable support for the Cortex-A9MPCore tile fitted to the
 	  Realview(R) Emulation Baseboard platform.

@@ -20,6 +21,7 @@ config REALVIEW_EB_ARM11MP
 	bool "Support ARM11MPCore Tile"
 	depends on MACH_REALVIEW_EB
 	select CPU_V6K
+	select HAVE_L2X0_L2CC
 	select ARCH_HAS_BARRIERS if SMP
 	help
 	  Enable support for the ARM11MPCore tile fitted to the Realview(R)

@@ -38,6 +40,7 @@ config MACH_REALVIEW_PB11MP
 	bool "Support RealView(R) Platform Baseboard for ARM11MPCore"
 	select CPU_V6K
 	select ARM_GIC
+	select HAVE_L2X0_L2CC
 	select HAVE_PATA_PLATFORM
 	select ARCH_HAS_BARRIERS if SMP
 	help

@@ -50,6 +53,7 @@ config MACH_REALVIEW_PB1176
 	bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S"
 	select CPU_V6
 	select ARM_GIC
+	select HAVE_L2X0_L2CC
 	select HAVE_TCM
 	help
 	  Include support for the ARM(R) RealView(R) Platform Baseboard for

@@ -77,6 +81,7 @@ config MACH_REALVIEW_PBA8
 config MACH_REALVIEW_PBX
 	bool "Support RealView(R) Platform Baseboard Explore"
 	select ARM_GIC
+	select HAVE_L2X0_L2CC
 	select HAVE_PATA_PLATFORM
 	select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
 	select ZONE_DMA if SPARSEMEM

arch/arm/mach-vexpress/Kconfig +1 -0

index 9311484..78d4f28 100644
@@ -5,6 +5,7 @@ config ARCH_VEXPRESS_CA9X4
 	bool "Versatile Express Cortex-A9x4 tile"
 	select CPU_V7
 	select ARM_GIC
+	select HAVE_L2X0_L2CC
 	select ARM_ERRATA_720789
 	select ARM_ERRATA_751472
 	select ARM_ERRATA_753970

arch/arm/mm/Kconfig +0 -0

index 67f75a0..bb743df 100644

arch/arm/mm/Kconfig config CACHE_FEROCEON_L2_WRITETHROUGH · line 821

Quoted 6 lines

arch/arm/mm/Kconfig +3 -0

@@ -816,13 +816,16 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 	  Say Y here to use the Feroceon L2 cache in writethrough mode.
 	  Unless you specifically require this, say N for writeback mode.
 
+config HAVE_L2X0_L2CC
+	bool
+	default n

n is the default already.

Quoted 16 lines

arch/arm/mm/Kconfig config CACHE_FEROCEON_L2_WRITETHROUGH · line 828
Quoted 12 lines
arch/arm/mm/Kconfig +5 -5
+	help
+	  This option should be selected by machines which have a L2x0
+	  or PL310 cache controller.
+
 config CACHE_L2X0
 	bool "Enable the L2x0 outer cache controller"
-	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-		   REALVIEW_EB_A9MP || ARCH_IMX_V6_V7 || MACH_REALVIEW_PBX || \
-		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
-		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
-		   ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_HIGHBANK
+	depends on HAVE_L2X0_L2CC
For platforms that run in non-secure mode, this shouldn't really be a user selectable option. Perhaps those should just select CACHE_L2X0 directly. I'm not sure which one's those are other than Highbank and OMAP4.

Highbank doesn't currently have this. Should I add this, or should we leave that for a separate patch?

Arguably, a refactoring patch shouldn't change the Kconfig behaviour -- possibly anything which is currently broken should stay broken (but can be fixed later).

Cheers
---Dave

Rob Herring

2011-12-12 15:31 UTC #7 lore raw

PATCH 1/1 ARM: pl2x0/pl310: Refactor Kconfig to be more maintainable

Quoted 2 lines · Dave Martin

Quoted 1 line · Rob Herring
On 11/29/2011 10:32 AM, Dave Martin wrote:

[snip]

Quoted 13 lines

Quoted 4 lines
Quoted 4 lines
config CACHE_L2X0
arch/arm/mm/Kconfig +0 -2
 	bool "Enable the L2x0 outer cache controller"
-	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-		   REALVIEW_EB_A9MP || ARCH_IMX_V6_V7 || MACH_REALVIEW_PBX || \
Quoted 8 lines
arch/arm/mm/Kconfig config CACHE_FEROCEON_L2_WRITETHROUGH · line 828
Quoted 4 lines
arch/arm/mm/Kconfig +1 -3
-		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
-		   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
-		   ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX || ARCH_HIGHBANK
+	depends on HAVE_L2X0_L2CC
For platforms that run in non-secure mode, this shouldn't really be a user selectable option. Perhaps those should just select CACHE_L2X0 directly. I'm not sure which one's those are other than Highbank and OMAP4.

Quoted 6 lines

Highbank doesn't currently have this. Should I add this, or should we leave that for a separate patch?
Arguably, a refactoring patch shouldn't change the Kconfig behaviour -- possibly anything which is currently broken should stay broken (but can be fixed later).

I thinking highbank wouldn't need HAVE_L2X0_L2CC, but it does to satisfy dependencies. So you're right, it should probably be separate.

Rob

Shawn Guo

2011-11-30 14:01 UTC #8 lore raw

PATCH 1/1 ARM: pl2x0/pl310: Refactor Kconfig to be more maintainable

In reply to Dave Martin

On Tue, Nov 29, 2011 at 04:32:25PM +0000, Dave Martin wrote:
[...]

arch/arm/plat-mxc/Kconfig config ARCH_IMX_V6_V7 · line 26

Quoted 13 lines

arch/arm/plat-mxc/Kconfig +1 -0

index b3a1f2b..6871ed7 100644
@@ -20,6 +20,7 @@ config ARCH_IMX_V6_V7
 	bool "i.MX3, i.MX6"
 	select AUTO_ZRELADDR if !ZBOOT_ROM
 	select ARM_PATCH_PHYS_VIRT
+	select HAVE_L2X0_L2CC
 	help
 	  This enables support for systems based on the Freescale i.MX3 and i.MX6
 	  family.

You may want to amend the following for above change.

arch/arm/mach-imx/Kconfig +0 -1

index 5f7f9c2..a134819 100644
@@ -609,7 +609,6 @@ comment "i.MX6 family:"
 config SOC_IMX6Q
        bool "i.MX6 Quad support"
        select ARM_GIC
-       select CACHE_L2X0
        select CPU_V7
        select HAVE_ARM_SCU
        select HAVE_IMX_GPC

Signature · 2 lines

Regards,
Shawn

Dave Martin

author

2011-11-30 14:03 UTC #9 lore raw

PATCH 1/1 ARM: pl2x0/pl310: Refactor Kconfig to be more maintainable

Quoted 23 lines · Shawn Guo

On Tue, Nov 29, 2011 at 04:32:25PM +0000, Dave Martin wrote:
[...]
arch/arm/plat-mxc/Kconfig config ARCH_IMX_V6_V7 · line 26
Quoted 13 lines
arch/arm/plat-mxc/Kconfig +1 -0
index b3a1f2b..6871ed7 100644
@@ -20,6 +20,7 @@ config ARCH_IMX_V6_V7
 	bool "i.MX3, i.MX6"
 	select AUTO_ZRELADDR if !ZBOOT_ROM
 	select ARM_PATCH_PHYS_VIRT
+	select HAVE_L2X0_L2CC
 	help
 	  This enables support for systems based on the Freescale i.MX3 and i.MX6
 	  family.
You may want to amend the following for above change.
arch/arm/mach-imx/Kconfig +0 -0
index 5f7f9c2..a134819 100644

arch/arm/mach-imx/Kconfig comment "i.MX6 family:" · line 614

Quoted 7 lines

arch/arm/mach-imx/Kconfig +0 -1

@@ -609,7 +609,6 @@ comment "i.MX6 family:"
 config SOC_IMX6Q
        bool "i.MX6 Quad support"
        select ARM_GIC
-       select CACHE_L2X0
        select CPU_V7
        select HAVE_ARM_SCU
        select HAVE_IMX_GPC

Platforms where the L2x0 is considered compulsory should still select it directly like this, instead of selecting HAVE_L2X0_L2CC.

Do you know whether it is OK to run mx6 with the L2 cache turned off? (I would hope that it is OK... in which case we could make the change)

Cheers
---Dave

Shawn Guo

2011-11-30 14:26 UTC #10 lore raw

PATCH 1/1 ARM: pl2x0/pl310: Refactor Kconfig to be more maintainable

Quoted 35 lines · Dave Martin

Quoted 23 lines · Shawn Guo
On Tue, Nov 29, 2011 at 04:32:25PM +0000, Dave Martin wrote:
[...]
arch/arm/plat-mxc/Kconfig config ARCH_IMX_V6_V7 · line 26
Quoted 13 lines
arch/arm/plat-mxc/Kconfig +1 -0
index b3a1f2b..6871ed7 100644
@@ -20,6 +20,7 @@ config ARCH_IMX_V6_V7
 	bool "i.MX3, i.MX6"
 	select AUTO_ZRELADDR if !ZBOOT_ROM
 	select ARM_PATCH_PHYS_VIRT
+	select HAVE_L2X0_L2CC
 	help
 	  This enables support for systems based on the Freescale i.MX3 and i.MX6
 	  family.
You may want to amend the following for above change.
arch/arm/mach-imx/Kconfig +0 -0
index 5f7f9c2..a134819 100644
arch/arm/mach-imx/Kconfig comment "i.MX6 family:" · line 614
Quoted 7 lines
arch/arm/mach-imx/Kconfig +0 -1
@@ -609,7 +609,6 @@ comment "i.MX6 family:"
 config SOC_IMX6Q
        bool "i.MX6 Quad support"
        select ARM_GIC
-       select CACHE_L2X0
        select CPU_V7
        select HAVE_ARM_SCU
        select HAVE_IMX_GPC
Platforms where the L2x0 is considered compulsory should still select it directly like this, instead of selecting HAVE_L2X0_L2CC.

Quoted 3 lines

Do you know whether it is OK to run mx6 with the L2 cache turned off? (I would hope that it is OK... in which case we could make the change)

We selected it not for it's compulsory but we want it anyway. It's actually OK to run imx6 with L2 cache turned off.

Signature · 2 lines

Regards,
Shawn

Dave Martin

author

2011-11-30 14:45 UTC #11 lore raw

PATCH 1/1 ARM: pl2x0/pl310: Refactor Kconfig to be more maintainable

Quoted 36 lines · Shawn Guo

Quoted 35 lines · Dave Martin
Quoted 23 lines · Shawn Guo
On Tue, Nov 29, 2011 at 04:32:25PM +0000, Dave Martin wrote:
[...]
arch/arm/plat-mxc/Kconfig config ARCH_IMX_V6_V7 · line 26
Quoted 13 lines
arch/arm/plat-mxc/Kconfig +1 -0
index b3a1f2b..6871ed7 100644
@@ -20,6 +20,7 @@ config ARCH_IMX_V6_V7
 	bool "i.MX3, i.MX6"
 	select AUTO_ZRELADDR if !ZBOOT_ROM
 	select ARM_PATCH_PHYS_VIRT
+	select HAVE_L2X0_L2CC
 	help
 	  This enables support for systems based on the Freescale i.MX3 and i.MX6
 	  family.
You may want to amend the following for above change.
arch/arm/mach-imx/Kconfig +0 -0
index 5f7f9c2..a134819 100644
arch/arm/mach-imx/Kconfig comment "i.MX6 family:" · line 614
Quoted 7 lines
arch/arm/mach-imx/Kconfig +0 -1
@@ -609,7 +609,6 @@ comment "i.MX6 family:"
 config SOC_IMX6Q
        bool "i.MX6 Quad support"
        select ARM_GIC
-       select CACHE_L2X0
        select CPU_V7
        select HAVE_ARM_SCU
        select HAVE_IMX_GPC
Platforms where the L2x0 is considered compulsory should still select it directly like this, instead of selecting HAVE_L2X0_L2CC.

Quoted 5 lines

Quoted 3 lines
Do you know whether it is OK to run mx6 with the L2 cache turned off? (I would hope that it is OK... in which case we could make the change)
We selected it not for it's compulsory but we want it anyway. It's actually OK to run imx6 with L2 cache turned off.

OK, I'll change that in my patch to use the new option.

Cheers
---Dave

Uwe Kleine-König

2011-12-12 15:47 UTC #12 lore raw

PATCH 1/1 ARM: pl2x0/pl310: Refactor Kconfig to be more maintainable

In reply to Dave Martin

$Subject ~= s/pl2x0/l2x0/

Best regards
Uwe

Signature · 2 lines

Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

Dave Martin

author

2011-12-13 10:50 UTC #13 lore raw

PATCH 1/1 ARM: pl2x0/pl310: Refactor Kconfig to be more maintainable

Quoted 4 lines · Uwe Kleine-K?nig

$Subject ~= s/pl2x0/l2x0/
Best regards
Uwe

You're right -- in fact I'd already spotted that and changed it locally. It will appear in the next post.

Thanks anyway
---Dave