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ARM: mach-shmobile: sh7372 A4S support

PATCH New Magnus Damm 1 participant 1 message Dec 18, 2011

Subsystems (4)
Arm (32-bit) Arm sub-architectures SuperH Arm/RISC-V/Renesas architecture
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Magnus Damm

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PATCH 1/1 ARM: mach-shmobile: sh7372 A4S support

From: Magnus Damm <[email protected]>

Add support for the sh7372 A4S power domain / sleep mode.

The sh7372 contains a power domain named A4S which in turn contains power domains for both I/O Devices and CPU cores.

At this point only System wide Suspend-to-RAM is supported, but the the hardware can also support CPUIdle. With more efforts in the future CPUIdle can work with bot A4S and A3SM.

Tested on the sh7372 Mackerel board.

Signed-off-by Magnus Damm <[email protected]>

---

 arch/arm/mach-shmobile/include/mach/common.h |    4 -
 arch/arm/mach-shmobile/include/mach/sh7372.h |    3 +
 arch/arm/mach-shmobile/intc-sh7372.c         |   49 ++++++++++++++++++++
 arch/arm/mach-shmobile/pm-sh7372.c           |   63 ++++++++++++++++++--------
 arch/arm/mach-shmobile/setup-sh7372.c        |    6 ++
 arch/arm/mach-shmobile/sleep-sh7372.S        |   21 ++++----
 6 files changed, 116 insertions(+), 30 deletions(-)
arch/arm/mach-shmobile/include/mach/common.h +2 -2
@@ -35,8 +35,8 @@ extern void sh7372_add_standard_devices(
 extern void sh7372_clock_init(void);
 extern void sh7372_pinmux_init(void);
 extern void sh7372_pm_init(void);
-extern void sh7372_resume_core_standby_a3sm(void);
-extern int sh7372_do_idle_a3sm(unsigned long unused);
+extern void sh7372_resume_core_standby_sysc(void);
+extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
 extern struct clk sh7372_extal1_clk;
 extern struct clk sh7372_extal2_clk;
arch/arm/mach-shmobile/include/mach/sh7372.h +3 -0
@@ -499,6 +499,7 @@ extern struct sh7372_pm_domain sh7372_d4
 extern struct sh7372_pm_domain sh7372_a4r;
 extern struct sh7372_pm_domain sh7372_a3rv;
 extern struct sh7372_pm_domain sh7372_a3ri;
+extern struct sh7372_pm_domain sh7372_a4s;
 extern struct sh7372_pm_domain sh7372_a3sp;
 extern struct sh7372_pm_domain sh7372_a3sg;
 

@@ -515,5 +516,7 @@ extern void sh7372_pm_add_subdomain(stru
 
 extern void sh7372_intcs_suspend(void);
 extern void sh7372_intcs_resume(void);
+extern void sh7372_intca_suspend(void);
+extern void sh7372_intca_resume(void);
 
 #endif /* __ASM_SH7372_H__ */
arch/arm/mach-shmobile/intc-sh7372.c +49 -0

52 lines not on this page · raw message

arch/arm/mach-shmobile/pm-sh7372.c +46 -17

117 lines not on this page · raw message

arch/arm/mach-shmobile/setup-sh7372.c +5 -1
@@ -994,12 +994,16 @@ void __init sh7372_add_standard_devices(
 	sh7372_init_pm_domain(&sh7372_a4r);
 	sh7372_init_pm_domain(&sh7372_a3rv);
 	sh7372_init_pm_domain(&sh7372_a3ri);
-	sh7372_init_pm_domain(&sh7372_a3sg);
+	sh7372_init_pm_domain(&sh7372_a4s);
 	sh7372_init_pm_domain(&sh7372_a3sp);
+	sh7372_init_pm_domain(&sh7372_a3sg);
 
 	sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
 	sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc);
 
+	sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sg);
+	sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sp);
+
 	platform_add_devices(sh7372_early_devices,
 			    ARRAY_SIZE(sh7372_early_devices));
arch/arm/mach-shmobile/sleep-sh7372.S +11 -10
@@ -37,13 +37,18 @@
 #if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
 	.align	12
 	.text
-	.global sh7372_resume_core_standby_a3sm
-sh7372_resume_core_standby_a3sm:
+	.global sh7372_resume_core_standby_sysc
+sh7372_resume_core_standby_sysc:
 	ldr     pc, 1f
 1:	.long   cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET
 
-	.global	sh7372_do_idle_a3sm
-sh7372_do_idle_a3sm:
+#define SPDCR 0xe6180008
+
+	/* A3SM & A4S power down */
+	.global	sh7372_do_idle_sysc
+sh7372_do_idle_sysc:
+	mov	r8, r0 /* sleep mode passed in r0 */
+
 	/*
 	 * Clear the SCTLR.C bit to prevent further data cache
 	 * allocation. Clearing SCTLR.C would make all the data accesses

@@ -80,13 +85,9 @@ sh7372_do_idle_a3sm:
 	dsb
 	dmb
 
-#define SPDCR 0xe6180008
-#define A3SM (1 << 12)
-
-	/* A3SM power down */
+	/* SYSC power down */
 	ldr     r0, =SPDCR
-	ldr     r1, £SM
-	str     r1, [r0]
+	str     r8, [r0]
 1:
 	b      1b