Add support for the OpenRISC architecture

Signed-off-by Stefan Kristiansson <[email protected]>

---

Changes in v2:
- Copyright/license information added to headers
- ptrace.h updated from Linux

 arch/openrisc/include/asm/bitops.h       |   28 ++
 arch/openrisc/include/asm/bitops/ffs.h   |   26 ++
 arch/openrisc/include/asm/bitops/fls.h   |   26 ++
 arch/openrisc/include/asm/byteorder.h    |    1 +
 arch/openrisc/include/asm/cache.h        |   35 ++
 arch/openrisc/include/asm/config.h       |   24 ++
 arch/openrisc/include/asm/errno.h        |    1 +
 arch/openrisc/include/asm/global_data.h  |   74 ++++
 arch/openrisc/include/asm/gpio.h         |   84 +++++
 arch/openrisc/include/asm/io.h           |  112 ++++++
 arch/openrisc/include/asm/openrisc_exc.h |   41 +++
 arch/openrisc/include/asm/posix_types.h  |   72 ++++
 arch/openrisc/include/asm/processor.h    |    4 +
 arch/openrisc/include/asm/ptrace.h       |  131 +++++++
 arch/openrisc/include/asm/spr-defs.h     |  567 ++++++++++++++++++++++++++++++
 arch/openrisc/include/asm/string.h       |    4 +
 arch/openrisc/include/asm/system.h       |   39 ++
 arch/openrisc/include/asm/types.h        |   79 ++++
 arch/openrisc/include/asm/u-boot.h       |   48 +++
 arch/openrisc/include/asm/unaligned.h    |    1 +
 20 files changed, 1397 insertions(+), 0 deletions(-)
 create mode 100644 arch/openrisc/include/asm/bitops.h
 create mode 100644 arch/openrisc/include/asm/bitops/ffs.h
 create mode 100644 arch/openrisc/include/asm/bitops/fls.h
 create mode 100644 arch/openrisc/include/asm/byteorder.h
 create mode 100644 arch/openrisc/include/asm/cache.h
 create mode 100644 arch/openrisc/include/asm/config.h
 create mode 100644 arch/openrisc/include/asm/errno.h
 create mode 100644 arch/openrisc/include/asm/global_data.h
 create mode 100644 arch/openrisc/include/asm/gpio.h
 create mode 100644 arch/openrisc/include/asm/io.h
 create mode 100644 arch/openrisc/include/asm/openrisc_exc.h
 create mode 100644 arch/openrisc/include/asm/posix_types.h

 create mode 100644 arch/openrisc/include/asm/processor.h
 create mode 100644 arch/openrisc/include/asm/ptrace.h
 create mode 100644 arch/openrisc/include/asm/spr-defs.h
 create mode 100644 arch/openrisc/include/asm/string.h
 create mode 100644 arch/openrisc/include/asm/system.h
 create mode 100644 arch/openrisc/include/asm/types.h
 create mode 100644 arch/openrisc/include/asm/u-boot.h
 create mode 100644 arch/openrisc/include/asm/unaligned.h

Signed-off-by Stefan Kristiansson <[email protected]>

---

Changes in v2:
- None

 common/image.c  |    1 +
 include/image.h |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)

Signed-off-by Stefan Kristiansson <[email protected]>

---

Changes in v2:
- Fix missing newline
- Bugfix for cache line size reading
- Make l.nop asm statements volatile
- Fix include order (asm after non-asm)
- Add static to functions only called locally
- Make unhandled exception printout into a look-up table

 arch/openrisc/config.mk        |   27 ++++
 arch/openrisc/cpu/Makefile     |   47 ++++++
 arch/openrisc/cpu/cache.c      |  151 ++++++++++++++++++
 arch/openrisc/cpu/cpu.c        |  157 +++++++++++++++++++
 arch/openrisc/cpu/exceptions.c |   85 ++++++++++
 arch/openrisc/cpu/interrupts.c |  121 +++++++++++++++
 arch/openrisc/cpu/start.S      |  335 ++++++++++++++++++++++++++++++++++++++++
 7 files changed, 923 insertions(+), 0 deletions(-)
 create mode 100644 arch/openrisc/config.mk
 create mode 100644 arch/openrisc/cpu/Makefile
 create mode 100644 arch/openrisc/cpu/cache.c
 create mode 100644 arch/openrisc/cpu/cpu.c
 create mode 100644 arch/openrisc/cpu/exceptions.c
 create mode 100644 arch/openrisc/cpu/interrupts.c
 create mode 100644 arch/openrisc/cpu/start.S

arch/openrisc/config.mk new file +27 -0

new file mode 100644
index 0000000..521e73a
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2011
+# Julius Baxter <[email protected]>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+CROSS_COMPILE ?= or32-elf-
+
+# r10 used for global object pointer, already set in OR32 GCC but just to be
+# clear
+PLATFORM_CPPFLAGS += -DCONFIG_OPENRISC -D__OR1K__ -ffixed-r10
+
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000

arch/openrisc/cpu/Makefile new file +47 -0

new file mode 100644
index 0000000..b3b1a24
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2011
+# Julius Baxter <[email protected]>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).o
+
+START	= start.o
+COBJS-y	= cache.o cpu.o exceptions.o interrupts.o
+
+SRCS	:= $(START:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

arch/openrisc/cpu/cache.c new file +100 -0

new file mode 100644
index 0000000..2a73a4f
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2011, Stefan Kristiansson <[email protected]>
+ * (C) Copyright 2011, Julius Baxter <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/system.h>
+
+void flush_dcache_range(unsigned long addr, unsigned long stop)
+{
+	ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;
+
+	while (addr < stop) {
+		mtspr(SPR_DCBFR, addr);
+		addr += block_size;
+	}
+}
+
+void invalidate_dcache_range(unsigned long addr, unsigned long stop)
+{
+	ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;
+
+	while (addr < stop) {
+		mtspr(SPR_DCBIR, addr);
+		addr += block_size;
+	}
+}
+
+static void invalidate_icache_range(unsigned long addr, unsigned long stop)
+{
+	ulong block_size = (mfspr(SPR_ICCFGR) & SPR_ICCFGR_CBS) ? 32 : 16;
+
+	while (addr < stop) {
+		mtspr(SPR_ICBIR, addr);
+		addr += block_size;
+	}
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+	flush_dcache_range(addr, addr + size);
+	invalidate_icache_range(addr, addr + size);
+}
+
+int icache_status(void)
+{
+	return mfspr(SPR_SR) & SPR_SR_ICE;
+}
+
+int checkicache(void)
+{
+	unsigned long iccfgr;
+	unsigned long cache_set_size;
+	unsigned long cache_ways;
+	unsigned long cache_block_size;
+
+	iccfgr = mfspr(SPR_ICCFGR);
+	cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
+	cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
+	cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
+
+	return cache_set_size * cache_ways * cache_block_size;
+}
+
+int dcache_status(void)
+{
+	return mfspr(SPR_SR) & SPR_SR_DCE;
+}
+
+int checkdcache(void)
+{
+	unsigned long dccfgr;
+	unsigned long cache_set_size;
+	unsigned long cache_ways;
+	unsigned long cache_block_size;
+
+	dccfgr = mfspr(SPR_DCCFGR);
+	cache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
+	cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
+	cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
+
+	return cache_set_size * cache_ways * cache_block_size;
+}
+
+void dcache_enable(void)

arch/openrisc/cpu/cache.c line 110

Quoted 12 lines · Stefan Kristiansson

arch/openrisc/cpu/cache.c new file +12 -0

+
+void dcache_enable(void)
+{
+	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");

This is interesting. Are there 8 nops?
Is there any reason for that? Is it just any waiting? If yes, maybe it will be worth to add any comment.

Quoted 17 lines · Michal Simek

arch/openrisc/cpu/cache.c line 110

Quoted 12 lines · Stefan Kristiansson

arch/openrisc/cpu/cache.c new file +12 -0

+
+void dcache_enable(void)
+{
+	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");

This is interesting. Are there 8 nops?
Is there any reason for that? Is it just any waiting? If yes, maybe it will be worth to add any comment.

Yes, the number of nops are kind of arbitrary,
they are there to add some headroom for the cache
to startup without any load/stores in flight.

But you are right, a comment about this might be in place.

Quoted 23 lines · On Thursday 22 December 2011 06:39:32 Stefan Kristiansson wrote:

Quoted 17 lines · Michal Simek

arch/openrisc/cpu/cache.c line 110

Quoted 12 lines · Stefan Kristiansson

arch/openrisc/cpu/cache.c new file +12 -0

+
+void dcache_enable(void)
+{
+	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");

This is interesting. Are there 8 nops?
Is there any reason for that? Is it just any waiting? If yes, maybe it will be worth to add any comment.

Yes, the number of nops are kind of arbitrary,
they are there to add some headroom for the cache
to startup without any load/stores in flight.

Quoted 1 line

But you are right, a comment about this might be in place.

this is usually why the ISA provides some sort of sync or latch mechanism. that way code is deterministic instead of being unsettling arbitrary (like it is here).

Quoted 26 lines · Mike Frysinger

Quoted 24 lines · On Thursday 22 December 2011 06:39:32 Stefan Kristiansson wrote:

Quoted 17 lines · Michal Simek

arch/openrisc/cpu/cache.c line 110

Quoted 12 lines · Stefan Kristiansson

arch/openrisc/cpu/cache.c new file +12 -0

+
+void dcache_enable(void)
+{
+	mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");
+	asm volatile("l.nop");

This is interesting. Are there 8 nops?
Is there any reason for that? Is it just any waiting? If yes, maybe it will be worth to add any comment.

Yes, the number of nops are kind of arbitrary,
they are there to add some headroom for the cache
to startup without any load/stores in flight.

But you are right, a comment about this might be in place.

Quoted 3 lines

this is usually why the ISA provides some sort of sync or latch mechanism. that way code is deterministic instead of being unsettling arbitrary (like it is here).

The OpenRISC ISA does provide synch mechanisms, but they are unfortunately optional and not supported by the (currently) only open implementation (or1200).

Signed-off-by Stefan Kristiansson <[email protected]>

---

Changes in v2:
- Fix missing newline
- Bugfix for cache line size reading
- Make l.nop asm statements volatile
- Fix include order (asm after non-asm)
- Add static to functions only called locally
- Make unhandled exception printout into a look-up table

 arch/openrisc/config.mk        |   27 ++++
 arch/openrisc/cpu/Makefile     |   47 ++++++
 arch/openrisc/cpu/cache.c      |  151 ++++++++++++++++++
 arch/openrisc/cpu/cpu.c        |  157 +++++++++++++++++++
 arch/openrisc/cpu/exceptions.c |   85 ++++++++++
 arch/openrisc/cpu/interrupts.c |  121 +++++++++++++++
 arch/openrisc/cpu/start.S      |  335 ++++++++++++++++++++++++++++++++++++++++
 7 files changed, 923 insertions(+), 0 deletions(-)
 create mode 100644 arch/openrisc/config.mk
 create mode 100644 arch/openrisc/cpu/Makefile
 create mode 100644 arch/openrisc/cpu/cache.c
 create mode 100644 arch/openrisc/cpu/cpu.c
 create mode 100644 arch/openrisc/cpu/exceptions.c
 create mode 100644 arch/openrisc/cpu/interrupts.c
 create mode 100644 arch/openrisc/cpu/start.S

Signed-off-by Stefan Kristiansson <[email protected]>

---

Changes in v2:
- Remove superfluous extern statements
- Use ARRAY_SIZE to determine end of function pointer list
- Remove references to deprecated CONFIG_NET_MULTI
- Fix include order (asm after non-asm)
- Remove function pointer typedef
- Remove simulation specific l.nop

 arch/openrisc/lib/Makefile |   47 ++++++++++++
 arch/openrisc/lib/board.c  |  168 ++++++++++++++++++++++++++++++++++++++++++++
 arch/openrisc/lib/bootm.c  |   84 ++++++++++++++++++++++
 arch/openrisc/lib/timer.c  |  104 +++++++++++++++++++++++++++
 4 files changed, 403 insertions(+), 0 deletions(-)
 create mode 100644 arch/openrisc/lib/Makefile
 create mode 100644 arch/openrisc/lib/board.c
 create mode 100644 arch/openrisc/lib/bootm.c
 create mode 100644 arch/openrisc/lib/timer.c

Signed-off-by Stefan Kristiansson <[email protected]>

---

Changes in v2:
- None

 common/cmd_bdinfo.c |   22 ++++++++++++++++++++++
 1 files changed, 22 insertions(+), 0 deletions(-)

Signed-off-by Stefan Kristiansson <[email protected]>

---

Changes in v2:
- None

 examples/standalone/stubs.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

Signed-off-by Stefan Kristiansson <[email protected]>

---

Changes in v2:
- Remove references to deprecated CONFIG_NET_MULTI

 board/openrisc/openrisc-generic/Makefile           |   43 +
 board/openrisc/openrisc-generic/config.mk          |   24 +
 board/openrisc/openrisc-generic/openrisc-generic.c |   55 ++
 board/openrisc/openrisc-generic/or1ksim.cfg        |  882 ++++++++++++++++++++
 board/openrisc/openrisc-generic/u-boot.lds         |   75 ++
 boards.cfg                                         |    1 +
 include/configs/openrisc-generic.h                 |  158 ++++
 7 files changed, 1238 insertions(+), 0 deletions(-)
 create mode 100644 board/openrisc/openrisc-generic/Makefile
 create mode 100644 board/openrisc/openrisc-generic/config.mk
 create mode 100644 board/openrisc/openrisc-generic/openrisc-generic.c
 create mode 100644 board/openrisc/openrisc-generic/or1ksim.cfg
 create mode 100644 board/openrisc/openrisc-generic/u-boot.lds
 create mode 100644 include/configs/openrisc-generic.h

Signed-off-by Stefan Kristiansson <[email protected]>

---

Changes in v2:
- None

 MAKEALL |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

Signed-off-by Stefan Kristiansson <[email protected]>

---

Changes in v2:
- None

 MAINTAINERS |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

This patch series adds support for the OpenRISC 1000 architecture.

The OpenRISC architecture has been around for about a decade and has experienced a revival in the last couple of years from the efforts of a small, but dedicated community compound of both commercial and independent contributors.

Most of the development takes place on opencores.org/or1k and openrisc.net.

The patches included in this series are also available in the 'for-upstream' branch in the following git repository:

git://openrisc.net/stefan/u-boot

which is also browsable here:

http://git.openrisc.net/cgit.cgi/stefan/u-boot/?h=for-upstream

NOTE: The openrisc-generic board depends on this pending patch to build properly:
net/ethoc: use flush_dcache_range instead of flush_dcache
(http://patchwork.ozlabs.org/patch/123622/)