ARM: Add generic instruction opcode manipulation helpers
PATCH v4 1/1 ARM: Add generic instruction opcode manipulation helpers
This patch adds some endianness-agnostic helpers to convert machine instructions between canonical integer form and in-memory representation.
A canonical integer form for representing instructions is also formalised here.
---
Changes since v1:
v4: Rebase on top of Leif's patch which created <asm/opcodes.h>
ARM: 7206/1: Add generic ARM instruction set condition code checks.
No functional changes.
v3: Fix some stupid errors:
* remove bogus extra (x) in __opcode_to_mem_arm
* fix use of nonexistent "thumb_opcode" argument in __opcode_thumb32_{first,second} which causes these macros to be broken.
v2: Remove unnecessary typedef for arm_opcode_t.
The general "everything is a word" concept works just fine here -- we don't need a typedef, and people will probably not use it anyway.
arch/arm/include/asm/opcodes.h | 68 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 68 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/opcodes.h
arch/arm/include/asm/opcodes.h new file +68 -0
@@ -0,0 +1,68 @@ +/* +* arch/arm/include/asm/opcodes.h +* +* Copyright (C) 2011 Linaro Limited +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#ifndef __ARM_OPCODES_H +#define __ARM_OPCODES_H + +#include <linux/types.h> +#include <linux/swab.h> + +/* +* Canonical instruction representation: +* +* ARM: 0xKKLLMMNN +* Thumb 16-bit: 0x0000KKLL, where KK < 0xE8 +* Thumb 32-bit: 0xKKLLMMNN, where KK >= 0xE8 +* +* There is no way to distinguish an ARM instruction in canonical representation +* from a Thumb instruction (just as these cannot be distinguished in memory). +* Where this distinction is important, it needs to be tracked separately. +* +* Note that values in the range 0x0000E800..0xE7FFFFFF intentionally do not +* represent any valid Thumb-2 instruction. For this range, +* __opcode_is_thumb32() and __opcode_is_thumb16() will both be false. +*/ + +#ifdef CONFIG_CPU_ENDIAN_BE8 +#define __opcode_to_mem_arm (x) swab32(x) +#define __opcode_to_mem_thumb16 (x) swab16(x) +#define __opcode_to_mem_thumb32 (x) swahb32(x) +#else +#define __opcode_to_mem_arm (x) ((u32)(x)) +#define __opcode_to_mem_thumb16 (x) ((u16)(x)) +#define __opcode_to_mem_thumb32 (x) swahw32(x) +#endif + +#define __mem_to_opcode_arm (x) __opcode_to_mem_arm(x) +#define __mem_to_opcode_thumb16 (x) __opcode_to_mem_thumb16(x) +#define __mem_to_opcode_thumb32 (x) __opcode_to_mem_thumb32(x) + +/* Operations specific to Thumb opcodes */ + +/* Instruction size checks: */ +#define __opcode_is_thumb32 (x) ((u32)(x) >= 0xE8000000UL) +#define __opcode_is_thumb16 (x) ((u32)(x) < 0xE800UL) + +/* Operations to construct or split 32-bit Thumb instructions: */ +#define __opcode_thumb32_first (x) ((u16)((x) >> 16)) +#define __opcode_thumb32_second (x) ((u16)(x)) +#define __opcode_thumb32_compose (first, second) \ + (((u32)(u16)(first) << 16) | (u32)(u16)(second)) + +#endif /* ! __ARM_OPCODES_H */
Signature · 5 lines
1.7.4.1 -------- arch/arm/include/asm/opcodes.h | 56 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 56 insertions(+), 0 deletions(-)
arch/arm/include/asm/opcodes.h +56 -0
66 lines not on this page · raw message
Signature · 1 line
1.7.4.1
PATCH v4 1/1 ARM: Add generic instruction opcode manipulation helpers
Quoted 7 lines · Dave Martin
This patch adds some endianness-agnostic helpers to convert machine instructions between canonical integer form and in-memory representation.
A canonical integer form for representing instructions is also formalised here.
Quoted 7 lines
Signed-off-by Dave Martin <[email protected]>Acked-by Nicolas Pitre <[email protected]>---
Changes since v1:v4: Rebase on top of Leif's patch which created <
asm/opcodes.h>
ARM: 7206/1: Add generic ARM instruction set condition code checks.
In that case you might be able to put your patch in the patch system, and then go back to add a note for Russell mentioning 7206/1 is a prerequisite.
Nicolas
PATCH v4 1/1 ARM: Add generic instruction opcode manipulation helpers
Quoted 14 lines · Nicolas Pitre
Quoted 12 lines · Dave Martin
This patch adds some endianness-agnostic helpers to convert machine instructions between canonical integer form and in-memory representation.
A canonical integer form for representing instructions is also formalised here.
Signed-off-by Dave Martin <[email protected]>Acked-by Nicolas Pitre <[email protected]>---
Changes since v1:
Quoted 6 lines
Quoted 2 lines
v4: Rebase on top of Leif's patch which created <
asm/opcodes.h>
ARM: 7206/1: Add generic ARM instruction set condition code checks.In that case you might be able to put your patch in the patch system, and then go back to add a note for Russell mentioning 7206/1 is a prerequisite.
OK, I'll try and do that.
Cheers
---Dave
PATCH v4 1/1 ARM: Add generic instruction opcode manipulation helpers
Quoted 10 lines · Dave Martin
Quoted 7 lines · Nicolas Pitre
Quoted 2 lines · Dave Martin
v4: Rebase on top of Leif's patch which created <
asm/opcodes.h> ? ? ARM: 7206/1: Add generic ARM instruction set condition code checks.In that case you might be able to put your patch in the patch system, and then go back to add a note for Russell mentioning 7206/1 is a prerequisite.
OK, I'll try and do that.
I notice it's there now as 7278/1, but there appears to be a problem with it. The patch system page shows the patch containing both the rebased and the earlier versions:
http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7278/1