arm, arm-kirkwood: disable l2c before linux boot

The decompressor expects the L2 cache to be disabled. This fixes booting some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled.

The decompressor expects the L2 cache to be disabled. This fixes booting some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled.

Signed-off-by Michael Walle <[email protected]>

Cc Albert ARIBAUD <[email protected]>

Cc Prafulla Wadaskar <[email protected]>

---
 arch/arm/cpu/arm926ejs/cache.c           |   15 +++++++++++
 arch/arm/cpu/arm926ejs/cpu.c             |    2 +
 arch/arm/cpu/arm926ejs/kirkwood/Makefile |    1 +
 arch/arm/cpu/arm926ejs/kirkwood/cache.c  |   41
++++++++++++++++++++++++++++++ 4 files changed, 59 insertions(+), 0
deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/kirkwood/cache.c

(quoted diff) +0 -0

b/arch/arm/cpu/arm926ejs/cache.c index 4415642..7a7d0a6 100644

arch/arm/cpu/arm926ejs/cache.c +15 -0

@@ -73,3 +73,18 @@ void  flush_cache(unsigned long start, unsigned long
 size) {
 }
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+/*
+ * Stub implementations for l2 cache operations
+ */
+void __l2_cache_enable(void)
+{
+}
+void l2_cache_enable(void)
+        __attribute__((weak, alias("__l2_cache_enable")));
+
+void __l2_cache_disable(void)
+{
+}
+void l2_cache_disable(void)
+        __attribute__((weak, alias("__l2_cache_disable")));

arch/arm/cpu/arm926ejs/cpu.c +2 -0

index 5c902df..626384c 100644
@@ -50,6 +50,8 @@ int cleanup_before_linux (void)
 	/* turn off I/D-cache */
 	icache_disable();
 	dcache_disable();
+	l2_cache_disable();
+
 	/* flush I/D-cache */
 	cache_flush();
 

(quoted diff) +0 -0

b/arch/arm/cpu/arm926ejs/kirkwood/Makefile index 0754297..777006c 100644

arch/arm/cpu/arm926ejs/kirkwood/Makefile +1 -0

@@ -30,6 +30,7 @@ COBJS-y	= cpu.o
 COBJS-y	+= dram.o
 COBJS-y	+= mpp.o
 COBJS-y	+= timer.o
+COBJS-y	+= cache.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))

(quoted diff) +0 -0

b/arch/arm/cpu/arm926ejs/kirkwood/cache.c new file mode 100644 index 0000000..84207f7

arch/arm/cpu/arm926ejs/kirkwood/cache.c new file +31 -0

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2011 Michael Walle
+ * Michael Walle <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+
+void l2_cache_enable()
+{
+	u32 ctrl;
+
+	ctrl = readfr_extra_feature_reg();
+	ctrl |= 1 << 22;	/* enable l2 cache */
+	writefr_extra_feature_reg(ctrl);

Please use #define <name> to define the magic value above (1 << 22) and then use it.

M

Am Montag 19 Dezember 2011, 00:04:18 schrieb Marek Vasut:
[..snip..]

Quoted 4 lines

Please use #define<name> to define the magic value above (1<< 22) and then use it.

M

The bit was taken from arch/arm/cpu/arm926ejs/kirkwood/cpu.c. Unfortunately there is no documentation publicly available, so i can only guess names.

FEROCEON_EXTRA_FEATURE_L2C_EN ?

Even the linux kernel has no proper macro names :(

I assume the patch was tested against a 3.2-rc1 kernel and also a pre-3.2-rc1 kernel to avoid regression?

The decompressor expects the L2 cache to be disabled. This fixes booting some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled.

Signed-off-by Michael Walle <[email protected]>

Cc Albert ARIBAUD <[email protected]>

Cc Prafulla Wadaskar <[email protected]>

---
 arch/arm/cpu/arm926ejs/cache.c           |   15 ++++++++++
 arch/arm/cpu/arm926ejs/cpu.c             |    2 +
 arch/arm/cpu/arm926ejs/kirkwood/Makefile |    1 +
 arch/arm/cpu/arm926ejs/kirkwood/cache.c  |   43
++++++++++++++++++++++++++++++ 4 files changed, 61 insertions(+), 0
deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/kirkwood/cache.c

(quoted diff) +0 -0

b/arch/arm/cpu/arm926ejs/cache.c index 4415642..7a7d0a6 100644

arch/arm/cpu/arm926ejs/cache.c +15 -0

@@ -73,3 +73,18 @@ void  flush_cache(unsigned long start, unsigned long
 size) {
 }
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+/*
+ * Stub implementations for l2 cache operations
+ */
+void __l2_cache_enable(void)
+{
+}
+void l2_cache_enable(void)
+        __attribute__((weak, alias("__l2_cache_enable")));
+
+void __l2_cache_disable(void)
+{
+}
+void l2_cache_disable(void)
+        __attribute__((weak, alias("__l2_cache_disable")));

arch/arm/cpu/arm926ejs/cpu.c +2 -0

index 5c902df..626384c 100644
@@ -50,6 +50,8 @@ int cleanup_before_linux (void)
 	/* turn off I/D-cache */
 	icache_disable();
 	dcache_disable();
+	l2_cache_disable();
+
 	/* flush I/D-cache */
 	cache_flush();
 

(quoted diff) +0 -0

b/arch/arm/cpu/arm926ejs/kirkwood/Makefile index 0754297..777006c 100644

arch/arm/cpu/arm926ejs/kirkwood/Makefile +1 -0

@@ -30,6 +30,7 @@ COBJS-y	= cpu.o
 COBJS-y	+= dram.o
 COBJS-y	+= mpp.o
 COBJS-y	+= timer.o
+COBJS-y	+= cache.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))

(quoted diff) +0 -0

b/arch/arm/cpu/arm926ejs/kirkwood/cache.c new file mode 100644 index 0000000..df90cb9

arch/arm/cpu/arm926ejs/kirkwood/cache.c new file +33 -0

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2011 Michael Walle
+ * Michael Walle <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+
+#define FEROCEON_EXTRA_FEATURE_L2C_EN (1<<22)
+
+void l2_cache_enable()
+{
+	u32 ctrl;
+
+	ctrl = readfr_extra_feature_reg();
+	ctrl |= FEROCEON_EXTRA_FEATURE_L2C_EN;
+	writefr_extra_feature_reg(ctrl);

The decompressor expects the L2 cache to be disabled. This fixes booting some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled.

Am Mittwoch 21 Dezember 2011, 00:35:46 schrieb Michael Walle:

Quoted 2 lines

The decompressor expects the L2 cache to be disabled. This fixes booting some kernels, which have CONFIG_ARM_PATCH_PHYS_VIRT enabled.

Ping :)

Also, I'm missing something: you introduce two functions, for enabling and disabling the cache, yet the code uses only the one for disabling. So what enabled it in the first place?

[Sorry can't answer to the original message, because it was blocked by spam filter]

Quoted 3 lines

Also, I'm missing something: you introduce two functions, for enabling and disabling the cache, yet the code uses only the one for disabling. So what enabled it in the first place?

The L2C is enabled in arch_misc_init() in
arch/arm/cpu/arm926ejs/kirkwood/cpu.c

My enable function is just for completeness atm.

Quoted 2 lines

My enable function is just for completeness atm.

Ping.

Is there something still uncertain?