nand_spl: store ecc data on the stack

PATCH New Scott Wood 2 participants 2 messages Jan 11, 2012 – Jan 12, 2012

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Scott Wood

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2012-01-11 22:34 UTC #0 lore raw

PATCH 1/1 nand_spl: store ecc data on the stack

Adapt the following patch from spl to nand_spl:

Author: Stefano Babic <[email protected]>
Date: Thu Dec 15 10:55:37 2011 +0100

nand_spl_simple: store ecc data on the stack

Currently nand_spl_simple puts it's temp data at 0x10000 offset in SDRAM which is likely to contain already loaded data.
The patch saves the oob data and the ecc on the stack replacing the fixed address in RAM.

Signed-off-by Stefano Babic <[email protected]>

CC Ilya Yanok <[email protected]>

CC Scott Wood <[email protected]>

CC Tom Rini <[email protected]>

CC Simon Schwarz <[email protected]>

CC Wolfgang Denk <[email protected]>

Signed-off-by Scott Wood <[email protected]>

While nand_spl is on its way out, in favor of spl, there are still many boards using it, and conversions are gradual. This allows us to get rid of CONFIG_SYS_NAND_ECCSTEPS and CONFIG_SYS_NAND_ECCTOTAL now, which would otherwise be likely to linger unreferenced after a conversion.

It also eliminates a temporary error in the hawkboard_nand build, since the spl version of the patch removed ECCSTEPS/TOTAL from hawkboard.h, but the spl conversion is pending (and may be merged via a different tree).

Signed-off-by Scott Wood <[email protected]>

---
 include/configs/PMC440.h         |    2 -
 include/configs/acadia.h         |    2 -
 include/configs/bamboo.h         |    2 -
 include/configs/cam_enc_4xx.h    |    3 --
 include/configs/canyonlands.h    |    2 -
 include/configs/kilauea.h        |    2 -
 include/configs/qi_lb60.h        |    4 ---
 include/configs/sequoia.h        |    2 -
 include/configs/smdk6400.h       |    4 ---
 include/configs/tam3517-common.h |    5 ----
 nand_spl/nand_boot.c             |   42 ++++++++++++++-----------------------
 11 files changed, 16 insertions(+), 54 deletions(-)

include/configs/PMC440.h +0 -2

index ed47a87..b820954 100644
@@ -200,9 +200,7 @@
 
 #define CONFIG_SYS_NAND_ECCSIZE	256
 #define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
 #define CONFIG_SYS_NAND_OOBSIZE	16
-#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 #define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
 #endif

include/configs/acadia.h +0 -2

index 5573dc7..8c447ca 100644
@@ -185,9 +185,7 @@
 
 #define CONFIG_SYS_NAND_ECCSIZE	256
 #define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
 #define CONFIG_SYS_NAND_OOBSIZE	16
-#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 #define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
 
 #ifdef CONFIG_ENV_IS_IN_NAND

include/configs/bamboo.h +0 -2

index 7b66fc0..506a558 100644
@@ -179,9 +179,7 @@
 
 #define CONFIG_SYS_NAND_ECCSIZE	256
 #define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
 #define CONFIG_SYS_NAND_OOBSIZE	16
-#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 #define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
 
 #ifdef CONFIG_ENV_IS_IN_NAND

include/configs/cam_enc_4xx.h +0 -3

index 86f74df..5d9672f 100644
@@ -235,9 +235,6 @@
 #define CONFIG_SYS_NAND_ECCBYTES	10
 #define CONFIG_SYS_NAND_OOBSIZE		64
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE /	 \
-					 CONFIG_SYS_NAND_ECCSIZE)
-#define CONFIG_SYS_NAND_ECCTOTAL	(40)
 
 /*
  * RBL searches from Block n (n = 1..24)

include/configs/canyonlands.h +0 -2

index 8c03582..acb127c 100644
@@ -197,9 +197,7 @@
 
 #define CONFIG_SYS_NAND_ECCSIZE	256
 #define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
 #define CONFIG_SYS_NAND_OOBSIZE	64
-#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 #define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47, \
 				 48, 49, 50, 51, 52, 53, 54, 55, \
 				 56, 57, 58, 59, 60, 61, 62, 63}

include/configs/kilauea.h +0 -2

index e66aadf..621dbb8 100644
@@ -210,9 +210,7 @@
 
 #define CONFIG_SYS_NAND_ECCSIZE	256
 #define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
 #define CONFIG_SYS_NAND_OOBSIZE	16
-#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 #define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
 
 #ifdef CONFIG_ENV_IS_IN_NAND

include/configs/qi_lb60.h +0 -4

index f2e605a..ebd8223 100644
@@ -99,10 +99,6 @@
 #define CONFIG_SYS_NAND_ECC_POS		(6 * NANONOTE_NAND_SIZE)
 #define CONFIG_SYS_NAND_ECCSIZE		512
 #define CONFIG_SYS_NAND_ECCBYTES	9
-#define CONFIG_SYS_NAND_ECCSTEPS	\
-	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
-#define CONFIG_SYS_NAND_ECCTOTAL	\
-	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 #define CONFIG_SYS_NAND_ECCPOS		\
 		{12, 13, 14, 15, 16, 17, 18, 19,\
 		20, 21, 22, 23, 24, 25, 26, 27, \

include/configs/sequoia.h +0 -2

index a406ca0..8e6954e 100644
@@ -205,9 +205,7 @@
 
 #define CONFIG_SYS_NAND_ECCSIZE	256
 #define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
 #define CONFIG_SYS_NAND_OOBSIZE	16
-#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 #define CONFIG_SYS_NAND_ECCPOS		{0, 1, 2, 3, 6, 7}
 
 #ifdef CONFIG_ENV_IS_IN_NAND

include/configs/smdk6400.h +0 -4

index 4d0b7b2..a2b9441 100644
@@ -262,12 +262,8 @@
 #define CONFIG_SYS_NAND_ECCSIZE	CONFIG_SYS_NAND_PAGE_SIZE
 /* Number of ECC bytes per OOB - S3C6400 calculates 4 bytes ECC in 1-bit mode */
 #define CONFIG_SYS_NAND_ECCBYTES	4
-/* Number of ECC-blocks per NAND page */
-#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
 /* Size of a single OOB region */
 #define CONFIG_SYS_NAND_OOBSIZE	64
-/* Number of ECC bytes per page */
-#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 /* ECC byte positions */
 #define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47, \
 				 48, 49, 50, 51, 52, 53, 54, 55, \

include/configs/tam3517-common.h +0 -5

index 817d468..f4963ac 100644
@@ -278,11 +278,6 @@
 #define CONFIG_SYS_NAND_ECCSIZE		256
 #define CONFIG_SYS_NAND_ECCBYTES	3
 
-#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
-						CONFIG_SYS_NAND_ECCSIZE)
-#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * \
-						CONFIG_SYS_NAND_ECCSTEPS)
-
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000

nand_spl/nand_boot.c +16 ~~-26~~

85 lines not on this page · raw message

Signature · 1 line

1.7.7.rc3.4.g8d714

Stefan Roese

2012-01-12 07:02 UTC #1 lore raw

PATCH 1/1 nand_spl: store ecc data on the stack

Quoted 20 lines · On Wednesday 11 January 2012 23:34:35 Scott Wood wrote:

Adapt the following patch from spl to nand_spl:
Author: Stefano Babic <[email protected]>
Date: Thu Dec 15 10:55:37 2011 +0100
nand_spl_simple: store ecc data on the stack
Currently nand_spl_simple puts it's temp data at 0x10000 offset in
SDRAM which is likely to contain already loaded data.
The patch saves the oob data and the ecc on the stack replacing the fixed address in RAM.
Signed-off-by Stefano Babic <[email protected]>
CC Ilya Yanok <[email protected]>
CC Scott Wood <[email protected]>
CC Tom Rini <[email protected]>
CC Simon Schwarz <[email protected]>
CC Wolfgang Denk <[email protected]>
Signed-off-by Scott Wood <[email protected]>

Quoted 8 lines

While nand_spl is on its way out, in favor of spl, there are still many boards using it, and conversions are gradual. This allows us to get rid of CONFIG_SYS_NAND_ECCSTEPS and CONFIG_SYS_NAND_ECCTOTAL now, which would otherwise be likely to linger unreferenced after a conversion.
It also eliminates a temporary error in the hawkboard_nand build, since the spl version of the patch removed ECCSTEPS/TOTAL from hawkboard.h, but the spl conversion is pending (and may be merged via a different tree).

Thanks Scott.

Tested on kilauea_nand, so:

Tested-by Stefan Roese <[email protected]>

Best regards,
Stefan

--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office at denx.de

From urwithsughosh at Hardy Thu Jan 12 07:23:12 2012
From: urwithsughosh at Hardy (Sughosh Ganu)
Date: Thu, 12 Jan 2012 11:53:12 +0530
Subject: [U-Boot] [PATCH 1/2 V2] arm926: Flush the data cache before
disabling it.
In-Reply-To: <[email protected]>
References: <[email protected]>

	<[email protected]>
	<20120111150952.GB4301@Hardy>
	<[email protected]>

Message-ID: <20120112062312.GA5879@Hardy>

Quoted 9 lines · Marek Vasut

Quoted 9 lines · Marek Vasut
Quoted 8 lines
Quoted 7 lines
More so, given the fact that we don't have any control over rbl -- so if rbl changes it's layout for any subsequent board, we'd have to add that as well to the nand driver, and both in u-boot as well as the kernel.
I guess the cleanest solution would have been for the rbl to have used the same layout as the one used by u-boot and linux.

Quoted 6 lines

Quoted 3 lines
Quoted 1 line
Yep, why not do that then?
Because rbl is a proprietary bootloader from TI.
Don't we actually have replacement bootloader in uboot already ? You don't need xloader with uboot anymore I think.

No, this rbl resides in the rom area on the SOC and cannot be done away with.

Quoted 4 lines

Quoted 4 lines
Quoted 4 lines
Quoted 3 lines
Btw, can you please review this change, that this patch fixes. ACK/NAK?

Quoted 8 lines

Quoted 6 lines
Quoted 2 lines
I'll think about it. It's ok, but it piles one workaround on top of another one, I don't like that approach.
Flushing the data cache before disabling it is not a workaround, it's a fix. The current code is invalidating the cache instead of flushing it.
Ok, but I'd like to see proper solution eventually.

I think patch holds true irrespective of whether we rbl boots spl, or u-boot.

-sughosh