reset edge sense circuit of i8259 on init
PATCH 1/1 reset edge sense circuit of i8259 on init
The spec says that during initialization "The edge sense circuit is reset which means that following initialization an interrupt request (IR) input must make a low-to-high transition to generate an interrupt", but currently if edge triggered interrupt is in IRR it is delivered after i8259 initialization.
arch/x86/kvm/i8259.c +1 -0
@@ -307,6 +307,7 @@ static void pic_ioport_write(void *opaque, u32 addr, u32 val)if (val &0x10 ) { s->init4 = val &1 ; s->last_irr =0 ; + s->irr &= s->elcr; s->imr =0 ; s->priority_add =0 ; s->special_mask =0 ;
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Gleb.
Quoted 12 lines · Gleb Natapov
The spec says that during initialization "The edge sense circuit is reset which means that following initialization an interrupt request (IR) input must make a low-to-high transition to generate an interrupt", but currently if edge triggered interrupt is in IRR it is delivered after i8259 initialization.
Signed-off-by Gleb Natapov <[email protected]>arch/x86/kvm/i8259.c +0
-0
arch/x86/kvm/i8259.c static void pic_ioport_write(void *opaque, u32 addr, u32 val) · line 310
Quoted 4 lines
arch/x86/kvm/i8259.c +1
-0@@ -307,6 +307,7 @@ static void pic_ioport_write(void *opaque, u32 addr, u32 val)if (val &0x10 ) { s->init4 = val &1 ; s->last_irr =0 ; + s->irr &= s->elcr;
Does & elcr make a relevant difference? QEMU simply sets irr to 0. If that's an issue, we need to fix both.
Jan
Signature · 2 lines
Siemens AG, Corporate Technology, CT T DE IT 1 Corporate Competence Center Embedded Linux
Quoted 7 lines · Jan Kiszka
Quoted 6 lines · Gleb Natapov
The spec says that during initialization "The edge sense circuit is reset which means that following initialization an interrupt request (IR) input must make a low-to-high transition to generate an interrupt", but currently if edge triggered interrupt is in IRR it is delivered after i8259 initialization.
Quoted 14 lines
arch/x86/kvm/i8259.c static void pic_ioport_write(void *opaque, u32 addr, u32 val) · line 310
Quoted 10 lines
Signed-off-by Gleb Natapov <[email protected]>arch/x86/kvm/i8259.c +1
-0@@ -307,6 +307,7 @@ static void pic_ioport_write(void *opaque, u32 addr, u32 val)if (val &0x10 ) { s->init4 = val &1 ; s->last_irr =0 ; + s->irr &= s->elcr;Does & elcr make a relevant difference? QEMU simply sets irr to 0. If that's an issue, we need to fix both.
I saw what QEMU does. It's hard to tell looking at the spec what's more correct. I think by zeroing irr we may lose level triggered interrupts that happened just before init.
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Gleb.
Quoted 22 lines · Gleb Natapov
Quoted 7 lines · Jan Kiszka
Quoted 6 lines · Gleb Natapov
The spec says that during initialization "The edge sense circuit is reset which means that following initialization an interrupt request (IR) input must make a low-to-high transition to generate an interrupt", but currently if edge triggered interrupt is in IRR it is delivered after i8259 initialization.
Quoted 14 lines
arch/x86/kvm/i8259.c static void pic_ioport_write(void *opaque, u32 addr, u32 val) · line 310
Quoted 10 lines
Signed-off-by Gleb Natapov <[email protected]>arch/x86/kvm/i8259.c +1
-0@@ -307,6 +307,7 @@ static void pic_ioport_write(void *opaque, u32 addr, u32 val)if (val &0x10 ) { s->init4 = val &1 ; s->last_irr =0 ; + s->irr &= s->elcr;Does & elcr make a relevant difference? QEMU simply sets irr to 0. If that's an issue, we need to fix both.
Quoted 3 lines
I saw what QEMU does. It's hard to tell looking at the spec what's more correct. I think by zeroing irr we may lose level triggered interrupts that happened just before init.
Right. If those are supposed to get through despite init, then it is a QEMU bug. Will read the spec again as well.
Jan
Signature · 2 lines
Siemens AG, Corporate Technology, CT T DE IT 1 Corporate Competence Center Embedded Linux
Quoted 23 lines · Jan Kiszka
Quoted 22 lines · Gleb Natapov
Quoted 21 lines · Jan Kiszka
Quoted 12 lines · Gleb Natapov
The spec says that during initialization "The edge sense circuit is reset which means that following initialization an interrupt request (IR) input must make a low-to-high transition to generate an interrupt", but currently if edge triggered interrupt is in IRR it is delivered after i8259 initialization.
Signed-off-by Gleb Natapov <[email protected]>arch/x86/kvm/i8259.c +0
-0arch/x86/kvm/i8259.c static void pic_ioport_write(void *opaque, u32 addr, u32 val) · line 310
Quoted 4 lines
arch/x86/kvm/i8259.c +1
-0@@ -307,6 +307,7 @@ static void pic_ioport_write(void *opaque, u32 addr, u32 val)if (val &0x10 ) { s->init4 = val &1 ; s->last_irr =0 ; + s->irr &= s->elcr;Does & elcr make a relevant difference? QEMU simply sets irr to 0. If that's an issue, we need to fix both.
Quoted 7 lines
Quoted 3 lines
I saw what QEMU does. It's hard to tell looking at the spec what's more correct. I think by zeroing irr we may lose level triggered interrupts that happened just before init.
Right. If those are supposed to get through despite init, then it is a QEMU bug. Will read the spec again as well.
On real HW they should go through if the IR line is still high.
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Gleb.
Quoted 24 lines · Gleb Natapov
Quoted 23 lines · Jan Kiszka
Quoted 22 lines · Gleb Natapov
Quoted 21 lines · Jan Kiszka
Quoted 12 lines · Gleb Natapov
The spec says that during initialization "The edge sense circuit is reset which means that following initialization an interrupt request (IR) input must make a low-to-high transition to generate an interrupt", but currently if edge triggered interrupt is in IRR it is delivered after i8259 initialization.
Signed-off-by Gleb Natapov <[email protected]>arch/x86/kvm/i8259.c +0
-0arch/x86/kvm/i8259.c static void pic_ioport_write(void *opaque, u32 addr, u32 val) · line 310
Quoted 4 lines
arch/x86/kvm/i8259.c +1
-0@@ -307,6 +307,7 @@ static void pic_ioport_write(void *opaque, u32 addr, u32 val)if (val &0x10 ) { s->init4 = val &1 ; s->last_irr =0 ; + s->irr &= s->elcr;Does & elcr make a relevant difference? QEMU simply sets irr to 0. If that's an issue, we need to fix both.
Quoted 8 lines
Quoted 7 lines
Quoted 3 lines
I saw what QEMU does. It's hard to tell looking at the spec what's more correct. I think by zeroing irr we may lose level triggered interrupts that happened just before init.
Right. If those are supposed to get through despite init, then it is a QEMU bug. Will read the spec again as well.
On real HW they should go through if the IR line is still high.
Looks like. IMR is cleared, so a level-triggered IRQ is free to pass and set IRR again - even if the chip clears it internally. Will write a patch.
Jan
Signature · 2 lines
Siemens AG, Corporate Technology, CT T DE IT 1 Corporate Competence Center Embedded Linux
Quoted 6 lines · Gleb Natapov
The spec says that during initialization "The edge sense circuit is reset which means that following initialization an interrupt request (IR) input must make a low-to-high transition to generate an interrupt", but currently if edge triggered interrupt is in IRR it is delivered after i8259 initialization.
ping
Quoted 14 lines
Signed-off-by Gleb Natapov <[email protected]>arch/x86/kvm/i8259.c +1
-1@@ -307,6 +307,7 @@ static void pic_ioport_write(void *opaque, u32 addr, u32 val)if (val &0x10 ) { s->init4 = val &1 ; s->last_irr =0 ; + s->irr &= s->elcr; s->imr =0 ; s->priority_add =0 ; s->special_mask =0 ; --
Quoted 5 lines
Gleb.
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Gleb.
Marcelo Tosatti
AppliedQuoted 5 lines · Gleb Natapov
The spec says that during initialization "The edge sense circuit is reset which means that following initialization an interrupt request (IR) input must make a low-to-high transition to generate an interrupt", but currently if edge triggered interrupt is in IRR it is delivered after i8259 initialization.
Applied, thanks.