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Pending S3C64xx updates

PATCH New Mark Brown 2 participants 7 messages Jan 24, 2012 – Jan 27, 2012

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Arm (32-bit) Arm sub-architectures Arm Samsung Exynos
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Mark Brown

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#0 lore raw

cover Pending S3C64xx updates

This patch series is a collection of s3c64xx updates I've had hanging round in my tree for varying lengths of time that it'd be good to get merged. There's no particularly relationship between them except that they're all for s3c64xx.

Mark Brown (4):
ARM: S3C64XX: Make s3c64xx_init_uarts() static
ARM: S3C64XX: Define some additional always off clocks
ARM: S3C6410: Use device names for both I2C clocks
ARM: S3C64XX: Add hookup for Tomatin module on Cragganmore

 arch/arm/mach-s3c64xx/clock.c                |  106 ++++++++++++++++++++++++++
 arch/arm/mach-s3c64xx/common.c               |    2 +-
 arch/arm/mach-s3c64xx/mach-crag6410-module.c |   27 ++++++-
 arch/arm/mach-s3c64xx/mach-crag6410.c        |   11 +++-
 4 files changed, 143 insertions(+), 3 deletions(-)

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author
#1 lore raw

PATCH 1/4 ARM: S3C64XX: Make s3c64xx_init_uarts() static

Now that it's in common.c it's not used in multiple source files.

Signed-off-by Mark Brown <[email protected]>
---
 arch/arm/mach-s3c64xx/common.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
arch/arm/mach-s3c64xx/common.c +1 -1
index 4a7394d..bee7dcd 100644
@@ -49,7 +49,7 @@
 
 /* uart registration process */
 
-void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 {
 	s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
 }
Signature · 1 line
1.7.9.rc1
author
#2 lore raw

PATCH 2/4 ARM: S3C64XX: Define some additional always off clocks

Add entries to clocks_off for some additional clocks which are not currently used by any mainline drivers. They default on at power up but are never actually used so

If these blocks are actually supported some of these bindings would need to be redone properly, for example hooking up to the muxes that use them, but that can be done incrementally.

Signed-off-by Mark Brown <[email protected]>
---
 arch/arm/mach-s3c64xx/clock.c |  101 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 101 insertions(+), 0 deletions(-)
arch/arm/mach-s3c64xx/clock.c +101 -0
index b58274f..63f2c8a 100644
@@ -220,6 +220,107 @@ static struct clk init_clocks_off[] = {
 		.parent		= &clk_h,
 		.enable		= s3c64xx_hclk_ctrl,
 		.ctrlbit	= S3C_CLKCON_HCLK_DMA1,
+	}, {
+		.name		= "3dse",
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_3DSE,
+	}, {
+		.name		= "hclk_secur",
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_SECUR,
+	}, {
+		.name		= "sdma1",
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_SDMA1,
+	}, {
+		.name		= "sdma0",
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_SDMA0,
+	}, {
+		.name		= "hclk_jpeg",
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_JPEG,
+	}, {
+		.name		= "camif",
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_CAMIF,
+	}, {
+		.name		= "hclk_scaler",
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_SCALER,
+	}, {
+		.name		= "2d",
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_2D,
+	}, {
+		.name		= "tv",
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_TV,
+	}, {
+		.name		= "post0",
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_POST0,
+	}, {
+		.name		= "rot",
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_ROT,
+	}, {
+		.name		= "hclk_mfc",
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_MFC,
+	}, {
+		.name		= "pclk_mfc",
+		.parent		= &clk_p,
+		.enable		= s3c64xx_pclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_PCLK_MFC,
+	}, {
+		.name		= "dac27",
+		.enable		= s3c64xx_sclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_SCLK_DAC27,
+	}, {
+		.name		= "tv27",
+		.enable		= s3c64xx_sclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_SCLK_TV27,
+	}, {
+		.name		= "scaler27",
+		.enable		= s3c64xx_sclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_SCLK_SCALER27,
+	}, {
+		.name		= "sclk_scaler",
+		.enable		= s3c64xx_sclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_SCLK_SCALER,
+	}, {
+		.name		= "post0_27",
+		.enable		= s3c64xx_sclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_SCLK_POST0_27,
+	}, {
+		.name		= "secur",
+		.enable		= s3c64xx_sclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_SCLK_SECUR,
+	}, {
+		.name		= "sclk_mfc",
+		.enable		= s3c64xx_sclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_SCLK_MFC,
+	}, {
+		.name		= "cam",
+		.enable		= s3c64xx_sclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_SCLK_CAM,
+	}, {
+		.name		= "sclk_jpeg",
+		.enable		= s3c64xx_sclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_SCLK_JPEG,
 	},
 };
Signature · 1 line
1.7.9.rc1
author
#3 lore raw

PATCH 3/4 ARM: S3C6410: Use device names for both I2C clocks

In reply to Mark Brown

When the S3C64xx CPUs were converted to clkdev mappings were added for the I2C controllers on them. On S3C6410 a device name is specified for I2C controller 1 but not for controller 0 which makes the code less robust as we'll falsely return the clock for controller 0 if there's an error in the request for controller 1.

Improve things by registering a device name for controller 0 as well. Due to the fact that we change the numbering for controller 0 depending on if we've registered controller 1 this requires an ifdef to choose the name.

Signed-off-by Mark Brown <[email protected]>
---
 arch/arm/mach-s3c64xx/clock.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)
arch/arm/mach-s3c64xx/clock.c +5 -0
index 63f2c8a..52f079a 100644
@@ -138,6 +138,11 @@ static struct clk init_clocks_off[] = {
 		.ctrlbit	= S3C_CLKCON_PCLK_TSADC,
 	}, {
 		.name		= "i2c",
+#ifdef CONFIG_S3C_DEV_I2C1
+		.devname        = "s3c2440-i2c.0",
+#else
+		.devname	= "s3c2440-i2c",
+#endif
 		.parent		= &clk_p,
 		.enable		= s3c64xx_pclk_ctrl,
 		.ctrlbit	= S3C_CLKCON_PCLK_IIC,
Signature · 1 line
1.7.9.rc1
author
#4 lore raw

PATCH 4/4 ARM: S3C64XX: Add hookup for Tomatin module on Cragganmore

In reply to Mark Brown

The Tomatin module carries a WM0010 audio DSP. Provide basic hookup for this, though additional platform data will be needed to fully integrate with the driver.

Signed-off-by Mark Brown <[email protected]>
---
 arch/arm/mach-s3c64xx/mach-crag6410-module.c |   27 +++++++++++++++++++++++++-
 arch/arm/mach-s3c64xx/mach-crag6410.c        |   11 +++++++++-
 2 files changed, 36 insertions(+), 2 deletions(-)
arch/arm/mach-s3c64xx/mach-crag6410-module.c +26 -1
index cd3c97e..b4ed351 100644
@@ -11,6 +11,7 @@
 #include <linux/export.h>
 #include <linux/interrupt.h>
 #include <linux/i2c.h>
+#include <linux/spi/spi.h>
 
 #include <linux/mfd/wm831x/irq.h>
 #include <linux/mfd/wm831x/gpio.h>

@@ -21,8 +22,25 @@
 #include <sound/wm8962.h>
 #include <sound/wm9081.h>
 
+#include <plat/s3c64xx-spi.h>
+
 #include <mach/crag6410.h>
 
+static struct s3c64xx_spi_csinfo wm0010_spi_csinfo = {
+	.set_level = gpio_set_value,
+	.line = S3C64XX_GPC(3),
+};
+
+static struct spi_board_info wm1253_devs[] = {
+	[0] = {
+		.modalias	= "wm0010",
+		.bus_num	= 0,
+		.chip_select	= 0,
+		.mode		= SPI_MODE_0,
+		.controller_data = &wm0010_spi_csinfo,
+	},
+};
+
 static struct wm5100_pdata wm5100_pdata = {
 	.ldo_ena = S3C64XX_GPN(7),
 	.irq_flags = IRQF_TRIGGER_HIGH,

@@ -158,6 +176,8 @@ static __devinitdata const struct {
 	const char *name;
 	const struct i2c_board_info *i2c_devs;
 	int num_i2c_devs;
+	const struct spi_board_info *spi_devs;
+	int num_spi_devs;
 } gf_mods[] = {
 	{ .id = 0x01, .name = "1250-EV1 Springbank" },
 	{ .id = 0x02, .name = "1251-EV1 Jura" },

@@ -165,7 +185,8 @@ static __devinitdata const struct {
 	{ .id = 0x11, .name = "6249-EV2 Glenfarclas", },
 	{ .id = 0x21, .name = "1275-EV1 Mortlach" },
 	{ .id = 0x25, .name = "1274-EV1 Glencadam" },
-	{ .id = 0x31, .name = "1253-EV1 Tomatin", },
+	{ .id = 0x31, .name = "1253-EV1 Tomatin",
+	  .spi_devs = wm1253_devs, .num_spi_devs = ARRAY_SIZE(wm1253_devs) },
 	{ .id = 0x39, .name = "1254-EV1 Dallas Dhu",
 	  .i2c_devs = wm1254_devs, .num_i2c_devs = ARRAY_SIZE(wm1254_devs) },
 	{ .id = 0x3a, .name = "1259-EV1 Tobermory",

@@ -197,12 +218,16 @@ static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
 	if (i < ARRAY_SIZE(gf_mods)) {
 		dev_info(&i2c->dev, "%s revision %d\n",
 			 gf_mods[i].name, rev + 1);
+
 		for (j = 0; j < gf_mods[i].num_i2c_devs; j++) {
 			if (!i2c_new_device(i2c->adapter,
 					    &(gf_mods[i].i2c_devs[j])))
 				dev_err(&i2c->dev,
 					"Failed to register dev: %d\n", ret);
 		}
+
+		spi_register_board_info(gf_mods[i].spi_devs,
+					gf_mods[i].num_spi_devs);
 	} else {
 		dev_warn(&i2c->dev, "Unknown module ID 0x%x revision %d\n",
 			 id, rev + 1);
arch/arm/mach-s3c64xx/mach-crag6410.c +10 -1
index 5b43a57..cdbc8cb 100644
@@ -581,11 +581,19 @@ static struct s3c2410_platform_i2c i2c0_pdata = {
 	.frequency = 400000,
 };
 
+static struct regulator_consumer_supply pvdd_1v2_consumers[] __initdata = {
+	REGULATOR_SUPPLY("DCVDD", "spi0.0"),
+	REGULATOR_SUPPLY("AVDD", "spi0.0"),
+};
+
 static struct regulator_init_data pvdd_1v2 __initdata = {
 	.constraints = {
 		.name = "PVDD_1V2",
-		.always_on = 1,
+		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
 	},
+
+	.consumer_supplies = pvdd_1v2_consumers,
+	.num_consumer_supplies = ARRAY_SIZE(pvdd_1v2_consumers),
 };
 
 static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = {

@@ -599,6 +607,7 @@ static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = {
 	REGULATOR_SUPPLY("AVDD2", "1-001a"),
 	REGULATOR_SUPPLY("DCVDD", "1-001a"),
 	REGULATOR_SUPPLY("AVDD", "1-001a"),
+	REGULATOR_SUPPLY("DBVDD", "spi0.0"),
 };
 
 static struct regulator_init_data pvdd_1v8 __initdata = {
Signature · 1 line
1.7.9.rc1
#5 lore raw

cover Pending S3C64xx updates

In reply to Mark Brown
Quoted 1 line · Mark Brown

Hi Mark,

Quoted 5 lines

This patch series is a collection of s3c64xx updates I've had hanging round in my tree for varying lengths of time that it'd be good to get merged. There's no particularly relationship between them except that they're all for s3c64xx.

OK, see my comments below.

Quoted 2 lines

Mark Brown (4):

      ARM: S3C64XX: Make s3c64xx_init_uarts() static

As I commented, I have pushed this into rmk's patch system but not applied yet. I discarded that just now in there so that I can apply this in my tree.

Quoted 1 line

ARM: S3C64XX: Define some additional always off clocks

Hmm, I know there were discussions about this with Tomasz Figa and I was waiting for his submitting. But now this looks ok to me so will apply this.

Quoted 1 line

ARM: S3C6410: Use device names for both I2C clocks

OK, will apply and let me sort out the #ifdef in Samsung stuff for single zImage later.

Quoted 1 line

ARM: S3C64XX: Add hookup for Tomatin module on Cragganmore

Already in my next/board-samsung.

Quoted 7 lines
 arch/arm/mach-s3c64xx/clock.c                |  106
++++++++++++++++++++++++++
 arch/arm/mach-s3c64xx/common.c               |    2 +-
 arch/arm/mach-s3c64xx/mach-crag6410-module.c |   27 ++++++-
 arch/arm/mach-s3c64xx/mach-crag6410.c        |   11 +++-
 4 files changed, 143 insertions(+), 3 deletions(-)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

author
#6 lore raw

cover Pending S3C64xx updates

Quoted 6 lines · Kukjin Kim
Quoted 1 line · Mark Brown

ARM: S3C64XX: Define some additional always off clocks

Hmm, I know there were discussions about this with Tomasz Figa and I was waiting for his submitting. But now this looks ok to me so will apply this.

The discussion there was around there being other out of tree drivers
that might at some point want to use these clocks - I don't think there
was any doubt that for current mainline this change makes sense.
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