ARM: OMAP2+: hwmod/timer: first set of cleanups for 3.4

This series does some cleanup and documentation on the OMAP hwmod code (and a bit of the OMAP4 data) and timer code. It is the first prerequisite series to removing a big chunk of hwmod data -- that will be done in a later series.

Boot-tested on an OMAP35xx BeagleBoard and OMAP44xx ES2 Pandaboard.

This series is also available via git from git://git.pwsan.com/linux-2.6 in the branch "hwmod_code_cleanup_3.4".

- Paul

---

hwmod_code_cleanup_3.4
text data bss dec hex filename
6592293 678588 5590684 12861565 c4407d vmlinux.orig
6592597 677948 5590684 12861229 c43f2d vmlinux.patched

Paul Walmsley (7):
ARM: OMAP2+: hwmod: control all hardreset lines attached to a hwmod
ARM: OMAP4: hwmod data: remove pseudo-hwmods associated with hardreset lines
ARM: OMAP2+: hwmod: ensure that SYSCONFIG bits are reprogrammed after a reset
ARM: OMAP2+: hwmod: provide a function to return the address space of the MPU RT
ARM: OMAP2+: hwmod: add omap_hwmod_get_mpu_irq() and omap_hwmod_get_mpu_rt_pa()
ARM: OMAP2+: timer: use a proper interface to get hwmod data
ARM: OMAP2+: hwmod: split the _setup() function

 arch/arm/mach-omap2/omap_hwmod.c             |  345 +++++++++++++++++++-------
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c   |  101 --------
 arch/arm/mach-omap2/timer.c                  |    8 -
 arch/arm/plat-omap/include/plat/omap_hwmod.h |    3 
 4 files changed, 263 insertions(+), 194 deletions(-)

Parts of the hwmod code test to see if a module has one and only one hardreset line before taking an action. It seems more appropriate to control all hardreset lines associated with a hwmod, not just one.

It so happens that with the current hwmod data, this will not change any behavior, since hwmods with hardreset lines have only one hardreset line associated with them, and 'pseudo-hwmods' are used to handle the other hardreset lines. But future hwmod data patches to remove the pseudo-hwmods will change this.

---
 arch/arm/mach-omap2/omap_hwmod.c |   29 +++++++++++++++--------------
 1 files changed, 15 insertions(+), 14 deletions(-)

index 5192cab..0ef2710 100644
@@ -1475,6 +1475,11 @@ static int _reset(struct omap_hwmod *oh)
 
 	pr_debug("omap_hwmod: %s: resetting\n", oh->name);
 
+	/*
+	 * XXX We're not resetting modules with hardreset lines
+	 * automatically here.  Should we do this also, or just expect
+	 * those modules to define custom reset functions?
+	 */
 	ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh);
 
 	return ret;

@@ -1490,7 +1495,7 @@ static int _reset(struct omap_hwmod *oh)
  */
 static int _enable(struct omap_hwmod *oh)
 {
-	int r;
+	int r, i;
 	int hwsup = 0;
 
 	pr_debug("omap_hwmod: %s: enabling\n", oh->name);

@@ -1522,15 +1527,15 @@ static int _enable(struct omap_hwmod *oh)
 		return -EINVAL;
 	}
 
-
 	/*
-	 * If an IP contains only one HW reset line, then de-assert it in order
+	 * If an IP contains HW reset lines, then de-assert them in order
 	 * to allow the module state transition. Otherwise the PRCM will return
 	 * Intransition status, and the init will failed.
 	 */
-	if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
-	     oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
-		_deassert_hardreset(oh, oh->rst_lines[0].name);
+	if (oh->_state == _HWMOD_STATE_INITIALIZED ||
+	    oh->_state == _HWMOD_STATE_DISABLED)
+		for (i = 0; i < oh->rst_lines_cnt; i++)
+			_deassert_hardreset(oh, oh->rst_lines[i].name);
 
 	/* Mux pins for device runtime if populated */
 	if (oh->mux && (!oh->mux->enabled ||

@@ -1677,7 +1682,7 @@ int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle)
  */
 static int _shutdown(struct omap_hwmod *oh)
 {
-	int ret;
+	int ret, i;
 	u8 prev_state;
 
 	if (oh->_state != _HWMOD_STATE_IDLE &&

@@ -1718,12 +1723,8 @@ static int _shutdown(struct omap_hwmod *oh)
 	}
 	/* XXX Should this code also force-disable the optional clocks? */
 
-	/*
-	 * If an IP contains only one HW reset line, then assert it
-	 * after disabling the clocks and before shutting down the IP.
-	 */
-	if (oh->rst_lines_cnt == 1)
-		_assert_hardreset(oh, oh->rst_lines[0].name);
+	for (i = 0; i < oh->rst_lines_cnt; i++)
+		_assert_hardreset(oh, oh->rst_lines[i].name);
 
 	/* Mux pins to safe mode or use populated off mode values */
 	if (oh->mux)

@@ -1776,7 +1777,7 @@ static int _setup(struct omap_hwmod *oh, void *data)
 	 * reset asserted. Exit without warning because that behavior is
 	 * expected.
 	 */
-	if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1)
+	if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt > 0)
 		return 0;
 
 	r = _enable(oh);

Remove the pseudo-hwmods associated with hardreset lines from the OMAP4 data file. Future patches will convert this data to register hwmods by interfaces, rather than registering hwmods directly; and these pseudo-hwmods aren't associated with any interfaces.

The hwmod code now resets processor IPs at the hwmod level, rather than individually. So, for example, if the IVA device driver code wishes to place one of the sequencer cores into reset, while leaving the other active, it must do so itself by calling the appropriate PRM functions.

This patch will cause a change in the initialization behavior of the DSP, IVA, and IPU.

---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  101 +---------------------------
 1 files changed, 3 insertions(+), 98 deletions(-)

index f9f1510..a3efb9e 100644
@@ -1105,11 +1105,8 @@ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 };
 
 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
-	{ .name = "mmu_cache", .rst_shift = 1 },
-};
-
-static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
 	{ .name = "dsp", .rst_shift = 0 },
+	{ .name = "mmu_cache", .rst_shift = 1 },
 };
 
 /* dsp -> iva */

@@ -1139,21 +1136,6 @@ static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
 	&omap44xx_l4_cfg__dsp,
 };
 
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
-	.name		= "dsp_c0",
-	.class		= &omap44xx_dsp_hwmod_class,
-	.clkdm_name	= "tesla_clkdm",
-	.flags		= HWMOD_INIT_NO_RESET,
-	.rst_lines	= omap44xx_dsp_c0_resets,
-	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_dsp_c0_resets),
-	.prcm = {
-		.omap4 = {
-			.rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
-		},
-	},
-};
-
 static struct omap_hwmod omap44xx_dsp_hwmod = {
 	.name		= "dsp",
 	.class		= &omap44xx_dsp_hwmod_class,

@@ -2502,15 +2484,9 @@ static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
 	{ .irq = -1 }
 };
 
-static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
+static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
 	{ .name = "cpu0", .rst_shift = 0 },
-};
-
-static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
 	{ .name = "cpu1", .rst_shift = 1 },
-};
-
-static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
 	{ .name = "mmu_cache", .rst_shift = 2 },
 };
 

@@ -2532,36 +2508,6 @@ static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
 	&omap44xx_l3_main_2__ipu,
 };
 
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
-	.name		= "ipu_c0",
-	.class		= &omap44xx_ipu_hwmod_class,
-	.clkdm_name	= "ducati_clkdm",
-	.flags		= HWMOD_INIT_NO_RESET,
-	.rst_lines	= omap44xx_ipu_c0_resets,
-	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_ipu_c0_resets),
-	.prcm = {
-		.omap4 = {
-			.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
-		},
-	},
-};
-
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
-	.name		= "ipu_c1",
-	.class		= &omap44xx_ipu_hwmod_class,
-	.clkdm_name	= "ducati_clkdm",
-	.flags		= HWMOD_INIT_NO_RESET,
-	.rst_lines	= omap44xx_ipu_c1_resets,
-	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_ipu_c1_resets),
-	.prcm = {
-		.omap4 = {
-			.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
-		},
-	},
-};
-
 static struct omap_hwmod omap44xx_ipu_hwmod = {
 	.name		= "ipu",
 	.class		= &omap44xx_ipu_hwmod_class,

@@ -2691,15 +2637,9 @@ static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
 };
 
 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
-	{ .name = "logic", .rst_shift = 2 },
-};
-
-static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
 	{ .name = "seq0", .rst_shift = 0 },
-};
-
-static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
 	{ .name = "seq1", .rst_shift = 1 },
+	{ .name = "logic", .rst_shift = 2 },
 };
 
 /* iva master ports */

@@ -2732,36 +2672,6 @@ static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
 	&omap44xx_l3_main_2__iva,
 };
 
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
-	.name		= "iva_seq0",
-	.class		= &omap44xx_iva_hwmod_class,
-	.clkdm_name	= "ivahd_clkdm",
-	.flags		= HWMOD_INIT_NO_RESET,
-	.rst_lines	= omap44xx_iva_seq0_resets,
-	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_iva_seq0_resets),
-	.prcm = {
-		.omap4 = {
-			.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
-		},
-	},
-};
-
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
-	.name		= "iva_seq1",
-	.class		= &omap44xx_iva_hwmod_class,
-	.clkdm_name	= "ivahd_clkdm",
-	.flags		= HWMOD_INIT_NO_RESET,
-	.rst_lines	= omap44xx_iva_seq1_resets,
-	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_iva_seq1_resets),
-	.prcm = {
-		.omap4 = {
-			.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
-		},
-	},
-};
-
 static struct omap_hwmod omap44xx_iva_hwmod = {
 	.name		= "iva",
 	.class		= &omap44xx_iva_hwmod_class,

@@ -5520,7 +5430,6 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 
 	/* dsp class */
 	&omap44xx_dsp_hwmod,
-	&omap44xx_dsp_c0_hwmod,
 
 	/* dss class */
 	&omap44xx_dss_hwmod,

@@ -5550,16 +5459,12 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 
 	/* ipu class */
 	&omap44xx_ipu_hwmod,
-	&omap44xx_ipu_c0_hwmod,
-	&omap44xx_ipu_c1_hwmod,
 
 	/* iss class */
 /*	&omap44xx_iss_hwmod, */
 
 	/* iva class */
 	&omap44xx_iva_hwmod,
-	&omap44xx_iva_seq0_hwmod,
-	&omap44xx_iva_seq1_hwmod,
 
 	/* kbd class */
 	&omap44xx_kbd_hwmod,

Move the code that reprograms the OCP_SYSCONFIG bits into the _reset() function to ensure that it is called after every reset. The code was previously in the _setup() function. So, before this patch, if _reset() was called from another function, the SYSCONFIG register won't be reprogrammed.

---
 arch/arm/mach-omap2/omap_hwmod.c |   23 +++++++++++------------
 1 files changed, 11 insertions(+), 12 deletions(-)

index 0ef2710..c991bd7 100644
@@ -1482,6 +1482,16 @@ static int _reset(struct omap_hwmod *oh)
 	 */
 	ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh);
 
+	/*
+	 * OCP_SYSCONFIG bits need to be reprogrammed after a
+	 * softreset.  The _enable() function should be split to avoid
+	 * the rewrite of the OCP_SYSCONFIG register.
+	 */
+	if (oh->class->sysc) {
+		_update_sysc_cache(oh);
+		_enable_sysc(oh);
+	}
+
 	return ret;
 }
 

@@ -1787,20 +1797,9 @@ static int _setup(struct omap_hwmod *oh, void *data)
 		return 0;
 	}
 
-	if (!(oh->flags & HWMOD_INIT_NO_RESET)) {
+	if (!(oh->flags & HWMOD_INIT_NO_RESET))
 		_reset(oh);
 
-		/*
-		 * OCP_SYSCONFIG bits need to be reprogrammed after a softreset.
-		 * The _enable() function should be split to
-		 * avoid the rewrite of the OCP_SYSCONFIG register.
-		 */
-		if (oh->class->sysc) {
-			_update_sysc_cache(oh);
-			_enable_sysc(oh);
-		}
-	}
-
 	postsetup_state = oh->_postsetup_state;
 	if (postsetup_state == _HWMOD_STATE_UNKNOWN)
 		postsetup_state = _HWMOD_STATE_ENABLED;

A subsequent patch will need to know the struct omap_hwmod_addr_space record corresponding to the module's register target, used by the MPU. So, convert _find_mpu_rt_base() into _find_mpu_rt_addr_space(). Then modify its sole current user, _populate_mpu_rt_base(), to extract the MPU RT base address itself from the struct omap_hwmod_addr_space record.

---
 arch/arm/mach-omap2/omap_hwmod.c |   57 ++++++++++++++++++++++----------------
 1 files changed, 33 insertions(+), 24 deletions(-)

index c991bd7..4e8d332 100644
@@ -917,24 +917,22 @@ static int __init _find_mpu_port_index(struct omap_hwmod *oh)
 }
 
 /**
- * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU
+ * _find_mpu_rt_addr_space - return MPU register target address space for @oh
  * @oh: struct omap_hwmod *
  *
- * Return the virtual address of the base of the register target of
- * device @oh, or NULL on error.
+ * Returns a pointer to the struct omap_hwmod_addr_space record representing
+ * the register target MPU address space; or returns NULL upon error.
  */
-static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
+static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh)
 {
 	struct omap_hwmod_ocp_if *os;
 	struct omap_hwmod_addr_space *mem;
-	int i = 0, found = 0;
-	void __iomem *va_start;
+	int found = 0, i = 0;
 
-	if (!oh || oh->slaves_cnt == 0)
+	if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0)
 		return NULL;
 
-	os = oh->slaves[index];
-
+	os = oh->slaves[oh->_mpu_port_index];
 	if (!os->addr)
 		return NULL;
 

@@ -944,20 +942,7 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
 			found = 1;
 	} while (!found && mem->pa_start != mem->pa_end);
 
-	if (found) {
-		va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
-		if (!va_start) {
-			pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
-			return NULL;
-		}
-		pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
-			 oh->name, va_start);
-	} else {
-		pr_debug("omap_hwmod: %s: no MPU register target found\n",
-			 oh->name);
-	}
-
-	return (found) ? va_start : NULL;
+	return (found) ? mem : NULL;
 }
 
 /**

@@ -2031,19 +2016,43 @@ int __init omap_hwmod_register(struct omap_hwmod **ohs)
 
 /*
  * _populate_mpu_rt_base - populate the virtual address for a hwmod
+ * @oh: struct omap_hwmod *
+ * @data: (unused)
  *
  * Must be called only from omap_hwmod_setup_*() so ioremap works properly.
  * Assumes the caller takes care of locking if needed.
  */
 static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
 {
+	struct omap_hwmod_addr_space *mem;
+	void __iomem *va_start;
+
+	if (!oh)
+		return 0;
+
 	if (oh->_state != _HWMOD_STATE_REGISTERED)
 		return 0;
 
 	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
 		return 0;
 
-	oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
+	mem = _find_mpu_rt_addr_space(oh);
+	if (!mem) {
+		pr_debug("omap_hwmod: %s: no MPU register target found\n",
+			 oh->name);
+		return 0;
+	}
+
+	va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
+	if (!va_start) {
+		pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
+		return 0;
+	}
+
+	pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
+		 oh->name, va_start);
+
+	oh->_mpu_rt_va = va_start;
 
 	return 0;
 }

The timer integration code pokes around in hwmod data structures. Those data structures are about to change. Define some functions for the timer integration code to use instead.

---
 arch/arm/mach-omap2/omap_hwmod.c             |   82 ++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/omap_hwmod.h |    3 +
 2 files changed, 85 insertions(+), 0 deletions(-)

index 4e8d332..f7bf759 100644
@@ -2794,3 +2794,85 @@ int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
 
 	return 0;
 }
+
+/*
+ * IP block data retrieval functions
+ */
+
+/**
+ * omap_hwmod_get_mpu_irq - return a hwmod's MPU IRQ line ID, if it only has one
+ * @oh: struct omap_hwmod * to examine MPU IRQs on
+ *
+ * If the IP block represented by @oh only has one IRQ line, return its
+ * ID; otherwise, return -ENOENT if the IP block has no MPU IRQs, or -EINVAL
+ * if @oh is null or hasn't yet been registered.
+ */
+int omap_hwmod_get_mpu_irq(struct omap_hwmod *oh)
+{
+	struct omap_hwmod_irq_info *ii;
+
+	if (!oh)
+		return -EINVAL;
+
+	if (oh->_state == _HWMOD_STATE_UNKNOWN)
+		return -EINVAL;
+
+	if (!oh->mpu_irqs)
+		return -ENOENT;
+
+	ii = &oh->mpu_irqs[0];
+
+	if (ii->irq == -1)
+		return -ENOENT;
+
+	return ii->irq;
+}
+
+/**
+ * omap_hwmod_get_mpu_rt_pa - get the register target physical start & end addrs
+ * @oh: struct omap_hwmod * to retrieve physical address information for
+ * @pa_start: ptr to a u32 to return the starting physical address of the RT
+ * @pa_end: ptr to a u32 to return the ending physical address of the RT
+ *
+ * For a given hwmod @oh, return the starting MPU physical address of
+ * @oh's register target address space in the u32 pointed to by
+ * @pa_start, and return the ending MPU physical address of @oh's
+ * register target address space in the u32 pointed to by @pa_end.
+ * (Device registers, particularly the OCP header registers, are
+ * expected to reside in this space.)  The previous contents of the
+ * data pointed to by @pa_start and @pa_end are ignored and
+ * overwritten.  @pa_start is usually (but not always) the same as the
+ * device's "base address."  Note that @pa_start and @pa_end are
+ * currently only guaranteed to be valid addresses for the MPU, not
+ * for other interconnect initiators.
+ *
+ * Returns 0 upon success, -EINVAL if any arguments are null or if the
+ * hwmod hasn't been registered, or -ENOENT if @oh has no MPU register
+ * target address space.
+ */
+int omap_hwmod_get_mpu_rt_pa(struct omap_hwmod *oh, u32 *pa_start, u32 *pa_end)
+{
+	struct omap_hwmod_addr_space *mem;
+
+	if (!oh || !pa_start || !pa_end)
+		return -EINVAL;
+
+	if (oh->_state == _HWMOD_STATE_UNKNOWN)
+		return -EINVAL;
+
+	if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+		return -ENOENT;
+
+	mem = _find_mpu_rt_addr_space(oh);
+	if (!mem) {
+		pr_debug("omap_hwmod: %s: no MPU register target found\n",
+			 oh->name);
+		return -ENOENT;
+	}
+
+	*pa_start = mem->pa_start;
+	*pa_end = mem->pa_end;
+
+	return 0;
+}
+

index 6470101..0d95c86 100644
@@ -610,6 +610,9 @@ int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
 
 int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx);
 
+int omap_hwmod_get_mpu_irq(struct omap_hwmod *oh);
+int omap_hwmod_get_mpu_rt_pa(struct omap_hwmod *oh, u32 *pa_start, u32 *pa_end);
+
 /*
  * Chip variant-specific hwmod init routines - XXX should be converted
  * to use initcalls once the initial boot ordering is straightened out

Hi,

Maybe these should use struct resource instead to make these more generic? Something like this maybe:

int omap_hwmod_get_resource(struct omap_hwmod *oh, unsigned int type,

				unsigned int num, struct resource *r);

Then the calling code would do:

	...
	struct resource r;
	int res;

	res = omap_hwmod_get_resource(oh, IORESOURCE_IRQ, 0, &r);
	...

Regards,

Tony

Hi

That's a good idea and will definitely look into that.

- Paul

arch/arm/mach-omap2/timer.c pokes around inside the hwmod data structures. Since the hwmod data structures are about to change, this code will break. This patch modifies the timer code to use recently-added hwmod functions instead.

---
 arch/arm/mach-omap2/timer.c |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)

index 6eeff0e..499d884 100644
@@ -145,6 +145,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 {
 	char name[10]; /* 10 = sizeof("gptXX_Xck0") */
 	struct omap_hwmod *oh;
+	u32 pa_start, pa_end;
 	size_t size;
 	int res = 0;
 

@@ -154,9 +155,10 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 	if (!oh)
 		return -ENODEV;
 
-	timer->irq = oh->mpu_irqs[0].irq;
-	timer->phys_base = oh->slaves[0]->addr->pa_start;
-	size = oh->slaves[0]->addr->pa_end - timer->phys_base;
+	timer->irq = omap_hwmod_get_mpu_irq(oh);
+	omap_hwmod_get_mpu_rt_pa(oh, &pa_start, &pa_end);
+	timer->phys_base = pa_start;
+	size = pa_end - pa_start;
 
 	/* Static mapping, never released */
 	timer->io_base = ioremap(timer->phys_base, size);

Split the interface clock setup from _setup() into _setup_iclk_autoidle() and split the post-setup state code from _setup() into _enter_postsetup_state(). Fix the existing, incorrect documentation for _setup(), and add documentation for the other two functions. The goal is to shrink the size of the _setup() function to make it easier to read and maintain.

---
 arch/arm/mach-omap2/omap_hwmod.c |  154 +++++++++++++++++++++++++++-----------
 1 files changed, 111 insertions(+), 43 deletions(-)

index f7bf759..41749bd 100644
@@ -1731,11 +1731,112 @@ static int _shutdown(struct omap_hwmod *oh)
 }
 
 /**
- * _setup - do initial configuration of omap_hwmod
+ * _setup_iclk_autoidle - configure an IP block's interface clocks
  * @oh: struct omap_hwmod *
  *
- * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
- * OCP_SYSCONFIG register.  Returns 0.
+ * Set up the module's interface clocks.  XXX This function is still mostly
+ * a stub; implementing this properly requires iclk autoidle usecounting in
+ * the clock code.   No return value.
+ */
+static void _setup_iclk_autoidle(struct omap_hwmod *oh)
+{
+	int i;
+
+	for (i = 0; i < oh->slaves_cnt; i++) {
+		struct omap_hwmod_ocp_if *os = oh->slaves[i];
+		struct clk *c = os->_clk;
+
+		if (!c)
+			continue;
+
+		if (os->flags & OCPIF_SWSUP_IDLE) {
+			/* XXX omap_iclk_deny_idle(c); */
+		} else {
+			/* XXX omap_iclk_allow_idle(c); */
+			clk_enable(c);
+		}
+	}
+}
+
+
+/**
+ * _enter_postsetup_state - transition to the appropriate state after _setup
+ * @oh: struct omap_hwmod *
+ *
+ * Place an IP block represented by @oh into a "post-setup" state --
+ * either IDLE, ENABLED, or DISABLED.  ("post-setup" simply means that
+ * this function is called at the end of _setup().)  The postsetup
+ * state for an IP block can be changed by calling
+ * omap_hwmod_enter_postsetup_state() early in the boot process,
+ * before one of the omap_hwmod_setup*() functions are called for the
+ * IP block.
+ *
+ * The IP block stays in this state until a PM runtime-based driver is
+ * loaded for that IP block.  A post-setup state of IDLE is
+ * appropriate for almost all IP blocks with runtime PM-enabled
+ * drivers, since those drivers are able to enable the IP block.  A
+ * post-setup state of ENABLED is appropriate for kernels with PM
+ * runtime disabled.  The DISABLED state is appropriate for unusual IP
+ * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers
+ * included, since the WDTIMER starts running on reset and will reset
+ * the MPU if left active.
+ *
+ * This post-setup mechanism is deprecated.  Once all of the OMAP
+ * drivers have been converted to use PM runtime, and all of the IP
+ * block data and interconnect data is available to the hwmod code, it
+ * should be possible to replace this mechanism with a "lazy reset"
+ * arrangement.  In a "lazy reset" setup, each IP block is enabled
+ * when the driver first probes, then all remaining IP blocks without
+ * drivers are either shut down or enabled after the drivers have
+ * loaded.  However, this cannot take place until the above
+ * preconditions have been met, since otherwise the late reset code
+ * has no way of knowing which IP blocks are in use by drivers, and
+ * which ones are unused.
+ *
+ * No return value.
+ */
+static void _enter_postsetup_state(struct omap_hwmod *oh)
+{
+	u8 postsetup_state;
+
+	postsetup_state = oh->_postsetup_state;
+	if (postsetup_state == _HWMOD_STATE_UNKNOWN)
+		postsetup_state = _HWMOD_STATE_ENABLED;
+
+	/*
+	 * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data -
+	 * it should be set by the core code as a runtime flag during startup
+	 */
+	if ((oh->flags & HWMOD_INIT_NO_IDLE) &&
+	    (postsetup_state == _HWMOD_STATE_IDLE)) {
+		oh->_int_flags |= _HWMOD_SKIP_ENABLE;
+		postsetup_state = _HWMOD_STATE_ENABLED;
+	}
+
+	if (postsetup_state == _HWMOD_STATE_IDLE)
+		_idle(oh);
+	else if (postsetup_state == _HWMOD_STATE_DISABLED)
+		_shutdown(oh);
+	else if (postsetup_state != _HWMOD_STATE_ENABLED)
+		WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
+		     oh->name, postsetup_state);
+}
+
+/**
+ * _setup - do initial configuration of an omap_hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Configure the IP block represented by @oh.  This may include
+ * enabling the IP block, resetting it, and placing it into a
+ * post-setup state, depending on the type of IP block and applicable
+ * flags.
+ *
+ * IP blocks are reset to prevent any previous configuration by the
+ * bootloader or previous operating system from interfering with power
+ * management or other parts of the system.  The reset can be avoided; see
+ * omap_hwmod_no_setup_reset().
+ *
+ * Returns 0.
  */
 static int _setup(struct omap_hwmod *oh, void *data)
 {

@@ -1746,22 +1847,8 @@ static int _setup(struct omap_hwmod *oh, void *data)
 		return 0;
 
 	/* Set iclk autoidle mode */
-	if (oh->slaves_cnt > 0) {
-		for (i = 0; i < oh->slaves_cnt; i++) {
-			struct omap_hwmod_ocp_if *os = oh->slaves[i];
-			struct clk *c = os->_clk;
-
-			if (!c)
-				continue;
-
-			if (os->flags & OCPIF_SWSUP_IDLE) {
-				/* XXX omap_iclk_deny_idle(c); */
-			} else {
-				/* XXX omap_iclk_allow_idle(c); */
-				clk_enable(c);
-			}
-		}
-	}
+	if (oh->slaves_cnt > 0)
+		_setup_iclk_autoidle(oh);
 
 	oh->_state = _HWMOD_STATE_INITIALIZED;
 

@@ -1785,27 +1872,7 @@ static int _setup(struct omap_hwmod *oh, void *data)
 	if (!(oh->flags & HWMOD_INIT_NO_RESET))
 		_reset(oh);
 
-	postsetup_state = oh->_postsetup_state;
-	if (postsetup_state == _HWMOD_STATE_UNKNOWN)
-		postsetup_state = _HWMOD_STATE_ENABLED;
-
-	/*
-	 * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data -
-	 * it should be set by the core code as a runtime flag during startup
-	 */
-	if ((oh->flags & HWMOD_INIT_NO_IDLE) &&
-	    (postsetup_state == _HWMOD_STATE_IDLE)) {
-		oh->_int_flags |= _HWMOD_SKIP_ENABLE;
-		postsetup_state = _HWMOD_STATE_ENABLED;
-	}
-
-	if (postsetup_state == _HWMOD_STATE_IDLE)
-		_idle(oh);
-	else if (postsetup_state == _HWMOD_STATE_DISABLED)
-		_shutdown(oh);
-	else if (postsetup_state != _HWMOD_STATE_ENABLED)
-		WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
-		     oh->name, postsetup_state);
+	_enter_postsetup_state(oh);
 
 	return 0;
 }

@@ -2660,9 +2727,10 @@ int omap_hwmod_for_each_by_class(const char *classname,
  *
  * Sets the hwmod state that @oh will enter at the end of _setup()
  * (called by omap_hwmod_setup_*()).  Only valid to call between
- * calling omap_hwmod_register() and omap_hwmod_setup_*().  Returns
- * 0 upon success or -EINVAL if there is a problem with the arguments
- * or if the hwmod is in the wrong state.
+ * calling omap_hwmod_register() and omap_hwmod_setup_*().  See also
+ * the documentation for _enter_postsetup_state(), above.  Returns 0
+ * upon success or -EINVAL if there is a problem with the arguments or
+ * if the hwmod is in the wrong state.
  */
 int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
 {

Hi Paul,

FYI... I tested this branch on my 4430ES2.1/Panda and got an infinite loop of L3 errors.

I haven't debugged which patch causes the problem, but thought you'd
like to know. I did notice that that booting v3.3-rc1, I see

[    0.309478] omap_hwmod: ipu: failed to hardreset

but booting your branch I see a few more reset failures:

[    0.308532] omap_hwmod: dsp: failed to hardreset
[    0.328979] omap_hwmod: dsp: failed to hardreset
[    0.358001] omap_hwmod: ipu: failed to hardreset
[    0.378448] omap_hwmod: ipu: failed to hardreset
[    0.398895] omap_hwmod: ipu: failed to hardreset
[    0.427520] omap_hwmod: iva: failed to hardreset
[    0.447967] omap_hwmod: iva: failed to hardreset

There's a full boot log below.

I noticed you tested on Panda too, but one difference between our setups is probably that I'm not using u-boot. Instead, I'm booting over USB using the usbboot tool written by Brian Swetland:
git://github.com/swetland/omap4boot.git. It could be that the
different bootloaders are leaving the other IPs in different states.

Kevin

Uncompressing Linux... done, booting the kernel.
Warning: Neither atags nor dtb found

[    0.000000] Booting Linux on physical CPU 0
[    0.000000] Linux version 3.3.0-rc1-pm+debug+cmdline+panda-00007-g86f3164 (khilman at paris) (gcc version 4.6.1 (Ubuntu/Linaro 4.6.1-9ubuntu3) ) #51 SMP Mon Jan 30 15:00:37 PST 2012
[    0.000000] CPU: ARMv7 Processor [411fc092] revision 2 (ARMv7), cr=10c53c7d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] Machine: OMAP4 Panda board
[    0.000000] Warning: Neither atags nor dtb found
[    0.000000] bootconsole [earlycon0] enabled
[    0.000000] Memory policy: ECC disabled, Data cache writealloc
[    0.000000] On node 0 totalpages: 116480
[    0.000000] free_area_init_node: node 0, pgdat c06e96c0, node_mem_map c0c41000
[    0.000000]   Normal zone: 912 pages used for memmap
[    0.000000]   Normal zone: 0 pages reserved
[    0.000000]   Normal zone: 115568 pages, LIFO batch:31
[    0.000000] OMAP4430 ES2.1
[    0.000000] PERCPU: Embedded 8 pages/cpu @c0fd9000 s12096 r8192 d12480 u32768
[    0.000000] pcpu-alloc: s12096 r8192 d12480 u32768 alloc=8*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1 
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 115568
[    0.000000] Kernel command line: mem=456M console=ttyO2,115200n8 debug earlyprintk rw ip=dhcp nfsroot=192.168.1.236:/opt/kjh/rootfs/debian/armel,rsize=4096,wsize=4096,nfsvers=3
[    0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[    0.000000] Memory: 455MB = 455MB total
[    0.000000] Memory: 449232k/449232k available, 17712k reserved, 0K highmem
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     vmalloc : 0xdd000000 - 0xff000000   ( 544 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xdc800000   ( 456 MB)
[    0.000000]     modules : 0xbf000000 - 0xc0000000   (  16 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0612a98   (6187 kB)
[    0.000000]       .init : 0xc0613000 - 0xc0660f40   ( 312 kB)
[    0.000000]       .data : 0xc0662000 - 0xc06eb0a8   ( 549 kB)
[    0.000000]        .bss : 0xc06eb0cc - 0xc0c4017c   (5461 kB)
[    0.000000] Hierarchical RCU implementation.
[    0.000000] NR_IRQS:410
[    0.000000] omap_hwmod: dpll_mpu_m2_ck: missing clockdomain for dpll_mpu_m2_ck.
[    0.000000] OMAP clockevent source: GPTIMER1 at 32768 Hz
[    0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms
[    0.000000] Console: colour dummy device 80x30
[    0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
[    0.000000] ... MAX_LOCKDEP_SUBCLASSES:  8
[    0.000000] ... MAX_LOCK_DEPTH:          48
[    0.000000] ... MAX_LOCKDEP_KEYS:        8191
[    0.000000] ... CLASSHASH_SIZE:          4096
[    0.000000] ... MAX_LOCKDEP_ENTRIES:     16384
[    0.000000] ... MAX_LOCKDEP_CHAINS:      32768
[    0.000000] ... CHAINHASH_SIZE:          16384
[    0.000000]  memory used by lock dependency info: 3695 kB
[    0.000000]  per task-struct memory footprint: 1152 bytes
[    0.056610] Calibrating delay loop... 2007.19 BogoMIPS (lpj=7839744)
[    0.129852] pid_max: default: 32768 minimum: 301
[    0.135253] Security Framework initialized
[    0.139739] Mount-cache hash table entries: 512
[    0.148162] CPU: Testing write buffer coherency: ok
[    0.154113] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.160491] Setting up static identity map for 0x804487b0 - 0x80448820
[    0.167327] L310 cache controller enabled
[    0.171569] l2x0: 16 ways, CACHE_ID 0x410000c4, AUX_CTRL 0x7e470000, Cache size: 1048576 B
[    0.182525] CPU1: Booted secondary processor
[    0.246398] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.246429] CPU1: Unknown IPI message 0x1
[    0.246551] Brought up 2 CPUs
[    0.246582] SMP: Total of 2 processors activated (4022.78 BogoMIPS).
[    0.277648] ttyO2 used as console in debug mode uart2 clocks will not be gated
[    0.285247] omap_hwmod: l3_div_ck: missing clockdomain for l3_div_ck.
[    0.308532] omap_hwmod: dsp: failed to hardreset
[    0.328979] omap_hwmod: dsp: failed to hardreset
[    0.336425] omap_hwmod: dsp: cannot be enabled (3)
[    0.358001] omap_hwmod: ipu: failed to hardreset
[    0.378417] omap_hwmod: ipu: failed to hardreset
[    0.398864] omap_hwmod: ipu: failed to hardreset
[    0.406280] omap_hwmod: ipu: _wait_target_disable failed
[    0.427459] omap_hwmod: iva: failed to hardreset
[    0.447906] omap_hwmod: iva: failed to hardreset
[    0.455505] omap_hwmod: mcpdm: cannot be enabled (3)
[    0.465301] print_constraints: dummy: 
[    0.470184] NET: Registered protocol family 16
[    0.475341] GPMC revision 6.0
[    0.483612] gpiochip_add: registered GPIOs 0 to 31 on device: gpio
[    0.490325] OMAP GPIO hardware version 0.1
[    0.494995] gpiochip_add: registered GPIOs 32 to 63 on device: gpio
[    0.502075] gpiochip_add: registered GPIOs 64 to 95 on device: gpio
[    0.509155] gpiochip_add: registered GPIOs 96 to 127 on device: gpio
[    0.516357] gpiochip_add: registered GPIOs 128 to 159 on device: gpio
[    0.523651] gpiochip_add: registered GPIOs 160 to 191 on device: gpio
[    0.533355] ------------[ cut here ]------------
[    0.538177] WARNING: at /work/kernel/omap/pm/arch/arm/mach-omap2/omap_l3_noc.c:113 l3_interrupt_handler+0x134/0x178()
[    0.549163] L3 custom error: MASTER:DucatiM3 TARGET:GPMC 
[    0.554779] Modules linked in:
[    0.558013] [<c00141d4>] (unwind_backtrace+0x0/0xf0) from [<c003a0a0>] (warn_slowpath_common+0x4c/0x64)
[    0.567749] [<c003a0a0>] (warn_slowpath_common+0x4c/0x64) from [<c003a14c>] (warn_slowpath_fmt+0x30/0x40)
[    0.577667] [<c003a14c>] (warn_slowpath_fmt+0x30/0x40) from [<c002ce0c>] (l3_interrupt_handler+0x134/0x178)
[    0.587768] [<c002ce0c>] (l3_interrupt_handler+0x134/0x178) from [<c00947a8>] (handle_irq_event_percpu+0x58/0x244)
[    0.598480] [<c00947a8>] (handle_irq_event_percpu+0x58/0x244) from [<c00949d0>] (handle_irq_event+0x3c/0x5c)
[    0.608673] [<c00949d0>] (handle_irq_event+0x3c/0x5c) from [<c00973b0>] (handle_fasteoi_irq+0x98/0x140)
[    0.618408] [<c00973b0>] (handle_fasteoi_irq+0x98/0x140) from [<c0094000>] (generic_handle_irq+0x30/0x48)
[    0.628326] [<c0094000>] (generic_handle_irq+0x30/0x48) from [<c000e618>] (handle_IRQ+0x4c/0xac)
[    0.637420] [<c000e618>] (handle_IRQ+0x4c/0xac) from [<c0008654>] (gic_handle_irq+0x24/0xa8)
[    0.646179] [<c0008654>] (gic_handle_irq+0x24/0xa8) from [<c04435a4>] (__irq_svc+0x44/0x60)
[    0.654846] Exception stack(0xdc033e30 to 0xdc033e78)
[    0.660095] 3e20:                                     00000001 00000001 00000000 00000000
[    0.668579] 3e40: 60000013 c0666114 00000000 c0666114 60000013 0000002a 00000000 0000002a
[    0.677062] 3e60: 00000490 dc033e78 c0086300 c044328c 20000013 ffffffff
[    0.683929] [<c04435a4>] (__irq_svc+0x44/0x60) from [<c044328c>] (_raw_spin_unlock_irqrestore+0x34/0x44)
[    0.693756] [<c044328c>] (_raw_spin_unlock_irqrestore+0x34/0x44) from [<c0095e14>] (__setup_irq+0x348/0x450)
[    0.703918] [<c0095e14>] (__setup_irq+0x348/0x450) from [<c0095fd4>] (request_threaded_irq+0xb8/0x140)
[    0.713592] [<c0095fd4>] (request_threaded_irq+0xb8/0x140) from [<c0424f14>] (omap4_l3_probe+0x204/0x29c)
[    0.723480] [<c0424f14>] (omap4_l3_probe+0x204/0x29c) from [<c0289894>] (platform_drv_probe+0x18/0x1c)
[    0.733123] [<c0289894>] (platform_drv_probe+0x18/0x1c) from [<c0288520>] (really_probe+0x60/0x15c)
[    0.742492] [<c0288520>] (really_probe+0x60/0x15c) from [<c0288760>] (driver_probe_device+0x48/0x60)
[    0.751953] [<c0288760>] (driver_probe_device+0x48/0x60) from [<c028880c>] (__driver_attach+0x94/0x98)
[    0.761627] [<c028880c>] (__driver_attach+0x94/0x98) from [<c02870c0>] (bus_for_each_dev+0x50/0x7c)
[    0.770996] [<c02870c0>] (bus_for_each_dev+0x50/0x7c) from [<c0288020>] (bus_add_driver+0x184/0x248)
[    0.780456] [<c0288020>] (bus_add_driver+0x184/0x248) from [<c0288cdc>] (driver_register+0x78/0x130)
[    0.789916] [<c0288cdc>] (driver_register+0x78/0x130) from [<c0008818>] (do_one_initcall+0x34/0x178)
[    0.799377] [<c0008818>] (do_one_initcall+0x34/0x178) from [<c06138ac>] (kernel_init+0x8c/0x130)
[    0.808502] [<c06138ac>] (kernel_init+0x8c/0x130) from [<c000e870>] (kernel_thread_exit+0x0/0x8)
[    0.817779] ---[ end trace 1b75b31a2719ed1c ]---
[    0.822631] ------------[ cut here ]------------
[    0.827484] WARNING: at /work/kernel/omap/pm/arch/arm/mach-omap2/omap_l3_noc.c:113 l3_interrupt_handler+0x134/0x178()
[    0.838439] L3 custom error: MASTER:DucatiM3 TARGET:GPMC 
[    0.844055] Modules linked in:
[    0.847290] [<c00141d4>] (unwind_backtrace+0x0/0xf0) from [<c003a0a0>] (warn_slowpath_common+0x4c/0x64)
[    0.857025] [<c003a0a0>] (warn_slowpath_common+0x4c/0x64) from [<c003a14c>] (warn_slowpath_fmt+0x30/0x40)
[    0.866943] [<c003a14c>] (warn_slowpath_fmt+0x30/0x40) from [<c002ce0c>] (l3_interrupt_handler+0x134/0x178)
[    0.877014] [<c002ce0c>] (l3_interrupt_handler+0x134/0x178) from [<c00947a8>] (handle_irq_event_percpu+0x58/0x244)
[    0.887725] [<c00947a8>] (handle_irq_event_percpu+0x58/0x244) from [<c00949d0>] (handle_irq_event+0x3c/0x5c)
[    0.897918] [<c00949d0>] (handle_irq_event+0x3c/0x5c) from [<c00973b0>] (handle_fasteoi_irq+0x98/0x140)
[    0.907623] [<c00973b0>] (handle_fasteoi_irq+0x98/0x140) from [<c0094000>] (generic_handle_irq+0x30/0x48)
[    0.917541] [<c0094000>] (generic_handle_irq+0x30/0x48) from [<c000e618>] (handle_IRQ+0x4c/0xac)
[    0.926635] [<c000e618>] (handle_IRQ+0x4c/0xac) from [<c0008654>] (gic_handle_irq+0x24/0xa8)
[    0.935394] [<c0008654>] (gic_handle_irq+0x24/0xa8) from [<c04435a4>] (__irq_svc+0x44/0x60)
[    0.944061] Exception stack(0xdc033d78 to 0xdc033dc0)
[    0.949310] 3d60:                                                       00000001 00000000
[    0.957794] 3d80: 00000000 c06fd460 00000202 c0660348 dc032000 0000001d 00000000 0000002a
[    0.966278] 3da0: 00000000 0000002a 00000000 dc033dc0 c00862bc c0040b84 60000013 ffffffff
[    0.974761] [<c04435a4>] (__irq_svc+0x44/0x60) from [<c0040b84>] (__do_softirq+0x6c/0x224)
[    0.983337] [<c0040b84>] (__do_softirq+0x6c/0x224) from [<c00411d4>] (irq_exit+0x94/0x9c)
[    0.991821] [<c00411d4>] (irq_exit+0x94/0x9c) from [<c000e61c>] (handle_IRQ+0x50/0xac)
[    1.000030] [<c000e61c>] (handle_IRQ+0x50/0xac) from [<c0008654>] (gic_handle_irq+0x24/0xa8)
[    1.008789] [<c0008654>] (gic_handle_irq+0x24/0xa8) from [<c04435a4>] (__irq_svc+0x44/0x60)
[    1.017425] Exception stack(0xdc033e30 to 0xdc033e78)
[    1.022705] 3e20:                                     00000001 00000001 00000000 00000000
[    1.031158] 3e40: 60000013 c0666114 00000000 c0666114 60000013 0000002a 00000000 0000002a
[    1.039642] 3e60: 00000490 dc033e78 c0086300 c044328c 20000013 ffffffff
[    1.046539] [<c04435a4>] (__irq_svc+0x44/0x60) from [<c044328c>] (_raw_spin_unlock_irqrestore+0x34/0x44)
[    1.056335] [<c044328c>] (_raw_spin_unlock_irqrestore+0x34/0x44) from [<c0095e14>] (__setup_irq+0x348/0x450)
[    1.066528] [<c0095e14>] (__setup_irq+0x348/0x450) from [<c0095fd4>] (request_threaded_irq+0xb8/0x140)
[    1.076171] [<c0095fd4>] (request_threaded_irq+0xb8/0x140) from [<c0424f14>] (omap4_l3_probe+0x204/0x29c)
[    1.086059] [<c0424f14>] (omap4_l3_probe+0x204/0x29c) from [<c0289894>] (platform_drv_probe+0x18/0x1c)
[    1.095703] [<c0289894>] (platform_drv_probe+0x18/0x1c) from [<c0288520>] (really_probe+0x60/0x15c)
[    1.105072] [<c0288520>] (really_probe+0x60/0x15c) from [<c0288760>] (driver_probe_device+0x48/0x60)
[    1.114532] [<c0288760>] (driver_probe_device+0x48/0x60) from [<c028880c>] (__driver_attach+0x94/0x98)
[    1.124176] [<c028880c>] (__driver_attach+0x94/0x98) from [<c02870c0>] (bus_for_each_dev+0x50/0x7c)
[    1.133544] [<c02870c0>] (bus_for_each_dev+0x50/0x7c) from [<c0288020>] (bus_add_driver+0x184/0x248)
[    1.143005] [<c0288020>] (bus_add_driver+0x184/0x248) from [<c0288cdc>] (driver_register+0x78/0x130)
[    1.152465] [<c0288cdc>] (driver_register+0x78/0x130) from [<c0008818>] (do_one_initcall+0x34/0x178)
[    1.161926] [<c0008818>] (do_one_initcall+0x34/0x178) from [<c06138ac>] (kernel_init+0x8c/0x130)
[    1.171051] [<c06138ac>] (kernel_init+0x8c/0x130) from [<c000e870>] (kernel_thread_exit+0x0/0x8)
[    1.180145] ---[ end trace 1b75b31a2719ed1d ]---
[    1.185028] ------------[ cut here ]------------
[    1.189849] WARNING: at /work/kernel/omap/pm/arch/arm/mach-omap2/omap_l3_noc.c:113 l3_interrupt_handler+0x134/0x178()
[    1.200836] L3 custom error: MASTER:DucatiM3 TARGET:GPMC 
[    1.206451] Modules linked in:
[    1.209655] [<c00141d4>] (unwind_backtrace+0x0/0xf0) from [<c003a0a0>] (warn_slowpath_common+0x4c/0x64)
[    1.219390] [<c003a0a0>] (warn_slowpath_common+0x4c/0x64) from [<c003a14c>] (warn_slowpath_fmt+0x30/0x40)
[    1.229309] [<c003a14c>] (warn_slowpath_fmt+0x30/0x40) from [<c002ce0c>] (l3_interrupt_handler+0x134/0x178)
[    1.239410] [<c002ce0c>] (l3_interrupt_handler+0x134/0x178) from [<c00947a8>] (handle_irq_event_percpu+0x58/0x244)
[    1.250122] [<c00947a8>] (handle_irq_event_percpu+0x58/0x244) from [<c00949d0>] (handle_irq_event+0x3c/0x5c)
[    1.260284] [<c00949d0>] (handle_irq_event+0x3c/0x5c) from [<c00973b0>] (handle_fasteoi_irq+0x98/0x140)
[    1.270019] [<c00973b0>] (handle_fasteoi_irq+0x98/0x140) from [<c0094000>] (generic_handle_irq+0x30/0x48)
[    1.279937] [<c0094000>] (generic_handle_irq+0x30/0x48) from [<c000e618>] (handle_IRQ+0x4c/0xac)
[    1.289031] [<c000e618>] (handle_IRQ+0x4c/0xac) from [<c0008654>] (gic_handle_irq+0x24/0xa8)
[    1.297760] [<c0008654>] (gic_handle_irq+0x24/0xa8) from [<c04435a4>] (__irq_svc+0x44/0x60)
[    1.306427] Exception stack(0xdc033d78 to 0xdc033dc0)
[    1.311706] 3d60:                                                       00000001 00000000
[    1.320159] 3d80: 00000000 c06fd460 00000202 c0660348 dc032000 0000001d 00000000 0000002a
[    1.328643] 3da0: 00000000 0000002a 00000000 dc033dc0 c00862bc c0040b84 60000013 ffffffff
[    1.337127] [<c04435a4>] (__irq_svc+0x44/0x60) from [<c0040b84>] (__do_softirq+0x6c/0x224)
[    1.345703] [<c0040b84>] (__do_softirq+0x6c/0x224) from [<c00411d4>] (irq_exit+0x94/0x9c)
[    1.354187] [<c00411d4>] (irq_exit+0x94/0x9c) from [<c000e61c>] (handle_IRQ+0x50/0xac)
[    1.362396] [<c000e61c>] (handle_IRQ+0x50/0xac) from [<c0008654>] (gic_handle_irq+0x24/0xa8)
[    1.371154] [<c0008654>] (gic_handle_irq+0x24/0xa8) from [<c04435a4>] (__irq_svc+0x44/0x60)
[    1.379791] Exception stack(0xdc033e30 to 0xdc033e78)
[    1.385070] 3e20:                                     00000001 00000001 00000000 00000000
[    1.393554] 3e40: 60000013 c0666114 00000000 c0666114 60000013 0000002a 00000000 0000002a
[    1.402008] 3e60: 00000490 dc033e78 c0086300 c044328c 20000013 ffffffff
[    1.408905] [<c04435a4>] (__irq_svc+0x44/0x60) from [<c044328c>] (_raw_spin_unlock_irqrestore+0x34/0x44)
[    1.418701] [<c044328c>] (_raw_spin_unlock_irqrestore+0x34/0x44) from [<c0095e14>] (__setup_irq+0x348/0x450)
[    1.428894] [<c0095e14>] (__setup_irq+0x348/0x450) from [<c0095fd4>] (request_threaded_irq+0xb8/0x140)
[    1.438537] [<c0095fd4>] (request_threaded_irq+0xb8/0x140) from [<c0424f14>] (omap4_l3_probe+0x204/0x29c)
[    1.448425] [<c0424f14>] (omap4_l3_probe+0x204/0x29c) from [<c0289894>] (platform_drv_probe+0x18/0x1c)
[    1.458068] [<c0289894>] (platform_drv_probe+0x18/0x1c) from [<c0288520>] (really_probe+0x60/0x15c)
[    1.467437] [<c0288520>] (really_probe+0x60/0x15c) from [<c0288760>] (driver_probe_device+0x48/0x60)
[    1.476898] [<c0288760>] (driver_probe_device+0x48/0x60) from [<c028880c>] (__driver_attach+0x94/0x98)
[    1.486541] [<c028880c>] (__driver_attach+0x94/0x98) from [<c02870c0>] (bus_for_each_dev+0x50/0x7c)
[    1.495910] [<c02870c0>] (bus_for_each_dev+0x50/0x7c) from [<c0288020>] (bus_add_driver+0x184/0x248)
[    1.505371] [<c0288020>] (bus_add_driver+0x184/0x248) from [<c0288cdc>] (driver_register+0x78/0x130)
[    1.514831] [<c0288cdc>] (driver_register+0x78/0x130) from [<c0008818>] (do_one_initcall+0x34/0x178)
[    1.524291] [<c0008818>] (do_one_initcall+0x34/0x178) from [<c06138ac>] (kernel_init+0x8c/0x130)
[    1.533416] [<c06138ac>] (kernel_init+0x8c/0x130) from [<c000e870>] (kernel_thread_exit+0x0/0x8)
[    1.542510] ---[ end trace 1b75b31a2719ed1e ]---
[    1.547332] ------------[ cut here ]------------

... and it continues forever.

Kevin

Thanks for the test and the report. I'll take a look at the situation. Your assumption about bootloaders is correct. I wonder if Brian's bootloader leaves things enabled.

- Paul

Hi Kevin and Paul,

It is becasue the code is iterating over every reset lines present in an hwmod now: DSP does have 2 lines, IPU: 3 and IVA should have 3 lines???

Thanks to the L3 log error:

[    0.838439] L3 custom error: MASTER:DucatiM3 TARGET:GPMC

I guess that I understand why I was not releasing the hardreset at boot time before:-)

DSP and CortexM3 cannot be released from reset until someone loaded a firmware in memory. Otherwise they will start executing some random instructions that in this case are trying to access an area that is not accessible.

We have to let the driver handle the hardreset because it is mainly used for processors.

Sorry Paul for having mislead you here.

Regards,
Benoit

Hi

Currently we're not asserting hardreset in the hwmod code during _reset(). I had that patch in the series at some point, but took it out before posting it. So maybe that might resolve this particular issue. Also sounds like we should make sure that we keep the processor IPs in hardreset until some driver explicitly releases it; we'll need to make sure the code does that too.

- Paul

Ooops, you're right we were talking about asserting the reset not de-asserting it.

So maybe in that case, this is because the reset line is already de-asserted by the fast boot and by enabling the clock we start executing some random code in the CortexM3... but this is still weird that this error was not happening before.

Regards,
Benoit