i.MX28: Fix ref_cpu clock setup
Subsystems (5)
PATCH 1/1 i.MX28: Fix ref_cpu clock setup
From: Robert Delien <[email protected]>
This set of patches fixes ref_cpu clock setup.
Robert Delien (4):
Renamed mx28_register to mx28_register_32 to prepare for
mx28_register_8
Introducing 8-bit wide register, mx28_register_8 Fix erroneous 32-bit access to hw_clkctrl_frac0 and
hw_clkctrl_frac1 registers
Preventing needless switching on and off PLL bypass mode,
allowing allow single-stepping through the SPL
arch/arm/cpu/arm926ejs/mx28/clock.c | 4 +- arch/arm/cpu/arm926ejs/mx28/iomux.c | 6 +- arch/arm/cpu/arm926ejs/mx28/mx28.c | 6 +- arch/arm/include/asm/arch-mx28/regs-apbh.h | 254 ++++++++++++------------ arch/arm/include/asm/arch-mx28/regs-bch.h | 42 ++-- arch/arm/include/asm/arch-mx28/regs-clkctrl.h | 58 +++--- arch/arm/include/asm/arch-mx28/regs-common.h | 12 +- arch/arm/include/asm/arch-mx28/regs-gpmi.h | 26 ++-- arch/arm/include/asm/arch-mx28/regs-i2c.h | 28 ++-- arch/arm/include/asm/arch-mx28/regs-ocotp.h | 86 ++++---- arch/arm/include/asm/arch-mx28/regs-pinctrl.h | 168 ++++++++-------- arch/arm/include/asm/arch-mx28/regs-power.h | 28 ++-- arch/arm/include/asm/arch-mx28/regs-rtc.h | 28 ++-- arch/arm/include/asm/arch-mx28/regs-ssp.h | 40 ++-- arch/arm/include/asm/arch-mx28/regs-timrot.h | 38 ++-- arch/arm/include/asm/arch-mx28/regs-usbphy.h | 20 +- arch/arm/include/asm/arch-mx28/sys_proto.h | 10 +- drivers/gpio/mxs_gpio.c | 16 +- drivers/usb/host/ehci-mxs.c | 8 +- 19 files changed, 441 insertions(+), 437 deletions(-)
PATCH v4 1/4 Renamed mx28_register to mx28_register_32 to prepare for mx28_register_8
From: Robert Delien <[email protected]>
This patch renames mx28_register to mx28_register_32 in order to prepare for the introduction of an 8-bit register, mx28_register_8.
--- arch/arm/cpu/arm926ejs/mx28/clock.c | 4 +- arch/arm/cpu/arm926ejs/mx28/iomux.c | 6 +- arch/arm/cpu/arm926ejs/mx28/mx28.c | 6 +- arch/arm/include/asm/arch-mx28/regs-apbh.h | 254 ++++++++++++------------ arch/arm/include/asm/arch-mx28/regs-bch.h | 42 ++-- arch/arm/include/asm/arch-mx28/regs-clkctrl.h | 58 +++--- arch/arm/include/asm/arch-mx28/regs-common.h | 12 +- arch/arm/include/asm/arch-mx28/regs-gpmi.h | 26 ++-- arch/arm/include/asm/arch-mx28/regs-i2c.h | 28 ++-- arch/arm/include/asm/arch-mx28/regs-ocotp.h | 86 ++++---- arch/arm/include/asm/arch-mx28/regs-pinctrl.h | 168 ++++++++-------- arch/arm/include/asm/arch-mx28/regs-power.h | 28 ++-- arch/arm/include/asm/arch-mx28/regs-rtc.h | 28 ++-- arch/arm/include/asm/arch-mx28/regs-ssp.h | 40 ++-- arch/arm/include/asm/arch-mx28/regs-timrot.h | 38 ++-- arch/arm/include/asm/arch-mx28/regs-usbphy.h | 20 +- arch/arm/include/asm/arch-mx28/sys_proto.h | 10 +- drivers/gpio/mxs_gpio.c | 16 +- drivers/usb/host/ehci-mxs.c | 8 +- 19 files changed, 441 insertions(+), 437 deletions(-)
arch/arm/cpu/arm926ejs/mx28/clock.c +2 -2
@@ -223,7 +223,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)return ; clkreg = (uint32_t )(&clkctrl_regs->hw_clkctrl_ssp0) + - (ssp *sizeof (struct mx28_register )); + (ssp *sizeof (struct mx28_register_32 ));clrbits_le32 (clkreg,CLKCTRL_SSP_CLKGATE );while (readl (clkreg) &CLKCTRL_SSP_CLKGATE )
@@ -272,7 +272,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)return XTAL_FREQ_KHZ ; clkreg = (uint32_t )(&clkctrl_regs->hw_clkctrl_ssp0) + - (ssp *sizeof (struct mx28_register )); + (ssp *sizeof (struct mx28_register_32 )); tmp =readl (clkreg) &CLKCTRL_SSP_DIV_MASK ;
arch/arm/cpu/arm926ejs/mx28/iomux.c +3 -3
@@ -43,7 +43,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) {u32 reg, ofs, bp, bm;void *iomux_base = (void *)MXS_PINCTRL_BASE ; -struct mx28_register *mxs_reg; +struct mx28_register_32 *mxs_reg;/* muxsel */ ofs =0x100 ;
@@ -70,7 +70,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)/* vol */ if (PAD_VOL_VALID (pad)) { bp =PAD_PIN (pad) %8 *4 +2 ; - mxs_reg = (struct mx28_register *)(iomux_base + ofs); + mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);if (PAD_VOL (pad))writel (1 << bp, &mxs_reg->reg_set);else
@@ -82,7 +82,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) ofs =PULL_OFFSET ; ofs +=PAD_BANK (pad) *0x10 ; bp =PAD_PIN (pad); - mxs_reg = (struct mx28_register *)(iomux_base + ofs); + mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);if (PAD_PULL (pad))writel (1 << bp, &mxs_reg->reg_set);else
arch/arm/cpu/arm926ejs/mx28/mx28.c +3 -3
@@ -63,7 +63,7 @@ void reset_cpu(ulong ignored) ; } -int mx28_wait_mask_set (struct mx28_register *reg,uint32_t mask,int timeout) +int mx28_wait_mask_set (struct mx28_register_32 *reg,uint32_t mask,int timeout) {while (--timeout) {if ((readl (®->reg) & mask) == mask)
@@ -74,7 +74,7 @@ int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout)return !timeout; } -int mx28_wait_mask_clr (struct mx28_register *reg,uint32_t mask,int timeout) +int mx28_wait_mask_clr (struct mx28_register_32 *reg,uint32_t mask,int timeout) {while (--timeout) {if ((readl (®->reg) & mask) ==0 )
@@ -85,7 +85,7 @@ int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout)return !timeout; } -int mx28_reset_block (struct mx28_register *reg) +int mx28_reset_block (struct mx28_register_32 *reg) {/* Clear SFTRST */ writel (MX28_BLOCK_SFTRST , ®->reg_clr);
arch/arm/include/asm/arch-mx28/regs-apbh.h +127 -127
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arch/arm/include/asm/arch-mx28/regs-bch.h +21 -21
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arch/arm/include/asm/arch-mx28/regs-clkctrl.h +29 -29
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arch/arm/include/asm/arch-mx28/regs-common.h +6 -6
@@ -47,20 +47,20 @@* */ -#define __mx28_reg (name) \ +#define __mx28_reg_32 (name) \ uint32_t name; \ uint32_t name##_set; \ uint32_t name##_clr; \ uint32_t name##_tog; -struct mx28_register { - __mx28_reg(reg) +struct mx28_register_32 { + __mx28_reg_32(reg) }; -#define mx28_reg (name) \ +#define mx28_reg_32 (name) \ union { \ - struct { __mx28_reg(name) }; \ - struct mx28_register name##_reg; \ + struct { __mx28_reg_32(name) }; \ + struct mx28_register_32 name##_reg; \ };#endif /* __MX28_REGS_COMMON_H__ */
arch/arm/include/asm/arch-mx28/regs-gpmi.h +13 -13
@@ -30,22 +30,22 @@#ifndef __ASSEMBLY__struct mx28_gpmi_regs { -mx28_reg (hw_gpmi_ctrl0) - mx28_reg(hw_gpmi_compare) -mx28_reg (hw_gpmi_eccctrl) - mx28_reg(hw_gpmi_ecccount) -mx28_reg (hw_gpmi_payload) - mx28_reg(hw_gpmi_auxiliary) -mx28_reg (hw_gpmi_ctrl1) - mx28_reg(hw_gpmi_timing0) -mx28_reg (hw_gpmi_timing1) +mx28_reg_32 (hw_gpmi_ctrl0) + mx28_reg_32(hw_gpmi_compare) +mx28_reg_32 (hw_gpmi_eccctrl) + mx28_reg_32(hw_gpmi_ecccount) +mx28_reg_32 (hw_gpmi_payload) + mx28_reg_32(hw_gpmi_auxiliary) +mx28_reg_32 (hw_gpmi_ctrl1) + mx28_reg_32(hw_gpmi_timing0) +mx28_reg_32 (hw_gpmi_timing1) uint32_t reserved[4]; -mx28_reg (hw_gpmi_data) - mx28_reg(hw_gpmi_stat) -mx28_reg (hw_gpmi_debug) - mx28_reg(hw_gpmi_version) +mx28_reg_32 (hw_gpmi_data) + mx28_reg_32(hw_gpmi_stat) +mx28_reg_32 (hw_gpmi_debug) + mx28_reg_32(hw_gpmi_version) };#endif
arch/arm/include/asm/arch-mx28/regs-i2c.h +14 -14
@@ -27,20 +27,20 @@#ifndef __ASSEMBLY__struct mx28_i2c_regs { -mx28_reg (hw_i2c_ctrl0) - mx28_reg(hw_i2c_timing0) -mx28_reg (hw_i2c_timing1) - mx28_reg(hw_i2c_timing2) -mx28_reg (hw_i2c_ctrl1) - mx28_reg(hw_i2c_stat) -mx28_reg (hw_i2c_queuectrl) - mx28_reg(hw_i2c_queuestat) -mx28_reg (hw_i2c_queuecmd) - mx28_reg(hw_i2c_queuedata) -mx28_reg (hw_i2c_data) - mx28_reg(hw_i2c_debug0) -mx28_reg (hw_i2c_debug1) - mx28_reg(hw_i2c_version) +mx28_reg_32 (hw_i2c_ctrl0) + mx28_reg_32(hw_i2c_timing0) +mx28_reg_32 (hw_i2c_timing1) + mx28_reg_32(hw_i2c_timing2) +mx28_reg_32 (hw_i2c_ctrl1) + mx28_reg_32(hw_i2c_stat) +mx28_reg_32 (hw_i2c_queuectrl) + mx28_reg_32(hw_i2c_queuestat) +mx28_reg_32 (hw_i2c_queuecmd) + mx28_reg_32(hw_i2c_queuedata) +mx28_reg_32 (hw_i2c_data) + mx28_reg_32(hw_i2c_debug0) +mx28_reg_32 (hw_i2c_debug1) + mx28_reg_32(hw_i2c_version) };#endif
arch/arm/include/asm/arch-mx28/regs-ocotp.h +43 -43
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arch/arm/include/asm/arch-mx28/regs-pinctrl.h +84 -84
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arch/arm/include/asm/arch-mx28/regs-power.h +14 -14
@@ -26,10 +26,10 @@ #ifndef __ASSEMBLY__ struct mx28_power_regs { - mx28_reg(hw_power_ctrl) - mx28_reg(hw_power_5vctrl) - mx28_reg(hw_power_minpwr) - mx28_reg(hw_power_charge) + mx28_reg_32(hw_power_ctrl) + mx28_reg_32(hw_power_5vctrl) + mx28_reg_32(hw_power_minpwr) + mx28_reg_32(hw_power_charge) uint32_t hw_power_vdddctrl; uint32_t reserved_vddd[3]; uint32_t hw_power_vddactrl;
@@ -44,23 +44,23 @@ struct mx28_power_regs {uint32_t reserved_misc[3 ];uint32_t hw_power_dclimits;uint32_t reserved_dclimits[3 ]; -mx28_reg (hw_power_loopctrl) +mx28_reg_32 (hw_power_loopctrl) uint32_t hw_power_sts;uint32_t reserved_sts[3 ]; -mx28_reg (hw_power_speed) +mx28_reg_32 (hw_power_speed) uint32_t hw_power_battmonitor;uint32_t reserved_battmonitor[3 ];uint32_t reserved[4 ]; - mx28_reg(hw_power_reset) - mx28_reg(hw_power_debug) - mx28_reg(hw_power_thermal) - mx28_reg(hw_power_usb1ctrl) - mx28_reg(hw_power_special) - mx28_reg(hw_power_version) - mx28_reg(hw_power_anaclkctrl) - mx28_reg(hw_power_refctrl) + mx28_reg_32(hw_power_reset) + mx28_reg_32(hw_power_debug) + mx28_reg_32(hw_power_thermal) + mx28_reg_32(hw_power_usb1ctrl) + mx28_reg_32(hw_power_special) + mx28_reg_32(hw_power_version) + mx28_reg_32(hw_power_anaclkctrl) + mx28_reg_32(hw_power_refctrl) };#endif
arch/arm/include/asm/arch-mx28/regs-rtc.h +14 -14
@@ -27,20 +27,20 @@#ifndef __ASSEMBLY__struct mx28_rtc_regs { -mx28_reg (hw_rtc_ctrl) - mx28_reg(hw_rtc_stat) -mx28_reg (hw_rtc_milliseconds) - mx28_reg(hw_rtc_seconds) -mx28_reg (hw_rtc_rtc_alarm) - mx28_reg(hw_rtc_watchdog) -mx28_reg (hw_rtc_persistent0) - mx28_reg(hw_rtc_persistent1) -mx28_reg (hw_rtc_persistent2) - mx28_reg(hw_rtc_persistent3) -mx28_reg (hw_rtc_persistent4) - mx28_reg(hw_rtc_persistent5) -mx28_reg (hw_rtc_debug) - mx28_reg(hw_rtc_version) +mx28_reg_32 (hw_rtc_ctrl) + mx28_reg_32(hw_rtc_stat) +mx28_reg_32 (hw_rtc_milliseconds) + mx28_reg_32(hw_rtc_seconds) +mx28_reg_32 (hw_rtc_rtc_alarm) + mx28_reg_32(hw_rtc_watchdog) +mx28_reg_32 (hw_rtc_persistent0) + mx28_reg_32(hw_rtc_persistent1) +mx28_reg_32 (hw_rtc_persistent2) + mx28_reg_32(hw_rtc_persistent3) +mx28_reg_32 (hw_rtc_persistent4) + mx28_reg_32(hw_rtc_persistent5) +mx28_reg_32 (hw_rtc_debug) + mx28_reg_32(hw_rtc_version) };#endif
arch/arm/include/asm/arch-mx28/regs-ssp.h +20 -20
@@ -29,26 +29,26 @@#ifndef __ASSEMBLY__struct mx28_ssp_regs { -mx28_reg (hw_ssp_ctrl0) - mx28_reg(hw_ssp_cmd0) -mx28_reg (hw_ssp_cmd1) - mx28_reg(hw_ssp_xfer_size) -mx28_reg (hw_ssp_block_size) - mx28_reg(hw_ssp_compref) -mx28_reg (hw_ssp_compmask) - mx28_reg(hw_ssp_timing) -mx28_reg (hw_ssp_ctrl1) - mx28_reg(hw_ssp_data) -mx28_reg (hw_ssp_sdresp0) - mx28_reg(hw_ssp_sdresp1) -mx28_reg (hw_ssp_sdresp2) - mx28_reg(hw_ssp_sdresp3) -mx28_reg (hw_ssp_ddr_ctrl) - mx28_reg(hw_ssp_dll_ctrl) -mx28_reg (hw_ssp_status) - mx28_reg(hw_ssp_dll_sts) -mx28_reg (hw_ssp_debug) - mx28_reg(hw_ssp_version) +mx28_reg_32 (hw_ssp_ctrl0) + mx28_reg_32(hw_ssp_cmd0) +mx28_reg_32 (hw_ssp_cmd1) + mx28_reg_32(hw_ssp_xfer_size) +mx28_reg_32 (hw_ssp_block_size) + mx28_reg_32(hw_ssp_compref) +mx28_reg_32 (hw_ssp_compmask) + mx28_reg_32(hw_ssp_timing) +mx28_reg_32 (hw_ssp_ctrl1) + mx28_reg_32(hw_ssp_data) +mx28_reg_32 (hw_ssp_sdresp0) + mx28_reg_32(hw_ssp_sdresp1) +mx28_reg_32 (hw_ssp_sdresp2) + mx28_reg_32(hw_ssp_sdresp3) +mx28_reg_32 (hw_ssp_ddr_ctrl) + mx28_reg_32(hw_ssp_dll_ctrl) +mx28_reg_32 (hw_ssp_status) + mx28_reg_32(hw_ssp_dll_sts) +mx28_reg_32 (hw_ssp_debug) + mx28_reg_32(hw_ssp_version) };#endif
arch/arm/include/asm/arch-mx28/regs-timrot.h +19 -19
@@ -29,25 +29,25 @@#ifndef __ASSEMBLY__struct mx28_timrot_regs { -mx28_reg (hw_timrot_rotctrl) - mx28_reg(hw_timrot_rotcount) -mx28_reg (hw_timrot_timctrl0) - mx28_reg(hw_timrot_running_count0) -mx28_reg (hw_timrot_fixed_count0) - mx28_reg(hw_timrot_match_count0) -mx28_reg (hw_timrot_timctrl1) - mx28_reg(hw_timrot_running_count1) -mx28_reg (hw_timrot_fixed_count1) - mx28_reg(hw_timrot_match_count1) -mx28_reg (hw_timrot_timctrl2) - mx28_reg(hw_timrot_running_count2) -mx28_reg (hw_timrot_fixed_count2) - mx28_reg(hw_timrot_match_count2) -mx28_reg (hw_timrot_timctrl3) - mx28_reg(hw_timrot_running_count3) -mx28_reg (hw_timrot_fixed_count3) - mx28_reg(hw_timrot_match_count3) - mx28_reg(hw_timrot_version) +mx28_reg_32 (hw_timrot_rotctrl) + mx28_reg_32(hw_timrot_rotcount) +mx28_reg_32 (hw_timrot_timctrl0) + mx28_reg_32(hw_timrot_running_count0) +mx28_reg_32 (hw_timrot_fixed_count0) + mx28_reg_32(hw_timrot_match_count0) +mx28_reg_32 (hw_timrot_timctrl1) + mx28_reg_32(hw_timrot_running_count1) +mx28_reg_32 (hw_timrot_fixed_count1) + mx28_reg_32(hw_timrot_match_count1) +mx28_reg_32 (hw_timrot_timctrl2) + mx28_reg_32(hw_timrot_running_count2) +mx28_reg_32 (hw_timrot_fixed_count2) + mx28_reg_32(hw_timrot_match_count2) +mx28_reg_32 (hw_timrot_timctrl3) + mx28_reg_32(hw_timrot_running_count3) +mx28_reg_32 (hw_timrot_fixed_count3) + mx28_reg_32(hw_timrot_match_count3) + mx28_reg_32(hw_timrot_version) };#endif
arch/arm/include/asm/arch-mx28/regs-usbphy.h +10 -10
@@ -24,16 +24,16 @@#define __REGS_USBPHY_H__struct mx28_usbphy_regs { -mx28_reg (hw_usbphy_pwd) - mx28_reg(hw_usbphy_tx) -mx28_reg (hw_usbphy_rx) - mx28_reg(hw_usbphy_ctrl) -mx28_reg (hw_usbphy_status) - mx28_reg(hw_usbphy_debug) -mx28_reg (hw_usbphy_debug0_status) - mx28_reg(hw_usbphy_debug1) -mx28_reg (hw_usbphy_version) - mx28_reg(hw_usbphy_ip) +mx28_reg_32 (hw_usbphy_pwd) + mx28_reg_32(hw_usbphy_tx) +mx28_reg_32 (hw_usbphy_rx) + mx28_reg_32(hw_usbphy_ctrl) +mx28_reg_32 (hw_usbphy_status) + mx28_reg_32(hw_usbphy_debug) +mx28_reg_32 (hw_usbphy_debug0_status) + mx28_reg_32(hw_usbphy_debug1) +mx28_reg_32 (hw_usbphy_version) + mx28_reg_32(hw_usbphy_ip) };#define USBPHY_PWD_RXPWDRX (1 << 20)
arch/arm/include/asm/arch-mx28/sys_proto.h +7 -3
@@ -23,9 +23,13 @@#ifndef __MX28_H__#define __MX28_H__ -int mx28_reset_block (struct mx28_register *reg); -int mx28_wait_mask_set (struct mx28_register *reg,uint32_t mask,int timeout); -int mx28_wait_mask_clr (struct mx28_register *reg,uint32_t mask,int timeout); +int mx28_reset_block (struct mx28_register_32 *reg); +int mx28_wait_mask_set (struct mx28_register_32 *reg, +uint32_t mask, +int timeout); +int mx28_wait_mask_clr (struct mx28_register_32 *reg, +uint32_t mask, +int timeout);int mxsmmc_initialize (bd_t *bis,int id,int (*wp)(int ));
drivers/gpio/mxs_gpio.c +8 -8
@@ -73,8 +73,8 @@ int gpio_get_value(unsigned gpio) {uint32_t bank =PAD_BANK (gpio);uint32_t offset =PINCTRL_DIN (bank); -struct mx28_register *reg = - (struct mx28_register *)(MXS_PINCTRL_BASE + offset); +struct mx28_register_32 *reg = + (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);return (readl (®->reg) >>PAD_PIN (gpio)) &1 ; }
@@ -83,8 +83,8 @@ void gpio_set_value(unsigned gpio, int value) {uint32_t bank =PAD_BANK (gpio);uint32_t offset =PINCTRL_DOUT (bank); -struct mx28_register *reg = - (struct mx28_register *)(MXS_PINCTRL_BASE + offset); +struct mx28_register_32 *reg = + (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);if (value)writel (1 <<PAD_PIN (gpio), ®->reg_set);
@@ -96,8 +96,8 @@ int gpio_direction_input(unsigned gpio) {uint32_t bank =PAD_BANK (gpio);uint32_t offset =PINCTRL_DOE (bank); -struct mx28_register *reg = - (struct mx28_register *)(MXS_PINCTRL_BASE + offset); +struct mx28_register_32 *reg = + (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);writel (1 <<PAD_PIN (gpio), ®->reg_clr);
@@ -108,8 +108,8 @@ int gpio_direction_output(unsigned gpio, int value) {uint32_t bank =PAD_BANK (gpio);uint32_t offset =PINCTRL_DOE (bank); -struct mx28_register *reg = - (struct mx28_register *)(MXS_PINCTRL_BASE + offset); +struct mx28_register_32 *reg = + (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);writel (1 <<PAD_PIN (gpio), ®->reg_set);
drivers/usb/host/ehci-mxs.c +4 -4
@@ -75,8 +75,8 @@ int ehci_hcd_init(void)int ret;uint32_t usb_base, cap_base; -struct mx28_register *digctl_ctrl = - (struct mx28_register *)HW_DIGCTL_CTRL ; +struct mx28_register_32 *digctl_ctrl = + (struct mx28_register_32 *)HW_DIGCTL_CTRL ;struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ;
@@ -119,8 +119,8 @@ int ehci_hcd_stop(void) {int ret;uint32_t tmp; -struct mx28_register *digctl_ctrl = - (struct mx28_register *)HW_DIGCTL_CTRL ; +struct mx28_register_32 *digctl_ctrl = + (struct mx28_register_32 *)HW_DIGCTL_CTRL ;struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ;
Signature · 1 line
1.7.0.4
PATCH v4 2/4 Introducing 8-bit wide register, mx28_register_8
In reply to robert at delien.nlFrom: Robert Delien <[email protected]>
This patch introduces an 8-bit register, mx28_register_8, in order to prepare for fixing erroneous 32-bit wide access of registers hw_clkctrl_frac0 and hw_clkctrl_frac1.
--- arch/arm/include/asm/arch-mx28/regs-common.h | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-)
arch/arm/include/asm/arch-mx28/regs-common.h +16 -0
@@ -47,16 +47,32 @@* */ +#define __mx28_reg_8 (name) \ + uint8_t name[4]; \ + uint8_t name##_set[4]; \ + uint8_t name##_clr[4]; \ + uint8_t name##_tog[4]; \ +#define __mx28_reg_32 (name) \ uint32_t name; \ uint32_t name##_set; \ uint32_t name##_clr; \ uint32_t name##_tog; +struct mx28_register_8 { +__mx28_reg_8 (reg) +}; +struct mx28_register_32 { __mx28_reg_32(reg) }; +#define mx28_reg_8 (name) \ + union { \ + struct { __mx28_reg_8(name) }; \ + struct mx28_register_32 name##_reg; \ + }; +#define mx28_reg_32 (name) \ union { \ struct { __mx28_reg_32(name) }; \
Signature · 1 line
1.7.0.4
PATCH v4 3/4 Fix erroneous 32-bit access to hw_clkctrl_frac0 and hw_clkctrl_frac1 registers
In reply to robert at delien.nlFrom: Robert Delien <[email protected]>
This patch fixes erroneous 32-bit access to registers hw_clkctrl_frac0 and hw_clkctrl_frac1.
--- arch/arm/cpu/arm926ejs/mx28/clock.c | 70 ++++++++++--------------- arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 26 ++++----- arch/arm/include/asm/arch-mx28/regs-clkctrl.h | 44 +++++----------- 3 files changed, 52 insertions(+), 88 deletions(-)
arch/arm/cpu/arm926ejs/mx28/clock.c +27 -43
@@ -46,8 +46,8 @@ static uint32_t mx28_get_pclk(void)struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ; -uint32_t clkctrl, clkseq, clkfrac; -uint32_t frac, div; +uint32_t clkctrl, clkseq, div; +uint8_t clkfrac, frac; clkctrl =readl (&clkctrl_regs->hw_clkctrl_cpu);
@@ -67,8 +67,8 @@ static uint32_t mx28_get_pclk(void) }/* REF Path */ - clkfrac =readl (&clkctrl_regs->hw_clkctrl_frac0); - frac = clkfrac &CLKCTRL_FRAC0_CPUFRAC_MASK ; + clkfrac =readb (&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU ]); + frac = clkfrac &CLKCTRL_FRAC_FRAC_MASK ; div = clkctrl &CLKCTRL_CPU_DIV_CPU_MASK ;return (PLL_FREQ_MHZ *PLL_FREQ_COEF / frac) / div; }
@@ -96,8 +96,8 @@ static uint32_t mx28_get_emiclk(void)struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ; -uint32_t frac, div; -uint32_t clkctrl, clkseq, clkfrac; +uint32_t clkctrl, clkseq, div; +uint8_t clkfrac, frac; clkseq =readl (&clkctrl_regs->hw_clkctrl_clkseq); clkctrl =readl (&clkctrl_regs->hw_clkctrl_emi);
@@ -109,11 +109,9 @@ static uint32_t mx28_get_emiclk(void)return XTAL_FREQ_MHZ / div; } - clkfrac =readl (&clkctrl_regs->hw_clkctrl_frac0); -/* REF Path */ - frac = (clkfrac &CLKCTRL_FRAC0_EMIFRAC_MASK ) >> -CLKCTRL_FRAC0_EMIFRAC_OFFSET ; + clkfrac =readb (&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI ]); + frac = clkfrac &CLKCTRL_FRAC_FRAC_MASK ; div = clkctrl &CLKCTRL_EMI_DIV_EMI_MASK ;return (PLL_FREQ_MHZ *PLL_FREQ_COEF / frac) / div; }
@@ -123,8 +121,8 @@ static uint32_t mx28_get_gpmiclk(void)struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ; -uint32_t frac, div; -uint32_t clkctrl, clkseq, clkfrac; +uint32_t clkctrl, clkseq, div; +uint8_t clkfrac, frac; clkseq =readl (&clkctrl_regs->hw_clkctrl_clkseq); clkctrl =readl (&clkctrl_regs->hw_clkctrl_gpmi);
@@ -135,11 +133,9 @@ static uint32_t mx28_get_gpmiclk(void)return XTAL_FREQ_MHZ / div; } - clkfrac =readl (&clkctrl_regs->hw_clkctrl_frac1); -/* REF Path */ - frac = (clkfrac &CLKCTRL_FRAC1_GPMIFRAC_MASK ) >> -CLKCTRL_FRAC1_GPMIFRAC_OFFSET ; + clkfrac =readb (&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI ]); + frac = clkfrac &CLKCTRL_FRAC_FRAC_MASK ; div = clkctrl &CLKCTRL_GPMI_DIV_MASK ;return (PLL_FREQ_MHZ *PLL_FREQ_COEF / frac) / div; }
@@ -152,11 +148,12 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ;uint32_t div; +int io_reg;if (freq ==0 )return ; -if (io >MXC_IOCLK1 ) +if ((io <MXC_IOCLK0 ) || (io >MXC_IOCLK1 ))return ; div = (PLL_FREQ_KHZ *PLL_FREQ_COEF ) / freq;
@@ -167,23 +164,13 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)if (div >35 ) div =35 ; -if (io ==MXC_IOCLK0 ) { -writel (CLKCTRL_FRAC0_CLKGATEIO0 , - &clkctrl_regs->hw_clkctrl_frac0_set); -clrsetbits_le32 (&clkctrl_regs->hw_clkctrl_frac0, -CLKCTRL_FRAC0_IO0FRAC_MASK , - div <<CLKCTRL_FRAC0_IO0FRAC_OFFSET ); -writel (CLKCTRL_FRAC0_CLKGATEIO0 , - &clkctrl_regs->hw_clkctrl_frac0_clr); - }else { -writel (CLKCTRL_FRAC0_CLKGATEIO1 , - &clkctrl_regs->hw_clkctrl_frac0_set); -clrsetbits_le32 (&clkctrl_regs->hw_clkctrl_frac0, -CLKCTRL_FRAC0_IO1FRAC_MASK , - div <<CLKCTRL_FRAC0_IO1FRAC_OFFSET ); -writel (CLKCTRL_FRAC0_CLKGATEIO1 , - &clkctrl_regs->hw_clkctrl_frac0_clr); - } + io_reg =MXC_IOCLK1 - io;/* Register order is reversed */ +writeb (CLKCTRL_FRAC_CLKGATE , + &clkctrl_regs->hw_clkctrl_frac0_set[io_reg]); +writeb (CLKCTRL_FRAC_CLKGATE | (div &CLKCTRL_FRAC_FRAC_MASK ), + &clkctrl_regs->hw_clkctrl_frac0[io_reg]); +writeb (CLKCTRL_FRAC_CLKGATE , + &clkctrl_regs->hw_clkctrl_frac0_clr[io_reg]); }/*
@@ -193,19 +180,16 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io) {struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ; -uint32_t tmp, ret; +uint8_t ret; +int io_reg; -if (io >MXC_IOCLK1 ) +if ((io <MXC_IOCLK0 ) || (io >MXC_IOCLK1 ))return 0 ; - tmp =readl (&clkctrl_regs->hw_clkctrl_frac0); + io_reg =MXC_IOCLK1 - io;/* Register order is reversed */ -if (io ==MXC_IOCLK0 ) - ret = (tmp &CLKCTRL_FRAC0_IO0FRAC_MASK ) >> -CLKCTRL_FRAC0_IO0FRAC_OFFSET ; -else - ret = (tmp &CLKCTRL_FRAC0_IO1FRAC_MASK ) >> -CLKCTRL_FRAC0_IO1FRAC_OFFSET ; + ret =readb (&clkctrl_regs->hw_clkctrl_frac0[io_reg]) & +CLKCTRL_FRAC_FRAC_MASK ;return (PLL_FREQ_KHZ *PLL_FREQ_COEF ) / ret; }
arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +12 -14
@@ -86,22 +86,20 @@ void mx28_mem_init_clock(void) (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ;/* Gate EMI clock */ -writel (CLKCTRL_FRAC0_CLKGATEEMI , - &clkctrl_regs->hw_clkctrl_frac0_set); +writeb (CLKCTRL_FRAC_CLKGATE , + &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI ]); -/* EMI = 205MHz */ -writel (CLKCTRL_FRAC0_EMIFRAC_MASK , - &clkctrl_regs->hw_clkctrl_frac0_set); -writel ((0x2a <<CLKCTRL_FRAC0_EMIFRAC_OFFSET ) & -CLKCTRL_FRAC0_EMIFRAC_MASK , - &clkctrl_regs->hw_clkctrl_frac0_clr); +/* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */ +writeb (CLKCTRL_FRAC_CLKGATE | (21 &CLKCTRL_FRAC_FRAC_MASK ), + &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI ]);/* Ungate EMI clock */ -writel (CLKCTRL_FRAC0_CLKGATEEMI , - &clkctrl_regs->hw_clkctrl_frac0_clr); +writeb (CLKCTRL_FRAC_CLKGATE , + &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI ]);early_delay (11000 ); +/* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */ writel ((2 <<CLKCTRL_EMI_DIV_EMI_OFFSET ) | (1 <<CLKCTRL_EMI_DIV_XTAL_OFFSET ), &clkctrl_regs->hw_clkctrl_emi);
@@ -118,10 +116,10 @@ void mx28_mem_setup_cpu_and_hbus(void)struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ; -/* CPU = 454MHz and ungate CPU clock */ -clrsetbits_le32 (&clkctrl_regs->hw_clkctrl_frac0, -CLKCTRL_FRAC0_CPUFRAC_MASK |CLKCTRL_FRAC0_CLKGATECPU , -19 <<CLKCTRL_FRAC0_CPUFRAC_OFFSET ); +/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz +* and ungate CPU clock */ +writeb (19 &CLKCTRL_FRAC_FRAC_MASK , + (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU ]);/* Set CPU bypass */ writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
arch/arm/include/asm/arch-mx28/regs-clkctrl.h +13 -31
56 lines not on this page · raw message
Signature · 1 line
1.7.0.4
PATCH v4 4/4 Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL
In reply to robert at delien.nlFrom: Robert Delien <[email protected]>
This patch prevents the needless switching on and off of PLL bypass mode. With this patch in place, single-stepping through the SPL is now possible.
--- arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 4 ---- arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 24 ------------------------ 2 files changed, 0 insertions(+), 28 deletions(-)
arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +0 -4
@@ -121,10 +121,6 @@ void mx28_mem_setup_cpu_and_hbus(void)writeb (19 &CLKCTRL_FRAC_FRAC_MASK , (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU ]); -/* Set CPU bypass */ -writel (CLKCTRL_CLKSEQ_BYPASS_CPU , - &clkctrl_regs->hw_clkctrl_clkseq_set); -/* HBUS = 151MHz */ writel (CLKCTRL_HBUS_DIV_MASK , &clkctrl_regs->hw_clkctrl_hbus_set); writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +0 -24
@@ -30,28 +30,6 @@#include "mx28_init.h" -void mx28_power_clock2xtal (void ) -{ -struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ; - -/* Set XTAL as CPU reference clock */ -writel (CLKCTRL_CLKSEQ_BYPASS_CPU , - &clkctrl_regs->hw_clkctrl_clkseq_set); -} - -void mx28_power_clock2pll (void ) -{ -struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ; - -writel (CLKCTRL_PLL0CTRL0_POWER , - &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); -early_delay (100 ); -writel (CLKCTRL_CLKSEQ_BYPASS_CPU , - &clkctrl_regs->hw_clkctrl_clkseq_clr); -} -void mx28_power_clear_auto_restart (void ) { struct mx28_rtc_regs *rtc_regs =
@@ -606,7 +584,6 @@ void mx28_power_configure_power_source(void)mx28_src_power_init ();mx28_5v_boot (); -mx28_power_clock2pll ();mx28_init_batt_bo ();mx28_switch_vddd_to_dcdc_source ();
@@ -880,7 +857,6 @@ void mx28_power_init(void)struct mx28_power_regs *power_regs = (struct mx28_power_regs *)MXS_POWER_BASE ; -mx28_power_clock2xtal ();mx28_power_clear_auto_restart ();mx28_power_set_linreg ();mx28_power_setup_5v_detect ();
Signature · 1 line
1.7.0.4
PATCH v4 4/4 Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL
Quoted 5 lines
From: Robert Delien <[email protected]>
This patch prevents the needless switching on and off of PLL bypass mode. With this patch in place, single-stepping through the SPL is now possible.
Why did FSL have it in the bootlets though? Fabio, can you explain?
M
Quoted 72 lines
Signed-off-by Robert Delien <[email protected]>--- arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 4 ---- arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 24------------------------ 2 files changed, 0 insertions(+), 28 deletions(-)
(quoted diff) +0
-0
b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.cindex f2fab7c..cf4361c 100644arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +0
-4@@ -121,10 +121,6 @@ void mx28_mem_setup_cpu_and_hbus(void)writeb (19 &CLKCTRL_FRAC_FRAC_MASK , (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU ]); -/* Set CPU bypass */ -writel (CLKCTRL_CLKSEQ_BYPASS_CPU , - &clkctrl_regs->hw_clkctrl_clkseq_set); -/* HBUS = 151MHz */ writel (CLKCTRL_HBUS_DIV_MASK , &clkctrl_regs->hw_clkctrl_hbus_set); writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,(quoted diff) +0
-0
b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.cindex 380b120..5e21a1e 100644arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +0
-24@@ -30,28 +30,6 @@#include "mx28_init.h" -void mx28_power_clock2xtal (void ) -{ -struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ; - -/* Set XTAL as CPU reference clock */ -writel (CLKCTRL_CLKSEQ_BYPASS_CPU , - &clkctrl_regs->hw_clkctrl_clkseq_set); -} - -void mx28_power_clock2pll (void ) -{ -struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ; - -writel (CLKCTRL_PLL0CTRL0_POWER , - &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); -early_delay (100 ); -writel (CLKCTRL_CLKSEQ_BYPASS_CPU , - &clkctrl_regs->hw_clkctrl_clkseq_clr); -} -void mx28_power_clear_auto_restart (void ) { struct mx28_rtc_regs *rtc_regs =@@ -606,7 +584,6 @@ void mx28_power_configure_power_source(void)mx28_src_power_init ();mx28_5v_boot (); -mx28_power_clock2pll ();mx28_init_batt_bo ();mx28_switch_vddd_to_dcdc_source ();@@ -880,7 +857,6 @@ void mx28_power_init(void)struct mx28_power_regs *power_regs = (struct mx28_power_regs *)MXS_POWER_BASE ; -mx28_power_clock2xtal ();mx28_power_clear_auto_restart ();mx28_power_set_linreg ();mx28_power_setup_5v_detect ();
Fabio Estevam
reviewerPATCH v4 4/4 Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL
Quoted 7 lines · Marek Vasut
Quoted 5 lines
From: Robert Delien <[email protected]>
This patch prevents the needless switching on and off of PLL bypass mode. With this patch in place, single-stepping through the SPL is now possible.
Why did FSL have it in the bootlets though? Fabio, can you explain?
Let me ask around and see what I can find about it.
Regards,
Fabio Estevam
Fabio Estevam
reviewerPATCH v4 4/4 Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL
In reply to Marek VasutHi Marek,
Quoted 7 lines · Marek Vasut
Quoted 5 lines
From: Robert Delien <[email protected]>
This patch prevents the needless switching on and off of PLL bypass mode. With this patch in place, single-stepping through the SPL is now possible.
Why did FSL have it in the bootlets though? Fabio, can you explain?
Anson (in Cc) explained the following:
"The switch of CPU clock is to make our EVK board can boot up the uboot and kernel with less than 100mA power consumption to meet the USB specification, because there is chance that the EVK board is power by USB cable only, we need to make sure in this scenario, before USB enum done, the total power consumption for our EVK board should be less than 100mA, but if CPU running with PLL on, the power consumption is > 100mA under uboot, so we need to disable PLL and switch CPU clock to XTAL before USB enum done."
Regards,
Fabio Estevam
PATCH v4 4/4 Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL
Quoted 13 lines
Hi Marek,
Quoted 7 lines · Marek Vasut
Quoted 5 lines
From: Robert Delien <[email protected]>
This patch prevents the needless switching on and off of PLL bypass mode. With this patch in place, single-stepping through the SPL is now possible.
Why did FSL have it in the bootlets though? Fabio, can you explain?
Anson (in Cc) explained the following:
Quoted 9 lines
"The switch of CPU clock is to make our EVK board can boot up the uboot and kernel with less than 100mA power consumption to meet the USB specification, because there is chance that the EVK board is power by USB cable only, we need to make sure in this scenario, before USB enum done, the total power consumption for our EVK board should be less than 100mA, but if CPU running with PLL on, the power consumption is > 100mA under uboot, so we need to disable PLL and switch CPU clock to XTAL before USB enum done."
And by running off XTAL, the consumption grows so dramatically?
M
A message that is not in the archive (sent off-list or not yet received): F0D11DBEB504444BA6C8DA07A395A35A0438D1@039-SN2MPN1-012.039d.mgd.msft.net
PATCH v4 4/4 Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL
Quoted 2 lines
That is because not only CPU running @ PLL, HBUS also source from
P_CLK, we switch CPU clock to XTAL, the HBUS clock also slow down.
Ok, but you switch it back to PLL after the power supply was configured. And then the consumption grows back.
M
Quoted 43 lines
Best Regards.
Anson huang ???Freescale Semiconductor Shanghai
?????????192?C?2?
201203
Tel:021-28937058$-----Original Message-----
$From: Marek Vasut [mailto:marek.vasut at gmail.com]
$Sent: Wednesday, February 08, 2012 10:43 AM
$To: Fabio Estevam
$Cc: Huang Yongcai-B20788; robert at delien.nl; u-boot at lists.denx.de $Subject: Re: [PATCH 4/4 v4] Preventing needless switching on and off PLL bypass $mode, allowing allow single-stepping through the SPL $
$> Hi Marek,
$>
$> On Tue, Feb 7, 2012 at 2:53 PM, Marek Vasut <[email protected]>
wrote: $> >> From: Robert Delien <[email protected]>
$> >>
$> >> This patch prevents the needless switching on and off of PLL bypass $> >> mode. With this patch in place, single-stepping through the SPL is $> >> now possible.
$> >
$> > Why did FSL have it in the bootlets though? Fabio, can you explain? $>
$> Anson (in Cc) explained the following:
$>
$> "The switch of CPU clock is to make our EVK board can boot up the $> uboot and kernel with less than 100mA power consumption to meet the $> USB specification, because there is chance that the EVK board is power $> by USB cable only, we need to make sure in this scenario, before USB $> enum done, the total power consumption for our EVK board should be $> less than 100mA, but if CPU running with PLL on, the power consumption $> is > 100mA under uboot, so we need to disable PLL and switch CPU clock $> to XTAL before USB enum done."
$>
$
$And by running off XTAL, the consumption grows so dramatically? $
$M
PATCH v4 4/4 Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL
Quoted 2 lines
Ok, but you switch it back to PLL after the power supply was configured. And then the consumption grows back.
Yes, power_init switches to PLL (yet incorrectly). And memory_init switches back to XTAL when configuring hbus for a brief moment, to switch to PLL after hbus is configured. My proposal is to leave out the incorrect first switch, and leave it on XTAL until hbus is configured. Thhough is still doesn't take care the <100mA requirement mentioned by Fabio...
A message that is not in the archive (sent off-list or not yet received): F0D11DBEB504444BA6C8DA07A395A35A043906@039-SN2MPN1-012.039d.mgd.msft.net
PATCH v4 4/4 Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL
Quoted 5 lines
1. Switch
P_CLKto XTAL;
2. Check power source, if there is battery available, we switch back to PLL and make CPU running @ full speed, and power is sourced from battery;
3. If battery is not available, and the power supply is from USB host, then we let CPU running @ XTAL until booting up kernel and USB driver enum done, then switch to PLL.
I fully agree.
PATCH v4 4/4 Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL
In reply to a message not in the archiveQuoted 2 lines
That is because not only CPU running @ PLL, HBUS also source from
P_CLK, we switch CPU clock to XTAL, the HBUS clock also slow down.
You're right, but I'm not switching back to XTAL. I'm just postponing the switch to PLL. Not in the last reason because the first switch to PLL is incorrect (and shouldn't even work).
PATCH v4 4/4 Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL
In reply to Marek VasutQuoted 1 line
And by running off XTAL, the consumption grows so dramatically?
No, switching on the PLL does.
And the PLL can use either the external XTAL or the internal ring- oscillator as a reference. The external XTAL is very accurate, but uses power. The ring-oscillator is not very accurate, but very energy efficient.
On the EVK, the external XTAL cannot be powered down separately, so if it's consuming power anyway, there\s not reason not to use it over the ring-oscillator. But a more generic design may want use ring-oscillator initially.
PATCH v4 4/4 Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL
In reply to Fabio EstevamQuoted 3 lines
"The switch of CPU clock is to make our EVK board can boot up the uboot and kernel with less than 100mA power consumption to meet the USB specification
That's actually a very good point. For that scenario we may even consider to use the SoC's internal 24MHz ring oscillator instead of the crystal.
But this also means that we should disable bypass mode either a whole lot later, or make it depend on CONFIG_USB.
PATCH 1/1 i.MX28: Fix ref_cpu clock setup
In reply to robert at delien.nlQuoted 26 lines
From: Robert Delien <[email protected]>
This set of patches fixes
ref_cpuclock setup.Robert Delien (4):
Renamedmx28_registertomx28_register_32to prepare formx28_register_8Introducing 8-bit wide register,
mx28_register_8Fix erroneous 32-bit access tohw_clkctrl_frac0and
hw_clkctrl_frac1registers
Preventing needless switching on and off PLL bypass mode,
allowing allow single-stepping through the SPLarch/arm/cpu/arm926ejs/mx28/clock.c | 4 +- arch/arm/cpu/arm926ejs/mx28/iomux.c | 6 +- arch/arm/cpu/arm926ejs/mx28/mx28.c | 6 +- arch/arm/include/asm/arch-mx28/regs-apbh.h | 254 ++++++++++++------------ arch/arm/include/asm/arch-mx28/regs-bch.h | 42 ++-- arch/arm/include/asm/arch-mx28/regs-clkctrl.h | 58 +++--- arch/arm/include/asm/arch-mx28/regs-common.h | 12 +- arch/arm/include/asm/arch-mx28/regs-gpmi.h | 26 ++-- arch/arm/include/asm/arch-mx28/regs-i2c.h | 28 ++-- arch/arm/include/asm/arch-mx28/regs-ocotp.h | 86 ++++---- arch/arm/include/asm/arch-mx28/regs-pinctrl.h | 168 ++++++++-------- arch/arm/include/asm/arch-mx28/regs-power.h | 28 ++--
Quoted 8 lines
arch/arm/include/asm/arch-mx28/regs-rtc.h | 28 ++-- arch/arm/include/asm/arch-mx28/regs-ssp.h | 40 ++-- arch/arm/include/asm/arch-mx28/regs-timrot.h | 38 ++-- arch/arm/include/asm/arch-mx28/regs-usbphy.h | 20 +- arch/arm/include/asm/arch-mx28/sys_proto.h | 10 +- drivers/gpio/mxs_gpio.c | 16 +- drivers/usb/host/ehci-mxs.c | 8 +- 19 files changed, 441 insertions(+), 437 deletions(-)
Robert, I tested first three patches on my board and it refuses to boot. Why?
M
PATCH 1/1 i.MX28: Fix ref_cpu clock setup
Quoted 1 line
Robert, I tested first three patches on my board and it refuses to boot. Why?
I'm trying to reproduce, but my workspace no longer builds after a pull... The set obviously works in my own workspace, so I'm trying to figure out the problem.
PATCH 1/1 i.MX28: Fix ref_cpu clock setup
In reply to Marek VasutQuoted 1 line
Robert, I tested first three patches on my board and it refuses to boot. Why?
I can reproduce now. It all goes south after patch 3. I'm working on it.
PATCH 1/1 i.MX28: Fix ref_cpu clock setup
Quoted 4 lines
Quoted 2 lines
Robert, I tested first three patches on my board and it refuses to boot. Why?
I can reproduce now. It all goes south after patch 3. I'm working on it.
Did you even test before submitting? Also, I think if I remove patch 3, it all works fine.
M
PATCH 1/1 i.MX28: Fix ref_cpu clock setup
Quoted 2 lines
Did you even test before submitting? Also, I think if I remove patch 3, it all works fine.
Naturally, I did. Yet on my own SVN controlled workspace, because my GIT workspace of the mainline didn't build yesterday.
I'm looking at the differences now, and there aren't any concerning i.mx28. But we're going on...
PATCH 1/1 i.MX28: Fix ref_cpu clock setup
Quoted 8 lines
Quoted 2 lines
Did you even test before submitting? Also, I think if I remove patch 3, it all works fine.
Naturally, I did. Yet on my own SVN controlled workspace, because my GIT workspace of the mainline didn't build yesterday.
I'm looking at the differences now, and there aren't any concerning i.mx28. But we're going on...
Should be fixed now (look for tbclk in u-boot mailing list) ... there's a patch
PATCH 1/1 i.MX28: Fix ref_cpu clock setup
In reply to Marek VasutQuoted 1 line
Robert, I tested first three patches on my board and it refuses to boot. Why?
The problem is in here:io_reg = MXC_IOCLK1 - io; /* Register order is reversed */
I will rework and resubmit the patches 'soon'. I'm a bit numb of reworking and resubmitting and I just received a board to bringup last week, and that's got my priority.
BTW: It seems that mx28evk DDR2 is overclocked a bit. For example tRCD is set to 3, where it should be. I didn't look into all the other settings yet, because lowering the clock helps for my board, for now.
PATCH 1/1 i.MX28: Fix ref_cpu clock setup
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Robert, I tested first three patches on my board and it refuses to boot. Why?
The problem is in here:
io_reg=MXC_IOCLK1- io; /* Register order is reversed */I will rework and resubmit the patches 'soon'. I'm a bit numb of reworking and resubmitting and I just received a board to bringup last week, and that's got my priority.
git rebase -i HEAD~3
(if you have the patch you want to rework 3 patches deep)
Change "pick" to the left of the patch to "edit"
Do the change in the file.
git add <file>
git rebase --continue
<submit>
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BTW: It seems that mx28evk DDR2 is overclocked a bit. For example tRCD is set to 3, where it should be. I didn't look into all the other settings yet, because lowering the clock helps for my board, for now.
Lowering the clock to what ? I was pondering about this too, the settings in spl_mem_init are for DENX m28 board, so maybe someone should abstract that out.
M
PATCH 1/1 i.MX28: Fix ref_cpu clock setup
Hi Marek,
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git rebase -i HEAD~3
(if you have the patch you want to rework 3 patches deep) Change "pick" to the left of the patch to "edit" Do the change in the file.
git add <file>
git rebase --continue
<submit>
May be tonight, at my hotel room.
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Lowering the clock to what ?
Down to 137MHz works for me. That's way too low, but at least it keeps my board going.
But there's nothing wrong with a frequency of 206MHz, as configured currently; We just should up the CAS to RAS delay to 5 cycles, from the 3 configured currently. Perhaps others parameters need a little attention too, but there are so many registers for DDR to check here...
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I was pondering about this too, the settings in
spl_mem_initare for DENX m28 board, so maybe someone should abstract that out.
I'm not happy with it either, but the way it is now seems to be the most common one. And due to the huge amount of registers, I doubt if it could be abstracted nicely, without turning it into an even bigger mess. I'm afraid there's little alternatives to tuning DDR parameters for each board separately.
Cheers,
Robert.