x86, intel_mid: ADC management

From: Alan Cox <[email protected]>

This is a fold up of the following ported to 3.3

commit f81040398e4b45323d4144fb05c126245e86866d

Author: Mika Westerberg <[email protected]>
Date:   Thu Jan 12 11:51:18 2012 +0200

x86, mrst: add platform data for gpadc driver

Now that the driver is converted to use intel_msic interfaces we can add the platform data back.

commit 6d9d2d390f6e18ce1d419b9e2762c9bf139a80ea

Author: Mika Westerberg <[email protected]>
Date:   Thu Jan 12 11:51:17 2012 +0200

gpadc: convert to use intel_msic

In Medfield all the subdevices in MSIC chip are handled by intel_msic MFD driver. This patch converts gpadc driver to use interfaces provided by intel_msic driver.

This will enable all the users (including sn95031 audio codec) to use gpadc again.

commit f1532c8454b8958aee933a9915862345d62ee3f8

Author: Mika Westerberg <[email protected]>
Date:   Thu Jan 12 11:51:16 2012 +0200

x86, mrst: remove gpadc platform data

Nowadays these devices are handled by intel_msic MFD driver which has slightly different way of passing platform data to the drivers.

So as a first step we remove the old platform data for gpadc driver. In subsequent patches we add it back in such format suitable for intel_msic driver.

commit 8444512429fd93786f114824bb5c258272aa1d2d

Author: Bin Yang <[email protected]>
Date:   Tue Oct 18 14:16:31 2011 +0100

gpadc: add reg dump after timeout

Sometimes, it is very hard to duplicate ADC timeout issue. Some issue only can be duplicated on a small quantity of boards. To add the registers dump after timeout will help debugging.

commit 26fc6e4e72d1cac189064b9c85290e3c8a907cf0

Author: Bin Yang <[email protected]>
Date:   Tue Oct 18 14:16:30 2011 +0100

gpadc: fix battery temp accuracy

From oscilloscope result, BPTHERM takes <1ms to stabilize. So it needs to add 1ms delay after VBUSREF is enabled.

commit 9dc5019e570c59e70349b34ec864bfc447a0d0c5

Author: Bin Yang <[email protected]>
Date:   Tue Oct 18 14:16:30 2011 +0100

gpadc: optimize driver initialization

ADC trimming cost a long time. It blocks the kernel boot sequence. Change to do trimming in a single workqueue.

commit 16149d8e3dfe0d663851318390ebafdede760281

Author: Bin Yang <[email protected]>
Date:   Tue Oct 18 14:16:29 2011 +0100

gpadc: read sample result in one loop

RR bit is used to inform HW for sample result read. it needs to hold the RR bit for all channels result read.

this patch moves the lines to set/clear RR bit outside the loop.

commit d910dd3b07b6e0766c96c59e48de5bcce1175f0c

Author: Bin Yang <[email protected]>
Date:   Tue Oct 18 14:16:29 2011 +0100

gpadc: fix logic err of last addr checking

it has logic error to check last addr which is used.

commit 1b688193bd96331da73482399925d51cbf535780

Author: Bin Yang <[email protected]>
Date:   Tue Oct 18 14:16:28 2011 +0100

gpadc: update the calibration algorithm

gpadc document had updated this algorithm in new version.

This patch updates the driver base on new document.

commit baa74900a34ad17de1619a8f009702e66eb4fbd4

Author: Bin Yang <[email protected]>
Date:   Tue Oct 18 14:16:28 2011 +0100

gpadc: fix sample result error

During stress test, ADC results have some bad valules.
Driver has a race condition issue. It initializes the output data to 0 first without any lock. And the caller may access the output pointer before function return.

This patch moves the output data initializing code inside mutex protected period. And it also adds a limitation which forbid caller to access output pointer before function return.

commit 9c53a361051541a7cb24a8fde90d5c75c5d52d91

Author: He Bo <[email protected]>
Date:   Tue Oct 18 14:16:26 2011 +0100

gpadc: system does not enter S3 after incoming call

intel_mid_gpadc driver causes deadlock in S3, fix it.

commit f25e645c187d3b9943ad0180e52984f51c77e64b

Author: Bin Yang <[email protected]>
Date:   Tue Oct 18 14:16:25 2011 +0100

gpadc: prevent CPU from S0i3 when ADC is active

Under the following scenario:
1. IPC1 request sent to SCU
2. PM_CMD s0ix entry request sent to SCU
3. MWAIT C6 abort (or no attempt at MWAIT C6)
If steps #1 an #2 are sufficiently close (maybe within 200us) there is
a possibility that SCU will handle the PM_CMD first and begin waiting on an ack_c6 response from the MWAIT that is expected. Since the MWAIT never comes (or is aborted) SCU will have to eventually time out before being able to move on and handle the IPC1 request.

commit fdd0adef95e6b5836cc4ed5764a398b81841945d

Author: Bin Yang <[email protected]>
Date:   Tue Oct 18 14:16:23 2011 +0100

The coulomb count interrupt is not used by kernel driver. It needs to be handled inside firmware.

commit 1f4f11af853a74c015a9ffb5bc22d3f9140ce6d5

Author: Bin Yang <[email protected]>
Date:   Tue Oct 18 14:16:19 2011 +0100

gpadc: add gpadc driver support

The general purpose ADC inside MSIC is used by battery and thermal. This driver provides the channel allocation and basic ADC functions.

---

 arch/x86/include/asm/intel_mid_gpadc.h   |   13 +
 arch/x86/platform/mrst/Makefile          |    1 
 arch/x86/platform/mrst/intel_mid_gpadc.c |  645 ++++++++++++++++++++++++++++++
 arch/x86/platform/mrst/mrst.c            |    6 
 4 files changed, 665 insertions(+), 0 deletions(-)
 create mode 100644 arch/x86/include/asm/intel_mid_gpadc.h
 create mode 100644 arch/x86/platform/mrst/intel_mid_gpadc.c

new file mode 100644
index 0000000..ae79309
@@ -0,0 +1,13 @@
+#ifndef __INTEL_MID_GPADC_H__
+#define __INTEL_MID_GPADC_H__
+
+#define CH_NEED_VREF		(1 << 8)
+#define CH_NEED_VCALIB		(1 << 9)
+#define CH_NEED_ICALIB		(1 << 10)
+
+int intel_mid_gpadc_gsmpulse_sample(int *vol, int *cur);
+int intel_mid_gpadc_sample(void *handle, int sample_count, ...);
+void intel_mid_gpadc_free(void *handle);
+void *intel_mid_gpadc_alloc(int count, ...);
+#endif
+

index af1da7e..66e006c 100644
@@ -1,3 +1,4 @@
 obj-$(CONFIG_X86_INTEL_MID)	+= mrst.o
 obj-$(CONFIG_X86_INTEL_MID)	+= vrtc.o
 obj-$(CONFIG_EARLY_PRINTK_INTEL_MID)	+= early_printk_mrst.o
+obj-$(CONFIG_X86_INTEL_MID)	+= intel_mid_gpadc.o

index bdd5ad1..9677d47 100644
@@ -790,6 +790,11 @@ static void *msic_generic_platform_data(void *info, enum intel_msic_block block)
 	return no_platform_data(info);
 }
 
+static void *msic_adc_platform_data(void *info)
+{
+	return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_ADC);
+}
+
 static void *msic_battery_platform_data(void *info)
 {
 	return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_BATTERY);

@@ -864,6 +869,7 @@ static const struct devs_id __initconst device_ids[] = {
 	{"smb347", SFI_DEV_TYPE_I2C, 0, &smb347_platform_data},
 
 	/* MSIC subdevices */
+	{"msic_adc", SFI_DEV_TYPE_IPC, 1, &msic_adc_platform_data},
 	{"msic_battery", SFI_DEV_TYPE_IPC, 1, &msic_battery_platform_data},
 	{"msic_gpio", SFI_DEV_TYPE_IPC, 1, &msic_gpio_platform_data},
 	{"msic_audio", SFI_DEV_TYPE_IPC, 1, &msic_audio_platform_data},

Looks sane at first glance - wanna submit it?

Thanks,

Ingo