i.MX28: Fix ref_cpu clock setup
Subsystems (5)
v5 cover i.MX28: Fix ref_cpu clock setup
From: Robert Delien <[email protected]>
This set of patches fixes ref_cpu clock setup.
Robert Delien (4):
Renamed mx28_register to mx28_register_32 to prepare for
mx28_register_8
Introducing 8-bit wide register, mx28_register_8
Fix erroneous 32-bit access to hw_clkctrl_frac0 and hw_clkctrl_frac1
registers
Preventing needless switching on and off PLL bypass mode, allowing
allow single-stepping through the SPL
arch/arm/cpu/arm926ejs/mx28/clock.c | 74 +++----- arch/arm/cpu/arm926ejs/mx28/iomux.c | 6 +- arch/arm/cpu/arm926ejs/mx28/mx28.c | 6 +- arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 30 ++-- arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 24 --- arch/arm/include/asm/arch-mx28/regs-apbh.h | 254 ++++++++++++------------ arch/arm/include/asm/arch-mx28/regs-bch.h | 42 ++-- arch/arm/include/asm/arch-mx28/regs-clkctrl.h | 98 ++++------ arch/arm/include/asm/arch-mx28/regs-common.h | 28 ++- arch/arm/include/asm/arch-mx28/regs-gpmi.h | 26 ++-- arch/arm/include/asm/arch-mx28/regs-i2c.h | 28 ++-- arch/arm/include/asm/arch-mx28/regs-ocotp.h | 86 ++++---- arch/arm/include/asm/arch-mx28/regs-pinctrl.h | 168 ++++++++-------- arch/arm/include/asm/arch-mx28/regs-power.h | 28 ++-- arch/arm/include/asm/arch-mx28/regs-rtc.h | 28 ++-- arch/arm/include/asm/arch-mx28/regs-ssp.h | 40 ++-- arch/arm/include/asm/arch-mx28/regs-timrot.h | 38 ++-- arch/arm/include/asm/arch-mx28/regs-usbphy.h | 20 +- arch/arm/include/asm/arch-mx28/sys_proto.h | 10 +- drivers/gpio/mxs_gpio.c | 16 +- drivers/usb/host/ehci-mxs.c | 8 +- 21 files changed, 507 insertions(+), 551 deletions(-)
PATCH v5 1/4 Renamed mx28_register to mx28_register_32 to prepare for mx28_register_8
From: Robert Delien <[email protected]>
This patch renames mx28_register to mx28_register_32 in order to prepare for the introduction of an 8-bit register, mx28_register_8.
--- arch/arm/cpu/arm926ejs/mx28/clock.c | 4 +- arch/arm/cpu/arm926ejs/mx28/iomux.c | 6 +- arch/arm/cpu/arm926ejs/mx28/mx28.c | 6 +- arch/arm/include/asm/arch-mx28/regs-apbh.h | 254 ++++++++++++------------ arch/arm/include/asm/arch-mx28/regs-bch.h | 42 ++-- arch/arm/include/asm/arch-mx28/regs-clkctrl.h | 58 +++--- arch/arm/include/asm/arch-mx28/regs-common.h | 12 +- arch/arm/include/asm/arch-mx28/regs-gpmi.h | 26 ++-- arch/arm/include/asm/arch-mx28/regs-i2c.h | 28 ++-- arch/arm/include/asm/arch-mx28/regs-ocotp.h | 86 ++++---- arch/arm/include/asm/arch-mx28/regs-pinctrl.h | 168 ++++++++-------- arch/arm/include/asm/arch-mx28/regs-power.h | 28 ++-- arch/arm/include/asm/arch-mx28/regs-rtc.h | 28 ++-- arch/arm/include/asm/arch-mx28/regs-ssp.h | 40 ++-- arch/arm/include/asm/arch-mx28/regs-timrot.h | 38 ++-- arch/arm/include/asm/arch-mx28/regs-usbphy.h | 20 +- arch/arm/include/asm/arch-mx28/sys_proto.h | 10 +- drivers/gpio/mxs_gpio.c | 16 +- drivers/usb/host/ehci-mxs.c | 8 +- 19 files changed, 441 insertions(+), 437 deletions(-)
arch/arm/cpu/arm926ejs/mx28/clock.c +2 -2
@@ -223,7 +223,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)return ; clkreg = (uint32_t )(&clkctrl_regs->hw_clkctrl_ssp0) + - (ssp *sizeof (struct mx28_register )); + (ssp *sizeof (struct mx28_register_32 ));clrbits_le32 (clkreg,CLKCTRL_SSP_CLKGATE );while (readl (clkreg) &CLKCTRL_SSP_CLKGATE )
@@ -272,7 +272,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)return XTAL_FREQ_KHZ ; clkreg = (uint32_t )(&clkctrl_regs->hw_clkctrl_ssp0) + - (ssp *sizeof (struct mx28_register )); + (ssp *sizeof (struct mx28_register_32 )); tmp =readl (clkreg) &CLKCTRL_SSP_DIV_MASK ;
arch/arm/cpu/arm926ejs/mx28/iomux.c +3 -3
@@ -43,7 +43,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) {u32 reg, ofs, bp, bm;void *iomux_base = (void *)MXS_PINCTRL_BASE ; -struct mx28_register *mxs_reg; +struct mx28_register_32 *mxs_reg;/* muxsel */ ofs =0x100 ;
@@ -70,7 +70,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)/* vol */ if (PAD_VOL_VALID (pad)) { bp =PAD_PIN (pad) %8 *4 +2 ; - mxs_reg = (struct mx28_register *)(iomux_base + ofs); + mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);if (PAD_VOL (pad))writel (1 << bp, &mxs_reg->reg_set);else
@@ -82,7 +82,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad) ofs =PULL_OFFSET ; ofs +=PAD_BANK (pad) *0x10 ; bp =PAD_PIN (pad); - mxs_reg = (struct mx28_register *)(iomux_base + ofs); + mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);if (PAD_PULL (pad))writel (1 << bp, &mxs_reg->reg_set);else
arch/arm/cpu/arm926ejs/mx28/mx28.c +3 -3
@@ -63,7 +63,7 @@ void reset_cpu(ulong ignored) ; } -int mx28_wait_mask_set (struct mx28_register *reg,uint32_t mask,int timeout) +int mx28_wait_mask_set (struct mx28_register_32 *reg,uint32_t mask,int timeout) {while (--timeout) {if ((readl (®->reg) & mask) == mask)
@@ -74,7 +74,7 @@ int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout)return !timeout; } -int mx28_wait_mask_clr (struct mx28_register *reg,uint32_t mask,int timeout) +int mx28_wait_mask_clr (struct mx28_register_32 *reg,uint32_t mask,int timeout) {while (--timeout) {if ((readl (®->reg) & mask) ==0 )
@@ -85,7 +85,7 @@ int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout)return !timeout; } -int mx28_reset_block (struct mx28_register *reg) +int mx28_reset_block (struct mx28_register_32 *reg) {/* Clear SFTRST */ writel (MX28_BLOCK_SFTRST , ®->reg_clr);
arch/arm/include/asm/arch-mx28/regs-apbh.h +127 -127
269 lines not on this page · raw message
arch/arm/include/asm/arch-mx28/regs-bch.h +21 -21
51 lines not on this page · raw message
arch/arm/include/asm/arch-mx28/regs-clkctrl.h +29 -29
67 lines not on this page · raw message
arch/arm/include/asm/arch-mx28/regs-common.h +6 -6
@@ -47,20 +47,20 @@* */ -#define __mx28_reg (name) \ +#define __mx28_reg_32 (name) \ uint32_t name; \ uint32_t name##_set; \ uint32_t name##_clr; \ uint32_t name##_tog; -struct mx28_register { - __mx28_reg(reg) +struct mx28_register_32 { + __mx28_reg_32(reg) }; -#define mx28_reg (name) \ +#define mx28_reg_32 (name) \ union { \ - struct { __mx28_reg(name) }; \ - struct mx28_register name##_reg; \ + struct { __mx28_reg_32(name) }; \ + struct mx28_register_32 name##_reg; \ };#endif /* __MX28_REGS_COMMON_H__ */
arch/arm/include/asm/arch-mx28/regs-gpmi.h +13 -13
@@ -30,22 +30,22 @@#ifndef __ASSEMBLY__struct mx28_gpmi_regs { -mx28_reg (hw_gpmi_ctrl0) - mx28_reg(hw_gpmi_compare) -mx28_reg (hw_gpmi_eccctrl) - mx28_reg(hw_gpmi_ecccount) -mx28_reg (hw_gpmi_payload) - mx28_reg(hw_gpmi_auxiliary) -mx28_reg (hw_gpmi_ctrl1) - mx28_reg(hw_gpmi_timing0) -mx28_reg (hw_gpmi_timing1) +mx28_reg_32 (hw_gpmi_ctrl0) + mx28_reg_32(hw_gpmi_compare) +mx28_reg_32 (hw_gpmi_eccctrl) + mx28_reg_32(hw_gpmi_ecccount) +mx28_reg_32 (hw_gpmi_payload) + mx28_reg_32(hw_gpmi_auxiliary) +mx28_reg_32 (hw_gpmi_ctrl1) + mx28_reg_32(hw_gpmi_timing0) +mx28_reg_32 (hw_gpmi_timing1) uint32_t reserved[4]; -mx28_reg (hw_gpmi_data) - mx28_reg(hw_gpmi_stat) -mx28_reg (hw_gpmi_debug) - mx28_reg(hw_gpmi_version) +mx28_reg_32 (hw_gpmi_data) + mx28_reg_32(hw_gpmi_stat) +mx28_reg_32 (hw_gpmi_debug) + mx28_reg_32(hw_gpmi_version) };#endif
arch/arm/include/asm/arch-mx28/regs-i2c.h +14 -14
@@ -27,20 +27,20 @@#ifndef __ASSEMBLY__struct mx28_i2c_regs { -mx28_reg (hw_i2c_ctrl0) - mx28_reg(hw_i2c_timing0) -mx28_reg (hw_i2c_timing1) - mx28_reg(hw_i2c_timing2) -mx28_reg (hw_i2c_ctrl1) - mx28_reg(hw_i2c_stat) -mx28_reg (hw_i2c_queuectrl) - mx28_reg(hw_i2c_queuestat) -mx28_reg (hw_i2c_queuecmd) - mx28_reg(hw_i2c_queuedata) -mx28_reg (hw_i2c_data) - mx28_reg(hw_i2c_debug0) -mx28_reg (hw_i2c_debug1) - mx28_reg(hw_i2c_version) +mx28_reg_32 (hw_i2c_ctrl0) + mx28_reg_32(hw_i2c_timing0) +mx28_reg_32 (hw_i2c_timing1) + mx28_reg_32(hw_i2c_timing2) +mx28_reg_32 (hw_i2c_ctrl1) + mx28_reg_32(hw_i2c_stat) +mx28_reg_32 (hw_i2c_queuectrl) + mx28_reg_32(hw_i2c_queuestat) +mx28_reg_32 (hw_i2c_queuecmd) + mx28_reg_32(hw_i2c_queuedata) +mx28_reg_32 (hw_i2c_data) + mx28_reg_32(hw_i2c_debug0) +mx28_reg_32 (hw_i2c_debug1) + mx28_reg_32(hw_i2c_version) };#endif
arch/arm/include/asm/arch-mx28/regs-ocotp.h +43 -43
92 lines not on this page · raw message
arch/arm/include/asm/arch-mx28/regs-pinctrl.h +84 -84
213 lines not on this page · raw message
arch/arm/include/asm/arch-mx28/regs-power.h +14 -14
@@ -26,10 +26,10 @@ #ifndef __ASSEMBLY__ struct mx28_power_regs { - mx28_reg(hw_power_ctrl) - mx28_reg(hw_power_5vctrl) - mx28_reg(hw_power_minpwr) - mx28_reg(hw_power_charge) + mx28_reg_32(hw_power_ctrl) + mx28_reg_32(hw_power_5vctrl) + mx28_reg_32(hw_power_minpwr) + mx28_reg_32(hw_power_charge) uint32_t hw_power_vdddctrl; uint32_t reserved_vddd[3]; uint32_t hw_power_vddactrl;
@@ -44,23 +44,23 @@ struct mx28_power_regs {uint32_t reserved_misc[3 ];uint32_t hw_power_dclimits;uint32_t reserved_dclimits[3 ]; -mx28_reg (hw_power_loopctrl) +mx28_reg_32 (hw_power_loopctrl) uint32_t hw_power_sts;uint32_t reserved_sts[3 ]; -mx28_reg (hw_power_speed) +mx28_reg_32 (hw_power_speed) uint32_t hw_power_battmonitor;uint32_t reserved_battmonitor[3 ];uint32_t reserved[4 ]; - mx28_reg(hw_power_reset) - mx28_reg(hw_power_debug) - mx28_reg(hw_power_thermal) - mx28_reg(hw_power_usb1ctrl) - mx28_reg(hw_power_special) - mx28_reg(hw_power_version) - mx28_reg(hw_power_anaclkctrl) - mx28_reg(hw_power_refctrl) + mx28_reg_32(hw_power_reset) + mx28_reg_32(hw_power_debug) + mx28_reg_32(hw_power_thermal) + mx28_reg_32(hw_power_usb1ctrl) + mx28_reg_32(hw_power_special) + mx28_reg_32(hw_power_version) + mx28_reg_32(hw_power_anaclkctrl) + mx28_reg_32(hw_power_refctrl) };#endif
arch/arm/include/asm/arch-mx28/regs-rtc.h +14 -14
@@ -27,20 +27,20 @@#ifndef __ASSEMBLY__struct mx28_rtc_regs { -mx28_reg (hw_rtc_ctrl) - mx28_reg(hw_rtc_stat) -mx28_reg (hw_rtc_milliseconds) - mx28_reg(hw_rtc_seconds) -mx28_reg (hw_rtc_rtc_alarm) - mx28_reg(hw_rtc_watchdog) -mx28_reg (hw_rtc_persistent0) - mx28_reg(hw_rtc_persistent1) -mx28_reg (hw_rtc_persistent2) - mx28_reg(hw_rtc_persistent3) -mx28_reg (hw_rtc_persistent4) - mx28_reg(hw_rtc_persistent5) -mx28_reg (hw_rtc_debug) - mx28_reg(hw_rtc_version) +mx28_reg_32 (hw_rtc_ctrl) + mx28_reg_32(hw_rtc_stat) +mx28_reg_32 (hw_rtc_milliseconds) + mx28_reg_32(hw_rtc_seconds) +mx28_reg_32 (hw_rtc_rtc_alarm) + mx28_reg_32(hw_rtc_watchdog) +mx28_reg_32 (hw_rtc_persistent0) + mx28_reg_32(hw_rtc_persistent1) +mx28_reg_32 (hw_rtc_persistent2) + mx28_reg_32(hw_rtc_persistent3) +mx28_reg_32 (hw_rtc_persistent4) + mx28_reg_32(hw_rtc_persistent5) +mx28_reg_32 (hw_rtc_debug) + mx28_reg_32(hw_rtc_version) };#endif
arch/arm/include/asm/arch-mx28/regs-ssp.h +20 -20
@@ -29,26 +29,26 @@#ifndef __ASSEMBLY__struct mx28_ssp_regs { -mx28_reg (hw_ssp_ctrl0) - mx28_reg(hw_ssp_cmd0) -mx28_reg (hw_ssp_cmd1) - mx28_reg(hw_ssp_xfer_size) -mx28_reg (hw_ssp_block_size) - mx28_reg(hw_ssp_compref) -mx28_reg (hw_ssp_compmask) - mx28_reg(hw_ssp_timing) -mx28_reg (hw_ssp_ctrl1) - mx28_reg(hw_ssp_data) -mx28_reg (hw_ssp_sdresp0) - mx28_reg(hw_ssp_sdresp1) -mx28_reg (hw_ssp_sdresp2) - mx28_reg(hw_ssp_sdresp3) -mx28_reg (hw_ssp_ddr_ctrl) - mx28_reg(hw_ssp_dll_ctrl) -mx28_reg (hw_ssp_status) - mx28_reg(hw_ssp_dll_sts) -mx28_reg (hw_ssp_debug) - mx28_reg(hw_ssp_version) +mx28_reg_32 (hw_ssp_ctrl0) + mx28_reg_32(hw_ssp_cmd0) +mx28_reg_32 (hw_ssp_cmd1) + mx28_reg_32(hw_ssp_xfer_size) +mx28_reg_32 (hw_ssp_block_size) + mx28_reg_32(hw_ssp_compref) +mx28_reg_32 (hw_ssp_compmask) + mx28_reg_32(hw_ssp_timing) +mx28_reg_32 (hw_ssp_ctrl1) + mx28_reg_32(hw_ssp_data) +mx28_reg_32 (hw_ssp_sdresp0) + mx28_reg_32(hw_ssp_sdresp1) +mx28_reg_32 (hw_ssp_sdresp2) + mx28_reg_32(hw_ssp_sdresp3) +mx28_reg_32 (hw_ssp_ddr_ctrl) + mx28_reg_32(hw_ssp_dll_ctrl) +mx28_reg_32 (hw_ssp_status) + mx28_reg_32(hw_ssp_dll_sts) +mx28_reg_32 (hw_ssp_debug) + mx28_reg_32(hw_ssp_version) };#endif
arch/arm/include/asm/arch-mx28/regs-timrot.h +19 -19
@@ -29,25 +29,25 @@#ifndef __ASSEMBLY__struct mx28_timrot_regs { -mx28_reg (hw_timrot_rotctrl) - mx28_reg(hw_timrot_rotcount) -mx28_reg (hw_timrot_timctrl0) - mx28_reg(hw_timrot_running_count0) -mx28_reg (hw_timrot_fixed_count0) - mx28_reg(hw_timrot_match_count0) -mx28_reg (hw_timrot_timctrl1) - mx28_reg(hw_timrot_running_count1) -mx28_reg (hw_timrot_fixed_count1) - mx28_reg(hw_timrot_match_count1) -mx28_reg (hw_timrot_timctrl2) - mx28_reg(hw_timrot_running_count2) -mx28_reg (hw_timrot_fixed_count2) - mx28_reg(hw_timrot_match_count2) -mx28_reg (hw_timrot_timctrl3) - mx28_reg(hw_timrot_running_count3) -mx28_reg (hw_timrot_fixed_count3) - mx28_reg(hw_timrot_match_count3) - mx28_reg(hw_timrot_version) +mx28_reg_32 (hw_timrot_rotctrl) + mx28_reg_32(hw_timrot_rotcount) +mx28_reg_32 (hw_timrot_timctrl0) + mx28_reg_32(hw_timrot_running_count0) +mx28_reg_32 (hw_timrot_fixed_count0) + mx28_reg_32(hw_timrot_match_count0) +mx28_reg_32 (hw_timrot_timctrl1) + mx28_reg_32(hw_timrot_running_count1) +mx28_reg_32 (hw_timrot_fixed_count1) + mx28_reg_32(hw_timrot_match_count1) +mx28_reg_32 (hw_timrot_timctrl2) + mx28_reg_32(hw_timrot_running_count2) +mx28_reg_32 (hw_timrot_fixed_count2) + mx28_reg_32(hw_timrot_match_count2) +mx28_reg_32 (hw_timrot_timctrl3) + mx28_reg_32(hw_timrot_running_count3) +mx28_reg_32 (hw_timrot_fixed_count3) + mx28_reg_32(hw_timrot_match_count3) + mx28_reg_32(hw_timrot_version) };#endif
arch/arm/include/asm/arch-mx28/regs-usbphy.h +10 -10
@@ -24,16 +24,16 @@#define __REGS_USBPHY_H__struct mx28_usbphy_regs { -mx28_reg (hw_usbphy_pwd) - mx28_reg(hw_usbphy_tx) -mx28_reg (hw_usbphy_rx) - mx28_reg(hw_usbphy_ctrl) -mx28_reg (hw_usbphy_status) - mx28_reg(hw_usbphy_debug) -mx28_reg (hw_usbphy_debug0_status) - mx28_reg(hw_usbphy_debug1) -mx28_reg (hw_usbphy_version) - mx28_reg(hw_usbphy_ip) +mx28_reg_32 (hw_usbphy_pwd) + mx28_reg_32(hw_usbphy_tx) +mx28_reg_32 (hw_usbphy_rx) + mx28_reg_32(hw_usbphy_ctrl) +mx28_reg_32 (hw_usbphy_status) + mx28_reg_32(hw_usbphy_debug) +mx28_reg_32 (hw_usbphy_debug0_status) + mx28_reg_32(hw_usbphy_debug1) +mx28_reg_32 (hw_usbphy_version) + mx28_reg_32(hw_usbphy_ip) };#define USBPHY_PWD_RXPWDRX (1 << 20)
arch/arm/include/asm/arch-mx28/sys_proto.h +7 -3
@@ -23,9 +23,13 @@#ifndef __MX28_H__#define __MX28_H__ -int mx28_reset_block (struct mx28_register *reg); -int mx28_wait_mask_set (struct mx28_register *reg,uint32_t mask,int timeout); -int mx28_wait_mask_clr (struct mx28_register *reg,uint32_t mask,int timeout); +int mx28_reset_block (struct mx28_register_32 *reg); +int mx28_wait_mask_set (struct mx28_register_32 *reg, +uint32_t mask, +int timeout); +int mx28_wait_mask_clr (struct mx28_register_32 *reg, +uint32_t mask, +int timeout);int mxsmmc_initialize (bd_t *bis,int id,int (*wp)(int ));
drivers/gpio/mxs_gpio.c +8 -8
@@ -73,8 +73,8 @@ int gpio_get_value(unsigned gpio) {uint32_t bank =PAD_BANK (gpio);uint32_t offset =PINCTRL_DIN (bank); -struct mx28_register *reg = - (struct mx28_register *)(MXS_PINCTRL_BASE + offset); +struct mx28_register_32 *reg = + (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);return (readl (®->reg) >>PAD_PIN (gpio)) &1 ; }
@@ -83,8 +83,8 @@ void gpio_set_value(unsigned gpio, int value) {uint32_t bank =PAD_BANK (gpio);uint32_t offset =PINCTRL_DOUT (bank); -struct mx28_register *reg = - (struct mx28_register *)(MXS_PINCTRL_BASE + offset); +struct mx28_register_32 *reg = + (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);if (value)writel (1 <<PAD_PIN (gpio), ®->reg_set);
@@ -96,8 +96,8 @@ int gpio_direction_input(unsigned gpio) {uint32_t bank =PAD_BANK (gpio);uint32_t offset =PINCTRL_DOE (bank); -struct mx28_register *reg = - (struct mx28_register *)(MXS_PINCTRL_BASE + offset); +struct mx28_register_32 *reg = + (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);writel (1 <<PAD_PIN (gpio), ®->reg_clr);
@@ -108,8 +108,8 @@ int gpio_direction_output(unsigned gpio, int value) {uint32_t bank =PAD_BANK (gpio);uint32_t offset =PINCTRL_DOE (bank); -struct mx28_register *reg = - (struct mx28_register *)(MXS_PINCTRL_BASE + offset); +struct mx28_register_32 *reg = + (struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);writel (1 <<PAD_PIN (gpio), ®->reg_set);
drivers/usb/host/ehci-mxs.c +4 -4
@@ -75,8 +75,8 @@ int ehci_hcd_init(void)int ret;uint32_t usb_base, cap_base; -struct mx28_register *digctl_ctrl = - (struct mx28_register *)HW_DIGCTL_CTRL ; +struct mx28_register_32 *digctl_ctrl = + (struct mx28_register_32 *)HW_DIGCTL_CTRL ;struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ;
@@ -119,8 +119,8 @@ int ehci_hcd_stop(void) {int ret;uint32_t tmp; -struct mx28_register *digctl_ctrl = - (struct mx28_register *)HW_DIGCTL_CTRL ; +struct mx28_register_32 *digctl_ctrl = + (struct mx28_register_32 *)HW_DIGCTL_CTRL ;struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ;
Signature · 1 line
1.7.0.4
PATCH v5 1/4 Renamed mx28_register to mx28_register_32 to prepare for mx28_register_8
Dear Robert at domain.unknown,
Quoted 9 lines · In message <[email protected]> you wrote:
From: Robert Delien <[email protected]>
This patch renames
mx28_registertomx28_register_32in order to prepare for the introduction of an 8-bit register,mx28_register_8.Signed-off-by Robert Delien <[email protected]>--- arch/arm/cpu/arm926ejs/mx28/clock.c | 4 +- arch/arm/cpu/arm926ejs/mx28/iomux.c | 6 +-
...
This is labeled as patch v5 - but I cannot see any log of what has been changed compared to previous versions, i. e. which review comments have been applied and which ignored.
You are supposed to follow the instructions, as documented for example here:
http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions
I don't have to time to run diff's over all your patches, and most others are in a similar situation.
Please consider this whole series as NAKed because of that.
Best regards,
Wolfgang Denk
Signature · 6 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Why don't you have a Linux partition installed so you can be working in a programmer-friendly environment instead of a keep-gates'-bank- account-happy one? :-) -- Tom Christiansen
PATCH v5 1/4 Renamed mx28_register to mx28_register_32 to prepare for mx28_register_8
Quoted 3 lines
This is labeled as patch v5 - but I cannot see any log of what has been changed compared to previous versions, i. e. which review comments have been applied and which ignored.
I did the curtesy of re-forming patch set v5 from a freshly pulled repository, because they no longer applied without fuzz.
I took me 5 patches of wondering where my comments went, before I discovered that the blank line between subject and body is required for git send-email to do it's job properly.
Quoted 6 lines
You are supposed to follow the instructions, as documented for example here:
http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versionsI don't have to time to run diff's over all your patches, and most others are in a similar situation.
I don'thave time to rework patches 50 times over, because I'm in the middle of a board bring-up, yet still I do because I think it's important.
Quoted 1 line
Please consider this whole series as NAKed because of that.
Please go ahead, NAK the other sets as well.
PATCH v5 1/4 Renamed mx28_register to mx28_register_32 to prepare for mx28_register_8
Dear =?iso-8859-1?Q?Robert_Deli=EBn?=,
Quoted 4 lines · In message <6EA3E0BCC03CC34B89B01BD57ECBC718F82A7F@POBOX.postoffice.danego.net>…
Quoted 2 lines
Please consider this whole series as NAKed because of that.
Please go ahead, NAK the other sets as well.
With "other sets" you mean v1 ... v4? No need to do that, as these have been obsoleted by your posting of a v5.
Best regards,
Wolfgang Denk
Signature · 4 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de God is real, unless declared integer.
PATCH v5 2/4 Introducing 8-bit wide register, mx28_register_8
In reply to Robert at domain.unknownFrom: Robert Delien <[email protected]>
This patch introduces an 8-bit register, mx28_register_8, in order to prepare for fixing erroneous 32-bit wide access of registers hw_clkctrl_frac0 and hw_clkctrl_frac1.
--- arch/arm/include/asm/arch-mx28/regs-common.h | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-)
arch/arm/include/asm/arch-mx28/regs-common.h +16 -0
@@ -47,16 +47,32 @@* */ +#define __mx28_reg_8 (name) \ + uint8_t name[4]; \ + uint8_t name##_set[4]; \ + uint8_t name##_clr[4]; \ + uint8_t name##_tog[4]; \ +#define __mx28_reg_32 (name) \ uint32_t name; \ uint32_t name##_set; \ uint32_t name##_clr; \ uint32_t name##_tog; +struct mx28_register_8 { +__mx28_reg_8 (reg) +}; +struct mx28_register_32 { __mx28_reg_32(reg) }; +#define mx28_reg_8 (name) \ + union { \ + struct { __mx28_reg_8(name) }; \ + struct mx28_register_32 name##_reg; \ + }; +#define mx28_reg_32 (name) \ union { \ struct { __mx28_reg_32(name) }; \
Signature · 1 line
1.7.0.4
PATCH v5 3/4 Fix erroneous 32-bit access to hw_clkctrl_frac0 and hw_clkctrl_frac1 registers
In reply to Robert at domain.unknownFrom: Robert Delien <[email protected]>
This patch fixes erroneous 32-bit access to registers hw_clkctrl_frac0 and hw_clkctrl_frac1.
--- arch/arm/cpu/arm926ejs/mx28/clock.c | 70 ++++++++++--------------- arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 26 ++++----- arch/arm/include/asm/arch-mx28/regs-clkctrl.h | 44 +++++----------- 3 files changed, 52 insertions(+), 88 deletions(-)
arch/arm/cpu/arm926ejs/mx28/clock.c +27 -43
@@ -46,8 +46,8 @@ static uint32_t mx28_get_pclk(void)struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ; -uint32_t clkctrl, clkseq, clkfrac; -uint32_t frac, div; +uint32_t clkctrl, clkseq, div; +uint8_t clkfrac, frac; clkctrl =readl (&clkctrl_regs->hw_clkctrl_cpu);
@@ -67,8 +67,8 @@ static uint32_t mx28_get_pclk(void) }/* REF Path */ - clkfrac =readl (&clkctrl_regs->hw_clkctrl_frac0); - frac = clkfrac &CLKCTRL_FRAC0_CPUFRAC_MASK ; + clkfrac =readb (&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU ]); + frac = clkfrac &CLKCTRL_FRAC_FRAC_MASK ; div = clkctrl &CLKCTRL_CPU_DIV_CPU_MASK ;return (PLL_FREQ_MHZ *PLL_FREQ_COEF / frac) / div; }
@@ -96,8 +96,8 @@ static uint32_t mx28_get_emiclk(void)struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ; -uint32_t frac, div; -uint32_t clkctrl, clkseq, clkfrac; +uint32_t clkctrl, clkseq, div; +uint8_t clkfrac, frac; clkseq =readl (&clkctrl_regs->hw_clkctrl_clkseq); clkctrl =readl (&clkctrl_regs->hw_clkctrl_emi);
@@ -109,11 +109,9 @@ static uint32_t mx28_get_emiclk(void)return XTAL_FREQ_MHZ / div; } - clkfrac =readl (&clkctrl_regs->hw_clkctrl_frac0); -/* REF Path */ - frac = (clkfrac &CLKCTRL_FRAC0_EMIFRAC_MASK ) >> -CLKCTRL_FRAC0_EMIFRAC_OFFSET ; + clkfrac =readb (&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI ]); + frac = clkfrac &CLKCTRL_FRAC_FRAC_MASK ; div = clkctrl &CLKCTRL_EMI_DIV_EMI_MASK ;return (PLL_FREQ_MHZ *PLL_FREQ_COEF / frac) / div; }
@@ -123,8 +121,8 @@ static uint32_t mx28_get_gpmiclk(void)struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ; -uint32_t frac, div; -uint32_t clkctrl, clkseq, clkfrac; +uint32_t clkctrl, clkseq, div; +uint8_t clkfrac, frac; clkseq =readl (&clkctrl_regs->hw_clkctrl_clkseq); clkctrl =readl (&clkctrl_regs->hw_clkctrl_gpmi);
@@ -135,11 +133,9 @@ static uint32_t mx28_get_gpmiclk(void)return XTAL_FREQ_MHZ / div; } - clkfrac =readl (&clkctrl_regs->hw_clkctrl_frac1); -/* REF Path */ - frac = (clkfrac &CLKCTRL_FRAC1_GPMIFRAC_MASK ) >> -CLKCTRL_FRAC1_GPMIFRAC_OFFSET ; + clkfrac =readb (&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI ]); + frac = clkfrac &CLKCTRL_FRAC_FRAC_MASK ; div = clkctrl &CLKCTRL_GPMI_DIV_MASK ;return (PLL_FREQ_MHZ *PLL_FREQ_COEF / frac) / div; }
@@ -152,11 +148,12 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ;uint32_t div; +int io_reg;if (freq ==0 )return ; -if (io >MXC_IOCLK1 ) +if ((io <MXC_IOCLK0 ) || (io >MXC_IOCLK1 ))return ; div = (PLL_FREQ_KHZ *PLL_FREQ_COEF ) / freq;
@@ -167,23 +164,13 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)if (div >35 ) div =35 ; -if (io ==MXC_IOCLK0 ) { -writel (CLKCTRL_FRAC0_CLKGATEIO0 , - &clkctrl_regs->hw_clkctrl_frac0_set); -clrsetbits_le32 (&clkctrl_regs->hw_clkctrl_frac0, -CLKCTRL_FRAC0_IO0FRAC_MASK , - div <<CLKCTRL_FRAC0_IO0FRAC_OFFSET ); -writel (CLKCTRL_FRAC0_CLKGATEIO0 , - &clkctrl_regs->hw_clkctrl_frac0_clr); - }else { -writel (CLKCTRL_FRAC0_CLKGATEIO1 , - &clkctrl_regs->hw_clkctrl_frac0_set); -clrsetbits_le32 (&clkctrl_regs->hw_clkctrl_frac0, -CLKCTRL_FRAC0_IO1FRAC_MASK , - div <<CLKCTRL_FRAC0_IO1FRAC_OFFSET ); -writel (CLKCTRL_FRAC0_CLKGATEIO1 , - &clkctrl_regs->hw_clkctrl_frac0_clr); - } + io_reg =CLKCTRL_FRAC0_IO0 - io;/* Register order is reversed */ +writeb (CLKCTRL_FRAC_CLKGATE , + &clkctrl_regs->hw_clkctrl_frac0_set[io_reg]); +writeb (CLKCTRL_FRAC_CLKGATE | (div &CLKCTRL_FRAC_FRAC_MASK ), + &clkctrl_regs->hw_clkctrl_frac0[io_reg]); +writeb (CLKCTRL_FRAC_CLKGATE , + &clkctrl_regs->hw_clkctrl_frac0_clr[io_reg]); }/*
@@ -193,19 +180,16 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io) {struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ; -uint32_t tmp, ret; +uint8_t ret; +int io_reg; -if (io >MXC_IOCLK1 ) +if ((io <MXC_IOCLK0 ) || (io >MXC_IOCLK1 ))return 0 ; - tmp =readl (&clkctrl_regs->hw_clkctrl_frac0); + io_reg =CLKCTRL_FRAC0_IO0 - io;/* Register order is reversed */ -if (io ==MXC_IOCLK0 ) - ret = (tmp &CLKCTRL_FRAC0_IO0FRAC_MASK ) >> -CLKCTRL_FRAC0_IO0FRAC_OFFSET ; -else - ret = (tmp &CLKCTRL_FRAC0_IO1FRAC_MASK ) >> -CLKCTRL_FRAC0_IO1FRAC_OFFSET ; + ret =readb (&clkctrl_regs->hw_clkctrl_frac0[io_reg]) & +CLKCTRL_FRAC_FRAC_MASK ;return (PLL_FREQ_KHZ *PLL_FREQ_COEF ) / ret; }
arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +12 -14
@@ -86,22 +86,20 @@ void mx28_mem_init_clock(void) (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ;/* Gate EMI clock */ -writel (CLKCTRL_FRAC0_CLKGATEEMI , - &clkctrl_regs->hw_clkctrl_frac0_set); +writeb (CLKCTRL_FRAC_CLKGATE , + &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI ]); -/* EMI = 205MHz */ -writel (CLKCTRL_FRAC0_EMIFRAC_MASK , - &clkctrl_regs->hw_clkctrl_frac0_set); -writel ((0x2a <<CLKCTRL_FRAC0_EMIFRAC_OFFSET ) & -CLKCTRL_FRAC0_EMIFRAC_MASK , - &clkctrl_regs->hw_clkctrl_frac0_clr); +/* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */ +writeb (CLKCTRL_FRAC_CLKGATE | (21 &CLKCTRL_FRAC_FRAC_MASK ), + &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI ]);/* Ungate EMI clock */ -writel (CLKCTRL_FRAC0_CLKGATEEMI , - &clkctrl_regs->hw_clkctrl_frac0_clr); +writeb (CLKCTRL_FRAC_CLKGATE , + &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI ]);early_delay (11000 ); +/* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */ writel ((2 <<CLKCTRL_EMI_DIV_EMI_OFFSET ) | (1 <<CLKCTRL_EMI_DIV_XTAL_OFFSET ), &clkctrl_regs->hw_clkctrl_emi);
@@ -118,10 +116,10 @@ void mx28_mem_setup_cpu_and_hbus(void)struct mx28_clkctrl_regs *clkctrl_regs = (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ; -/* CPU = 454MHz and ungate CPU clock */ -clrsetbits_le32 (&clkctrl_regs->hw_clkctrl_frac0, -CLKCTRL_FRAC0_CPUFRAC_MASK |CLKCTRL_FRAC0_CLKGATECPU , -19 <<CLKCTRL_FRAC0_CPUFRAC_OFFSET ); +/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz +* and ungate CPU clock */ +writeb (19 &CLKCTRL_FRAC_FRAC_MASK , + (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU ]);/* Set CPU bypass */ writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
arch/arm/include/asm/arch-mx28/regs-clkctrl.h +13 -31
56 lines not on this page · raw message
Signature · 1 line
1.7.0.4
PATCH v5 4/4 Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL
In reply to Robert at domain.unknownFrom: Robert Delien <[email protected]>
This patch prevents the needless switching on and off of PLL bypass mode. With this patch in place, single-stepping through the SPL is now possible.
--- arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 4 ---- arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 24 ------------------------ 2 files changed, 0 insertions(+), 28 deletions(-)
arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +0 -4
@@ -121,10 +121,6 @@ void mx28_mem_setup_cpu_and_hbus(void)writeb (19 &CLKCTRL_FRAC_FRAC_MASK , (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU ]); -/* Set CPU bypass */ -writel (CLKCTRL_CLKSEQ_BYPASS_CPU , - &clkctrl_regs->hw_clkctrl_clkseq_set); -/* HBUS = 151MHz */ writel (CLKCTRL_HBUS_DIV_MASK , &clkctrl_regs->hw_clkctrl_hbus_set); writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +0 -24
@@ -30,28 +30,6 @@#include "mx28_init.h" -void mx28_power_clock2xtal (void ) -{ -struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ; - -/* Set XTAL as CPU reference clock */ -writel (CLKCTRL_CLKSEQ_BYPASS_CPU , - &clkctrl_regs->hw_clkctrl_clkseq_set); -} - -void mx28_power_clock2pll (void ) -{ -struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE ; - -writel (CLKCTRL_PLL0CTRL0_POWER , - &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); -early_delay (100 ); -writel (CLKCTRL_CLKSEQ_BYPASS_CPU , - &clkctrl_regs->hw_clkctrl_clkseq_clr); -} -void mx28_power_clear_auto_restart (void ) { struct mx28_rtc_regs *rtc_regs =
@@ -606,7 +584,6 @@ void mx28_power_configure_power_source(void)mx28_src_power_init ();mx28_5v_boot (); -mx28_power_clock2pll ();mx28_init_batt_bo ();mx28_switch_vddd_to_dcdc_source ();
@@ -888,7 +865,6 @@ void mx28_power_init(void)struct mx28_power_regs *power_regs = (struct mx28_power_regs *)MXS_POWER_BASE ; -mx28_power_clock2xtal ();mx28_power_clear_auto_restart ();mx28_power_set_linreg ();mx28_power_setup_5v_detect ();
Signature · 1 line
1.7.0.4
v5 cover i.MX28: Fix ref_cpu clock setup
In reply to Robert at domain.unknownQuoted 1 line
From: Robert Delien <[email protected]>
Why did you repost? Fix that "domain.unknown"
M
Quoted 35 lines
This set of patches fixes
ref_cpuclock setup.Robert Delien (4):
Renamedmx28_registertomx28_register_32to prepare formx28_register_8Introducing 8-bit wide register,
mx28_register_8
Fix erroneous 32-bit access tohw_clkctrl_frac0andhw_clkctrl_frac1
registers
Preventing needless switching on and off PLL bypass mode, allowing
allow single-stepping through the SPLarch/arm/cpu/arm926ejs/mx28/clock.c | 74 +++----- arch/arm/cpu/arm926ejs/mx28/iomux.c | 6 +- arch/arm/cpu/arm926ejs/mx28/mx28.c | 6 +- arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 30 ++-- arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 24 --- arch/arm/include/asm/arch-mx28/regs-apbh.h | 254 ++++++++++++------------ arch/arm/include/asm/arch-mx28/regs-bch.h | 42 ++-- arch/arm/include/asm/arch-mx28/regs-clkctrl.h | 98 ++++------ arch/arm/include/asm/arch-mx28/regs-common.h | 28 ++- arch/arm/include/asm/arch-mx28/regs-gpmi.h | 26 ++-- arch/arm/include/asm/arch-mx28/regs-i2c.h | 28 ++-- arch/arm/include/asm/arch-mx28/regs-ocotp.h | 86 ++++---- arch/arm/include/asm/arch-mx28/regs-pinctrl.h | 168 ++++++++-------- arch/arm/include/asm/arch-mx28/regs-power.h | 28 ++-- arch/arm/include/asm/arch-mx28/regs-rtc.h | 28 ++-- arch/arm/include/asm/arch-mx28/regs-ssp.h | 40 ++-- arch/arm/include/asm/arch-mx28/regs-timrot.h | 38 ++-- arch/arm/include/asm/arch-mx28/regs-usbphy.h | 20 +- arch/arm/include/asm/arch-mx28/sys_proto.h | 10 +- drivers/gpio/mxs_gpio.c | 16 +- drivers/usb/host/ehci-mxs.c | 8 +- 21 files changed, 507 insertions(+), 551 deletions(-)
v5 cover i.MX28: Fix ref_cpu clock setup
Quoted 1 line
Why did you repost?
I reposted with your ack in 1 to 3. Still they don't seem to show up in the mailing list.
Quoted 1 line
Fix that "domain.unknown"
I can't. It's Agilent's smpt server's way to tell it's not happy with relaying messages from my email address.
v5 cover i.MX28: Fix ref_cpu clock setup
Quoted 4 lines
Quoted 1 line
Why did you repost?
I reposted with your ack in 1 to 3. Still they don't seem to show up in the mailing list.
Patchwork handles that.
Quoted 5 lines
Quoted 2 lines
Fix that "domain.unknown"
I can't. It's Agilent's smpt server's way to tell it's not happy with relaying messages from my email address.
Sure you can ...
$ cat .gitconfig
[user]
name = Us Er
email = user at ma.ilDone
v5 cover i.MX28: Fix ref_cpu clock setup
Quoted 8 lines
Sure you can ...
$ cat .gitconfig [user] name = Us Er email = user at ma.ilDone
Thanks of the hint, but I configured that some time ago already (in ~/.gitconfig). Git even confirms:
$ git config -l user.name=Rxbert Dxlien user.email=rxbert at dxlien.nl color.diff=auto color.status=auto color.branch=auto core.repositoryformatversion=0 core.filemode=true core.bare=false core.logallrefupdates=true remote.origin.fetch=+refs/heads/*:refs/remotes/origin/* remote.origin.url=git://git.denx.de/u-boot-imx.git branch.master.remote=origin branch.master.merge=refs/heads/master
But still no dice.
v5 cover i.MX28: Fix ref_cpu clock setup
Dear Rxbert,
Quoted 5 lines · In message <6EA3E0BCC03CC34B89B01BD57ECBC718F82A89@POBOX.postoffice.danego.net>…
Git even confirms:
$ git config -l user.name=Rxbert Dxlien user.email=rxbert at dxlien.nl
And is this information correct?
Please STOP posting with non-existent mail addresses (Robert at domain.unknown, Delien at domain.unknown) on the Cc: list. Fix this, or I will block such messages.
Best regards,
Wolfgang Denk
Signature · 4 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Life would be so much easier if everyone read the manual.
Fabio Estevam
reviewerv5 cover i.MX28: Fix ref_cpu clock setup
In reply to Robert DeliënRobert,
Quoted 1 line · Robert Deli?n
Thanks of the hint, but I configured that some time ago already (in ~/.gitconfig).
If you have trouble to setup the gitconfig on your company network, maybe you can use a gmail account.
cat .gitconfig
[user]
name = User Name
email = username at gmail.com
[sendemail]
smtpserver = smtp.gmail.com
smtpserverport = 587
smtpencryption = tls
smtpuser = username at gmail.com
You can then use "git send-email" without issues.
Regards,
Fabio Estevam
v5 cover i.MX28: Fix ref_cpu clock setup
In reply to Robert DeliënDear =?iso-8859-1?Q?Robert_Deli=EBn?=,
Quoted 4 lines · In message <6EA3E0BCC03CC34B89B01BD57ECBC718F829B4@POBOX.postoffice.danego.net>…
Quoted 1 line
Why did you repost?
I reposted with your ack in 1 to 3. Still they don't seem to show up in the mailing list.
Never do this. ACKs and such are tracked in patchwork.
And _if_ you repost, then play by the rules and add a changelog.
Quoted 4 lines
Quoted 1 line
Fix that "domain.unknown"
I can't. It's Agilent's smpt server's way to tell it's not happy with relaying messages from my email address.
Then use a better relay. Please fix it, it is a PITA not being able to use "reply".
Best regards,
Wolfgang Denk
Signature · 4 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de panic: kernel trap (ignored)
v5 cover i.MX28: Fix ref_cpu clock setup
Quoted 1 line
Never do this. ACKs and such are tracked in patchwork.
It's a hard to satsify everybody. I added the ack and and test per Marek's request, and reposted.
Quoted 4 lines
And _if_ you repost, then play by the rules and add a changelog.
Then use a better relay. Please fix it, it is a PITA not being able to use "reply".
That I can imagine.
It seems that git send-email doesn't handle --from"Name Domain <[email protected]>" properly, so that's fixed now.
v5 cover i.MX28: Fix ref_cpu clock setup
In reply to Robert at domain.unknownHi Robert,
Le 15/02/2012 11:29, Robert at domain.unknown a ?crit :
Quoted 4 lines
From: Robert Delien<[email protected]>
This set of patches fixes
ref_cpuclock setup.
Quoted 8 lines
Robert Delien (4):
Renamedmx28_registertomx28_register_32to prepare formx28_register_8Introducing 8-bit wide register,
mx28_register_8
Fix erroneous 32-bit access tohw_clkctrl_frac0andhw_clkctrl_frac1
registers
Preventing needless switching on and off PLL bypass mode, allowing
allow single-stepping through the SPL
P
I don't see this V5 on patchwork. Please a V6 with up-to-date Tested-By / Acked-By etc -- and of course make sure the e-mail address stays correct.
Besides, this touches i.MX, so I think Stefano should be at least Cc:
Amicalement,
Signature · 1 line
Albert.
v5 cover i.MX28: Fix ref_cpu clock setup
Quoted 15 lines · Albert ARIBAUD
Hi Robert,
Le 15/02/2012 11:29, Robert at domain.unknown a ?crit :
Quoted 4 lines
From: Robert Delien<[email protected]>
This set of patches fixes
ref_cpuclock setup.Quoted 8 lines
Robert Delien (4):
Renamedmx28_registertomx28_register_32to prepare formx28_register_8Introducing 8-bit wide register,
mx28_register_8
Fix erroneous 32-bit access tohw_clkctrl_frac0andhw_clkctrl_frac1
registers
Preventing needless switching on and off PLL bypass mode, allowing
allow single-stepping through the SPL
Quoted 5 lines
P
I don't see this V5 on patchwork. Please a V6 with up-to-date Tested-By / Acked-By etc -- and of course make sure the e-mail address stays correct.Besides, this touches i.MX, so I think Stefano should be at least Cc:
Right - Robert, I miss also which is the state of the current patches - is there still an issue that avoid boards to boot ?
Stefano
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de =====================================================================
v5 cover i.MX28: Fix ref_cpu clock setup
Quoted 22 lines · Albert ARIBAUD
Quoted 21 lines
Hi Robert,
Le 15/02/2012 11:29, Robert at domain.unknown a ?crit :
Quoted 17 lines
From: Robert Delien<[email protected]>
This set of patches fixes
ref_cpuclock setup.Robert Delien (4):
Renamedmx28_registertomx28_register_32to prepare formx28_register_8Introducing 8-bit wide register,
mx28_register_8
Fix erroneous 32-bit access tohw_clkctrl_frac0andhw_clkctrl_frac1registers
Preventing needless switching on and off PLL bypass mode, allowing
allow single-stepping through the SPL
Quoted 8 lines
Quoted 6 lines
P
I don't see this V5 on patchwork. Please a V6 with up-to-date Tested-By / Acked-By etc -- and of course make sure the e-mail address stays correct.Besides, this touches i.MX, so I think Stefano should be at least Cc:
Right - Robert, I miss also which is the state of the current patches - is there still an issue that avoid boards to boot ?
Yea ... that issue is fixed. I acked patches 1,2,3 ... I'm still unsure about patch 4.
M
Quoted 2 lines
Stefano
v5 cover i.MX28: Fix ref_cpu clock setup
Le 20/02/2012 08:40, Marek Vasut a ?crit :
Quoted 27 lines
Quoted 27 lines · Albert ARIBAUD
Quoted 25 lines
Hi Robert,
Le 15/02/2012 11:29, Robert at domain.unknown a ?crit :
Quoted 9 lines
From: Robert Delien<[email protected]>
This set of patches fixes
ref_cpuclock setup.Robert Delien (4):
Renamedmx28_registertomx28_register_32to prepare for
mx28_register_8Quoted 8 lines
Introducing 8-bit wide register,
mx28_register_8
Fix erroneous 32-bit access tohw_clkctrl_frac0andhw_clkctrl_frac1registers
Preventing needless switching on and off PLL bypass mode, allowing
allow single-stepping through the SPL
P
I don't see this V5 on patchwork. Please a V6 with up-to-date Tested-By / Acked-By etc -- and of course make sure the e-mail address stays correct.
Quoted 10 lines
Quoted 3 lines
Quoted 1 line
Besides, this touches i.MX, so I think Stefano should be at least Cc:
Right - Robert, I miss also which is the state of the current patches - is there still an issue that avoid boards to boot ?
Yea ... that issue is fixed. I acked patches 1,2,3 ... I'm still unsure about patch 4.
M
Quoted 2 lines
Stefano
I had an offline e-mail exchange with Robert, the conclusion of which is that he will not follow up on the patch series and we should cancel it.
Amicalement,
Signature · 1 line
Albert.
Fabio Estevam
reviewerv5 cover i.MX28: Fix ref_cpu clock setup
In reply to Marek VasutHi Stefano,
Quoted 2 lines · Marek Vasut
Yea ... that issue is fixed. I acked patches 1,2,3 ... I'm still unsure about patch 4.
Can patches 1,2,3 be applied? They fix the kernel reset issue.
Thanks,
Fabio Estevam
v5 cover i.MX28: Fix ref_cpu clock setup
Quoted 11 lines
Hi Stefano,
Quoted 2 lines · Marek Vasut
Yea ... that issue is fixed. I acked patches 1,2,3 ... I'm still unsure about patch 4.
Can patches 1,2,3 be applied? They fix the kernel reset issue.
Thanks,
Fabio Estevam
I'll apply and retest what's suitable tomorrow. Then I'll submit pullrq to stefano. We already decided on that.
M