powerpc: perf: power_pmu_start restores incorrect values, breaking frequency events

PATCH In review Anton Blanchard 3 participants 3 messages Feb 16, 2012 – Feb 19, 2012

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PowerPC perf events

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Anton Blanchard

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2012-02-16 04:48 UTC #0 lore raw

PATCH 1/1 powerpc: perf: power_pmu_start restores incorrect values, breaking frequency events

perf on POWER stopped working after commit e050e3f0a71b (perf: Fix broken interrupt rate throttling). That patch exposed a bug in the POWER perf_events code.

Since the PMCs count upwards and take an exception when the top bit is set, we want to write 0x80000000 - left in power_pmu_start. We were instead programming in left which effectively disables the counter until we eventually hit 0x80000000. This could take seconds or longer.

With the patch applied I get the expected number of samples:

# taskset -c 0 yes > /dev/null &
# perf record -C 0 -a sleep 10
# perf report -D | grep SAMPLE | tail -1
          SAMPLE events:       9948

Signed-off-by Anton Blanchard <[email protected]>

---
Cc: <[email protected]>

arch/powerpc/kernel/perf_event.c +7 -1

Index: linux-build/arch/powerpc/kernel/perf_event.c
===================================================================
@@ -865,6 +865,7 @@ static void power_pmu_start(struct perf_
 {
 	unsigned long flags;
 	s64 left;
+	unsigned long val;
 
 	if (!event->hw.idx || !event->hw.sample_period)
 		return;

@@ -880,7 +881,12 @@ static void power_pmu_start(struct perf_
 
 	event->hw.state = 0;
 	left = local64_read(&event->hw.period_left);
-	write_pmc(event->hw.idx, left);
+
+	val = 0;
+	if (left < 0x80000000L)
+		val = 0x80000000L - left;
+
+	write_pmc(event->hw.idx, val);
 
 	perf_event_update_userpage(event);
 	perf_pmu_enable(event->pmu);

Paul Mackerras

Acked-by on v1 1/1

2012-02-16 04:57 UTC #1 lore raw

Quoted 10 lines · Anton Blanchard

perf on POWER stopped working after commit e050e3f0a71b (perf: Fix broken interrupt rate throttling). That patch exposed a bug in the POWER perf_events code.
Since the PMCs count upwards and take an exception when the top bit is set, we want to write 0x80000000 - left in power_pmu_start. We were instead programming in left which effectively disables the counter until we eventually hit 0x80000000. This could take seconds or longer.

Quoted 8 lines

With the patch applied I get the expected number of samples:
# taskset -c 0 yes > /dev/null &
# perf record -C 0 -a sleep 10
# perf report -D | grep SAMPLE | tail -1
          SAMPLE events:       9948
Signed-off-by Anton Blanchard <[email protected]>

Acked-by Paul Mackerras <[email protected]>

Stephane Eranian

2012-02-19 11:13 UTC #2 lore raw

Glad to see you fixed the PPC problem.

Quoted 21 lines · Paul Mackerras

Quoted 10 lines · Anton Blanchard
perf on POWER stopped working after commit e050e3f0a71b (perf: Fix broken interrupt rate throttling). That patch exposed a bug in the POWER perf_events code.
Since the PMCs count upwards and take an exception when the top bit is set, we want to write 0x80000000 - left in power_pmu_start. We were instead programming in left which effectively disables the counter until we eventually hit 0x80000000. This could take seconds or longer.
Quoted 8 lines
With the patch applied I get the expected number of samples:
# taskset -c 0 yes > /dev/null &
# perf record -C 0 -a sleep 10
# perf report -D | grep SAMPLE | tail -1
          SAMPLE events:       9948
Signed-off-by Anton Blanchard <[email protected]>
Acked-by Paul Mackerras <[email protected]>