ARM: perf: limit sample_period to half max_period in non-sampling mode

On ARM, the PMU does not stop counting after an overflow and therefore IRQ latency affects the new counter value read by the kernel. This is significant for non-sampling runs where it is possible for the new value to overtake the previous one, causing the delta to be out by up to max_period events.

Commit a737823d ("ARM: 6835/1: perf: ensure overflows aren't missed due to IRQ latency") attempted to fix this problem by allowing interrupt handlers to pass an overflow flag to the event update function, causing the overflow calculation to assume that the counter passed through zero when going from prev to new. Unfortunately, this doesn't work when overflow occurs on the perf_task_tick path because we have the flag cleared and end up computing a large negative delta.

This patch removes the overflow flag from armpmu_event_update and instead limits the sample_period to half of the max_period for non-sampling profiling runs.

Cc Ming Lei <[email protected]>

Signed-off-by Will Deacon <[email protected]>

---

?arch/arm/include/asm/pmu.h ? ? ? ? ?| ? ?2 +-
?arch/arm/kernel/perf_event.c ? ? ? ?| ? 22 +++++++++++-----------
?arch/arm/kernel/perf_event_v6.c ? ? | ? ?2 +-
?arch/arm/kernel/perf_event_v7.c ? ? | ? ?2 +-
?arch/arm/kernel/perf_event_xscale.c | ? ?4 ++--

?5 files changed, 16 insertions(+), 16 deletions(-)

arch/arm/include/asm/pmu.h +1 -1

index b5a5be2..90114fa 100644
@@ -134,7 +134,7 @@ int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
 
 ?u64 armpmu_event_update(struct perf_event *event,
 ? ? ? ? ? ? ? ? ? ? ? ?struct hw_perf_event *hwc,
- ? ? ? ? ? ? ? ? ? ? ? int idx, int overflow);
+ ? ? ? ? ? ? ? ? ? ? ? int idx);
 
 ?int armpmu_event_set_period(struct perf_event *event,
 ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct hw_perf_event *hwc,

arch/arm/kernel/perf_event.c +0 -0

index 5bb91bf..56173ae 100644
@@ -180,7 +180,7 @@ armpmu_event_set_period(struct perf_event *event,

?u64
?armpmu_event_update(struct perf_event *event, ? ? ? ? ? ? ? ? ? ?struct hw_perf_event *hwc,
- ? ? ? ? ? ? ? ? ? int idx, int overflow)
+ ? ? ? ? ? ? ? ? ? int idx)
?{
? ? ? ?struct arm_pmu *armpmu = to_arm_pmu(event->pmu); ? ? ? ?u64 delta, prev_raw_count, new_raw_count;

arch/arm/kernel/perf_event.c +0 -0

@@ -193,13 +193,7 @@ again:
 ? ? ? ? ? ? ? ? ? ? ? ? ? ? new_raw_count) != prev_raw_count)

Quoted 15 lines · Will Deacon

arch/arm/kernel/perf_event.c +0 -0

index 5bb91bf..56173ae 100644
@@ -180,7 +180,7 @@ armpmu_event_set_period(struct perf_event *event,

?u64
?armpmu_event_update(struct perf_event *event, ? ? ? ? ? ? ? ? ? ?struct hw_perf_event *hwc,
- ? ? ? ? ? ? ? ? ? int idx, int overflow)
+ ? ? ? ? ? ? ? ? ? int idx)
?{
? ? ? ?struct arm_pmu *armpmu = to_arm_pmu(event->pmu); ? ? ? ?u64 delta, prev_raw_count, new_raw_count;

arch/arm/kernel/perf_event.c +0 -0

@@ -193,13 +193,7 @@ again:
 ? ? ? ? ? ? ? ? ? ? ? ? ? ? new_raw_count) != prev_raw_count)

arch/arm/kernel/perf_event.c again: · line 196

Quoted 10 lines

arch/arm/kernel/perf_event.c +1 -7

 ? ? ? ? ? ? ? ?goto again;
 
- ? ? ? new_raw_count &= armpmu->max_period;
- ? ? ? prev_raw_count &= armpmu->max_period;
-
- ? ? ? if (overflow)
- ? ? ? ? ? ? ? delta = armpmu->max_period - prev_raw_count + new_raw_count + 1;
- ? ? ? else
- ? ? ? ? ? ? ? delta = new_raw_count - prev_raw_count;
+ ? ? ? delta = (new_raw_count - prev_raw_count) & armpmu->max_period;

Please add

Signed-off-by Ming Lei <[email protected]>

Sure, didn't want to add anything more than a CC until I was sure you were happy with it.

On the plus side, the warnings from Stephane's IRQ throttling code have been fixed in -rc4 by f39d47ff ("perf: Fix double start/stop in x86_pmu_start()").

So the ball should be back in the OMAP court now as far as enabling perf on Panda.