Set of various i.MX28 patches

PATCH New Marek Vasut 3 participants 21 messages Feb 26, 2012 – Mar 9, 2012

Subsystems (5)

Arm (32-bit) USB Arm i.MX and Layerscape GPIO +1 more subsystems

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Marek Vasut

author

2012-02-26 22:15 UTC #0 lore raw

cover Set of various i.MX28 patches

These patches fix random issues on the i.MX28 series.

Marek Vasut (4):
M28: Fix LCD PINMUX
M28: Support for the old M28 SoM v1.0 i.MX28: Reformat the DRAM memory configuration data i.MX28: Enable additional DRAM address bits

Robert Delien (3):
Renamed mx28_register to mx28_register_32 to prepare for

    mx28_register_8

Introducing 8-bit wide register, mx28_register_8
Fix erroneous 32-bit access to hw_clkctrl_frac0 and hw_clkctrl_frac1
registers

 arch/arm/cpu/arm926ejs/mx28/clock.c           |   74 +++-----
 arch/arm/cpu/arm926ejs/mx28/iomux.c           |    6 +-
 arch/arm/cpu/arm926ejs/mx28/mx28.c            |    6 +-
 arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c    |  112 ++++++-----
 arch/arm/include/asm/arch-mx28/regs-apbh.h    |  254 ++++++++++++------------
 arch/arm/include/asm/arch-mx28/regs-bch.h     |   42 ++--
 arch/arm/include/asm/arch-mx28/regs-clkctrl.h |   98 ++++------
 arch/arm/include/asm/arch-mx28/regs-common.h  |   28 ++-
 arch/arm/include/asm/arch-mx28/regs-gpmi.h    |   26 ++--
 arch/arm/include/asm/arch-mx28/regs-i2c.h     |   28 ++--
 arch/arm/include/asm/arch-mx28/regs-ocotp.h   |   86 ++++----
 arch/arm/include/asm/arch-mx28/regs-pinctrl.h |  168 ++++++++--------
 arch/arm/include/asm/arch-mx28/regs-power.h   |   28 ++--
 arch/arm/include/asm/arch-mx28/regs-rtc.h     |   28 ++--
 arch/arm/include/asm/arch-mx28/regs-ssp.h     |   40 ++--
 arch/arm/include/asm/arch-mx28/regs-timrot.h  |   38 ++--
 arch/arm/include/asm/arch-mx28/regs-usbphy.h  |   20 +-
 arch/arm/include/asm/arch-mx28/sys_proto.h    |   10 +-
 board/denx/m28evk/spl_boot.c                  |   16 +-
 drivers/gpio/mxs_gpio.c                       |   16 +-
 drivers/usb/host/ehci-mxs.c                   |    8 +-
 21 files changed, 562 insertions(+), 570 deletions(-)

Signature · 1 line

1.7.9

Marek Vasut

author

2012-02-26 22:15 UTC #1 lore raw

PATCH 1/7 M28: Fix LCD PINMUX

The LCD pins configuration was wrong in U-Boot, configure pins properly.

Signed-off-by Marek Vasut <[email protected]>

Cc Wolfgang Denk <[email protected]>

Cc Detlev Zundel <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Fabio Estevam <[email protected]>

---
 board/denx/m28evk/spl_boot.c |   11 ++---------
 1 files changed, 2 insertions(+), 9 deletions(-)

board/denx/m28evk/spl_boot.c +2 -9

index 86d7d87..91316a7 100644
@@ -31,7 +31,7 @@
 #include <asm/arch/sys_proto.h>
 
 #define	MUX_CONFIG_LED	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-#define	MUX_CONFIG_LCD	(MXS_PAD_3V3 | MXS_PAD_4MA)
+#define	MUX_CONFIG_LCD	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
 #define	MUX_CONFIG_TSC	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
 #define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
 #define	MUX_CONFIG_SSP2	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)

@@ -68,15 +68,8 @@ const iomux_cfg_t iomux_setup[] = {
 	MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD,
 	MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD,
 	MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD,
 	MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_ENABLE__GPIO_1_31 | MUX_CONFIG_LCD,
-	MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD,
+	MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
 
 	/* UART1 */
 	MX28_PAD_PWM0__DUART_RX,

Signature · 1 line

1.7.9

Stefano Babic

2012-03-03 09:06 UTC #2 lore raw

PATCH 1/7 M28: Fix LCD PINMUX

Quoted 8 lines · Marek Vasut

The LCD pins configuration was wrong in U-Boot, configure pins properly.
Signed-off-by Marek Vasut <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Detlev Zundel <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Fabio Estevam <[email protected]>
---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Marek Vasut

author

2012-02-26 22:15 UTC #3 lore raw

PATCH 2/7 M28: Support for the old M28 SoM v1.0

In reply to Marek Vasut

This prototype version SoM is unused and not available to public. Support this only for internal debugging purposes.

Signed-off-by Marek Vasut <[email protected]>

---
 board/denx/m28evk/spl_boot.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

board/denx/m28evk/spl_boot.c +5 -0

index 91316a7..a04fe18 100644
@@ -72,8 +72,13 @@ const iomux_cfg_t iomux_setup[] = {
 	MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
 
 	/* UART1 */
+#ifdef	CONFIG_DENX_M28_V10
+	MX28_PAD_AUART0_CTS__DUART_RX,
+	MX28_PAD_AUART0_RTS__DUART_TX,
+#else
 	MX28_PAD_PWM0__DUART_RX,
 	MX28_PAD_PWM1__DUART_TX,
+#endif
 	MX28_PAD_AUART0_TX__DUART_RTS,
 	MX28_PAD_AUART0_RX__DUART_CTS,

Signature · 1 line

1.7.9

Stefano Babic

2012-03-03 09:07 UTC #4 lore raw

PATCH 2/7 M28: Support for the old M28 SoM v1.0

Quoted 5 lines · Marek Vasut

This prototype version SoM is unused and not available to public. Support this only for internal debugging purposes.
Signed-off-by Marek Vasut <[email protected]>
---

Applied to u-boot-imx, thanks

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Marek Vasut

author

2012-02-26 22:15 UTC #5 lore raw

PATCH 3/7 i.MX28: Reformat the DRAM memory configuration data

In reply to Marek Vasut

Reformat the data so it's easier to navigate through them.

Signed-off-by Marek Vasut <[email protected]>

---
 arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c |   86 +++++++++++++++------------
 1 files changed, 48 insertions(+), 38 deletions(-)

arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +48 ~~-38~~

index db67011..4af9eb7 100644
@@ -32,44 +32,54 @@
 #include "mx28_init.h"
 
 uint32_t dram_vals[] = {
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00010101, 0x01010101, 0x000f0f01, 0x0f02020a,
-	0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000,
-	0x00000002, 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
-	0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 0x02030202,
-	0x00c8001c, 0x00000000, 0x00000000, 0x00012100, 0xffff0303,
-	0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00012100,
-	0xffff0303, 0x00000003, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000612, 0x01000F02, 0x06120612, 0x00000200,
-	0x00020007, 0xf5014b27, 0xf5014b27, 0xf5014b27, 0xf5014b27,
-	0x07000300, 0x07000300, 0x07000300, 0x07000300, 0x00000006,
-	0x00000000, 0x00000000, 0x01000000, 0x01020408, 0x08040201,
-	0x000f1133, 0x00000000, 0x00001f04, 0x00001f04, 0x00001f04,
-	0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00010000, 0x00020304, 0x00000004,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x01010000, 0x01000000, 0x03030000, 0x00010303,
-	0x01020202, 0x00000000, 0x02040303, 0x21002103, 0x00061200,
-	0x06120612, 0x04320432, 0x04320432, 0x00040004, 0x00040004,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010001
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000100, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00010101, 0x01010101,
+	0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
+	0x00000100, 0x00000100, 0x00000000, 0x00000002,
+	0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
+	0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612,
+	0x02030202, 0x00c8001c, 0x00000000, 0x00000000,
+	0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+	0x00012100, 0xffff0303, 0x00012100, 0xffff0303,
+	0x00000003, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000612, 0x01000F02,
+	0x06120612, 0x00000200, 0x00020007, 0xf5014b27,
+	0xf5014b27, 0xf5014b27, 0xf5014b27, 0x07000300,
+	0x07000300, 0x07000300, 0x07000300, 0x00000006,
+	0x00000000, 0x00000000, 0x01000000, 0x01020408,
+	0x08040201, 0x000f1133, 0x00000000, 0x00001f04,
+	0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04,
+	0x00001f04, 0x00001f04, 0x00001f04, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00010000, 0x00020304,
+	0x00000004, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x01010000,
+	0x01000000, 0x03030000, 0x00010303, 0x01020202,
+	0x00000000, 0x02040303, 0x21002103, 0x00061200,
+	0x06120612, 0x04320432, 0x04320432, 0x00040004,
+	0x00040004, 0x00000000, 0x00000000, 0x00000000,
+	0x00000000, 0x00010001
 };
 
 void init_m28_200mhz_ddr2(void)

Signature · 1 line

1.7.9

Stefano Babic

2012-03-03 09:09 UTC #6 lore raw

PATCH 3/7 i.MX28: Reformat the DRAM memory configuration data

Quoted 7 lines · Marek Vasut

Reformat the data so it's easier to navigate through them.
Signed-off-by Marek Vasut <[email protected]>
---
 arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c |   86 +++++++++++++++------------
 1 files changed, 48 insertions(+), 38 deletions(-)

Applied to u-boot-imx, thanks

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Marek Vasut

author

2012-02-26 22:15 UTC #7 lore raw

PATCH 4/7 i.MX28: Enable additional DRAM address bits

In reply to Marek Vasut

Signed-off-by Marek Vasut <[email protected]>

---
 arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +1 -1

index 4af9eb7..fd18f70 100644
@@ -39,7 +39,7 @@ uint32_t dram_vals[] = {
 	0x00000000, 0x00000100, 0x00000000, 0x00000000,
 	0x00000000, 0x00000000, 0x00000000, 0x00000000,
 	0x00000000, 0x00000000, 0x00010101, 0x01010101,
-	0x000f0f01, 0x0f02020a, 0x00000000, 0x00010101,
+	0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101,
 	0x00000100, 0x00000100, 0x00000000, 0x00000002,
 	0x01010000, 0x05060302, 0x06005003, 0x0a0000c8,
 	0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612,

Signature · 1 line

1.7.9

Fabio Estevam

reviewer

2012-03-01 15:22 UTC #8 lore raw

PATCH 4/7 i.MX28: Enable additional DRAM address bits

Quoted 4 lines · Marek Vasut

Signed-off-by Marek Vasut <[email protected]>
---
?arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | ? ?2 +- ?1 files changed, 1 insertions(+), 1 deletions(-)

Could you please elaborate a commit message for this?

Marek Vasut

author

2012-03-01 18:34 UTC #9 lore raw

PATCH 4/7 i.MX28: Enable additional DRAM address bits

Quoted 11 lines · Marek Vasut

Quoted 4 lines
Signed-off-by Marek Vasut <[email protected]>
---
 arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
Could you please elaborate a commit message for this?
From what I could see this is changing from 0x0f02020a to 0x0f02010a, and it would be nice to have in the commit message an explanation of what this register is, what you are changing and why.

If I could get my hands on Office 2010 to open that stupid memory thing supplied by freescale, I would. But since I can't ... basically, this is magic which enables all fourteen address lines. From what I remember, the piece at 0xf << 8 says how many address bits are to be disabled and 0 is prohibited.

Since all of them should be enabled now, I don't consider it necessary to poke into this anymore. Or does it break anything for you?

Fabio Estevam

reviewer

2012-03-01 18:39 UTC #10 lore raw

PATCH 4/7 i.MX28: Enable additional DRAM address bits

Quoted 7 lines · Marek Vasut

If I could get my hands on Office 2010 to open that stupid memory thing supplied by freescale, I would. But since I can't ... basically, this is magic which enables all fourteen address lines. From what I remember, the piece at 0xf << 8 says how many address bits are to be disabled and 0 is prohibited.
Since all of them should be enabled now, I don't consider it necessary to poke into this anymore. Or does it break anything for you?

I haven't had a chance to test it yet. My comment was more towards putting a brief explanation in the commit log.

Marek Vasut

author

2012-03-01 18:52 UTC #11 lore raw

PATCH 4/7 i.MX28: Enable additional DRAM address bits

Quoted 7 lines · Marek Vasut

Quoted 6 lines
If I could get my hands on Office 2010 to open that stupid memory thing supplied by freescale, I would. But since I can't ... basically, this is magic which enables all fourteen address lines. From what I remember, the piece at 0xf << 8 says how many address bits are to be disabled and 0 is prohibited.

Quoted 5 lines

Quoted 2 lines
Since all of them should be enabled now, I don't consider it necessary to poke into this anymore. Or does it break anything for you?
I haven't had a chance to test it yet. My comment was more towards putting a brief explanation in the commit log.

Well ... it was more verbose than FSL docs ;-) I got your point though, but I'll not be resending it unless completely necessary, I don't see this very important. I'd eventually love this transformed properly to a structure or something.

Stefano Babic

2012-03-03 10:21 UTC #12 lore raw

PATCH 4/7 i.MX28: Enable additional DRAM address bits

Quoted 1 line · Marek Vasut

Well ... it was more verbose than FSL docs ;-)

Well, you are only saying that it is only a little more of nothing... ;-)

Quoted 4 lines

I got your point though, but I'll
not be resending it unless completely necessary, I don't see this very important. I'd eventually love this transformed properly to a structure or something.

Ok - what about if I merge the patch adding in the commit message "enables all fourteen address lines for DRAM" ?

Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Marek Vasut

author

2012-03-03 12:02 UTC #13 lore raw

PATCH 4/7 i.MX28: Enable additional DRAM address bits

Quoted 10 lines · Marek Vasut

Quoted 1 line
Well ... it was more verbose than FSL docs ;-)
Well, you are only saying that it is only a little more of nothing... ;-)
Quoted 4 lines
I got your point though, but I'll
not be resending it unless completely necessary, I don't see this very important. I'd eventually love this transformed properly to a structure or something.

Quoted 4 lines

Ok - what about if I merge the patch adding in the commit message "enables all fourteen address lines for DRAM" ?
Stefano

Acked-by Marek Vasut <[email protected]>

and ...

Tested-by Marek Vasut <[email protected]>

^--- I'm definitelly making enough brownie points with this "Tested-by" to make it to the first place in that category in 2012.03 release :D

Stefano Babic

2012-03-09 13:39 UTC #14 lore raw

PATCH 4/7 i.MX28: Enable additional DRAM address bits

In reply to Marek Vasut

Quoted 2 lines · Marek Vasut

Signed-off-by Marek Vasut <[email protected]>
---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Marek Vasut

author

2012-02-26 22:15 UTC #15 lore raw

PATCH 5/7 Renamed mx28_register to mx28_register_32 to prepare for mx28_register_8

In reply to Marek Vasut

From: Robert Delien <[email protected]>

This patch renames mx28_register to mx28_register_32 in order to prepare for the introduction of an 8-bit register, mx28_register_8.

Signed-off-by Robert Delien <[email protected]>

Acked-by Marek Vasut <[email protected]>

Tested-by Marek Vasut <[email protected]>

---
 arch/arm/cpu/arm926ejs/mx28/clock.c           |    4 +-
 arch/arm/cpu/arm926ejs/mx28/iomux.c           |    6 +-
 arch/arm/cpu/arm926ejs/mx28/mx28.c            |    6 +-
 arch/arm/include/asm/arch-mx28/regs-apbh.h    |  254 ++++++++++++------------
 arch/arm/include/asm/arch-mx28/regs-bch.h     |   42 ++--
 arch/arm/include/asm/arch-mx28/regs-clkctrl.h |   58 +++---
 arch/arm/include/asm/arch-mx28/regs-common.h  |   12 +-
 arch/arm/include/asm/arch-mx28/regs-gpmi.h    |   26 ++--
 arch/arm/include/asm/arch-mx28/regs-i2c.h     |   28 ++--
 arch/arm/include/asm/arch-mx28/regs-ocotp.h   |   86 ++++----
 arch/arm/include/asm/arch-mx28/regs-pinctrl.h |  168 ++++++++--------
 arch/arm/include/asm/arch-mx28/regs-power.h   |   28 ++--
 arch/arm/include/asm/arch-mx28/regs-rtc.h     |   28 ++--
 arch/arm/include/asm/arch-mx28/regs-ssp.h     |   40 ++--
 arch/arm/include/asm/arch-mx28/regs-timrot.h  |   38 ++--
 arch/arm/include/asm/arch-mx28/regs-usbphy.h  |   20 +-
 arch/arm/include/asm/arch-mx28/sys_proto.h    |   10 +-
 drivers/gpio/mxs_gpio.c                       |   16 +-
 drivers/usb/host/ehci-mxs.c                   |    8 +-
 19 files changed, 441 insertions(+), 437 deletions(-)

arch/arm/cpu/arm926ejs/mx28/clock.c +2 -2

index f698506..9d3a018 100644
@@ -223,7 +223,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
 		return;
 
 	clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
-			(ssp * sizeof(struct mx28_register));
+			(ssp * sizeof(struct mx28_register_32));
 
 	clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
 	while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)

@@ -272,7 +272,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
 		return XTAL_FREQ_KHZ;
 
 	clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
-			(ssp * sizeof(struct mx28_register));
+			(ssp * sizeof(struct mx28_register_32));
 
 	tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;

arch/arm/cpu/arm926ejs/mx28/iomux.c +3 -3

index 9ea411f..12916b6 100644
@@ -43,7 +43,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
 {
 	u32 reg, ofs, bp, bm;
 	void *iomux_base = (void *)MXS_PINCTRL_BASE;
-	struct mx28_register *mxs_reg;
+	struct mx28_register_32 *mxs_reg;
 
 	/* muxsel */
 	ofs = 0x100;

@@ -70,7 +70,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
 	/* vol */
 	if (PAD_VOL_VALID(pad)) {
 		bp = PAD_PIN(pad) % 8 * 4 + 2;
-		mxs_reg = (struct mx28_register *)(iomux_base + ofs);
+		mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
 		if (PAD_VOL(pad))
 			writel(1 << bp, &mxs_reg->reg_set);
 		else

@@ -82,7 +82,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
 		ofs = PULL_OFFSET;
 		ofs += PAD_BANK(pad) * 0x10;
 		bp = PAD_PIN(pad);
-		mxs_reg = (struct mx28_register *)(iomux_base + ofs);
+		mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
 		if (PAD_PULL(pad))
 			writel(1 << bp, &mxs_reg->reg_set);
 		else

arch/arm/cpu/arm926ejs/mx28/mx28.c +3 -3

index b235091..9bfd83b 100644
@@ -63,7 +63,7 @@ void reset_cpu(ulong ignored)
 		;
 }
 
-int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout)
+int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout)
 {
 	while (--timeout) {
 		if ((readl(&reg->reg) & mask) == mask)

@@ -74,7 +74,7 @@ int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout)
 	return !timeout;
 }
 
-int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout)
+int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout)
 {
 	while (--timeout) {
 		if ((readl(&reg->reg) & mask) == 0)

@@ -85,7 +85,7 @@ int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout)
 	return !timeout;
 }
 
-int mx28_reset_block(struct mx28_register *reg)
+int mx28_reset_block(struct mx28_register_32 *reg)
 {
 	/* Clear SFTRST */
 	writel(MX28_BLOCK_SFTRST, &reg->reg_clr);

arch/arm/include/asm/arch-mx28/regs-apbh.h +127 ~~-127~~

269 lines not on this page · raw message

arch/arm/include/asm/arch-mx28/regs-bch.h +21 ~~-21~~

51 lines not on this page · raw message

arch/arm/include/asm/arch-mx28/regs-clkctrl.h +29 ~~-29~~

67 lines not on this page · raw message

arch/arm/include/asm/arch-mx28/regs-common.h +6 -6

index efe975b..75cc9a6 100644
@@ -47,20 +47,20 @@
  *
  */
 
-#define	__mx28_reg(name)		\
+#define	__mx28_reg_32(name)		\
 	uint32_t name;			\
 	uint32_t name##_set;		\
 	uint32_t name##_clr;		\
 	uint32_t name##_tog;
 
-struct mx28_register {
-	__mx28_reg(reg)
+struct mx28_register_32 {
+	__mx28_reg_32(reg)
 };
 
-#define	mx28_reg(name)					\
+#define	mx28_reg_32(name)				\
 	union {						\
-		struct { __mx28_reg(name) };		\
-		struct mx28_register name##_reg;	\
+		struct { __mx28_reg_32(name) };		\
+		struct mx28_register_32 name##_reg;	\
 	};
 
 #endif	/* __MX28_REGS_COMMON_H__ */

arch/arm/include/asm/arch-mx28/regs-gpmi.h +13 ~~-13~~

index 0096793..1b487f4 100644
@@ -30,22 +30,22 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_gpmi_regs {
-	mx28_reg(hw_gpmi_ctrl0)
-	mx28_reg(hw_gpmi_compare)
-	mx28_reg(hw_gpmi_eccctrl)
-	mx28_reg(hw_gpmi_ecccount)
-	mx28_reg(hw_gpmi_payload)
-	mx28_reg(hw_gpmi_auxiliary)
-	mx28_reg(hw_gpmi_ctrl1)
-	mx28_reg(hw_gpmi_timing0)
-	mx28_reg(hw_gpmi_timing1)
+	mx28_reg_32(hw_gpmi_ctrl0)
+	mx28_reg_32(hw_gpmi_compare)
+	mx28_reg_32(hw_gpmi_eccctrl)
+	mx28_reg_32(hw_gpmi_ecccount)
+	mx28_reg_32(hw_gpmi_payload)
+	mx28_reg_32(hw_gpmi_auxiliary)
+	mx28_reg_32(hw_gpmi_ctrl1)
+	mx28_reg_32(hw_gpmi_timing0)
+	mx28_reg_32(hw_gpmi_timing1)
 
 	uint32_t	reserved[4];
 
-	mx28_reg(hw_gpmi_data)
-	mx28_reg(hw_gpmi_stat)
-	mx28_reg(hw_gpmi_debug)
-	mx28_reg(hw_gpmi_version)
+	mx28_reg_32(hw_gpmi_data)
+	mx28_reg_32(hw_gpmi_stat)
+	mx28_reg_32(hw_gpmi_debug)
+	mx28_reg_32(hw_gpmi_version)
 };
 #endif

arch/arm/include/asm/arch-mx28/regs-i2c.h +14 ~~-14~~

index 30e0ed7..2e2e814 100644
@@ -27,20 +27,20 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_i2c_regs {
-	mx28_reg(hw_i2c_ctrl0)
-	mx28_reg(hw_i2c_timing0)
-	mx28_reg(hw_i2c_timing1)
-	mx28_reg(hw_i2c_timing2)
-	mx28_reg(hw_i2c_ctrl1)
-	mx28_reg(hw_i2c_stat)
-	mx28_reg(hw_i2c_queuectrl)
-	mx28_reg(hw_i2c_queuestat)
-	mx28_reg(hw_i2c_queuecmd)
-	mx28_reg(hw_i2c_queuedata)
-	mx28_reg(hw_i2c_data)
-	mx28_reg(hw_i2c_debug0)
-	mx28_reg(hw_i2c_debug1)
-	mx28_reg(hw_i2c_version)
+	mx28_reg_32(hw_i2c_ctrl0)
+	mx28_reg_32(hw_i2c_timing0)
+	mx28_reg_32(hw_i2c_timing1)
+	mx28_reg_32(hw_i2c_timing2)
+	mx28_reg_32(hw_i2c_ctrl1)
+	mx28_reg_32(hw_i2c_stat)
+	mx28_reg_32(hw_i2c_queuectrl)
+	mx28_reg_32(hw_i2c_queuestat)
+	mx28_reg_32(hw_i2c_queuecmd)
+	mx28_reg_32(hw_i2c_queuedata)
+	mx28_reg_32(hw_i2c_data)
+	mx28_reg_32(hw_i2c_debug0)
+	mx28_reg_32(hw_i2c_debug1)
+	mx28_reg_32(hw_i2c_version)
 };
 #endif

arch/arm/include/asm/arch-mx28/regs-ocotp.h +43 ~~-43~~

92 lines not on this page · raw message

arch/arm/include/asm/arch-mx28/regs-pinctrl.h +84 ~~-84~~

213 lines not on this page · raw message

arch/arm/include/asm/arch-mx28/regs-power.h +14 ~~-14~~

index 9da63ad..8eadc6d 100644
@@ -26,10 +26,10 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_power_regs {
-	mx28_reg(hw_power_ctrl)
-	mx28_reg(hw_power_5vctrl)
-	mx28_reg(hw_power_minpwr)
-	mx28_reg(hw_power_charge)
+	mx28_reg_32(hw_power_ctrl)
+	mx28_reg_32(hw_power_5vctrl)
+	mx28_reg_32(hw_power_minpwr)
+	mx28_reg_32(hw_power_charge)
 	uint32_t	hw_power_vdddctrl;
 	uint32_t	reserved_vddd[3];
 	uint32_t	hw_power_vddactrl;

@@ -44,23 +44,23 @@ struct mx28_power_regs {
 	uint32_t	reserved_misc[3];
 	uint32_t	hw_power_dclimits;
 	uint32_t	reserved_dclimits[3];
-	mx28_reg(hw_power_loopctrl)
+	mx28_reg_32(hw_power_loopctrl)
 	uint32_t	hw_power_sts;
 	uint32_t	reserved_sts[3];
-	mx28_reg(hw_power_speed)
+	mx28_reg_32(hw_power_speed)
 	uint32_t	hw_power_battmonitor;
 	uint32_t	reserved_battmonitor[3];
 
 	uint32_t	reserved[4];
 
-	mx28_reg(hw_power_reset)
-	mx28_reg(hw_power_debug)
-	mx28_reg(hw_power_thermal)
-	mx28_reg(hw_power_usb1ctrl)
-	mx28_reg(hw_power_special)
-	mx28_reg(hw_power_version)
-	mx28_reg(hw_power_anaclkctrl)
-	mx28_reg(hw_power_refctrl)
+	mx28_reg_32(hw_power_reset)
+	mx28_reg_32(hw_power_debug)
+	mx28_reg_32(hw_power_thermal)
+	mx28_reg_32(hw_power_usb1ctrl)
+	mx28_reg_32(hw_power_special)
+	mx28_reg_32(hw_power_version)
+	mx28_reg_32(hw_power_anaclkctrl)
+	mx28_reg_32(hw_power_refctrl)
 };
 #endif

arch/arm/include/asm/arch-mx28/regs-rtc.h +14 ~~-14~~

index fe2fda9..e605a03 100644
@@ -27,20 +27,20 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_rtc_regs {
-	mx28_reg(hw_rtc_ctrl)
-	mx28_reg(hw_rtc_stat)
-	mx28_reg(hw_rtc_milliseconds)
-	mx28_reg(hw_rtc_seconds)
-	mx28_reg(hw_rtc_rtc_alarm)
-	mx28_reg(hw_rtc_watchdog)
-	mx28_reg(hw_rtc_persistent0)
-	mx28_reg(hw_rtc_persistent1)
-	mx28_reg(hw_rtc_persistent2)
-	mx28_reg(hw_rtc_persistent3)
-	mx28_reg(hw_rtc_persistent4)
-	mx28_reg(hw_rtc_persistent5)
-	mx28_reg(hw_rtc_debug)
-	mx28_reg(hw_rtc_version)
+	mx28_reg_32(hw_rtc_ctrl)
+	mx28_reg_32(hw_rtc_stat)
+	mx28_reg_32(hw_rtc_milliseconds)
+	mx28_reg_32(hw_rtc_seconds)
+	mx28_reg_32(hw_rtc_rtc_alarm)
+	mx28_reg_32(hw_rtc_watchdog)
+	mx28_reg_32(hw_rtc_persistent0)
+	mx28_reg_32(hw_rtc_persistent1)
+	mx28_reg_32(hw_rtc_persistent2)
+	mx28_reg_32(hw_rtc_persistent3)
+	mx28_reg_32(hw_rtc_persistent4)
+	mx28_reg_32(hw_rtc_persistent5)
+	mx28_reg_32(hw_rtc_debug)
+	mx28_reg_32(hw_rtc_version)
 };
 #endif

arch/arm/include/asm/arch-mx28/regs-ssp.h +20 ~~-20~~

index ab3870c..be71d48 100644
@@ -29,26 +29,26 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_ssp_regs {
-	mx28_reg(hw_ssp_ctrl0)
-	mx28_reg(hw_ssp_cmd0)
-	mx28_reg(hw_ssp_cmd1)
-	mx28_reg(hw_ssp_xfer_size)
-	mx28_reg(hw_ssp_block_size)
-	mx28_reg(hw_ssp_compref)
-	mx28_reg(hw_ssp_compmask)
-	mx28_reg(hw_ssp_timing)
-	mx28_reg(hw_ssp_ctrl1)
-	mx28_reg(hw_ssp_data)
-	mx28_reg(hw_ssp_sdresp0)
-	mx28_reg(hw_ssp_sdresp1)
-	mx28_reg(hw_ssp_sdresp2)
-	mx28_reg(hw_ssp_sdresp3)
-	mx28_reg(hw_ssp_ddr_ctrl)
-	mx28_reg(hw_ssp_dll_ctrl)
-	mx28_reg(hw_ssp_status)
-	mx28_reg(hw_ssp_dll_sts)
-	mx28_reg(hw_ssp_debug)
-	mx28_reg(hw_ssp_version)
+	mx28_reg_32(hw_ssp_ctrl0)
+	mx28_reg_32(hw_ssp_cmd0)
+	mx28_reg_32(hw_ssp_cmd1)
+	mx28_reg_32(hw_ssp_xfer_size)
+	mx28_reg_32(hw_ssp_block_size)
+	mx28_reg_32(hw_ssp_compref)
+	mx28_reg_32(hw_ssp_compmask)
+	mx28_reg_32(hw_ssp_timing)
+	mx28_reg_32(hw_ssp_ctrl1)
+	mx28_reg_32(hw_ssp_data)
+	mx28_reg_32(hw_ssp_sdresp0)
+	mx28_reg_32(hw_ssp_sdresp1)
+	mx28_reg_32(hw_ssp_sdresp2)
+	mx28_reg_32(hw_ssp_sdresp3)
+	mx28_reg_32(hw_ssp_ddr_ctrl)
+	mx28_reg_32(hw_ssp_dll_ctrl)
+	mx28_reg_32(hw_ssp_status)
+	mx28_reg_32(hw_ssp_dll_sts)
+	mx28_reg_32(hw_ssp_debug)
+	mx28_reg_32(hw_ssp_version)
 };
 #endif

arch/arm/include/asm/arch-mx28/regs-timrot.h +19 ~~-19~~

index 1b941cf..3e8dfe7 100644
@@ -29,25 +29,25 @@
 
 #ifndef	__ASSEMBLY__
 struct mx28_timrot_regs {
-	mx28_reg(hw_timrot_rotctrl)
-	mx28_reg(hw_timrot_rotcount)
-	mx28_reg(hw_timrot_timctrl0)
-	mx28_reg(hw_timrot_running_count0)
-	mx28_reg(hw_timrot_fixed_count0)
-	mx28_reg(hw_timrot_match_count0)
-	mx28_reg(hw_timrot_timctrl1)
-	mx28_reg(hw_timrot_running_count1)
-	mx28_reg(hw_timrot_fixed_count1)
-	mx28_reg(hw_timrot_match_count1)
-	mx28_reg(hw_timrot_timctrl2)
-	mx28_reg(hw_timrot_running_count2)
-	mx28_reg(hw_timrot_fixed_count2)
-	mx28_reg(hw_timrot_match_count2)
-	mx28_reg(hw_timrot_timctrl3)
-	mx28_reg(hw_timrot_running_count3)
-	mx28_reg(hw_timrot_fixed_count3)
-	mx28_reg(hw_timrot_match_count3)
-	mx28_reg(hw_timrot_version)
+	mx28_reg_32(hw_timrot_rotctrl)
+	mx28_reg_32(hw_timrot_rotcount)
+	mx28_reg_32(hw_timrot_timctrl0)
+	mx28_reg_32(hw_timrot_running_count0)
+	mx28_reg_32(hw_timrot_fixed_count0)
+	mx28_reg_32(hw_timrot_match_count0)
+	mx28_reg_32(hw_timrot_timctrl1)
+	mx28_reg_32(hw_timrot_running_count1)
+	mx28_reg_32(hw_timrot_fixed_count1)
+	mx28_reg_32(hw_timrot_match_count1)
+	mx28_reg_32(hw_timrot_timctrl2)
+	mx28_reg_32(hw_timrot_running_count2)
+	mx28_reg_32(hw_timrot_fixed_count2)
+	mx28_reg_32(hw_timrot_match_count2)
+	mx28_reg_32(hw_timrot_timctrl3)
+	mx28_reg_32(hw_timrot_running_count3)
+	mx28_reg_32(hw_timrot_fixed_count3)
+	mx28_reg_32(hw_timrot_match_count3)
+	mx28_reg_32(hw_timrot_version)
 };
 #endif

arch/arm/include/asm/arch-mx28/regs-usbphy.h +10 ~~-10~~

index e823e19..0291d81 100644
@@ -24,16 +24,16 @@
 #define __REGS_USBPHY_H__
 
 struct mx28_usbphy_regs {
-	mx28_reg(hw_usbphy_pwd)
-	mx28_reg(hw_usbphy_tx)
-	mx28_reg(hw_usbphy_rx)
-	mx28_reg(hw_usbphy_ctrl)
-	mx28_reg(hw_usbphy_status)
-	mx28_reg(hw_usbphy_debug)
-	mx28_reg(hw_usbphy_debug0_status)
-	mx28_reg(hw_usbphy_debug1)
-	mx28_reg(hw_usbphy_version)
-	mx28_reg(hw_usbphy_ip)
+	mx28_reg_32(hw_usbphy_pwd)
+	mx28_reg_32(hw_usbphy_tx)
+	mx28_reg_32(hw_usbphy_rx)
+	mx28_reg_32(hw_usbphy_ctrl)
+	mx28_reg_32(hw_usbphy_status)
+	mx28_reg_32(hw_usbphy_debug)
+	mx28_reg_32(hw_usbphy_debug0_status)
+	mx28_reg_32(hw_usbphy_debug1)
+	mx28_reg_32(hw_usbphy_version)
+	mx28_reg_32(hw_usbphy_ip)
 };
 
 #define	USBPHY_PWD_RXPWDRX				(1 << 20)

arch/arm/include/asm/arch-mx28/sys_proto.h +7 -3

index f101494..15d8de3 100644
@@ -23,9 +23,13 @@
 #ifndef __MX28_H__
 #define __MX28_H__
 
-int mx28_reset_block(struct mx28_register *reg);
-int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout);
-int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout);
+int mx28_reset_block(struct mx28_register_32 *reg);
+int mx28_wait_mask_set(struct mx28_register_32 *reg,
+		       uint32_t mask,
+		       int timeout);
+int mx28_wait_mask_clr(struct mx28_register_32 *reg,
+		       uint32_t mask,
+		       int timeout);
 
 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int));

drivers/gpio/mxs_gpio.c +8 -8

index 0365812..38dbc81 100644
@@ -73,8 +73,8 @@ int gpio_get_value(unsigned gpio)
 {
 	uint32_t bank = PAD_BANK(gpio);
 	uint32_t offset = PINCTRL_DIN(bank);
-	struct mx28_register *reg =
-		(struct mx28_register *)(MXS_PINCTRL_BASE + offset);
+	struct mx28_register_32 *reg =
+		(struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
 
 	return (readl(&reg->reg) >> PAD_PIN(gpio)) & 1;
 }

@@ -83,8 +83,8 @@ void gpio_set_value(unsigned gpio, int value)
 {
 	uint32_t bank = PAD_BANK(gpio);
 	uint32_t offset = PINCTRL_DOUT(bank);
-	struct mx28_register *reg =
-		(struct mx28_register *)(MXS_PINCTRL_BASE + offset);
+	struct mx28_register_32 *reg =
+		(struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
 
 	if (value)
 		writel(1 << PAD_PIN(gpio), &reg->reg_set);

@@ -96,8 +96,8 @@ int gpio_direction_input(unsigned gpio)
 {
 	uint32_t bank = PAD_BANK(gpio);
 	uint32_t offset = PINCTRL_DOE(bank);
-	struct mx28_register *reg =
-		(struct mx28_register *)(MXS_PINCTRL_BASE + offset);
+	struct mx28_register_32 *reg =
+		(struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
 
 	writel(1 << PAD_PIN(gpio), &reg->reg_clr);

@@ -108,8 +108,8 @@ int gpio_direction_output(unsigned gpio, int value)
 {
 	uint32_t bank = PAD_BANK(gpio);
 	uint32_t offset = PINCTRL_DOE(bank);
-	struct mx28_register *reg =
-		(struct mx28_register *)(MXS_PINCTRL_BASE + offset);
+	struct mx28_register_32 *reg =
+		(struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
 
 	writel(1 << PAD_PIN(gpio), &reg->reg_set);

drivers/usb/host/ehci-mxs.c +4 -4

index c795f23..e1bd37e 100644
@@ -75,8 +75,8 @@ int ehci_hcd_init(void)
 
 	int ret;
 	uint32_t usb_base, cap_base;
-	struct mx28_register *digctl_ctrl =
-		(struct mx28_register *)HW_DIGCTL_CTRL;
+	struct mx28_register_32 *digctl_ctrl =
+		(struct mx28_register_32 *)HW_DIGCTL_CTRL;
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;

@@ -119,8 +119,8 @@ int ehci_hcd_stop(void)
 {
 	int ret;
 	uint32_t tmp;
-	struct mx28_register *digctl_ctrl =
-		(struct mx28_register *)HW_DIGCTL_CTRL;
+	struct mx28_register_32 *digctl_ctrl =
+		(struct mx28_register_32 *)HW_DIGCTL_CTRL;
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;

Signature · 1 line

1.7.9

Stefano Babic

2012-03-03 09:13 UTC #16 lore raw

PATCH 5/7 Renamed mx28_register to mx28_register_32 to prepare for mx28_register_8

Quoted 9 lines · Marek Vasut

From: Robert Delien <[email protected]>
This patch renames mx28_register to mx28_register_32 in order to prepare for the introduction of an 8-bit register, mx28_register_8.
Signed-off-by Robert Delien <[email protected]>
Acked-by Marek Vasut <[email protected]>
Tested-by Marek Vasut <[email protected]>
---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Marek Vasut

author

2012-02-26 22:15 UTC #17 lore raw

PATCH 6/7 Introducing 8-bit wide register, mx28_register_8

In reply to Marek Vasut

From: Robert Delien <[email protected]>

This patch introduces an 8-bit register, mx28_register_8, in order to prepare for fixing erroneous 32-bit wide access of registers hw_clkctrl_frac0 and hw_clkctrl_frac1.

Signed-off-by Robert Delien <[email protected]>

Acked-by Marek Vasut <[email protected]>

Tested-by Marek Vasut <[email protected]>

---
 arch/arm/include/asm/arch-mx28/regs-common.h |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

arch/arm/include/asm/arch-mx28/regs-common.h +16 -0

index 75cc9a6..94b512d 100644
@@ -47,16 +47,32 @@
  *
  */
 
+#define	__mx28_reg_8(name)		\
+	uint8_t	name[4];		\
+	uint8_t	name##_set[4];		\
+	uint8_t	name##_clr[4];		\
+	uint8_t	name##_tog[4];		\
+
 #define	__mx28_reg_32(name)		\
 	uint32_t name;			\
 	uint32_t name##_set;		\
 	uint32_t name##_clr;		\
 	uint32_t name##_tog;
 
+struct mx28_register_8 {
+	__mx28_reg_8(reg)
+};
+
 struct mx28_register_32 {
 	__mx28_reg_32(reg)
 };
 
+#define	mx28_reg_8(name)				\
+	union {						\
+		struct { __mx28_reg_8(name) };		\
+		struct mx28_register_32 name##_reg;	\
+	};
+
 #define	mx28_reg_32(name)				\
 	union {						\
 		struct { __mx28_reg_32(name) };		\

Signature · 1 line

1.7.9

Stefano Babic

2012-03-03 09:14 UTC #18 lore raw

PATCH 6/7 Introducing 8-bit wide register, mx28_register_8

Quoted 10 lines · Marek Vasut

From: Robert Delien <[email protected]>
This patch introduces an 8-bit register, mx28_register_8, in order to prepare for fixing erroneous 32-bit wide access of registers hw_clkctrl_frac0 and hw_clkctrl_frac1.
Signed-off-by Robert Delien <[email protected]>
Acked-by Marek Vasut <[email protected]>
Tested-by Marek Vasut <[email protected]>
---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Marek Vasut

author

2012-02-26 22:15 UTC #19 lore raw

PATCH 7/7 Fix erroneous 32-bit access to hw_clkctrl_frac0 and hw_clkctrl_frac1 registers

In reply to Marek Vasut

From: Robert Delien <[email protected]>

This patch fixes erroneous 32-bit access to registers hw_clkctrl_frac0 and hw_clkctrl_frac1.

Signed-off-by Robert Delien <[email protected]>

Acked-by Marek Vasut <[email protected]>

Tested-by Marek Vasut <[email protected]>

---
 arch/arm/cpu/arm926ejs/mx28/clock.c           |   70 ++++++++++---------------
 arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c    |   26 ++++-----
 arch/arm/include/asm/arch-mx28/regs-clkctrl.h |   44 +++++-----------
 3 files changed, 52 insertions(+), 88 deletions(-)

arch/arm/cpu/arm926ejs/mx28/clock.c +27 ~~-43~~

index 9d3a018..0439f9c 100644
@@ -46,8 +46,8 @@ static uint32_t mx28_get_pclk(void)
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
-	uint32_t clkctrl, clkseq, clkfrac;
-	uint32_t frac, div;
+	uint32_t clkctrl, clkseq, div;
+	uint8_t clkfrac, frac;
 
 	clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu);

@@ -67,8 +67,8 @@ static uint32_t mx28_get_pclk(void)
 	}
 
 	/* REF Path */
-	clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0);
-	frac = clkfrac & CLKCTRL_FRAC0_CPUFRAC_MASK;
+	clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
+	frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
 	div = clkctrl & CLKCTRL_CPU_DIV_CPU_MASK;
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
 }

@@ -96,8 +96,8 @@ static uint32_t mx28_get_emiclk(void)
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
-	uint32_t frac, div;
-	uint32_t clkctrl, clkseq, clkfrac;
+	uint32_t clkctrl, clkseq, div;
+	uint8_t clkfrac, frac;
 
 	clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
 	clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi);

@@ -109,11 +109,9 @@ static uint32_t mx28_get_emiclk(void)
 		return XTAL_FREQ_MHZ / div;
 	}
 
-	clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac0);
-
 	/* REF Path */
-	frac = (clkfrac & CLKCTRL_FRAC0_EMIFRAC_MASK) >>
-		CLKCTRL_FRAC0_EMIFRAC_OFFSET;
+	clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
+	frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
 	div = clkctrl & CLKCTRL_EMI_DIV_EMI_MASK;
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
 }

@@ -123,8 +121,8 @@ static uint32_t mx28_get_gpmiclk(void)
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
-	uint32_t frac, div;
-	uint32_t clkctrl, clkseq, clkfrac;
+	uint32_t clkctrl, clkseq, div;
+	uint8_t clkfrac, frac;
 
 	clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
 	clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi);

@@ -135,11 +133,9 @@ static uint32_t mx28_get_gpmiclk(void)
 		return XTAL_FREQ_MHZ / div;
 	}
 
-	clkfrac = readl(&clkctrl_regs->hw_clkctrl_frac1);
-
 	/* REF Path */
-	frac = (clkfrac & CLKCTRL_FRAC1_GPMIFRAC_MASK) >>
-		CLKCTRL_FRAC1_GPMIFRAC_OFFSET;
+	clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]);
+	frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
 	div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
 	return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
 }

@@ -152,11 +148,12 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 	uint32_t div;
+	int io_reg;
 
 	if (freq == 0)
 		return;
 
-	if (io > MXC_IOCLK1)
+	if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
 		return;
 
 	div = (PLL_FREQ_KHZ * PLL_FREQ_COEF) / freq;

@@ -167,23 +164,13 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
 	if (div > 35)
 		div = 35;
 
-	if (io == MXC_IOCLK0) {
-		writel(CLKCTRL_FRAC0_CLKGATEIO0,
-			&clkctrl_regs->hw_clkctrl_frac0_set);
-		clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
-				CLKCTRL_FRAC0_IO0FRAC_MASK,
-				div << CLKCTRL_FRAC0_IO0FRAC_OFFSET);
-		writel(CLKCTRL_FRAC0_CLKGATEIO0,
-			&clkctrl_regs->hw_clkctrl_frac0_clr);
-	} else {
-		writel(CLKCTRL_FRAC0_CLKGATEIO1,
-			&clkctrl_regs->hw_clkctrl_frac0_set);
-		clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
-				CLKCTRL_FRAC0_IO1FRAC_MASK,
-				div << CLKCTRL_FRAC0_IO1FRAC_OFFSET);
-		writel(CLKCTRL_FRAC0_CLKGATEIO1,
-			&clkctrl_regs->hw_clkctrl_frac0_clr);
-	}
+	io_reg = CLKCTRL_FRAC0_IO0 - io;	/* Register order is reversed */
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_set[io_reg]);
+	writeb(CLKCTRL_FRAC_CLKGATE | (div & CLKCTRL_FRAC_FRAC_MASK),
+		&clkctrl_regs->hw_clkctrl_frac0[io_reg]);
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_clr[io_reg]);
 }
 
 /*

@@ -193,19 +180,16 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
 {
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
-	uint32_t tmp, ret;
+	uint8_t ret;
+	int io_reg;
 
-	if (io > MXC_IOCLK1)
+	if ((io < MXC_IOCLK0) || (io > MXC_IOCLK1))
 		return 0;
 
-	tmp = readl(&clkctrl_regs->hw_clkctrl_frac0);
+	io_reg = CLKCTRL_FRAC0_IO0 - io;	/* Register order is reversed */
 
-	if (io == MXC_IOCLK0)
-		ret = (tmp & CLKCTRL_FRAC0_IO0FRAC_MASK) >>
-			CLKCTRL_FRAC0_IO0FRAC_OFFSET;
-	else
-		ret = (tmp & CLKCTRL_FRAC0_IO1FRAC_MASK) >>
-			CLKCTRL_FRAC0_IO1FRAC_OFFSET;
+	ret = readb(&clkctrl_regs->hw_clkctrl_frac0[io_reg]) &
+		CLKCTRL_FRAC_FRAC_MASK;
 
 	return (PLL_FREQ_KHZ * PLL_FREQ_COEF) / ret;
 }

arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +12 ~~-14~~

index fd18f70..43a90ff 100644
@@ -96,22 +96,20 @@ void mx28_mem_init_clock(void)
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
 	/* Gate EMI clock */
-	writel(CLKCTRL_FRAC0_CLKGATEEMI,
-		&clkctrl_regs->hw_clkctrl_frac0_set);
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
 
-	/* EMI = 205MHz */
-	writel(CLKCTRL_FRAC0_EMIFRAC_MASK,
-		&clkctrl_regs->hw_clkctrl_frac0_set);
-	writel((0x2a << CLKCTRL_FRAC0_EMIFRAC_OFFSET) &
-		CLKCTRL_FRAC0_EMIFRAC_MASK,
-		&clkctrl_regs->hw_clkctrl_frac0_clr);
+	/* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */
+	writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK),
+		&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
 
 	/* Ungate EMI clock */
-	writel(CLKCTRL_FRAC0_CLKGATEEMI,
-		&clkctrl_regs->hw_clkctrl_frac0_clr);
+	writeb(CLKCTRL_FRAC_CLKGATE,
+		&clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]);
 
 	early_delay(11000);
 
+	/* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */
 	writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
 		(1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
 		&clkctrl_regs->hw_clkctrl_emi);

@@ -128,10 +126,10 @@ void mx28_mem_setup_cpu_and_hbus(void)
 	struct mx28_clkctrl_regs *clkctrl_regs =
 		(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
-	/* CPU = 454MHz and ungate CPU clock */
-	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
-		CLKCTRL_FRAC0_CPUFRAC_MASK | CLKCTRL_FRAC0_CLKGATECPU,
-		19 << CLKCTRL_FRAC0_CPUFRAC_OFFSET);
+	/* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
+	 * and ungate CPU clock */
+	writeb(19 & CLKCTRL_FRAC_FRAC_MASK,
+		(uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]);
 
 	/* Set CPU bypass */
 	writel(CLKCTRL_CLKSEQ_BYPASS_CPU,

arch/arm/include/asm/arch-mx28/regs-clkctrl.h +13 ~~-31~~

56 lines not on this page · raw message

Signature · 1 line

1.7.9

Stefano Babic

2012-03-03 09:16 UTC #20 lore raw

PATCH 7/7 Fix erroneous 32-bit access to hw_clkctrl_frac0 and hw_clkctrl_frac1 registers

Quoted 9 lines · Marek Vasut

From: Robert Delien <[email protected]>
This patch fixes erroneous 32-bit access to registers hw_clkctrl_frac0 and hw_clkctrl_frac1.
Signed-off-by Robert Delien <[email protected]>
Acked-by Marek Vasut <[email protected]>
Tested-by Marek Vasut <[email protected]>
---

Applied to u-boot-imx, thanks

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================