tegra: Add fdt definitions and USB driver

This series brings in the Linux kernel fdt file and provides a working USB driver for Tegra2 Seaboard.

(I have done this in one series since otherwise most of the fdt additions will just look like dead code.)

The driver requires CONFIG_OF_CONTROL and a device tree to operate.

Some enhancements to fdtdec are required to make this easier, and these are included in the series also. I have had to bring in basic GPIO support due to the request to put the USB VBUS into the fdt.

Since the kernel recently got a very minimal USB binding, I have started with that and extended it where appropriate.

Tegra likes to have cache-aligned buffers. I have dropped the patch which implements this since we will solve this problem by making callers align their buffers (as we did with MMC).

Changes in v2:
- Add setting of pinmux for USB VBUS GPIO
- Decode USB VBUS GPIO from the fdt
- Decode phy type differently (to match new kernel fdt)
- Improve debug() printouts in case of failure to init USB
- Remove 0x from fdt aliases
- Remove non-fdt operation of USB, since it is not needed
- Remove unneeded CONFIG_TEGRA_USBx defines
- Rename params to timing
- Rename tegra20-usb to tegra20-ehcui (to match new kernel fdt)
- Store entire fdt config in port list, not just register pointer
- Use "okay" instead of "ok" for fdt node status

Changes in v3:
- Disable USB2 which is not used on Seaboard
- Drop Tegra USB alignment patch as we will deal with this another way
- Fix device tree indenting with tabs instead of spaces
- Remove "okay" from nodes since this is the default anyway
- Remove usbparams properties from fdt and moved them to C code

Changes in v4:
- Add clock bindings for Tegra2x
- Add fdtdec function to return peripheral ID
- Add staging area for device tree bindings used in U-Boot
- Use peripheral clock node to obtain peripheral ID
- Use updated fdtdec alias functiona to get USB aliases

Changes in v5:
- Add CONFIG_EHCI_DCACHE which is needed for dcache operation
- Add additional debugging to report active USB ports
- Add dr_mode property to control host/device/otg mode
- Add nvidia,has-legacy-mode property per review comments
- Allow any port to operate in otg mode
- Change device tree comment style from // to /* */
- Correct PTS_MASK value to be unsigned
- Drop unused CONFIG_USB_EHCI_DATA_ALIGN option
- Fixed endian bug in fdtdec_decode_gpios()
- Implement new device tree properties
- Make sure GPIO name is NULL if incorrectly decoded
- Put pinmux setting into a board-specific function
- Remove checking of peripheral ID and try to use only device tree
- Remove support-host-mode property
- Report error if phy clock does not start up
- Update README to indicate that we will commit fdt documentation to U-Boot

Changes in v6:
- Add clock bindings from Stephen Warren's latest patch
- Add new patch to bring in clock bindings to seaboard
- Drop fdt alignment patch as we will handle this after generic reloc
- Move peripheral decode function into Tegra's clock.c
- Remove dr_mode properties from SOC .dtsi file and move to boards
- Use updated clock_decode_periph_id() function

Simon Glass (20):
fdt: Tidy up a few fdtdec problems
fdt: Add functions to access phandles, arrays and bools
fdt: Add basic support for decoding GPIO definitions
arm: fdt: Add skeleton device tree file from kernel
tegra: fdt: Add Tegra2x device tree file from kernel
tegra: fdt: Add device tree file for Tegra2 Seaboard from kernel
fdt: Add staging area for device tree binding documentation
fdt: Add tegra-usb bindings file from linux
tegra: fdt: Add additional USB binding
tegra: fdt: Add clock bindings
tegra: fdt: Add clock bindings for Tegra2 Seaboard
tegra: usb: fdt: Add additional device tree definitions for USB ports
tegra: usb: fdt: Add USB definitions for Tegra2 Seaboard
usb: Add support for txfifo threshold
tegra: fdt: Add function to return peripheral/clock ID
tegra: usb: Add support for Tegra USB peripheral
tegra: usb: Add USB support to nvidia boards
tegra: usb: Add common USB defines for tegra2 boards
tegra: usb: Enable USB on Seaboard
tegra: fdt: Enable FDT support for Seaboard

 README                                             |    3 +
 arch/arm/cpu/armv7/tegra2/Makefile                 |    4 +-
 arch/arm/cpu/armv7/tegra2/clock.c                  |   19 +
 arch/arm/cpu/armv7/tegra2/config.mk                |    2 +
 arch/arm/cpu/armv7/tegra2/usb.c                    |  460 ++++++++++++++++++++
 arch/arm/dts/skeleton.dtsi                         |   13 +
 arch/arm/dts/tegra20.dtsi                          |  188 ++++++++
 arch/arm/include/asm/arch-tegra2/clock.h           |   13 +
 arch/arm/include/asm/arch-tegra2/tegra2.h          |    2 +
 arch/arm/include/asm/arch-tegra2/usb.h             |  252 +++++++++++
 board/nvidia/common/board.c                        |   12 +
 board/nvidia/common/board.h                        |    6 +
 board/nvidia/dts/tegra2-seaboard.dts               |   57 +++
 board/nvidia/seaboard/seaboard.c                   |    6 +
 doc/device-tree-bindings/README                    |   17 +
 .../clock/nvidia,tegra20-car.txt                   |  207 +++++++++
 doc/device-tree-bindings/usb/tegra-usb.txt         |   25 +
 drivers/usb/host/Makefile                          |    1 +
 drivers/usb/host/ehci-hcd.c                        |    7 +
 drivers/usb/host/ehci-tegra.c                      |   62 +++
 drivers/usb/host/ehci.h                            |    6 +-
 include/configs/seaboard.h                         |   12 +
 include/configs/tegra2-common.h                    |   10 +
 include/fdtdec.h                                   |  108 +++++-
 lib/fdtdec.c                                       |  169 +++++++-
 25 files changed, 1649 insertions(+), 12 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/tegra2/usb.c
 create mode 100644 arch/arm/dts/skeleton.dtsi
 create mode 100644 arch/arm/dts/tegra20.dtsi
 create mode 100644 arch/arm/include/asm/arch-tegra2/usb.h
 create mode 100644 board/nvidia/dts/tegra2-seaboard.dts
 create mode 100644 doc/device-tree-bindings/README
 create mode 100644 doc/device-tree-bindings/clock/nvidia,tegra20-car.txt
 create mode 100644 doc/device-tree-bindings/usb/tegra-usb.txt
 create mode 100644 drivers/usb/host/ehci-tegra.c

1.7.7.3

This fixes five trivial issues in fdtdec.c:
1. fdtdec_get_is_enabled() doesn't really need a default value
2. The fdt must be word-aligned, since otherwise it will fail on ARM
3. The compat_names[] array is missing its first element. This is needed only because the first fdt_compat_id is defined to be invalid.
4. Added a header prototype for fdtdec_next_compatible()
5. Change fdtdec_next_alias() to only increment its 'upto' parameter on success, to make the display error messages in the caller easier.

---

 include/fdtdec.h |   23 +++++++++++++++++++----
 lib/fdtdec.c     |   22 ++++++++++++++++------
 2 files changed, 35 insertions(+), 10 deletions(-)

index 3a15f55..01badd4 100644
@@ -82,6 +82,21 @@ int fdtdec_next_alias(const void *blob, const char *name,
 		enum fdt_compat_id id, int *upto);
 
 /**
+ * Find the next compatible node for a peripheral.
+ *
+ * Do the first call with node = 0. This function will return a pointer to
+ * the next compatible node. Next time you call this function, pass the
+ * value returned, and the next node will be provided.
+ *
+ * @param blob		FDT blob to use
+ * @param node		Start node for search
+ * @param id		Compatible ID to look for (enum fdt_compat_id)
+ * @return offset of next compatible node, or -FDT_ERR_NOTFOUND if no more
+ */
+int fdtdec_next_compatible(const void *blob, int node,
+		enum fdt_compat_id id);
+
+/**
  * Look up an address property in a node and return it as an address.
  * The property must hold either one address with no trailing data or
  * one address with a length. This is only tested on 32-bit machines.

@@ -112,14 +127,14 @@ s32 fdtdec_get_int(const void *blob, int node, const char *prop_name,
  * Checks whether a node is enabled.
  * This looks for a 'status' property. If this exists, then returns 1 if
  * the status is 'ok' and 0 otherwise. If there is no status property,
- * it returns the default value.
+ * it returns 1 on the assumption that anything mentioned should be enabled
+ * by default.
  *
  * @param blob	FDT blob
  * @param node	node to examine
- * @param default_val	default value to return if no 'status' property exists
- * @return integer value 0/1, if found, or default_val if not
+ * @return integer value 0 (not enabled) or 1 (enabled)
  */
-int fdtdec_get_is_enabled(const void *blob, int node, int default_val);
+int fdtdec_get_is_enabled(const void *blob, int node);
 
 /**
  * Checks whether we have a valid fdt available to control U-Boot, and panic

index 3852038..846ec3f 100644
@@ -33,6 +33,7 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 #define COMPAT(id, name) name
 static const char * const compat_names[COMPAT_COUNT] = {
+	COMPAT(UNKNOWN, "<none>"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)

@@ -89,14 +90,21 @@ s32 fdtdec_get_int(const void *blob, int node, const char *prop_name,
 	return default_val;
 }
 
-int fdtdec_get_is_enabled(const void *blob, int node, int default_val)
+int fdtdec_get_is_enabled(const void *blob, int node)
 {
 	const char *cell;
 
+	/*
+	 * It should say "okay", so only allow that. Some fdts use "ok" but
+	 * this is a bug. Please fix your device tree source file. See here
+	 * for discussion:
+	 *
+	 * http://www.mail-archive.com/[email protected]/msg71598.html
+	 */
 	cell = fdt_getprop(blob, node, "status", NULL);
 	if (cell)
-		return 0 == strcmp(cell, "ok");
-	return default_val;
+		return 0 == strcmp(cell, "okay");
+	return 1;
 }
 
 enum fdt_compat_id fd_dec_lookup(const void *blob, int node)

@@ -127,14 +135,16 @@ int fdtdec_next_alias(const void *blob, const char *name,
 	/* snprintf() is not available */
 	assert(strlen(name) < MAX_STR_LEN);
 	sprintf(str, "%.*s%d", MAX_STR_LEN, name, *upto);
-	(*upto)++;
 	node = find_alias_node(blob, str);
 	if (node < 0)
 		return node;
 	err = fdt_node_check_compatible(blob, node, compat_names[id]);
 	if (err < 0)
 		return err;
-	return err ? -FDT_ERR_NOTFOUND : node;
+	if (err)
+		return -FDT_ERR_NOTFOUND;
+	(*upto)++;
+	return node;
 }
 
 /* TODO: Can we tighten this code up a little? */

@@ -254,7 +264,7 @@ int fdtdec_find_aliases_for_id(const void *blob, const char *name,
 int fdtdec_check_fdt(void)
 {
 	/* We must have an fdt */
-	if (fdt_check_header(gd->fdt_blob))
+	if (((uintptr_t)gd->fdt_blob & 3) || fdt_check_header(gd->fdt_blob))
 		panic("No valid fdt found - please append one to U-Boot\n"
 			"binary or define CONFIG_OF_EMBED\n");
 	return 0;

1.7.7.3

Add a function to look up a property which is a phandle in a node, and another to read a fixed-length integer array from an fdt property. Also add a function to read boolean properties, although there is no actual boolean type in U-Boot.

---

 include/fdtdec.h |   39 +++++++++++++++++++++++++++++++
 lib/fdtdec.c     |   67 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 106 insertions(+), 0 deletions(-)

index 01badd4..047f603 100644
@@ -188,3 +188,42 @@ int fdtdec_find_aliases_for_id(const void *blob, const char *name,
  * @return compatible string for that id
  */
 const char *fdtdec_get_compatible(enum fdt_compat_id id);
+
+/* Look up a phandle and follow it to its node. Then return the offset
+ * of that node.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @return node offset if found, -ve error code on error
+ */
+int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name);
+
+/**
+ * Look up a property in a node and return its contents in an integer
+ * array of given length. The property must have at least enough data for
+ * the array (4*count bytes). It may have more, but this will be ignored.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @param array		array to fill with data
+ * @param count		number of array elements
+ * @return 0 if ok, or -FDT_ERR_NOTFOUND if the property is not found,
+ *		or -FDT_ERR_BADLAYOUT if not enough data
+ */
+int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
+		u32 *array, int count);
+
+/**
+ * Look up a boolean property in a node and return it.
+ *
+ * A boolean properly is true if present in the device tree and false if not
+ * present, regardless of its value.
+ *
+ * @param blob	FDT blob
+ * @param node	node to examine
+ * @param prop_name	name of property to find
+ * @return 1 if the properly is present; 0 if it isn't present
+ */
+int fdtdec_get_bool(const void *blob, int node, const char *prop_name);

1.7.7.3

This adds some support into fdtdec for reading GPIO definitions from the fdt. We permit up to FDT_GPIO_MAX GPIOs in the system. Each GPIO is of the form:

gpio-function-name = <phandle gpio_num flags>;

where:

phandle is a pointer to the GPIO node
gpio_num is the number of the GPIO (0 to 223)
flags is a flag, as follows:

bit meaning
0 0=polarity normal, 1=active low (inverted)

An example is:

enable-propounder-gpios = <&gpio 43 0>;

which means that GPIO 43 is used to enable the propounder (setting the GPIO high), or that you can detect that the propounder is enabled by checking if the GPIO is high (the fdt does not indicate input/output).

Two main functions are provided:

fdtdec_decode_gpio() reads a GPIO property from an fdt node and decodes it into a structure.

fdtdec_setup_gpio() sets up the GPIO by calling gpio_request for you.

Both functions can cope with the property being missing, which is taken to mean that that GPIO function is not available or is not needed.

[For reference, from Stephen Warren <[email protected]>. It may be that we add this extra complexity later if needed:

The correct way to parse such a GPIO property in general is:

* Read the first cell.
* Find the node referenced by the phandle (the controller).
* Ensure property gpio-controller is present in the controller node.
* Read property #gpio-cells from the controller node.
* Extract #gpio-cells from the original property.
* Keep processing more cells from the original property; there may be multiple GPIOs listed.

According to the binding documentation in the Linux kernel, Samsung Exynos4 doesn't use this format, and while all other chips do have a flags cell, about 50% of the controllers indicate the cell is unused. ]

---
Changes in v5:
- Fixed endian bug in fdtdec_decode_gpios()
- Make sure GPIO name is NULL if incorrectly decoded

 include/fdtdec.h |   45 ++++++++++++++++++++++++++++++
 lib/fdtdec.c     |   79 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 124 insertions(+), 0 deletions(-)

index 047f603..6c0a2d1 100644
@@ -61,6 +61,23 @@ enum fdt_compat_id {
 	COMPAT_COUNT,
 };
 
+/* GPIOs are numbered from 0 */
+enum {
+	FDT_GPIO_NONE = -1U,	/* an invalid GPIO used to end our list */
+
+	FDT_GPIO_ACTIVE_LOW = 1 << 0,	/* input is active low (else high) */
+};
+
+/* This is the state of a GPIO pin as defined by the fdt */
+struct fdt_gpio_state {
+	const char *name;	/* name of the fdt property defining this */
+	uint gpio;		/* GPIO number, or FDT_GPIO_NONE if none */
+	u8 flags;		/* FDT_GPIO_... flags */
+};
+
+/* This tells us whether a fdt_gpio_state record is valid or not */
+#define fdt_gpio_isvalid(x) ((x)->gpio != FDT_GPIO_NONE)
+
 /**
  * Find the next numbered alias for a peripheral. This is used to enumerate
  * all the peripherals of a certain type.

@@ -227,3 +244,31 @@ int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
  * @return 1 if the properly is present; 0 if it isn't present
  */
 int fdtdec_get_bool(const void *blob, int node, const char *prop_name);
+
+/**
+ * Decode a single GPIOs from an FDT.
+ *
+ * If the property is not found, then the GPIO structure will still be
+ * initialised, with gpio set to FDT_GPIO_NONE. This makes it easy to
+ * provide optional GPIOs.
+ *
+ * @param blob		FDT blob to use
+ * @param node		Node to look at
+ * @param prop_name	Node property name
+ * @param gpio		gpio elements to fill from FDT
+ * @return 0 if ok, -FDT_ERR_NOTFOUND if the property is missing.
+ */
+int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name,
+		struct fdt_gpio_state *gpio);
+
+/**
+ * Set up a GPIO pin according to the provided gpio information. At present this
+ * just requests the GPIO.
+ *
+ * If the gpio is FDT_GPIO_NONE, no action is taken. This makes it easy to
+ * deal with optional GPIOs.
+ *
+ * @param gpio		GPIO info to use for set up
+ * @return 0 if all ok or gpio was FDT_GPIO_NONE; -1 on error
+ */
+int fdtdec_setup_gpio(struct fdt_gpio_state *gpio);

1.7.7.3

This was taken from commit b48c54e2 at:
git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git

---

 arch/arm/dts/skeleton.dtsi |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/dts/skeleton.dtsi

new file mode 100644
index 0000000..b41d241
@@ -0,0 +1,13 @@
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value.  The bootloader will typically populate the memory
+ * node.
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	chosen { };
+	aliases { };
+	memory { device_type = "memory"; reg = <0 0>; };
+};

1.7.7.3

This was taken from commit b48c54e2 at:
git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git

config.mk is updated to provide this file to boards through the built-in mechanism:

/include/ ARCH_CPU_DTS

---

 arch/arm/cpu/armv7/tegra2/config.mk |    2 +
 arch/arm/dts/tegra20.dtsi           |  168 +++++++++++++++++++++++++++++++++++
 2 files changed, 170 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/dts/tegra20.dtsi

index 2303dba..fe9ef5b 100644
@@ -31,3 +31,5 @@ CFLAGS_arch/arm/lib/board.o += -march=armv4t
 endif
 
 USE_PRIVATE_LIBGCC = yes
+
+CONFIG_ARCH_DEVICE_TREE := tegra20

1.7.7.3

This was taken from commit b48c54e2 at:
git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git

---

 board/nvidia/dts/tegra2-seaboard.dts |   36 ++++++++++++++++++++++++++++++++++
 1 files changed, 36 insertions(+), 0 deletions(-)
 create mode 100644 board/nvidia/dts/tegra2-seaboard.dts

new file mode 100644
index 0000000..dde5d03
@@ -0,0 +1,36 @@
+/dts-v1/;
+
+/memreserve/ 0x1c000000 0x04000000;
+/include/ ARCH_CPU_DTS
+
+/ {
+	model = "NVIDIA Seaboard";
+	compatible = "nvidia,seaboard", "nvidia,tegra20";
+
+	chosen {
+		bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = < 0x00000000 0x40000000 >;
+	};
+
+	serial@70006300 {
+		clock-frequency = < 216000000 >;
+	};
+
+	sdhci@c8000400 {
+		cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+	};
+
+	sdhci@c8000600 {
+		support-8bit;
+	};
+
+	usb@c5000000 {
+		nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+	};
+};

1.7.7.3

This adds a property to indicate a port which can switch between host and device mode.

---
Changes in v5:
- Add dr_mode property to control host/device/otg mode
- Add nvidia,has-legacy-mode property per review comments

 doc/device-tree-bindings/usb/tegra-usb.txt |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

index 035d63d..b7174a3 100644
@@ -11,3 +11,15 @@ Required properties :
  - phy_type : Should be one of "ulpi" or "utmi".
  - nvidia,vbus-gpio : If present, specifies a gpio that needs to be
    activated for the bus to be powered.
+
+Optional properties:
+  - dr_mode : dual role mode. Indicates the working mode for
+   nvidia,tegra20-ehci compatible controllers.  Can be "host", "peripheral",
+   or "otg".  Default to "host" if not defined for backward compatibility.
+      host means this is a host controller
+      peripheral means it is device controller
+      otg means it can operate as either ("on the go")
+  - nvidia,has-legacy-mode : boolean indicates whether this controller can
+    operate in legacy mode (as APX 2500 / 2600). In legacy mode some
+    registers are accessed through the APB_MISC base address instead of
+    the USB controller.

1.7.7.3

...

...

nvpublic

This adds a basic binding for the oscillator and peripheral clocks. The second cell is the clock number, defined as the bit number within the clock enable register if the peripheral clock.

This uses the RFC clock bindings from Grant Likely so may change later:

https://lkml.org/lkml/2011/12/12/498

It is taken from Stephen Warren's patch here:

http://patchwork.ozlabs.org/patch/141359/

---
Changes in v4:
- Add clock bindings for Tegra2x

Changes in v6:
- Add clock bindings from Stephen Warren's latest patch

 arch/arm/dts/tegra20.dtsi                          |   16 ++
 .../clock/nvidia,tegra20-car.txt                   |  207 ++++++++++++++++++++
 2 files changed, 223 insertions(+), 0 deletions(-)
 create mode 100644 doc/device-tree-bindings/clock/nvidia,tegra20-car.txt

index a9a98ea..2c46e11 100644
@@ -4,6 +4,22 @@
 	compatible = "nvidia,tegra20";
 	interrupt-parent = <&intc>;
 
+	tegra_car: clock@60006000 {
+		compatible = "nvidia,tegra20-car";
+		reg = <0x60006000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		osc: clock {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
 	intc: interrupt-controller@50041000 {
 		compatible = "nvidia,tegra20-gic";
 		interrupt-controller;

1.7.7.3

Add the definition of the oscillator clock frequency.

---
Changes in v6:
- Add new patch to bring in clock bindings to seaboard

 board/nvidia/dts/tegra2-seaboard.dts |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

index dde5d03..87f58fb 100644
@@ -16,6 +16,16 @@
 		reg = < 0x00000000 0x40000000 >;
 	};
 
+	clocks {
+		osc {
+			clock-frequency = <12000000>;
+		};
+	};
+
+	clock@60006000 {
+		clocks = <&osc>;
+	};
+
 	serial@70006300 {
 		clock-frequency = < 216000000 >;
 	};

1.7.7.3

Hi Stephen,

Yes I saw that - but it adds an i2c binding which I don't yet have. I add i2c in the next series.

I will add that one i2c node here.

Regards,
Simon

Simon Glass wrote at Tuesday, February 28, 2012 10:21 AM:

The clock doesn't /have/ to be represented by its full I2C source; you could represent it as another global fixed-clock source until the I2C node is available to act as a clock source.

Note that in order to actually use the tps6586x node to provide the clock source, you'll need to write or modify the tps6586x's bindings to document which clock sources it provides. I haven't actually looked at the tps6586x's bindings at all; it's possible that part of the example is entirely incorrect. In my original email I quoted above, the part of the example I was caring about was that the CAR itself needs two entries in its clocks property; I don't really care where they come from at present.

nvpublic

Hi Stephen,

I don't have tps6586x bindings and don't have support for them in U-Boot at present. U-Boot also doesn't look at the clocks property so I think your request is entirely about keeping things in sync with what we expect will go into the kernel in the future.

I am going to add your binding, less the #clock-cells which U-Boot currently can't support because it conflicts with the C preprocessor (at some point I may look at a patch to use sed or some other means of avoiding this).

Regards,
Simon

Simon Glass wrote at Tuesday, February 28, 2012 10:38 AM:
...

Out of curiosity, why does the C preprocessor come into it? Is U-Boot's build process running cpp on the .dts files or something? That's non- standard, although perhaps it could be a useful standard...

nvpublic

Hi Stephen,

Yes, but at the moment we only use it for '/include/ ARCH_CPU_DTS'.

Still hoping your symbolic stuff will go in though.

Regards,
Simon

Simon Glass wrote at Tuesday, February 28, 2012 11:37 AM:

Uggh. That's going to make the device tree files look different between the kernel and U-Boot:-( With # disallowed in particular, it's going to prevent U-Boot from /ever/ using the correct protocols for parsing the device tree. This seems like an extremely bad idea.

That looks extremely unlikely in its current form. Ideally, I will get time to take Jon's or David's patches and push one of them forward to provide a more complete solution, but it's a very long way out either way.

nvpublic

Hi Stephen,

Until we change it in U-Boot, you mean. We could move to sed or pre- and post-process the file to remove and re-insert the #.

That's a shame.

Regards,
Simon

Rather, to convert # signs into something that the DTS cannot contain and the compiler can withstand (and it should be printable ASCII, too). is '##' a good candidate?

If so, a forward conversion would e.g. map '/include/' to '#include' and any '#' to '##', and the reverse conversion would turn all '##' to '#'.

But something that simple is bound to be wrong in some way...

Amicalement,

Albert.

Hi Albert,

It seems reasonable, although the /include/ is handled by the dtc itself. If we bypath that then line number reporting won't work. However I do have problems getting dtc to find its include files - I wish it had a -I option.

I will take a look at this in a few weeks once this series in is and I have looked at the include file problem in more detail.

Regards,
Simon

Keeping my TI hat on, I think it'd be a bad idea to have dts stuff divergent from the kernel. Have you raised the problem you're trying to solve to the general DT gurus? My very high level hope is that someday we can have them shared between kernel and u-boot (either directly or something silly like a .dtss that spits out a kernel dts and a u-boot dts). Going with a manual sync from kernel form to u-boot form seems like adding a burden on ourselves we might not have to.

Tom

Hi Tom,

I agree, of course. I think the best solution may be to implement search paths in dtc. I sent a patch today so let's see what people think.

It is even worse when we copy the .dts and .dtsi files somewhere else (e.g. losing the original directory tree relationship by copying all into one directory).

Regards,
Simon

This adds clock references to the USB part of the device tree for U-Boot, and marks USB1 as supporting legacy mode (which we disable in the driver).

The USB timing information may vary between boards sometimes, but for now we hard-code it in C. This is because all current T2x boards use the same values, we will deal with T3x later and we first need to agree on the format for this timing information in the fdt and may in fact decide that it has no place there.

---
Changes in v5:
- Add dr_mode property to control host/device/otg mode
- Add nvidia,has-legacy-mode property per review comments
- Change device tree comment style from // to /* */

Changes in v6:
- Remove dr_mode properties from SOC .dtsi file and move to boards

 arch/arm/dts/tegra20.dtsi |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

index 2c46e11..d6bc9f1 100644
@@ -165,6 +165,8 @@
 		reg = <0xc5000000 0x4000>;
 		interrupts = < 52 >;
 		phy_type = "utmi";
+		clocks = <&tegra_car 22>;	/* PERIPH_ID_USBD */
+		nvidia,has-legacy-mode;
 	};
 
 	usb@c5004000 {

@@ -172,6 +174,7 @@
 		reg = <0xc5004000 0x4000>;
 		interrupts = < 53 >;
 		phy_type = "ulpi";
+		clocks = <&tegra_car 58>;	/* PERIPH_ID_USB2 */
 	};
 
 	usb@c5008000 {

@@ -179,6 +182,7 @@
 		reg = <0xc5008000 0x4000>;
 		interrupts = < 129 >;
 		phy_type = "utmi";
+		clocks = <&tegra_car 59>;	/* PERIPH_ID_USB3 */
 	};
 
 };

1.7.7.3

This adds basic support for the Tegra2 USB controller. Board files should call board_usb_init() to set things up.

Configuration is performed through the FDT, with aliases used to set the order of the ports, like this fragment:

        aliases {
		/* This defines the order of our USB ports */
                usb0 = "/usb@0xc5008000";
                usb1 = "/usb@0xc5000000";
        };

drivers/usb/host files ONLY: Acked-by: Remy Bohmer <linux-SYUVB/[email protected]>

---
Changes in v2:
- Decode USB VBUS GPIO from the fdt
- Decode phy type differently (to match new kernel fdt)
- Improve debug() printouts in case of failure to init USB
- Remove non-fdt operation of USB, since it is not needed
- Rename params to timing
- Rename tegra20-usb to tegra20-ehcui (to match new kernel fdt)
- Store entire fdt config in port list, not just register pointer

Changes in v3:
- Remove usbparams properties from fdt and moved them to C code

Changes in v4:
- Use peripheral clock node to obtain peripheral ID
- Use updated fdtdec alias functiona to get USB aliases

Changes in v5:
- Add additional debugging to report active USB ports
- Allow any port to operate in otg mode
- Correct PTS_MASK value to be unsigned
- Implement new device tree properties
- Remove checking of peripheral ID and try to use only device tree
- Report error if phy clock does not start up

Changes in v6:
- Use updated clock_decode_periph_id() function

 arch/arm/cpu/armv7/tegra2/Makefile        |    4 +-
 arch/arm/cpu/armv7/tegra2/usb.c           |  460 +++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-tegra2/tegra2.h |    2 +
 arch/arm/include/asm/arch-tegra2/usb.h    |  252 ++++++++++++++++
 drivers/usb/host/Makefile                 |    1 +
 drivers/usb/host/ehci-tegra.c             |   62 ++++
 include/fdtdec.h                          |    1 +
 lib/fdtdec.c                              |    1 +
 8 files changed, 782 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/tegra2/usb.c
 create mode 100644 arch/arm/include/asm/arch-tegra2/usb.h
 create mode 100644 drivers/usb/host/ehci-tegra.c

index f668a81..e9ac6c9 100644
@@ -33,8 +33,10 @@ include $(TOPDIR)/config.mk
 LIB	=  $(obj)lib$(SOC).o
 
 SOBJS	:= lowlevel_init.o
-COBJS	:= ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
+COBJS-y	:= ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
+COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
 
+COBJS	:= $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
 

index 8941443..baae2eb 100644
@@ -41,6 +41,8 @@
 #define TEGRA2_SPI_BASE		(NV_PA_APB_MISC_BASE + 0xC380)
 #define NV_PA_PMC_BASE		0x7000E400
 #define NV_PA_CSITE_BASE	0x70040000
+#define TEGRA_USB1_BASE		0xC5000000
+#define TEGRA_USB3_BASE		0xC5008000
 
 #define TEGRA2_SDRC_CS0		NV_PA_SDRAM_BASE
 #define LOW_LEVEL_SRAM_STACK	0x4000FFFC

index 77e217f..a11cebb 100644
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
 COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
 COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o
 COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
+COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 
 COBJS	:= $(COBJS-y)

index 6c0a2d1..2ac8c9c 100644
@@ -57,6 +57,7 @@ struct fdt_memory {
  */
 enum fdt_compat_id {
 	COMPAT_UNKNOWN,
+	COMPAT_NVIDIA_TEGRA20_USB,	/* Tegra2 USB port */
 
 	COMPAT_COUNT,
 };

index c748cac..5f137a5 100644
@@ -37,6 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define COMPAT(id, name) name
 static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(UNKNOWN, "<none>"),
+	COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)

1.7.7.3

This adds basic USB support for port 0. The other port is not supported yet.

Tegra2 (SeaBoard) # usb start
(Re)start USB...
USB: Register 10011 NbrPorts 1
USB EHCI 1.00
scanning bus for devices... 5 USB Device(s) found
scanning bus for storage devices... 1 Storage Device(s) found
Tegra2 (SeaBoard) # ext2load usb 0:3 10000000 /boot/vmlinuz Loading file "/boot/vmlinuz" from usb device 0:3 (ROOT-A) 2932976 bytes read

---
Changes in v2:
- Add setting of pinmux for USB VBUS GPIO

Changes in v5:
- Put pinmux setting into a board-specific function

 board/nvidia/common/board.c      |   12 ++++++++++++
 board/nvidia/common/board.h      |    6 ++++++
 board/nvidia/seaboard/seaboard.c |    6 ++++++
 3 files changed, 24 insertions(+), 0 deletions(-)

index e8253a0..72d8630 100644
@@ -33,6 +33,7 @@
 #include <asm/arch/pinmux.h>
 #include <asm/arch/uart.h>
 #include <spi.h>
+#include <asm/arch/usb.h>
 #include "board.h"
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -50,6 +51,12 @@ int timer_init(void)
 	return 0;
 }
 
+void __pin_mux_usb(void)
+{
+}
+
+void pin_mux_usb(void) __attribute__((weak, alias("__pin_mux_usb")));
+
 /*
  * Routine: board_init
  * Description: Early hardware init.

@@ -69,6 +76,11 @@ int board_init(void)
 	/* boot param addr */
 	gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
 
+#ifdef CONFIG_USB_EHCI_TEGRA
+	pin_mux_usb();
+	board_usb_init(gd->fdt_blob);
+#endif
+
 	return 0;
 }
 

index a638af2..09fb158 100644
@@ -27,4 +27,10 @@
 void gpio_config_uart(void);
 void gpio_early_init_uart(void);
 
+/*
+ * Set up any pin muxing needed for USB (for now, since fdt doesn't support
+ * it). Boards can overwrite the default fucction which does nothing.
+ */
+void pin_mux_usb(void);
+
 #endif	/* BOARD_H */

index 9ab6825..94efb1e 100644
@@ -90,3 +90,9 @@ int board_mmc_init(bd_t *bd)
 	return 0;
 }
 #endif
+
+void pin_mux_usb(void)
+{
+	/* For USB's GPIO PD0. For now, since we have no pinmux in fdt */
+	pinmux_tristate_disable(PINGRP_SLXK);
+}

1.7.7.3

All Tegra2 boards should include tegra2-common. This adds the required USB config to that file.

---
Changes in v5:
- Add CONFIG_EHCI_DCACHE which is needed for dcache operation
- Drop unused CONFIG_USB_EHCI_DATA_ALIGN option

 include/configs/tegra2-common.h |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

index e6f385f..266d0e5 100644
@@ -84,6 +84,16 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
 
+/*
+ * This parameter affects a TXFILLTUNING field that controls how much data is
+ * sent to the latency fifo before it is sent to the wire. Without this
+ * parameter, the default (2) causes occasional Data Buffer Errors in OUT
+ * packets depending on the buffer address and size.
+ */
+#define CONFIG_USB_EHCI_TXFIFO_THRESH	10
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_EHCI_DCACHE
+
 /* include default commands */
 #include <config_cmd_default.h>
 

1.7.7.3

Seaboard has a top port which is USB host or device, and a side port which is host only.

---
Changes in v2:
- Remove unneeded CONFIG_TEGRA_USBx defines

 include/configs/seaboard.h |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

index 261f952..b6d9f7a 100644
@@ -72,4 +72,11 @@
 
 #define CONFIG_ENV_SECT_SIZE    CONFIG_ENV_SIZE
 #define CONFIG_ENV_OFFSET       (CONFIG_SPI_FLASH_SIZE - CONFIG_ENV_SECT_SIZE)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
 #endif /* __CONFIG_H */

1.7.7.3

Add a directory to hold device tree binding files, to permit easy review of this material in U-Boot patches.

---
Changes in v4:
- Add staging area for device tree bindings used in U-Boot

Changes in v5:
- Update README to indicate that we will commit fdt documentation to U-Boot

 doc/device-tree-bindings/README |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)
 create mode 100644 doc/device-tree-bindings/README

new file mode 100644
index 0000000..2ea3439
@@ -0,0 +1,17 @@
+Device Tree Bindings Staging Area
+=================================
+
+This directory contains device tree bindings for U-Boot.
+
+These follow along with Linux kernel bindings, with a few additions. By
+adding the files here, U-Boot patches can clearly show thees additions.
+This makes it easier for device tree people to review these additions in
+patches sent to the U-Boot mailing list.
+
+The intent IS to commit these files to U-Boot. Hopefully at some point
+the files will be stored in another repo (shared with Linux) which is
+brought in as needed. Changes here are intended to mirror changes in the
+Linux Documentation/devicetree/bindings/ directory.
+
[email protected]
+17-Jan-12

1.7.7.3

This file is taken from the Linux mailing list.

---

 doc/device-tree-bindings/usb/tegra-usb.txt |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)
 create mode 100644 doc/device-tree-bindings/usb/tegra-usb.txt

new file mode 100644
index 0000000..035d63d
@@ -0,0 +1,13 @@
+Tegra SOC USB controllers
+
+The device node for a USB controller that is part of a Tegra
+SOC is as described in the document "Open Firmware Recommended
+Practice : Universal Serial Bus" with the following modifications
+and additions :
+
+Required properties :
+ - compatible : Should be "nvidia,tegra20-ehci" for USB controllers
+   used in host mode.
+ - phy_type : Should be one of "ulpi" or "utmi".
+ - nvidia,vbus-gpio : If present, specifies a gpio that needs to be
+   activated for the bus to be powered.

1.7.7.3

We set up two USB ports, one of which can be host or device. For some reason the kernel version does enable both ports.

---
Changes in v2:
- Remove 0x from fdt aliases
- Use "okay" instead of "ok" for fdt node status

Changes in v3:
- Disable USB2 which is not used on Seaboard
- Fix device tree indenting with tabs instead of spaces
- Remove "okay" from nodes since this is the default anyway

Changes in v5:
- Remove support-host-mode property

Changes in v6:
- Remove dr_mode properties from SOC .dtsi file and move to boards

 board/nvidia/dts/tegra2-seaboard.dts |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

index 87f58fb..4fbb252 100644
@@ -11,6 +11,12 @@
 		bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
 	};
 
+	aliases {
+		/* This defines the order of our USB ports */
+		usb0 = "/usb@c5008000";
+		usb1 = "/usb@c5000000";
+	};
+
 	memory {
 		device_type = "memory";
 		reg = < 0x00000000 0x40000000 >;

@@ -42,5 +48,10 @@
 
 	usb@c5000000 {
 		nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+		dr_mode = "otg";
+	};
+
+	usb@c5004000 {
+		status = "disabled";
 	};
 };

1.7.7.3

CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the txfilltuning field in the EHCI controller on reset.

---

 README                      |    3 +++
 drivers/usb/host/ehci-hcd.c |    7 +++++++
 drivers/usb/host/ehci.h     |    6 +++++-
 3 files changed, 15 insertions(+), 1 deletions(-)

index 9d713e8..7adf7c7 100644
@@ -1135,6 +1135,9 @@ The following options need to be configured:
 				May be defined to allow interrupt polling
 				instead of using asynchronous interrupts
 
+		CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
+		txfilltuning field in the EHCI controller on reset.
+
 - USB Device:
 		Define the below if you wish to use the USB console.
 		Once firmware is rebuilt from a serial console issue the

index 3f7bc2c..d893b2a 100644
@@ -259,6 +259,13 @@ static int ehci_reset(void)
 #endif
 		ehci_writel(reg_ptr, tmp);
 	}
+
+#ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
+	cmd = ehci_readl(&hcor->or_txfilltuning);
+	cmd &= ~TXFIFO_THRESH(0x3f);
+	cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
+	ehci_writel(&hcor->or_txfilltuning, cmd);
+#endif
 out:
 	return ret;
 }

index 3d0ad0c..cc00ce4 100644
@@ -80,7 +80,11 @@ struct ehci_hcor {
 	uint32_t or_ctrldssegment;
 	uint32_t or_periodiclistbase;
 	uint32_t or_asynclistaddr;
-	uint32_t _reserved_[9];
+	uint32_t _reserved_0_;
+	uint32_t or_burstsize;
+	uint32_t or_txfilltuning;
+#define TXFIFO_THRESH(p)		((p & 0x3f) << 16)
+	uint32_t _reserved_1_[6];
 	uint32_t or_configflag;
 #define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
 	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];

1.7.7.3

A common requirement is to find the clock ID for a peripheral. This is the second cell of the 'clocks' property (the first being the phandle itself).

---
Changes in v4:
- Add fdtdec function to return peripheral ID

Changes in v6:
- Move peripheral decode function into Tegra's clock.c

 arch/arm/cpu/armv7/tegra2/clock.c        |   19 +++++++++++++++++++
 arch/arm/include/asm/arch-tegra2/clock.h |   13 +++++++++++++
 2 files changed, 32 insertions(+), 0 deletions(-)

index 11d2346..ffbfc28 100644
@@ -28,6 +28,7 @@
 #include <asm/arch/tegra2.h>
 #include <common.h>
 #include <div64.h>
+#include <fdtdec.h>
 
 /*
  * This is our record of the current clock rate of each clock. We don't

@@ -918,6 +919,24 @@ void clock_ll_start_uart(enum periph_id periph_id)
 	reset_set_enable(periph_id, 0);
 }
 
+
+int clock_decode_periph_id(const void *blob, int node)
+{
+	enum periph_id id;
+	int err, valid;
+	u32 cell[2];
+
+	err = fdtdec_get_int_array(blob, node, "clocks", cell,
+				   ARRAY_SIZE(cell));
+	if (err)
+		return -1;
+	id = cell[1];
+
+	valid = clock_periph_id_isvalid(id);
+	assert(valid);
+	return valid ? id : PERIPH_ID_NONE;
+}
+
 int clock_verify(void)
 {
 	struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);

index 080ef18..6b12c76 100644
@@ -177,6 +177,7 @@ enum periph_id {
 	PERIPH_ID_CRAM2,
 
 	PERIPH_ID_COUNT,
+	PERIPH_ID_NONE = -1,
 };
 
 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U */

@@ -355,6 +356,18 @@ unsigned clock_get_rate(enum clock_id clkid);
  */
 void clock_ll_start_uart(enum periph_id periph_id);
 
+/**
+ * Decode a peripheral ID from a device tree node.
+ *
+ * This works by looking up the peripheral's 'clocks' node and reading out
+ * the second cell, which is the clock number / peripheral ID.
+ *
+ * @param blob		FDT blob to use
+ * @param node		Node to look at
+ * @return peripheral ID, or PERIPH_ID_NONE if none
+ */
+enum periph_id clock_decode_periph_id(const void *blob, int node);
+
 /*
  * Checks that clocks are valid and prints a warning if not
  *

1.7.7.3

Hi Stephen,

Ick.

Why is 7 in there, and did you miss 76? Also U-Boot only goes up to 88 at present so should I change the first test to match?

Regards,
Simon

Simon Glass wrote at Tuesday, February 28, 2012 10:46 AM:

7 affects both the UART2 and VFIR clocks/blocks.

No, that's the undocumented "la" clock.

No, clocks 89, 90, 92, 93, and 94 are defined in the binding, which matches the CLK_OUT_ENB registers in the Tegra CAR HW (albeit not the CLK_RST registers, since there are some differences between the two).

nvpublic

Hi Stephen,

For both of your comments, since they aren't used in U-Boot, wouldn't it be more correct to flag these as errors also? We would have to update at least the clock.h header to support them.

Regards,
Simon

Simon Glass wrote at Tuesday, February 28, 2012 11:44 AM:

It's probably more correct to update the periph_id enum to define all the valid values, but either way is fine.

nvpublic

Hi Stephen,

OK - BTW what does 'LA' stand for?

Regards,
Simon

Simon Glass wrote at Tuesday, February 28, 2012 4:50 PM:

...

....

Sorry, I don't know; it's not documented. I just confirmed it exists.

nvpublic

This switches Seaboard over to use FDT for run-time config instead of CONFIG options. USB is the only user at present.

---
Changes in v3:
- Drop Tegra USB alignment patch as we will deal with this another way

Changes in v6:
- Drop fdt alignment patch as we will handle this after generic reloc

 include/configs/seaboard.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

index b6d9f7a..1dc775a 100644
@@ -27,6 +27,11 @@
 #include <asm/sizes.h>
 #include "tegra2-common.h"
 
+/* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra2-seaboard
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
 /* High-level configuration options */
 #define TEGRA2_SYSMEM		"mem=384M@0M nvmem=128M@384M mem=512M@512M"
 #define V_PROMPT		"Tegra2 (SeaBoard) # "

1.7.7.3

Aside from the issues I just pointed out, this series looks fine. I didn't review most of the patches in detail though, just those related to the DT binding.

nvpublic

Hi,

OK I have resent those three patches. Please can we fix up any other issues later and get this into U-Boot? Of course the .dts files in the kernel will change every now and then, but it is really easy to create a patch to bring U-Boot's copy up to date.

I also hit the C preprocessor problem with your binding - will need to be fixed at some point since others will hit it also. I'm tempted to move to sed, but if you don't get anywhere with your symbolic names in device tree then I won't.

Regards,
Simon

Hi Tom,

Have just sent the new i2c patches. I had to do minor updates for 3 of the 9 patches, so just sent those (as version 4).

You should already have warmboot, which is next, but let me know if there are problems with it.

Regards,
Simon