AT91 more DT bindings
Subsystems (4)
cover AT91 more DT bindings
HI,
The following patch series add the bindings for:
- PMC
- SDRAM/DDR Controller
- Reset Controller
- Shutdown Controller
The following changes since commit c5ec01650adb1976f928177cd7e71afcb82026c5:
ARM: at91: dt: enable usb ehci for sam9g45 and sam9x5 (2012-03-02 00:46:37 +0800)
are available in the git repository at:
git://github.com/at91linux/linux-at91.git ..BRANCH.NOT.VERIFIED..
Jean-Christophe PLAGNIOL-VILLARD (6):
ARM: at91/dt: add specific DT soc init
ARM: at91: add pmc DT support
ARM: at91: always enable sam9 restart
ARM: at91: add RSTC (Reset Controller) dt support
ARM: at91: add ram controller DT support
ARM: at91: add Shutdown Controller (SHDWC) DT support
.../devicetree/bindings/arm/atmel-at91.txt | 60 ++++++++ .../devicetree/bindings/arm/atmel-pmc.txt | 11 ++ arch/arm/boot/dts/at91sam9g20.dtsi | 20 +++ arch/arm/boot/dts/at91sam9g45.dtsi | 21 +++ arch/arm/boot/dts/at91sam9m10g45ek.dts | 11 ++ arch/arm/boot/dts/at91sam9x5.dtsi | 20 +++ arch/arm/boot/dts/at91sam9x5cm.dtsi | 11 ++ arch/arm/boot/dts/usb_a9g20.dts | 11 ++ arch/arm/mach-at91/Kconfig | 10 +- arch/arm/mach-at91/at91sam9x5.c | 7 - arch/arm/mach-at91/board-dt.c | 8 +- arch/arm/mach-at91/clock.c | 54 ++++++- arch/arm/mach-at91/generic.h | 2 + arch/arm/mach-at91/include/mach/at91_shdwc.h | 4 +- arch/arm/mach-at91/include/mach/at91sam9x5.h | 5 - arch/arm/mach-at91/setup.c | 158 ++++++++++++++++++++ 16 files changed, 380 insertions(+), 33 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/atmel-pmc.txt
Best Regards,
J.
PATCH 1/6 ARM: at91/dt: add specific DT soc init
This will allow to have static Device mapping and DT probe mapping for the System Controller.
Temporary keep the call to ioremap_registers() until we have the binding for the SDRAM/DDR Controller.
Temporary keep the main clock hardcoded to 12MHz until we have the binding for the PMC.
--- arch/arm/mach-at91/board-dt.c | 8 +------- arch/arm/mach-at91/generic.h | 1 + arch/arm/mach-at91/setup.c | 18 ++++++++++++++++++ 3 files changed, 20 insertions(+), 7 deletions(-)
arch/arm/mach-at91/board-dt.c +1 -7
@@ -30,12 +30,6 @@#include "generic.h" -static void __init ek_init_early (void ) -{ -/* Initialize processor: 12.000 MHz crystal */ -at91_initialize (12000000 ); -} -static const struct of_device_id irq_of_match[]__initconst = { { .compatible ="atmel,at91rm9200-aic" , .data = at91_aic_of_init },
@@ -65,7 +59,7 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")/* Maintainer: Atmel */ .timer = &at91sam926x_timer, .map_io = at91_map_io, - .init_early = ek_init_early, + .init_early = at91_dt_initialize, .init_irq = at91_dt_init_irq, .init_machine = at91_dt_device_init, .dt_compat = at91_dt_board_compat,
arch/arm/mach-at91/generic.h +1 -0
@@ -20,6 +20,7 @@ extern void __init at91_init_sram(int bank, unsigned long base,extern void __init at91rm9200_set_type (int type);extern void __init at91_initialize (unsigned long main_clock);extern void __init at91x40_initialize (unsigned long main_clock); +extern void __init at91_dt_initialize (void );/* Interrupts */ extern void __init at91_init_irq_default (void );
arch/arm/mach-at91/setup.c +18 -0
@@ -9,6 +9,7 @@#include <linux/io.h> #include <linux/mm.h> #include <linux/pm.h> +#include <linux/of_address.h> #include <asm/mach/map.h>
@@ -285,6 +286,23 @@ void __init at91_ioremap_matrix(u32 base_addr)panic ("Impossible to ioremap at91_matrix_base\n" ); } +#if defined(CONFIG_OF ) +void __init at91_dt_initialize (void ) +{ +/* temporary until have the ramc binding*/ + at91_boot_soc.ioremap_registers (); + +/* temporary until have the pmc binding */ +/* Init clock subsystem */ +at91_clock_init (12000000 ); + +/* Register the processor-specific clocks */ + at91_boot_soc.register_clocks (); + + at91_boot_soc.init (); +} +#endif +void __init at91_initialize (unsigned long main_clock) { at91_boot_soc.ioremap_registers ();
Signature · 1 line
1.7.7
PATCH 2/6 ARM: at91: add pmc DT support
In reply to Jean-Christophe PLAGNIOL-VILLARDSpecified the main Oscillator via clock binding.
This will allow to do not hardcode it anymore in the DT board at 12MHz.
--- .../devicetree/bindings/arm/atmel-pmc.txt | 11 ++++ arch/arm/boot/dts/at91sam9g20.dtsi | 5 ++ arch/arm/boot/dts/at91sam9g45.dtsi | 5 ++ arch/arm/boot/dts/at91sam9m10g45ek.dts | 11 ++++ arch/arm/boot/dts/at91sam9x5.dtsi | 5 ++ arch/arm/boot/dts/at91sam9x5cm.dtsi | 11 ++++ arch/arm/boot/dts/usb_a9g20.dts | 11 ++++ arch/arm/mach-at91/clock.c | 56 ++++++++++++++++++-- arch/arm/mach-at91/generic.h | 1 + arch/arm/mach-at91/setup.c | 3 +- 10 files changed, 112 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/atmel-pmc.txt
Documentation/devicetree/bindings/arm/atmel-pmc.txt new file +11 -0
@@ -0,0 +1,11 @@ +* Power Management Controller (PMC) + +Required properties: +- compatible: Should be "atmel,at91rm9200-pmc" +- reg: Should contain PMC registers location and length + +Examples: + pmc: pmc at fffffc00 { + compatible = "atmel,at91rm9200-pmc"; + reg = <0xfffffc00 0x100>; + };
arch/arm/boot/dts/at91sam9g20.dtsi +5 -0
@@ -59,6 +59,11 @@ reg = <0xfffff000 0x200>; }; + pmc: pmc at fffffc00 { + compatible = "atmel,at91rm9200-pmc"; + reg = <0xfffffc00 0x100>; + }; + pit: timer at fffffd30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>;
arch/arm/boot/dts/at91sam9g45.dtsi +5 -0
@@ -60,6 +60,11 @@ reg = <0xfffff000 0x200>; }; + pmc: pmc at fffffc00 { + compatible = "atmel,at91rm9200-pmc"; + reg = <0xfffffc00 0x100>; + }; + pit: timer at fffffd30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>;
arch/arm/boot/dts/at91sam9m10g45ek.dts +11 -0
@@ -21,6 +21,17 @@ reg = <0x70000000 0x4000000>; }; + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock at 0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + ahb { apb { dbgu: serial at ffffee00 {
arch/arm/boot/dts/at91sam9x5.dtsi +5 -0
@@ -58,6 +58,11 @@ reg = <0xfffff000 0x200>; }; + pmc: pmc at fffffc00 { + compatible = "atmel,at91rm9200-pmc"; + reg = <0xfffffc00 0x100>; + }; + pit: timer at fffffe30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>;
arch/arm/boot/dts/at91sam9x5cm.dtsi +11 -0
@@ -12,6 +12,17 @@ reg = <0x20000000 0x8000000>; }; + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock at 0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + ahb { nand0: nand at 40000000 { nand-bus-width = <8>;
arch/arm/boot/dts/usb_a9g20.dts +11 -0
@@ -20,6 +20,17 @@ reg = <0x20000000 0x4000000>; }; + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock at 0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + ahb { apb { dbgu: serial at fffff200 {
arch/arm/mach-at91/clock.c +51 -5
79 lines not on this page · raw message
arch/arm/mach-at91/generic.h +1 -0
@@ -53,6 +53,7 @@ extern void __init at91sam9rl_set_console_clock(int id);extern void __init at91sam9g45_set_console_clock (int id);#ifdef CONFIG_AT91_PMC_UNIT extern int __init at91_clock_init (unsigned long main_clock); +extern int __init at91_dt_clock_init (void );#else static int inline at91_clock_init (unsigned long main_clock) {return 0 ; }#endif
arch/arm/mach-at91/setup.c +1 -2
@@ -292,9 +292,8 @@ void __init at91_dt_initialize(void)/* temporary until have the ramc binding*/ at91_boot_soc.ioremap_registers (); -/* temporary until have the pmc binding */ /* Init clock subsystem */ -at91_clock_init (12000000 ); +at91_dt_clock_init ();/* Register the processor-specific clocks */ at91_boot_soc.register_clocks ();
Signature · 1 line
1.7.7
PATCH 3/6 ARM: at91: always enable sam9 restart
In reply to Jean-Christophe PLAGNIOL-VILLARDThis is need for multiple SoC in the same kernel image and DT. As we will chose the restart function via binding.
--- arch/arm/mach-at91/Kconfig | 10 ++-------- 1 files changed, 2 insertions(+), 8 deletions(-)
arch/arm/mach-at91/Kconfig +2 -8
@@ -20,9 +20,11 @@ config HAVE_AT91_USART5 config AT91_SAM9_ALT_RESET bool + default !ARCH_AT91X40 config AT91_SAM9G45_RESET bool + default !ARCH_AT91X40 menu "Atmel AT91 System-on-Chip"
@@ -45,7 +47,6 @@ config ARCH_AT91SAM9260 select HAVE_AT91_USART4 select HAVE_AT91_USART5 select HAVE_NET_MACB - select AT91_SAM9_ALT_RESET config ARCH_AT91SAM9261 bool "AT91SAM9261"
@@ -53,7 +54,6 @@ config ARCH_AT91SAM9261 select GENERIC_CLOCKEVENTS select HAVE_FB_ATMEL select HAVE_AT91_DBGU0 - select AT91_SAM9_ALT_RESET config ARCH_AT91SAM9G10 bool "AT91SAM9G10"
@@ -61,7 +61,6 @@ config ARCH_AT91SAM9G10 select GENERIC_CLOCKEVENTS select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL - select AT91_SAM9_ALT_RESET config ARCH_AT91SAM9263 bool "AT91SAM9263"
@@ -70,7 +69,6 @@ config ARCH_AT91SAM9263 select HAVE_FB_ATMEL select HAVE_NET_MACB select HAVE_AT91_DBGU1 - select AT91_SAM9_ALT_RESET config ARCH_AT91SAM9RL bool "AT91SAM9RL"
@@ -79,7 +77,6 @@ config ARCH_AT91SAM9RL select HAVE_AT91_USART3 select HAVE_FB_ATMEL select HAVE_AT91_DBGU0 - select AT91_SAM9_ALT_RESET config ARCH_AT91SAM9G20 bool "AT91SAM9G20"
@@ -90,7 +87,6 @@ config ARCH_AT91SAM9G20 select HAVE_AT91_USART4 select HAVE_AT91_USART5 select HAVE_NET_MACB - select AT91_SAM9_ALT_RESET config ARCH_AT91SAM9G45 bool "AT91SAM9G45"
@@ -100,7 +96,6 @@ config ARCH_AT91SAM9G45 select HAVE_FB_ATMEL select HAVE_NET_MACB select HAVE_AT91_DBGU1 - select AT91_SAM9G45_RESET config ARCH_AT91SAM9X5 bool "AT91SAM9x5 family"
@@ -109,7 +104,6 @@ config ARCH_AT91SAM9X5 select HAVE_FB_ATMEL select HAVE_NET_MACB select HAVE_AT91_DBGU0 - select AT91_SAM9G45_RESET config ARCH_AT91X40 bool "AT91x40"
Signature · 1 line
1.7.7
PATCH 4/6 ARM: at91: add RSTC (Reset Controller) dt support
In reply to Jean-Christophe PLAGNIOL-VILLARD--- .../devicetree/bindings/arm/atmel-at91.txt | 12 ++++++++ arch/arm/boot/dts/at91sam9g20.dtsi | 5 +++ arch/arm/boot/dts/at91sam9g45.dtsi | 5 +++ arch/arm/boot/dts/at91sam9x5.dtsi | 5 +++ arch/arm/mach-at91/at91sam9x5.c | 1 - arch/arm/mach-at91/setup.c | 30 ++++++++++++++++++++ 6 files changed, 57 insertions(+), 1 deletions(-)
Documentation/devicetree/bindings/arm/atmel-at91.txt +12 -0
@@ -30,3 +30,15 @@ One interrupt per TC channel in a TC block: reg = <0xfffdc000 0x100>; interrupts = <26 4 27 4 28 4>; }; + +RSTC Reset Controller required properties: +- compatible: Should be "atmel,<chip>-rstc". + <chip> can be "at91sam9260" or "at91sam9g45" +- reg: Should contain registers location and length + +Example: + + rstc at fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + };
arch/arm/boot/dts/at91sam9g20.dtsi +5 -0
@@ -64,6 +64,11 @@ reg = <0xfffffc00 0x100>; }; + rstc at fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + }; + pit: timer at fffffd30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>;
arch/arm/boot/dts/at91sam9g45.dtsi +5 -0
@@ -65,6 +65,11 @@ reg = <0xfffffc00 0x100>; }; + rstc at fffffd00 { + compatible = "atmel,at91sam9g45-rstc"; + reg = <0xfffffd00 0x10>; + }; + pit: timer at fffffd30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>;
arch/arm/boot/dts/at91sam9x5.dtsi +5 -0
@@ -63,6 +63,11 @@ reg = <0xfffffc00 0x100>; }; + rstc at fffffe00 { + compatible = "atmel,at91sam9g45-rstc"; + reg = <0xfffffe00 0x10>; + }; + pit: timer at fffffe30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>;
arch/arm/mach-at91/at91sam9x5.c +0 -1
@@ -309,7 +309,6 @@ static void __init at91sam9x5_ioremap_registers(void)void __init at91sam9x5_initialize (void ) { - arm_pm_restart = at91sam9g45_restart; at91_extern_irq = (1 <<AT91SAM9X5_ID_IRQ0 );/* Register GPIO subsystem (using DT) */
arch/arm/mach-at91/setup.c +30 -0
@@ -287,8 +287,38 @@ void __init at91_ioremap_matrix(u32 base_addr) }#if defined(CONFIG_OF ) +static struct of_device_id rstc_ids[] = { + { .compatible ="atmel,at91sam9260-rstc" , .data = at91sam9_alt_restart }, + { .compatible ="atmel,at91sam9g45-rstc" , .data = at91sam9g45_restart }, + {/*sentinel*/ } +}; + +static void at91_dt_rstc (void ) +{ +struct device_node *np; +const struct of_device_id *of_id; + + np =of_find_matching_node (NULL , rstc_ids); +if (!np) +panic ("unable to find compatible rstc node in dtb\n" ); + + at91_rstc_base =of_iomap (np,0 ); +if (!at91_rstc_base) +panic ("unable to map rstc cpu registers\n" ); + + of_id =of_match_node (rstc_ids, np); +if (!of_id) +panic ("AT91: rtsc no restart function availlable\n" ); + + arm_pm_restart = of_id->data; + +of_node_put (np); +} +void __init at91_dt_initialize (void ) { +at91_dt_rstc (); +/* temporary until have the ramc binding*/ at91_boot_soc.ioremap_registers ();
Signature · 1 line
1.7.7
PATCH 5/6 ARM: at91: add ram controller DT support
In reply to Jean-Christophe PLAGNIOL-VILLARDWe can now drop the call to ioremap_registers() as we have the binding for the SDRAM/DDR Controller.
Drop ioremap_registers() for sam9x5 too.
--- .../devicetree/bindings/arm/atmel-at91.txt | 19 ++++++++++++++ arch/arm/boot/dts/at91sam9g20.dtsi | 5 +++ arch/arm/boot/dts/at91sam9g45.dtsi | 6 ++++ arch/arm/boot/dts/at91sam9x5.dtsi | 5 +++ arch/arm/mach-at91/at91sam9x5.c | 6 ---- arch/arm/mach-at91/include/mach/at91sam9x5.h | 5 --- arch/arm/mach-at91/setup.c | 27 +++++++++++++++++-- 7 files changed, 59 insertions(+), 14 deletions(-)
Documentation/devicetree/bindings/arm/atmel-at91.txt +19 -0
@@ -42,3 +42,22 @@ Example: compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; }; + +RAMC SDRAM/DDR Controller required properties: +- compatible: Should be "atmel,at91sam9260-sdramc", + "atmel,at91sam9g45-ddramc", +- reg: Should contain registers location and length + For at91sam9263 and at91sam9g45 you must specify 2 entries. + +Examples: + + ramc0: ramc at ffffe800 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe800 0x200>; + }; + + ramc0: ramc at ffffe400 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe400 0x200 + 0xffffe600 0x200>; + };
arch/arm/boot/dts/at91sam9g20.dtsi +5 -0
@@ -59,6 +59,11 @@ reg = <0xfffff000 0x200>; }; + ramc0: ramc at ffffea00 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffea00 0x200>; + }; + pmc: pmc at fffffc00 { compatible = "atmel,at91rm9200-pmc"; reg = <0xfffffc00 0x100>;
arch/arm/boot/dts/at91sam9g45.dtsi +6 -0
@@ -60,6 +60,12 @@ reg = <0xfffff000 0x200>; }; + ramc0: ramc at ffffe400 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe400 0x200 + 0xffffe600 0x200>; + }; + pmc: pmc at fffffc00 { compatible = "atmel,at91rm9200-pmc"; reg = <0xfffffc00 0x100>;
arch/arm/boot/dts/at91sam9x5.dtsi +5 -0
@@ -58,6 +58,11 @@ reg = <0xfffff000 0x200>; }; + ramc0: ramc at ffffe800 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe800 0x200>; + }; + pmc: pmc at fffffc00 { compatible = "atmel,at91rm9200-pmc"; reg = <0xfffffc00 0x100>;
arch/arm/mach-at91/at91sam9x5.c +0 -6
@@ -302,11 +302,6 @@ static void __init at91sam9x5_map_io(void)at91_init_sram (0 ,AT91SAM9X5_SRAM_BASE ,AT91SAM9X5_SRAM_SIZE ); } -static void __init at91sam9x5_ioremap_registers (void ) -{ -at91_ioremap_ramc (0 ,AT91SAM9X5_BASE_DDRSDRC0 ,512 ); -} -void __init at91sam9x5_initialize (void ) { at91_extern_irq = (1 <<AT91SAM9X5_ID_IRQ0 );
@@ -359,7 +354,6 @@ static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {struct at91_init_soc __initdata at91sam9x5_soc = { .map_io = at91sam9x5_map_io, .default_irq_priority = at91sam9x5_default_irq_priority, - .ioremap_registers = at91sam9x5_ioremap_registers, .register_clocks = at91sam9x5_register_clocks, .init = at91sam9x5_initialize, };
arch/arm/mach-at91/include/mach/at91sam9x5.h +0 -5
@@ -55,11 +55,6 @@#define AT91SAM9X5_BASE_USART2 0xf8024000/* -* System Peripherals -*/ -#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800 - -/* * Base addresses for early serial code (uncompress.h) */ #define AT91_DBGU AT91_BASE_DBGU0
arch/arm/mach-at91/setup.c +24 -3
@@ -315,12 +315,33 @@ static void at91_dt_rstc(void)of_node_put (np); } +static struct of_device_id ramc_ids[] = { + { .compatible ="atmel,at91sam9260-sdramc" }, + { .compatible ="atmel,at91sam9g45-ddramc" }, + {/*sentinel*/ } +}; + +static void at91_dt_ramc (void ) +{ +struct device_node *np; + + np =of_find_matching_node (NULL , ramc_ids); +if (!np) +panic ("unable to find compatible ram conroller node in dtb\n" ); + + at91_ramc_base[0 ] =of_iomap (np,0 ); +if (!at91_ramc_base[0 ]) +panic ("unable to map ramc[0] cpu registers\n" ); +/* the controller may have 2 banks */ + at91_ramc_base[1 ] =of_iomap (np,1 ); + +of_node_put (np); +} +void __init at91_dt_initialize (void ) {at91_dt_rstc (); - -/* temporary until have the ramc binding*/ - at91_boot_soc.ioremap_registers (); +at91_dt_ramc ();/* Init clock subsystem */ at91_dt_clock_init ();
Signature · 1 line
1.7.7
PATCH 5/6 ARM: at91: add ram controller DT support
Quoted 144 lines · Jean-Christophe PLAGNIOL-VILLARD
We can now drop the call to
ioremap_registers()as we have the binding for the SDRAM/DDR Controller.Drop
ioremap_registers()for sam9x5 too.Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>Acked-by Nicolas Ferre <[email protected]>--- .../devicetree/bindings/arm/atmel-at91.txt | 19 ++++++++++++++ arch/arm/boot/dts/at91sam9g20.dtsi | 5 +++ arch/arm/boot/dts/at91sam9g45.dtsi | 6 ++++ arch/arm/boot/dts/at91sam9x5.dtsi | 5 +++ arch/arm/mach-at91/at91sam9x5.c | 6 ---- arch/arm/mach-at91/include/mach/at91sam9x5.h | 5 --- arch/arm/mach-at91/setup.c | 27 +++++++++++++++++-- 7 files changed, 59 insertions(+), 14 deletions(-)Documentation/devicetree/bindings/arm/atmel-at91.txt +19
-0@@ -42,3 +42,22 @@ Example: compatible = "atmel,at91sam9260-rstc"; reg = <0xfffffd00 0x10>; }; + +RAMC SDRAM/DDR Controller required properties: +- compatible: Should be "atmel,at91sam9260-sdramc", + "atmel,at91sam9g45-ddramc", +- reg: Should contain registers location and length + For at91sam9263 and at91sam9g45 you must specify 2 entries. + +Examples: + + ramc0: ramc at ffffe800 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe800 0x200>; + }; + + ramc0: ramc at ffffe400 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe400 0x200 + 0xffffe600 0x200>; + };arch/arm/boot/dts/at91sam9g20.dtsi +5
-0@@ -59,6 +59,11 @@ reg = <0xfffff000 0x200>; }; + ramc0: ramc at ffffea00 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffea00 0x200>; + }; + pmc: pmc at fffffc00 { compatible = "atmel,at91rm9200-pmc"; reg = <0xfffffc00 0x100>;arch/arm/boot/dts/at91sam9g45.dtsi +6
-0@@ -60,6 +60,12 @@ reg = <0xfffff000 0x200>; }; + ramc0: ramc at ffffe400 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe400 0x200 + 0xffffe600 0x200>; + }; + pmc: pmc at fffffc00 { compatible = "atmel,at91rm9200-pmc"; reg = <0xfffffc00 0x100>;arch/arm/boot/dts/at91sam9x5.dtsi +5
-0@@ -58,6 +58,11 @@ reg = <0xfffff000 0x200>; }; + ramc0: ramc at ffffe800 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe800 0x200>; + }; + pmc: pmc at fffffc00 { compatible = "atmel,at91rm9200-pmc"; reg = <0xfffffc00 0x100>;arch/arm/mach-at91/at91sam9x5.c +0
-6@@ -302,11 +302,6 @@ static void __init at91sam9x5_map_io(void)at91_init_sram (0 ,AT91SAM9X5_SRAM_BASE ,AT91SAM9X5_SRAM_SIZE ); } -static void __init at91sam9x5_ioremap_registers (void ) -{ -at91_ioremap_ramc (0 ,AT91SAM9X5_BASE_DDRSDRC0 ,512 ); -} -void __init at91sam9x5_initialize (void ) { at91_extern_irq = (1 <<AT91SAM9X5_ID_IRQ0 );@@ -359,7 +354,6 @@ static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {struct at91_init_soc __initdata at91sam9x5_soc = { .map_io = at91sam9x5_map_io, .default_irq_priority = at91sam9x5_default_irq_priority, - .ioremap_registers = at91sam9x5_ioremap_registers, .register_clocks = at91sam9x5_register_clocks, .init = at91sam9x5_initialize, };arch/arm/mach-at91/include/mach/at91sam9x5.h +0
-5@@ -55,11 +55,6 @@#define AT91SAM9X5_BASE_USART2 0xf8024000/* -* System Peripherals -*/ -#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800 - -/* * Base addresses for early serial code (uncompress.h) */ #define AT91_DBGU AT91_BASE_DBGU0arch/arm/mach-at91/setup.c +3
-0@@ -315,12 +315,33 @@ static void at91_dt_rstc(void)of_node_put (np); } +static struct of_device_id ramc_ids[] = { + { .compatible ="atmel,at91sam9260-sdramc" }, + { .compatible ="atmel,at91sam9g45-ddramc" },
arch/arm/mach-at91/setup.c static void at91_dt_rstc(void) · line 330
Quoted 10 lines
arch/arm/mach-at91/setup.c +10
-0+ {/*sentinel*/ } +}; + +static void at91_dt_ramc (void ) +{ +struct device_node *np; + + np =of_find_matching_node (NULL , ramc_ids); +if (!np) +panic ("unable to find compatible ram conroller node in dtb\n" );
You really can't boot if this fails? A WARN is better if it allows you to boot until at least your console is actually up.
Quoted 20 lines
arch/arm/mach-at91/setup.c +11
-3+ + at91_ramc_base[0 ] =of_iomap (np,0 ); +if (!at91_ramc_base[0 ]) +panic ("unable to map ramc[0] cpu registers\n" ); +/* the controller may have 2 banks */ + at91_ramc_base[1 ] =of_iomap (np,1 ); + +of_node_put (np); +} +void __init at91_dt_initialize (void ) {at91_dt_rstc (); - -/* temporary until have the ramc binding*/ - at91_boot_soc.ioremap_registers (); +at91_dt_ramc ();/* Init clock subsystem */ at91_dt_clock_init ();
PATCH 5/6 ARM: at91: add ram controller DT support
Quoted 24 lines
Quoted 24 lines
arch/arm/mach-at91/include/mach/at91sam9x5.h +0
-5@@ -55,11 +55,6 @@#define AT91SAM9X5_BASE_USART2 0xf8024000/* -* System Peripherals -*/ -#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800 - -/* * Base addresses for early serial code (uncompress.h) */ #define AT91_DBGU AT91_BASE_DBGU0arch/arm/mach-at91/setup.c +0
-0@@ -315,12 +315,33 @@ static void at91_dt_rstc(void)of_node_put (np); }
Quoted 16 lines
arch/arm/mach-at91/setup.c static void at91_dt_rstc(void) · line 330
Quoted 13 lines
arch/arm/mach-at91/setup.c +13
-0+static struct of_device_id ramc_ids[] = { + { .compatible ="atmel,at91sam9260-sdramc" }, + { .compatible ="atmel,at91sam9g45-ddramc" }, + {/*sentinel*/ } +}; + +static void at91_dt_ramc (void ) +{ +struct device_node *np; + + np =of_find_matching_node (NULL , ramc_ids); +if (!np) +panic ("unable to find compatible ram conroller node in dtb\n" );You really can't boot if this fails? A WARN is better if it allows you to boot until at least your console is actually up.
if the restart is called you will have a oops so no it's a basic mandatory device on at91
Best Regards,
J.
PATCH 5/6 ARM: at91: add ram controller DT support
Quoted 40 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 24 lines
Quoted 24 lines
arch/arm/mach-at91/include/mach/at91sam9x5.h +0
-5@@ -55,11 +55,6 @@#define AT91SAM9X5_BASE_USART2 0xf8024000/* -* System Peripherals -*/ -#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800 - -/* * Base addresses for early serial code (uncompress.h) */ #define AT91_DBGU AT91_BASE_DBGU0arch/arm/mach-at91/setup.c +0
-0@@ -315,12 +315,33 @@ static void at91_dt_rstc(void)of_node_put (np); }Quoted 16 lines
arch/arm/mach-at91/setup.c static void at91_dt_rstc(void) · line 330
Quoted 13 lines
arch/arm/mach-at91/setup.c +13
-0+static struct of_device_id ramc_ids[] = { + { .compatible ="atmel,at91sam9260-sdramc" }, + { .compatible ="atmel,at91sam9g45-ddramc" }, + {/*sentinel*/ } +}; + +static void at91_dt_ramc (void ) +{ +struct device_node *np; + + np =of_find_matching_node (NULL , ramc_ids); +if (!np) +panic ("unable to find compatible ram conroller node in dtb\n" );You really can't boot if this fails? A WARN is better if it allows you to boot until at least your console is actually up.
Quoted 3 lines
if the restart is called you will have a oops so no it's a basic mandatory device on at91
But you may never see the panic message because your console is not up. If you WARN and can continue to boot, then the user can see the problem and fix it. Otherwise you get nothing and have to go rebuild and turn on earlyprintk.
Rob
PATCH 5/6 ARM: at91: add ram controller DT support
Quoted 41 lines · Rob Herring
Quoted 40 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 40 lines
Quoted 27 lines
arch/arm/mach-at91/include/mach/at91sam9x5.h +0
-5@@ -55,11 +55,6 @@#define AT91SAM9X5_BASE_USART2 0xf8024000/* -* System Peripherals -*/ -#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800 - -/* * Base addresses for early serial code (uncompress.h) */ #define AT91_DBGU AT91_BASE_DBGU0arch/arm/mach-at91/setup.c +3
-0@@ -315,12 +315,33 @@ static void at91_dt_rstc(void)of_node_put (np); } +static struct of_device_id ramc_ids[] = { + { .compatible ="atmel,at91sam9260-sdramc" }, + { .compatible ="atmel,at91sam9g45-ddramc" },arch/arm/mach-at91/setup.c static void at91_dt_rstc(void) · line 330
Quoted 10 lines
arch/arm/mach-at91/setup.c +10
-0+ {/*sentinel*/ } +}; + +static void at91_dt_ramc (void ) +{ +struct device_node *np; + + np =of_find_matching_node (NULL , ramc_ids); +if (!np) +panic ("unable to find compatible ram conroller node in dtb\n" );You really can't boot if this fails? A WARN is better if it allows you to boot until at least your console is actually up.
Quoted 8 lines
Quoted 3 lines
if the restart is called you will have a oops so no it's a basic mandatory device on at91
But you may never see the panic message because your console is not up. If you WARN and can continue to boot, then the user can see the problem and fix it. Otherwise you get nothing and have to go rebuild and turn on earlyprintk.
yeah agreed but if the restart id use before the console is enable you will have the same issue. the ramc controller are basic device so people usally don't touch it except you add a SoC support.
so I prefer to panic
Best Regards,
J.
PATCH 5/6 ARM: at91: add ram controller DT support
Quoted 50 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 41 lines · Rob Herring
Quoted 40 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 40 lines
Quoted 27 lines
arch/arm/mach-at91/include/mach/at91sam9x5.h +0
-5@@ -55,11 +55,6 @@#define AT91SAM9X5_BASE_USART2 0xf8024000/* -* System Peripherals -*/ -#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800 - -/* * Base addresses for early serial code (uncompress.h) */ #define AT91_DBGU AT91_BASE_DBGU0arch/arm/mach-at91/setup.c +3
-0@@ -315,12 +315,33 @@ static void at91_dt_rstc(void)of_node_put (np); } +static struct of_device_id ramc_ids[] = { + { .compatible ="atmel,at91sam9260-sdramc" }, + { .compatible ="atmel,at91sam9g45-ddramc" },arch/arm/mach-at91/setup.c static void at91_dt_rstc(void) · line 330
Quoted 10 lines
arch/arm/mach-at91/setup.c +10
-0+ {/*sentinel*/ } +}; + +static void at91_dt_ramc (void ) +{ +struct device_node *np; + + np =of_find_matching_node (NULL , ramc_ids); +if (!np) +panic ("unable to find compatible ram conroller node in dtb\n" );You really can't boot if this fails? A WARN is better if it allows you to boot until at least your console is actually up.
Quoted 8 lines
Quoted 3 lines
if the restart is called you will have a oops so no it's a basic mandatory device on at91
But you may never see the panic message because your console is not up. If you WARN and can continue to boot, then the user can see the problem and fix it. Otherwise you get nothing and have to go rebuild and turn on earlyprintk.
Quoted 6 lines
yeah agreed but if the restart id use before the console is enable you will have the same issue. the ramc controller are basic device so people usally don't touch it except you add a SoC support.
so I prefer to panic
Then panic in the restart code if it doesn't have something it needs.
Rob
PATCH 5/6 ARM: at91: add ram controller DT support
Quoted 51 lines · Rob Herring
Quoted 50 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 49 lines · Rob Herring
Quoted 40 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 24 lines
Quoted 24 lines
arch/arm/mach-at91/include/mach/at91sam9x5.h +0
-5@@ -55,11 +55,6 @@#define AT91SAM9X5_BASE_USART2 0xf8024000/* -* System Peripherals -*/ -#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800 - -/* * Base addresses for early serial code (uncompress.h) */ #define AT91_DBGU AT91_BASE_DBGU0arch/arm/mach-at91/setup.c +0
-0@@ -315,12 +315,33 @@ static void at91_dt_rstc(void)of_node_put (np); }Quoted 16 lines
arch/arm/mach-at91/setup.c static void at91_dt_rstc(void) · line 330
Quoted 13 lines
arch/arm/mach-at91/setup.c +13
-0+static struct of_device_id ramc_ids[] = { + { .compatible ="atmel,at91sam9260-sdramc" }, + { .compatible ="atmel,at91sam9g45-ddramc" }, + {/*sentinel*/ } +}; + +static void at91_dt_ramc (void ) +{ +struct device_node *np; + + np =of_find_matching_node (NULL , ramc_ids); +if (!np) +panic ("unable to find compatible ram conroller node in dtb\n" );You really can't boot if this fails? A WARN is better if it allows you to boot until at least your console is actually up.
Quoted 3 lines
if the restart is called you will have a oops so no it's a basic mandatory device on at91
But you may never see the panic message because your console is not up. If you WARN and can continue to boot, then the user can see the problem and fix it. Otherwise you get nothing and have to go rebuild and turn on earlyprintk.
Quoted 8 lines
Quoted 6 lines
yeah agreed but if the restart id use before the console is enable you will have the same issue. the ramc controller are basic device so people usally don't touch it except you add a SoC support.
so I prefer to panic
Then panic in the restart code if it doesn't have something it needs.
The code is in assembly (mandatory) so difficult
The warn on other missing binding agreed but here please let go It's basic device that except the maintainer will never touch
People will just include the dtsi and if you really need to debug soc init enable earlyprintk is fine
Best Regards,
J.
PATCH 5/6 ARM: at91: add ram controller DT support
Quoted 59 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 58 lines · Rob Herring
Quoted 56 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 41 lines · Rob Herring
Quoted 40 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 40 lines
Quoted 27 lines
arch/arm/mach-at91/include/mach/at91sam9x5.h +0
-5@@ -55,11 +55,6 @@#define AT91SAM9X5_BASE_USART2 0xf8024000/* -* System Peripherals -*/ -#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800 - -/* * Base addresses for early serial code (uncompress.h) */ #define AT91_DBGU AT91_BASE_DBGU0arch/arm/mach-at91/setup.c +3
-0@@ -315,12 +315,33 @@ static void at91_dt_rstc(void)of_node_put (np); } +static struct of_device_id ramc_ids[] = { + { .compatible ="atmel,at91sam9260-sdramc" }, + { .compatible ="atmel,at91sam9g45-ddramc" },arch/arm/mach-at91/setup.c static void at91_dt_rstc(void) · line 330
Quoted 10 lines
arch/arm/mach-at91/setup.c +10
-0+ {/*sentinel*/ } +}; + +static void at91_dt_ramc (void ) +{ +struct device_node *np; + + np =of_find_matching_node (NULL , ramc_ids); +if (!np) +panic ("unable to find compatible ram conroller node in dtb\n" );You really can't boot if this fails? A WARN is better if it allows you to boot until at least your console is actually up.
Quoted 8 lines
Quoted 3 lines
if the restart is called you will have a oops so no it's a basic mandatory device on at91
But you may never see the panic message because your console is not up. If you WARN and can continue to boot, then the user can see the problem and fix it. Otherwise you get nothing and have to go rebuild and turn on earlyprintk.
yeah agreed but if the restart id use before the console is enable you will have the same issue. the ramc controller are basic device so people usally don't touch it except you add a SoC support.
so I prefer to panic
Quoted 8 lines
Quoted 1 line
Then panic in the restart code if it doesn't have something it needs.
The code is in assembly (mandatory) so difficult
The warn on other missing binding agreed but here please let go It's basic device that except the maintainer will never touch
People will just include the dtsi and if you really need to debug soc init enable earlyprintk is fine
Okay.
PATCH 6/6 ARM: at91: add Shutdown Controller (SHDWC) DT support
In reply to Jean-Christophe PLAGNIOL-VILLARDUse a string to specific the wakeup mode to make it more readable.
Add the Real-time Clock Wake-up support too for sam9g45 and sam9x5. Add AT91_SHDW_CPTWK0_MAX to specific the Max of the Wakeup Counter.
--- .../devicetree/bindings/arm/atmel-at91.txt | 29 +++++++ arch/arm/boot/dts/at91sam9g20.dtsi | 5 + arch/arm/boot/dts/at91sam9g45.dtsi | 5 + arch/arm/boot/dts/at91sam9x5.dtsi | 5 + arch/arm/mach-at91/include/mach/at91_shdwc.h | 4 +- arch/arm/mach-at91/setup.c | 89 ++++++++++++++++++++ 6 files changed, 136 insertions(+), 1 deletions(-)
Documentation/devicetree/bindings/arm/atmel-at91.txt +29 -0
@@ -61,3 +61,32 @@ Examples: reg = <0xffffe400 0x200 0xffffe600 0x200>; }; + +SHDWC Shutdown Controller + +required properties: +- compatible: Should be "atmel,<chip>-shdwc". + <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5". +- reg: Should contain registers location and length + +optional properties: +- atmel,wakeup-mode: String, operation mode of the wakeup mode. + Supported values are: "none", "high", "low", "any". +- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf). + +optional at91sam9260 properties: +- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. + +optional at91sam9rl properties: +- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. +- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. + +optional at91sam9x5 properties: +- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. + +Example: + + rstc at fffffd00 { + compatible = "atmel,at91sam9260-rstc"; + reg = <0xfffffd00 0x10>; + };
arch/arm/boot/dts/at91sam9g20.dtsi +5 -0
@@ -74,6 +74,11 @@ reg = <0xfffffd00 0x10>; }; + shdwc at fffffd10 { + compatible = "atmel,at91sam9260-shdwc"; + reg = <0xfffffd10 0x10>; + }; + pit: timer at fffffd30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>;
arch/arm/boot/dts/at91sam9g45.dtsi +5 -0
@@ -83,6 +83,11 @@ }; + shdwc at fffffd10 { + compatible = "atmel,at91sam9rl-shdwc"; + reg = <0xfffffd10 0x10>; + }; + tcb0: timer at fff7c000 { compatible = "atmel,at91rm9200-tcb"; reg = <0xfff7c000 0x100>;
arch/arm/boot/dts/at91sam9x5.dtsi +5 -0
@@ -73,6 +73,11 @@ reg = <0xfffffe00 0x10>; }; + shdwc at fffffe10 { + compatible = "atmel,at91sam9x5-shdwc"; + reg = <0xfffffe10 0x10>; + }; + pit: timer at fffffe30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>;
arch/arm/mach-at91/include/mach/at91_shdwc.h +3 -1
@@ -36,9 +36,11 @@ extern void __iomem *at91_shdwc_base;#define AT91_SHDW_WKMODE0_HIGH 1#define AT91_SHDW_WKMODE0_LOW 2#define AT91_SHDW_WKMODE0_ANYLEVEL 3 -#define AT91_SHDW_CPTWK0 (0xf << 4)/* Counter On Wake Up 0 */ +#define AT91_SHDW_CPTWK0_MAX 0xf/* Maximum Counter On Wake Up 0 */ +#define AT91_SHDW_CPTWK0 (AT91_SHDW_CPTWK0_MAX << 4)/* Counter On Wake Up 0 */ #define AT91_SHDW_CPTWK0_ (x) ((x) << 4)#define AT91_SHDW_RTTWKEN (1 << 16)/* Real Time Timer Wake-up Enable */ +#define AT91_SHDW_RTCWKEN (1 << 17)/* Real Time Clock Wake-up Enable */ #define AT91_SHDW_SR 0x08/* Shut Down Status Register */ #define AT91_SHDW_WAKEUP0 (1 << 0)/* Wake-up 0 Status */
arch/arm/mach-at91/setup.c +89 -0
99 lines not on this page · raw message
Signature · 1 line
1.7.7
PATCH 6/6 ARM: at91: add Shutdown Controller (SHDWC) DT support
Quoted 11 lines · Jean-Christophe PLAGNIOL-VILLARD
arch/arm/mach-at91/setup.c +11
-0+ } + +if (of_device_is_compatible (np,"atmel,at91sam9x5-shdwc" )) { + have_rtt = false; + have_rtc = true; + }else if (of_device_is_compatible (np,"atmel,at91sam9rl-shdwc" )) { + have_rtt = true; + have_rtc = true; + }else { + have_rtt = true; + have_rtc = false;
arch/arm/mach-at91/setup.c static void at91_dt_ramc(void) · line 422
Quoted 10 lines
arch/arm/mach-at91/setup.c +10
-0+ } + +if (have_rtc &&of_property_read_bool (np,"atmel,wakeup-rtc-timer" )) + mode |=AT91_SHDW_RTCWKEN ; + +if (have_rtt &&of_property_read_bool (np,"atmel,wakeup-rtt-timer" )) + mode |=AT91_SHDW_RTTWKEN ; + +at91_shdwc_write (AT91_SHDW_MR , wakeup_mode | mode); +
Hi Jean-Christophe,
I don't understand why you check the specific part here. Isn't it enough to check the property when you already mandate that they can only be present on devices that support the specific wakeup?
If there is a good explanation for that, maybe add a code comment why it's required.
Arnd
PATCH 6/6 ARM: at91: add Shutdown Controller (SHDWC) DT support
Quoted 25 lines · Arnd Bergmann
Quoted 11 lines · Jean-Christophe PLAGNIOL-VILLARD
arch/arm/mach-at91/setup.c +11
-0+ } + +if (of_device_is_compatible (np,"atmel,at91sam9x5-shdwc" )) { + have_rtt = false; + have_rtc = true; + }else if (of_device_is_compatible (np,"atmel,at91sam9rl-shdwc" )) { + have_rtt = true; + have_rtc = true; + }else { + have_rtt = true; + have_rtc = false;arch/arm/mach-at91/setup.c static void at91_dt_ramc(void) · line 422
Quoted 10 lines
arch/arm/mach-at91/setup.c +10
-0+ } + +if (have_rtc &&of_property_read_bool (np,"atmel,wakeup-rtc-timer" )) + mode |=AT91_SHDW_RTCWKEN ; + +if (have_rtt &&of_property_read_bool (np,"atmel,wakeup-rtt-timer" )) + mode |=AT91_SHDW_RTTWKEN ; + +at91_shdwc_write (AT91_SHDW_MR , wakeup_mode | mode); +Hi Jean-Christophe,
Quoted 6 lines
I don't understand why you check the specific part here. Isn't it enough to check the property when you already mandate that they can only be present on devices that support the specific wakeup?
If there is a good explanation for that, maybe add a code comment why it's required.
some wake update source exist on few soc and we are not supposed to set the bit otherwise
Ill put a comment.
Best Regards,
J.
PATCH 6/6 ARM: at91: add Shutdown Controller (SHDWC) DT support
Quoted 26 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 25 lines · Arnd Bergmann
Quoted 11 lines · Jean-Christophe PLAGNIOL-VILLARD
arch/arm/mach-at91/setup.c +11
-0+ } + +if (of_device_is_compatible (np,"atmel,at91sam9x5-shdwc" )) { + have_rtt = false; + have_rtc = true; + }else if (of_device_is_compatible (np,"atmel,at91sam9rl-shdwc" )) { + have_rtt = true; + have_rtc = true; + }else { + have_rtt = true; + have_rtc = false;arch/arm/mach-at91/setup.c static void at91_dt_ramc(void) · line 422
Quoted 10 lines
arch/arm/mach-at91/setup.c +10
-0+ } + +if (have_rtc &&of_property_read_bool (np,"atmel,wakeup-rtc-timer" )) + mode |=AT91_SHDW_RTCWKEN ; + +if (have_rtt &&of_property_read_bool (np,"atmel,wakeup-rtt-timer" )) + mode |=AT91_SHDW_RTTWKEN ; + +at91_shdwc_write (AT91_SHDW_MR , wakeup_mode | mode); +Hi Jean-Christophe,
Quoted 9 lines
Quoted 6 lines
I don't understand why you check the specific part here. Isn't it enough to check the property when you already mandate that they can only be present on devices that support the specific wakeup?
If there is a good explanation for that, maybe add a code comment why it's required.
some wake update source exist on few soc and we are not supposed to set the bit otherwise
I still don't understand: Doesn't the property already give the information? In general, you should try to encode these things in specific properties instead of checking the compatible property.
Arnd
PATCH 6/6 ARM: at91: add Shutdown Controller (SHDWC) DT support
Quoted 31 lines · Arnd Bergmann
Quoted 30 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 29 lines · Arnd Bergmann
Quoted 11 lines · Jean-Christophe PLAGNIOL-VILLARD
arch/arm/mach-at91/setup.c +11
-0+ } + +if (of_device_is_compatible (np,"atmel,at91sam9x5-shdwc" )) { + have_rtt = false; + have_rtc = true; + }else if (of_device_is_compatible (np,"atmel,at91sam9rl-shdwc" )) { + have_rtt = true; + have_rtc = true; + }else { + have_rtt = true; + have_rtc = false;arch/arm/mach-at91/setup.c static void at91_dt_ramc(void) · line 422
Quoted 10 lines
arch/arm/mach-at91/setup.c +10
-0+ } + +if (have_rtc &&of_property_read_bool (np,"atmel,wakeup-rtc-timer" )) + mode |=AT91_SHDW_RTCWKEN ; + +if (have_rtt &&of_property_read_bool (np,"atmel,wakeup-rtt-timer" )) + mode |=AT91_SHDW_RTTWKEN ; + +at91_shdwc_write (AT91_SHDW_MR , wakeup_mode | mode); +Hi Jean-Christophe,
I don't understand why you check the specific part here. Isn't it enough to check the property when you already mandate that they can only be present on devices that support the specific wakeup?
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
If there is a good explanation for that, maybe add a code comment why it's required.
some wake update source exist on few soc and we are not supposed to set the bit otherwise
I still don't understand: Doesn't the property already give the information?
Yes
Quoted 2 lines
In general, you should try to encode these things in specific properties instead of checking the compatible property.
But I check that no mistake is done in the DT as the source of wakeup is availlable on different version of the IP
Just more cautious
Best Regards,
J.
PATCH 6/6 ARM: at91: add Shutdown Controller (SHDWC) DT support
In reply to Arnd BergmannQuoted 33 lines · Arnd Bergmann
Quoted 32 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 31 lines · Arnd Bergmann
Quoted 11 lines · Jean-Christophe PLAGNIOL-VILLARD
arch/arm/mach-at91/setup.c +11
-0+ } + +if (of_device_is_compatible (np,"atmel,at91sam9x5-shdwc" )) { + have_rtt = false; + have_rtc = true; + }else if (of_device_is_compatible (np,"atmel,at91sam9rl-shdwc" )) { + have_rtt = true; + have_rtc = true; + }else { + have_rtt = true; + have_rtc = false;arch/arm/mach-at91/setup.c static void at91_dt_ramc(void) · line 422
Quoted 10 lines
arch/arm/mach-at91/setup.c +10
-0+ } + +if (have_rtc &&of_property_read_bool (np,"atmel,wakeup-rtc-timer" )) + mode |=AT91_SHDW_RTCWKEN ; + +if (have_rtt &&of_property_read_bool (np,"atmel,wakeup-rtt-timer" )) + mode |=AT91_SHDW_RTTWKEN ; + +at91_shdwc_write (AT91_SHDW_MR , wakeup_mode | mode); +Hi Jean-Christophe,
I don't understand why you check the specific part here. Isn't it enough to check the property when you already mandate that they can only be present on devices that support the specific wakeup?
If there is a good explanation for that, maybe add a code comment why it's required.
Quoted 8 lines
Quoted 3 lines
some wake update source exist on few soc and we are not supposed to set the bit otherwise
I still don't understand: Doesn't the property already give the information? In general, you should try to encode these things in specific properties instead of checking the compatible property.
Or vice-versa, the compatible properties distinguish things enough that the property is not needed. If it is fixed in the SOC design, then you should distinguish things with the compatible property.
Rob
Quoted 6 lines
Arnd
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH 6/6 ARM: at91: add Shutdown Controller (SHDWC) DT support
Quoted 9 lines · Rob Herring
Quoted 5 lines
I still don't understand: Doesn't the property already give the information? In general, you should try to encode these things in specific properties instead of checking the compatible property.
Or vice-versa, the compatible properties distinguish things enough that the property is not needed. If it is fixed in the SOC design, then you should distinguish things with the compatible property.
Well, one of the two, basically. I would suggest using special properties in order to be prepared when other SOCs have the same requirement. If you know for certain that each one will only ever be needed in one specific SOC, then the compatible property is enough, but if it's likely that others will have the same requirement in the future, I think it's much better to have just a single check rather than a list of SOCs.
Arnd
cover AT91 more DT bindings
In reply to Jean-Christophe PLAGNIOL-VILLARDHi,
Rob is ok for you?
Best Regards,
J.
Quoted 49 lines · Jean-Christophe PLAGNIOL-VILLARD
HI,
The following patch series add the bindings for:
- PMC
- SDRAM/DDR Controller
- Reset Controller
- Shutdown ControllerThe following changes since commit
c5ec01650adb1976f928177cd7e71afcb82026c5:ARM: at91: dt: enable usb ehci for sam9g45 and sam9x5 (2012-03-02 00:46:37 +0800)
are available in the git repository at:
git://github.com/at91linux/linux-at91.git..BRANCH.NOT.VERIFIED..Jean-Christophe PLAGNIOL-VILLARD (6):
ARM: at91/dt: add specific DT soc init
ARM: at91: add pmc DT support
ARM: at91: always enable sam9 restart
ARM: at91: add RSTC (Reset Controller) dt support
ARM: at91: add ram controller DT support
ARM: at91: add Shutdown Controller (SHDWC) DT support.../devicetree/bindings/arm/atmel-at91.txt | 60 ++++++++ .../devicetree/bindings/arm/atmel-pmc.txt | 11 ++ arch/arm/boot/dts/at91sam9g20.dtsi | 20 +++ arch/arm/boot/dts/at91sam9g45.dtsi | 21 +++ arch/arm/boot/dts/at91sam9m10g45ek.dts | 11 ++ arch/arm/boot/dts/at91sam9x5.dtsi | 20 +++ arch/arm/boot/dts/at91sam9x5cm.dtsi | 11 ++ arch/arm/boot/dts/usb_a9g20.dts | 11 ++ arch/arm/mach-at91/Kconfig | 10 +- arch/arm/mach-at91/at91sam9x5.c | 7 - arch/arm/mach-at91/board-dt.c | 8 +- arch/arm/mach-at91/clock.c | 54 ++++++- arch/arm/mach-at91/generic.h | 2 + arch/arm/mach-at91/include/mach/at91_shdwc.h | 4 +- arch/arm/mach-at91/include/mach/at91sam9x5.h | 5 - arch/arm/mach-at91/setup.c | 158 ++++++++++++++++++++ 16 files changed, 380 insertions(+), 33 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/atmel-pmc.txtBest Regards,
J._______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel