ARM: SPEAr600: Add device-tree support to SPEAr600 boards

This patch adds a generic target for SPEAr600 board that can be configured via the device-tree. Currently the following devices are supported via the devicetree:

- VIC interrupts
- PL011 UART
- PL061 GPIO
- Synopsys DW I2C
- Synopsys DW ethernet

Signed-off-by Stefan Roese <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Jean-Christophe PLAGNIOL-VILLARD <[email protected]>

Quoted 10 lines · Stefan Roese

This patch adds a generic target for SPEAr600 board that can be configured via the device-tree. Currently the following devices are supported via the devicetree:

- VIC interrupts
- PL011 UART
- PL061 GPIO
- Synopsys DW I2C
- Synopsys DW ethernet

Quoted 4 lines

Signed-off-by Stefan Roese <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Jean-Christophe PLAGNIOL-VILLARD <[email protected]>

Acked-by Viresh Kumar <[email protected]>

I have one query (as part of my learning of DT) to all DT experts:

arch/arm/boot/dts/spear600.dtsi line 139

Quoted 12 lines

arch/arm/boot/dts/spear600.dtsi new file +10 -0

+                       /* local/cpu GPIO */
+                       gpio0: gpio at f0100000 {
+                               #gpio-cells = <2>;
+                               compatible = "arm,pl061", "arm,primecell";
+                               gpio-controller;
+                               reg = <0xf0100000 0x1000>;
+                               interrupt-parent = <&vic0>;
+                               interrupts = <18>;
+                       };
+

Can we add name property here:

				name = "gpio0"

So that we don't need to do below stuff.

This patch adds a generic target for SPEAr600 board that can be configured via the device-tree. Currently the following devices are supported via the devicetree:

- VIC interrupts
- PL011 UART
- PL061 GPIO
- Synopsys DW I2C
- Synopsys DW ethernet

Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will follow in later patches.

Only the spear600-evb is currently supported. Other SPEAr600 based boards will follow later.

Since the current mainline SPEAr600 code only supports the SPEAr600 evaluation board, with nearly zero peripheral devices (only UART and GPIO), it makes sense to switch over to DT based configuration completely now. So this patch also removes all non-DT stuff, mainly platform device data. The files spear600.c and spear600_evb.c are removed completely.

Signed-off-by Stefan Roese <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Jean-Christophe PLAGNIOL-VILLARD <[email protected]>

---
v4:
- Added memory node to all dts/dtsi files
- Reorganizes bus topology in the dtsi file, to match the real SoC layout

v3:
- Removed non-DT SPEAr600 board support completely
- Removed OF_DEV_AUXDATA and changed clkdev instead, since we don't support non-DT targets any more
- Changed gmac0 -> gmac etc for single instance devices in the dts
- Added max memory size to memory node (instead of 0)
- Dropped mac-address property
- Removed some headers from spear6xx.c

v2:
- Added DT support to spear6xx.c instead of creating board-dt.c
- Removed UART (PL011) and GPIO (PL061) platform data for devicetree board port. This works now via DT probing
- Added OF_DEV_AUXDATA for clock device name matching for some device drivers
- Removed sper600.c file completely
- Added DW I2C and ethernet nodes to the dts files
- Added other DT nodes (SMI, FSMC, ECHI, OHCI), currently disabled since the corresponding device drivers don't support DT probing
- Removed Linaro/FSL copyright notice from SPEAr DT files (copy-paste cruft)
- Many smaller modification to the dts/dtsi files
- Changed Documentation/devicetree/bindings/arm/spear.txt to match the changed bindings

 Documentation/devicetree/bindings/arm/spear.txt |    8 ++
 arch/arm/boot/dts/spear600-evb.dts              |   37 +++++
 arch/arm/boot/dts/spear600.dtsi                 |  170 +++++++++++++++++++++++
 arch/arm/mach-spear6xx/Kconfig                  |    7 +-
 arch/arm/mach-spear6xx/Makefile                 |    6 -
 arch/arm/mach-spear6xx/clock.c                  |   14 +-
 arch/arm/mach-spear6xx/spear600.c               |   25 ----
 arch/arm/mach-spear6xx/spear600_evb.c           |   54 -------
 arch/arm/mach-spear6xx/spear6xx.c               |  132 +++++-------------
 9 files changed, 262 insertions(+), 191 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/spear.txt
 create mode 100644 arch/arm/boot/dts/spear600-evb.dts
 create mode 100644 arch/arm/boot/dts/spear600.dtsi
 delete mode 100644 arch/arm/mach-spear6xx/spear600.c
 delete mode 100644 arch/arm/mach-spear6xx/spear600_evb.c

Documentation/devicetree/bindings/arm/spear.txt new file +8 -0

new file mode 100644
index 0000000..f8e54f0
@@ -0,0 +1,8 @@
+ST SPEAr Platforms Device Tree Bindings
+---------------------------------------
+
+Boards with the ST SPEAr600 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear600";

arch/arm/boot/dts/spear600-evb.dts new file +23 -0

new file mode 100644
index 0000000..bf706b2
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2012 Stefan Roese <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear600.dtsi"
+
+/ {
+	model = "ST SPEAr600 Evaluation Board";
+	compatible = "st,spear600-evb", "st,spear600";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x10000000>;

arch/arm/boot/dts/spear600-evb.dts new file +4 -0

+			};
+		};
+	};
+};

arch/arm/boot/dts/spear600.dtsi new file +131 -0

new file mode 100644
index 0000000..cf14762
@@ -0,0 +1,170 @@
+/*
+ * Copyright 2012 Stefan Roese <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "st,spear600";
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x40000000>;
+	};
+
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		vic0: interrupt-controller at f1100000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1100000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		vic1: interrupt-controller at f1000000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1000000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		gmac: ethernet at e0800000 {
+			compatible = "st,spear600-gmac";
+			reg = <0xe0800000 0x8000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <24 23>;
+			interrupt-names = "macirq", "eth_wake_irq";
+		};
+
+		fsmc: flash at d1800000 {
+			status = "disabled";
+			compatible = "st,spear600-fsmc-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd1800000 0x1000	/* FSMC Register */
+			       0xd2000000 0x4000>;	/* NAND Base */
+			reg-names = "fsmc_regs", "nand_data";
+			st,ale-off = <0x20000>;
+			st,cle-off = <0x10000>;
+		};
+
+		smi: flash at fc000000 {
+			status = "disabled";
+			compatible = "st,spear600-smi";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xfc000000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <12>;
+		};
+
+		ehci at e1800000 {
+			status = "disabled";
+			compatible = "st,spear600-ehci", "usb-ehci";
+			reg = <0xe1800000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <27>;
+		};
+
+		ehci at e2000000 {
+			status = "disabled";
+			compatible = "st,spear600-ehci", "usb-ehci";
+			reg = <0xe2000000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <29>;
+		};
+
+		ohci at e1900000 {
+			status = "disabled";
+			compatible = "st,spear600-ohci", "usb-ohci";
+			reg = <0xe1900000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <26>;
+		};
+
+		ohci at e2100000 {
+			status = "disabled";
+			compatible = "st,spear600-ohci", "usb-ohci";
+			reg = <0xe2100000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <28>;
+		};
+
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges;
+
+			serial at d0000000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xd0000000 0x1000>;
+				interrupt-parent = <&vic0>;
+				interrupts = <24>;
+			};
+
+			serial at d0080000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xd0080000 0x1000>;
+				interrupt-parent = <&vic0>;
+				interrupts = <25>;
+			};
+
+			/* local/cpu GPIO */
+			gpio0: gpio at f0100000 {

arch/arm/boot/dts/spear600.dtsi new file +29 -0

+				#gpio-cells = <2>;
+				compatible = "arm,pl061", "arm,primecell";
+				gpio-controller;
+				reg = <0xfc980000 0x1000>;
+				interrupt-parent = <&vic1>;
+				interrupts = <19>;
+			};
+
+			/* appl GPIO */
+			gpio2: gpio at d8100000 {
+				#gpio-cells = <2>;
+				compatible = "arm,pl061", "arm,primecell";
+				gpio-controller;
+				reg = <0xd8100000 0x1000>;
+				interrupt-parent = <&vic1>;
+				interrupts = <4>;
+			};
+
+			i2c at d0200000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,designware-i2c";
+				reg = <0xd0200000 0x1000>;
+				interrupt-parent = <&vic0>;
+				interrupts = <28>;
+			};
+		};
+	};
+};

arch/arm/mach-spear6xx/Kconfig +4 -3

index ff4ae5b..fbe298b 100644
@@ -5,11 +5,12 @@
 if ARCH_SPEAR6XX
 
 menu "SPEAr6xx Implementations"
-config BOARD_SPEAR600_EVB
-	bool "SPEAr600 Evaluation Board"
+config BOARD_SPEAR600_DT
+	bool "SPEAr600 generic board configured via device-tree"
 	select MACH_SPEAR600
+	select USE_OF
 	help
-	  Supports ST SPEAr600 Evaluation Board
+	  Supports ST SPEAr600 boards configured via the device-tree
 
 endmenu
 

arch/arm/mach-spear6xx/Makefile +0 -6

index cc1a4d8..76e5750 100644
@@ -4,9 +4,3 @@
 
 # common files
 obj-y	+= clock.o spear6xx.o
-
-# spear600 specific files
-obj-$(CONFIG_MACH_SPEAR600) += spear600.o
-
-# spear600 boards files
-obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o

arch/arm/mach-spear6xx/clock.c +0 -0

index ac70e0d..358f280 100644

Quoted 10 lines · Stefan Roese

This patch adds a generic target for SPEAr600 board that can be configured via the device-tree. Currently the following devices are supported via the devicetree:

- VIC interrupts
- PL011 UART
- PL061 GPIO
- Synopsys DW I2C
- Synopsys DW ethernet

Quoted 2 lines

Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will follow in later patches.

so drop USB, nand & co from the dtsi

this will be add later when the binding will documentated and Acked

Quoted 16 lines · Jean-Christophe PLAGNIOL-VILLARD

Quoted 4 lines · Stefan Roese

This patch adds a generic target for SPEAr600 board that can be configured via the device-tree. Currently the following devices are supported via the devicetree:

Quoted 8 lines

- VIC interrupts
- PL011 UART
- PL061 GPIO
- Synopsys DW I2C
- Synopsys DW ethernet

Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will follow in later patches.

so drop USB, nand & co from the dtsi

Quoted 1 line

this will be add later when the binding will documentated and Acked

I actually like to see the devices in there, and it already helped figure out that there are two buses instead of just one. Maybe we can agree on putting them in the file but commenting them out using /* */ with an added notice that they will get enabled once we have bindings?

Quoted 5 lines

I actually like to see the devices in there, and it already helped figure out that there are two buses instead of just one. Maybe we can agree on putting them in the file but commenting them out using /* */ with an added notice that they will get enabled once we have bindings?

It would be great to have a decision on this. I'm leaving for a short vacation in a few hours and would like to have the new (hopefully final) patch out before that.

Quoted 6 lines · Stefan Roese

Quoted 5 lines

I actually like to see the devices in there, and it already helped figure out that there are two buses instead of just one. Maybe we can agree on putting them in the file but commenting them out using /* */ with an added notice that they will get enabled once we have bindings?

Quoted 3 lines

It would be great to have a decision on this. I'm leaving for a short vacation in a few hours and would like to have the new (hopefully final) patch out before that.

It's not a show-stopper for me either way, your patches look great.

Quoted 10 lines · Stefan Roese

This patch adds a generic target for SPEAr600 board that can be configured via the device-tree. Currently the following devices are supported via the devicetree:

- VIC interrupts
- PL011 UART
- PL061 GPIO
- Synopsys DW I2C
- Synopsys DW ethernet

Quoted 2 lines

Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will follow in later patches.

so drop USB, nand & co from the dtsi

this will be add later when the binding will documentated and Acked

Quoted 117 lines

Only the spear600-evb is currently supported. Other SPEAr600 based boards will follow later.

Since the current mainline SPEAr600 code only supports the SPEAr600 evaluation board, with nearly zero peripheral devices (only UART and GPIO), it makes sense to switch over to DT based configuration completely now. So this patch also removes all non-DT stuff, mainly platform device data. The files spear600.c and spear600_evb.c are removed completely.

Signed-off-by Stefan Roese <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Jean-Christophe PLAGNIOL-VILLARD <[email protected]>

---
v4:
- Added memory node to all dts/dtsi files
- Reorganizes bus topology in the dtsi file, to match the

real SoC layout

v3:
- Removed non-DT SPEAr600 board support completely
- Removed OF_DEV_AUXDATA and changed clkdev instead, since we

don't support non-DT targets any more

- Changed gmac0 -> gmac etc for single instance devices in the

dts

- Added max memory size to memory node (instead of 0)
- Dropped mac-address property
- Removed some headers from spear6xx.c

v2:
- Added DT support to spear6xx.c instead of creating board-dt.c
- Removed UART (PL011) and GPIO (PL061) platform data for

devicetree board port. This works now via DT probing

- Added OF_DEV_AUXDATA for clock device name matching for some

device drivers

- Removed sper600.c file completely
- Added DW I2C and ethernet nodes to the dts files
- Added other DT nodes (SMI, FSMC, ECHI, OHCI), currently disabled

since the corresponding device drivers don't support DT probing

- Removed Linaro/FSL copyright notice from SPEAr DT files (copy-paste cruft) - Many smaller modification to the dts/dtsi files
- Changed Documentation/devicetree/bindings/arm/spear.txt to match

the changed bindings

 Documentation/devicetree/bindings/arm/spear.txt |    8 ++
 arch/arm/boot/dts/spear600-evb.dts              |   37 +++++
 arch/arm/boot/dts/spear600.dtsi                 |  170
 +++++++++++++++++++++++ arch/arm/mach-spear6xx/Kconfig                 
 |    7 +-
 arch/arm/mach-spear6xx/Makefile                 |    6 -
 arch/arm/mach-spear6xx/clock.c                  |   14 +-
 arch/arm/mach-spear6xx/spear600.c               |   25 ----
 arch/arm/mach-spear6xx/spear600_evb.c           |   54 -------
 arch/arm/mach-spear6xx/spear6xx.c               |  132
 +++++------------- 9 files changed, 262 insertions(+), 191 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/spear.txt
 create mode 100644 arch/arm/boot/dts/spear600-evb.dts
 create mode 100644 arch/arm/boot/dts/spear600.dtsi
 delete mode 100644 arch/arm/mach-spear6xx/spear600.c
 delete mode 100644 arch/arm/mach-spear6xx/spear600_evb.c

(quoted diff) +0 -0

b/Documentation/devicetree/bindings/arm/spear.txt new file mode 100644 index 0000000..f8e54f0

Documentation/devicetree/bindings/arm/spear.txt new file +8 -0

@@ -0,0 +1,8 @@
+ST SPEAr Platforms Device Tree Bindings
+---------------------------------------
+
+Boards with the ST SPEAr600 SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "st,spear600";

(quoted diff) +0 -0

b/arch/arm/boot/dts/spear600-evb.dts new file mode 100644 index 0000000..bf706b2

arch/arm/boot/dts/spear600-evb.dts new file +23 -0

@@ -0,0 +1,37 @@
+/*
+ * Copyright 2012 Stefan Roese <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear600.dtsi"
+
+/ {
+	model = "ST SPEAr600 Evaluation Board";
+	compatible = "st,spear600-evb", "st,spear600";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x10000000>;

arch/arm/boot/dts/spear600-evb.dts line 33

Quoted 10 lines

arch/arm/boot/dts/spear600-evb.dts new file +10 -0

+	};
+
+	ahb {
+		gmac: ethernet at e0800000 {
+			phy-mode = "gmii";
+		};
+
+		apb {
+			i2c at d0200000 {
+				clock-frequency = <400000>;

disable everything not core is good in the dtsi
so board enable what they need and do not get surprised whe updating the dtsi

but you need to consistant

Quoted 145 lines

arch/arm/boot/dts/spear600-evb.dts new file +4 -0

+			};
+		};
+	};
+};

(quoted diff) +0 -0

b/arch/arm/boot/dts/spear600.dtsi new file mode 100644 index 0000000..cf14762

arch/arm/boot/dts/spear600.dtsi new file +135 -0

@@ -0,0 +1,170 @@
+/*
+ * Copyright 2012 Stefan Roese <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	compatible = "st,spear600";
+
+	cpus {
+		cpu at 0 {
+			compatible = "arm,arm926ejs";
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x40000000>;
+	};
+
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		vic0: interrupt-controller at f1100000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1100000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		vic1: interrupt-controller at f1000000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1000000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
+		gmac: ethernet at e0800000 {
+			compatible = "st,spear600-gmac";
+			reg = <0xe0800000 0x8000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <24 23>;
+			interrupt-names = "macirq", "eth_wake_irq";
+		};
+
+		fsmc: flash at d1800000 {
+			status = "disabled";
+			compatible = "st,spear600-fsmc-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xd1800000 0x1000	/* FSMC Register */
+			       0xd2000000 0x4000>;	/* NAND Base */
+			reg-names = "fsmc_regs", "nand_data";
+			st,ale-off = <0x20000>;
+			st,cle-off = <0x10000>;
+		};
+
+		smi: flash at fc000000 {
+			status = "disabled";
+			compatible = "st,spear600-smi";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0xfc000000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <12>;
+		};
+
+		ehci at e1800000 {
+			status = "disabled";
+			compatible = "st,spear600-ehci", "usb-ehci";
+			reg = <0xe1800000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <27>;
+		};
+
+		ehci at e2000000 {
+			status = "disabled";
+			compatible = "st,spear600-ehci", "usb-ehci";
+			reg = <0xe2000000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <29>;
+		};
+
+		ohci at e1900000 {
+			status = "disabled";
+			compatible = "st,spear600-ohci", "usb-ohci";
+			reg = <0xe1900000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <26>;
+		};
+
+		ohci at e2100000 {
+			status = "disabled";
+			compatible = "st,spear600-ohci", "usb-ohci";
+			reg = <0xe2100000 0x1000>;
+			interrupt-parent = <&vic1>;
+			interrupts = <28>;
+		};
+
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges;
+
+			serial at d0000000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xd0000000 0x1000>;
+				interrupt-parent = <&vic0>;
+				interrupts = <24>;
+			};
+
+			serial at d0080000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xd0080000 0x1000>;
+				interrupt-parent = <&vic0>;
+				interrupts = <25>;
+			};
+
+			/* local/cpu GPIO */
+			gpio0: gpio at f0100000 {
+				#gpio-cells = <2>;
+				compatible = "arm,pl061", "arm,primecell";
+				gpio-controller;
+				reg = <0xf0100000 0x1000>;

arch/arm/boot/dts/spear600.dtsi line 141

Quoted 6 lines

arch/arm/boot/dts/spear600.dtsi new file +6 -0

+				interrupt-parent = <&vic0>;
+				interrupts = <18>;
+			};
+
+			/* basic GPIO */
+			gpio1: gpio at fc980000 {

on ST SoC the gpio are usally called pio so pio0

Quoted 80 lines

arch/arm/boot/dts/spear600.dtsi new file +29 -0

+				#gpio-cells = <2>;
+				compatible = "arm,pl061", "arm,primecell";
+				gpio-controller;
+				reg = <0xfc980000 0x1000>;
+				interrupt-parent = <&vic1>;
+				interrupts = <19>;
+			};
+
+			/* appl GPIO */
+			gpio2: gpio at d8100000 {
+				#gpio-cells = <2>;
+				compatible = "arm,pl061", "arm,primecell";
+				gpio-controller;
+				reg = <0xd8100000 0x1000>;
+				interrupt-parent = <&vic1>;
+				interrupts = <4>;
+			};
+
+			i2c at d0200000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "snps,designware-i2c";
+				reg = <0xd0200000 0x1000>;
+				interrupt-parent = <&vic0>;
+				interrupts = <28>;
+			};
+		};
+	};
+};

(quoted diff) +0 -0

b/arch/arm/mach-spear6xx/Kconfig index ff4ae5b..fbe298b 100644

arch/arm/mach-spear6xx/Kconfig +3 -2

@@ -5,11 +5,12 @@
 
 if ARCH_SPEAR6XX
 
 menu "SPEAr6xx Implementations"
 
-config BOARD_SPEAR600_EVB
-	bool "SPEAr600 Evaluation Board"
+config BOARD_SPEAR600_DT
+	bool "SPEAr600 generic board configured via device-tree"
 
 	select MACH_SPEAR600
 
+	select USE_OF
 

arch/arm/mach-spear6xx/Kconfig +1 -1

 	help
 
-	  Supports ST SPEAr600 Evaluation Board
+	  Supports ST SPEAr600 boards configured via the device-tree
 
 endmenu

(quoted diff) +0 -0

b/arch/arm/mach-spear6xx/Makefile index cc1a4d8..76e5750 100644

arch/arm/mach-spear6xx/Makefile +0 -6

@@ -4,9 +4,3 @@
 
 # common files
 obj-y	+= clock.o spear6xx.o
 
-
-# spear600 specific files
-obj-$(CONFIG_MACH_SPEAR600) += spear600.o
-
-# spear600 boards files
-obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o

(quoted diff) +0 -0

b/arch/arm/mach-spear6xx/clock.c index ac70e0d..358f280 100644

arch/arm/mach-spear6xx/clock.c +0 -0

@@ -641,8 +641,8 @@ static struct clk_lookup spear_clk_lookups[] = {
 
 	{ .con_id = "gpt0_synth_clk",	.clk = &gpt0_synth_clk},
 	{ .con_id = "gpt2_synth_clk",	.clk = &gpt2_synth_clk},
 	{ .con_id = "gpt3_synth_clk",	.clk = &gpt3_synth_clk},
 

arch/arm/mach-spear6xx/clock.c static struct clk_lookup spear_clk_lookups[] = { · line 645

Quoted 4 lines

arch/arm/mach-spear6xx/clock.c +2 -2

-	{ .dev_id = "uart0",		.clk = &uart0_clk},
-	{ .dev_id = "uart1",		.clk = &uart1_clk},
+	{ .dev_id = "d0000000.serial",	.clk = &uart0_clk},
+	{ .dev_id = "d0080000.serial",	.clk = &uart1_clk},

switch to the macro CLK_.. will be good but can be done later

otherwise look good

v4:
- Added memory node to all dts/dtsi files
- Reorganizes bus topology in the dtsi file, to match the real SoC layout

arch/arm/boot/dts/spear600.dtsi new file +20 -0

+
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		vic0: interrupt-controller at f1100000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1100000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
...
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges;
+

Quoted 5 lines · Stefan Roese

v4:
- Added memory node to all dts/dtsi files
- Reorganizes bus topology in the dtsi file, to match the

real SoC layout

Looks good.

Quoted 27 lines

arch/arm/boot/dts/spear600.dtsi new file +26 -0

+
+	ahb {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		vic0: interrupt-controller at f1100000 {
+			compatible = "arm,pl190-vic";
+			interrupt-controller;
+			reg = <0xf1100000 0x1000>;
+			#interrupt-cells = <1>;
+		};
+
...
+		apb {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges;
+
+			serial at d0000000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xd0000000 0x1000>;
+				interrupt-parent = <&vic0>;
+				interrupts = <24>;
+			};

arch/arm/boot/dts/spear600-evb.dts line 34

Quoted 4 lines

...

arch/arm/boot/dts/spear600-evb.dts new file +3 -0

+		};
+	};
+};

I would prefer to see non-empty ranges properties here. I expected the buses to be contiguous address ranges per bus, but apparently that is not the case -- you have 0xd... and 0xf... on both of them.

The simplest ranges property would be to have in the ahb node:

	ranges = <0xd0000000 0xd0000000 0x30000000>;

Which just means that the bus is limited to those addresses (if that is indeed the case -- I don't know much about ahb and apb).