Config.in.arch: add help and less cryptic names to architecture menu
PATCH 1/1 Config.in.arch: add help and less cryptic names to architecture menu
From: "Alvaro G. M" <[email protected]>
---
This is my penitence for the extra quote on Microblaze. I am not quite sure the help texts are good enough, but couldn't think of anything better.
--- target/Config.in.arch | 95 ++++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 83 insertions(+), 12 deletions(-)
target/Config.in.arch +83 -12
@@ -8,40 +8,111 @@ choice Select the target architecture family to build for. config BR2_arm - bool "arm" + bool "ARM (little endian)" + help + ARM is a 32-bit reduced instruction set computer (RISC) instruction + set architecture (ISA) developed by ARM Holdings. Little endian. + http://www.arm.com/ + http://en.wikipedia.org/wiki/ARM config BR2_armeb - bool "armeb" + bool "ARM (big endian)" + help + ARM is a 32-bit reduced instruction set computer (RISC) instruction + set architecture (ISA) developed by ARM Holdings. Big endian. + http://www.arm.com/ + http://en.wikipedia.org/wiki/ARM config BR2_avr32 - bool "avr32" + bool "AVR32" select BR2_SOFT_FLOAT + help + The AVR32 is a 32-bit RISC microprocessor architecture designed by + Atmel. + http://www.atmel.com/ + http://en.wikipedia.org/wiki/Avr32 config BR2_bfin - bool "bfin" + bool "Blackfin" + help + The Blackfin is a family of 16 or 32-bit microprocessors developed, + manufactured and marketed by Analog Devices. + http://www.analog.com/ + http://en.wikipedia.org/wiki/Blackfin config BR2_i386 bool "i386" + help + Intel i386 architecture compatible microprocessor + http://en.wikipedia.org/wiki/I386 config BR2_m68k bool "m68k" depends on BROKEN # ice in uclibc / inet_ntoa_r + help + Motorola 68000 family microprocessor + http://en.wikipedia.org/wiki/M68k config BR2_microblazeel - bool "Microblaze AXI (little-endian)" + bool "Microblaze AXI (little endian)" + help + Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus + based architecture (little endian) + http://www.xilinx.com + http://en.wikipedia.org/wiki/Microblaze config BR2_microblazebe bool "Microblaze non-AXI (big-endian)" + help + Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus + based architecture (non-AXI, big endian) + http://www.xilinx.com + http://en.wikipedia.org/wiki/Microblaze config BR2_mips - bool "mips" + bool "MIPS (big endian)" + help + MIPS is a RISC microprocessor from MIPS Technologies. Big endian. + http://www.mips.com/ + http://en.wikipedia.org/wiki/MIPS_Technologies config BR2_mipsel - bool "mipsel" + bool "MIPS (little endian)" + help + MIPS is a RISC microprocessor from MIPS Technologies. Little endian. + http://www.mips.com/ + http://en.wikipedia.org/wiki/MIPS_Technologies config BR2_powerpc - bool "powerpc" + bool "PowerPC" + help + PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance. + http://www.power.org/ + http://en.wikipedia.org/wiki/Powerpc config BR2_sh - bool "superh" + bool "SuperH" + help + SuperH (or SH) is a 32-bit reduced instruction set computer (RISC) + instruction set architecture (ISA) developed by Hitachi. + http://www.hitachi.com/ + http://en.wikipedia.org/wiki/SuperH config BR2_sh64 - bool "superh64" + bool "SuperH64" + help + SuperH64 (or SH) is a 64-bit reduced instruction set computer (RISC) + instruction set architecture (ISA) developed by Hitachi. + http://www.hitachi.com/ + http://en.wikipedia.org/wiki/SuperH config BR2_sparc - bool "sparc" + bool "SPARC" + help + SPARC (from Scalable Processor Architecture) is a RISC instruction + set architecture (ISA) developed by Sun Microsystems. + http://www.oracle.com/sun + http://en.wikipedia.org/wiki/Sparc config BR2_x86_64 bool "x86_64" select BR2_ARCH_IS_64 + help + x86-64 is an extension of the x86 instruction set (Intel i386 + architecture compatible microprocessor). + http://en.wikipedia.org/wiki/X86_64 config BR2_xtensa - bool "xtensa" + bool "Xtensa" + help + Xtensa is a Tensilica processor IP architecture. + http://en.wikipedia.org/wiki/Xtensa + http://www.tensilica.com/ endchoice config BR2_microblaze
Signature · 1 line
1.7.9.1
PATCH 1/1 Config.in.arch: add help and less cryptic names to architecture menu
Quoted 4 lines · On Monday 19 March 2012 00:13:01 Alvaro G. M wrote:
From: "Alvaro G. M" <[email protected]>
Signed-off-by Alvaro G. M <[email protected]>
Except for the small issues mentioned below:
Quoted 2 lines
---
This is my penitence for the extra quote on Microblaze.
Good work! Feel free to add extra quotes all over the place if this
is your penitence :-)
Quoted 2 lines
I am not quite
sure the help texts are good enough, but couldn't think of anything better.
Good enough for me, for sure. The links to wikipedia are really a
good idea.
Quoted 9 lines
--- target/Config.in.arch | 95 ++++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 83 insertions(+), 12 deletions(-)target/Config.in.arch +0
-0
target/Config.in.arch choice · line 14
Quoted 8 lines
target/Config.in.arch +4
-1@@ -8,40 +8,111 @@ choice Select the target architecture family to build for. config BR2_arm - bool "arm" + bool "ARM (little endian)" + help + ARM is a 32-bit reduced instruction set computer (RISC) instruction + set architecture (ISA) developed by ARM Holdings. Little endian.
Whitespace error: spaces instead of tab.
target/Config.in.arch choice · line 17
Quoted 3 lines
target/Config.in.arch +2
-0+ http://www.arm.com/ + http://en.wikipedia.org/wiki/ARM config BR2_armeb
There should be an empty line between the help text and the next
config, otherwise it doesn't look good in xconfig.
target/Config.in.arch choice · line 21
Quoted 5 lines
target/Config.in.arch +4
-1- bool "armeb" + bool "ARM (big endian)" + help + ARM is a 32-bit reduced instruction set computer (RISC) instruction + set architecture (ISA) developed by ARM Holdings. Big endian.
Whitespace error: spaces instead of tab.
target/Config.in.arch choice · line 23
Quoted 2 lines
target/Config.in.arch +2
-0+ http://www.arm.com/ + http://en.wikipedia.org/wiki/ARM
[snip]
Regards,
Arnout
Signature · 9 lines
Arnout Vandecappelle arnout at mind be Senior Embedded Software Architect +32-16-286540 Essensium/Mind http://www.mind.be G.Geenslaan 9, 3001 Leuven, Belgium BE 872 984 063 RPR Leuven LinkedIn profile: http://www.linkedin.com/in/arnoutvandecappelle GPG fingerprint: 7CB5 E4CC 6C2E EFD4 6E3D A754 F963 ECAB 2450 2F1F -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.busybox.net/pipermail/buildroot/attachments/20120319/874f79b7/attachment-0001.html>
PATCH 1/1 Config.in.arch: add help and less cryptic names to architecture menu
In reply to Alvaro G. MFrom: "Alvaro G. M" <[email protected]>
---
My editor previously tricked me with the tabs. This solves that and adds newline after help. It's also prettier on menuconfig.
--- target/Config.in.arch | 110 +++++++++++++++++++++++++++++++++++++++++++----- 1 files changed, 98 insertions(+), 12 deletions(-)
target/Config.in.arch +98 -12
@@ -8,40 +8,126 @@ choice Select the target architecture family to build for. config BR2_arm - bool "arm" + bool "ARM (little endian)" + help + ARM is a 32-bit reduced instruction set computer (RISC) instruction + set architecture (ISA) developed by ARM Holdings. Little endian. + http://www.arm.com/ + http://en.wikipedia.org/wiki/ARM + config BR2_armeb - bool "armeb" + bool "ARM (big endian)" + help + ARM is a 32-bit reduced instruction set computer (RISC) instruction + set architecture (ISA) developed by ARM Holdings. Big endian. + http://www.arm.com/ + http://en.wikipedia.org/wiki/ARM + config BR2_avr32 - bool "avr32" + bool "AVR32" select BR2_SOFT_FLOAT + help + The AVR32 is a 32-bit RISC microprocessor architecture designed by + Atmel. + http://www.atmel.com/ + http://en.wikipedia.org/wiki/Avr32 + config BR2_bfin - bool "bfin" + bool "Blackfin" + help + The Blackfin is a family of 16 or 32-bit microprocessors developed, + manufactured and marketed by Analog Devices. + http://www.analog.com/ + http://en.wikipedia.org/wiki/Blackfin + config BR2_i386 bool "i386" + help + Intel i386 architecture compatible microprocessor + http://en.wikipedia.org/wiki/I386 + config BR2_m68k bool "m68k" depends on BROKEN # ice in uclibc / inet_ntoa_r + help + Motorola 68000 family microprocessor + http://en.wikipedia.org/wiki/M68k + config BR2_microblazeel - bool "Microblaze AXI (little-endian)" + bool "Microblaze AXI (little endian)" + help + Soft processor core designed for Xilinx FPGAs from Xilinx. AXI bus + based architecture (little endian) + http://www.xilinx.com + http://en.wikipedia.org/wiki/Microblaze + config BR2_microblazebe bool "Microblaze non-AXI (big-endian)" + help + Soft processor core designed for Xilinx FPGAs from Xilinx. PLB bus + based architecture (non-AXI, big endian) + http://www.xilinx.com + http://en.wikipedia.org/wiki/Microblaze + config BR2_mips - bool "mips" + bool "MIPS (big endian)" + help + MIPS is a RISC microprocessor from MIPS Technologies. Big endian. + http://www.mips.com/ + http://en.wikipedia.org/wiki/MIPS_Technologies + config BR2_mipsel - bool "mipsel" + bool "MIPS (little endian)" + help + MIPS is a RISC microprocessor from MIPS Technologies. Little endian. + http://www.mips.com/ + http://en.wikipedia.org/wiki/MIPS_Technologies + config BR2_powerpc - bool "powerpc" + bool "PowerPC" + help + PowerPC is a RISC architecture created by Apple-IBM-Motorola alliance. + http://www.power.org/ + http://en.wikipedia.org/wiki/Powerpc + config BR2_sh - bool "superh" + bool "SuperH" + help + SuperH (or SH) is a 32-bit reduced instruction set computer (RISC) + instruction set architecture (ISA) developed by Hitachi. + http://www.hitachi.com/ + http://en.wikipedia.org/wiki/SuperH + config BR2_sh64 - bool "superh64" + bool "SuperH64" + help + SuperH64 (or SH) is a 64-bit reduced instruction set computer (RISC) + instruction set architecture (ISA) developed by Hitachi. + http://www.hitachi.com/ + http://en.wikipedia.org/wiki/SuperH + config BR2_sparc - bool "sparc" + bool "SPARC" + help + SPARC (from Scalable Processor Architecture) is a RISC instruction + set architecture (ISA) developed by Sun Microsystems. + http://www.oracle.com/sun + http://en.wikipedia.org/wiki/Sparc + config BR2_x86_64 bool "x86_64" select BR2_ARCH_IS_64 + help + x86-64 is an extension of the x86 instruction set (Intel i386 + architecture compatible microprocessor). + http://en.wikipedia.org/wiki/X86_64 + config BR2_xtensa - bool "xtensa" + bool "Xtensa" + help + Xtensa is a Tensilica processor IP architecture. + http://en.wikipedia.org/wiki/Xtensa + http://www.tensilica.com/ endchoice config BR2_microblaze
Signature · 1 line
1.7.9.1
PATCH 1/1 Config.in.arch: add help and less cryptic names to architecture menu
Quoted 1 line · On Monday 19 March 2012 22:56:06 Alvaro G. M wrote:
Signed-off-by Alvaro G. M <[email protected]>
Signature · 6 lines
Arnout Vandecappelle arnout at mind be Senior Embedded Software Architect +32-16-286540 Essensium/Mind http://www.mind.be G.Geenslaan 9, 3001 Leuven, Belgium BE 872 984 063 RPR Leuven LinkedIn profile: http://www.linkedin.com/in/arnoutvandecappelle GPG fingerprint: 7CB5 E4CC 6C2E EFD4 6E3D A754 F963 ECAB 2450 2F1F
PATCH 1/1 Config.in.arch: add help and less cryptic names to architecture menu
In reply to Alvaro G. MLe Mon, 19 Mar 2012 22:56:06 +0100,
"Alvaro G. M" <[email protected]> a ?crit :
Quoted 3 lines
From: "Alvaro G. M" <[email protected]>
Signed-off-by Alvaro G. M <[email protected]>
Thanks!
One minor nitpick, below.
target/Config.in.arch choice · line 57
Quoted 4 lines
target/Config.in.arch +3
-1+ bool "ARM (little endian)" + bool "ARM (big endian)" - bool "Microblaze AXI (little-endian)" + bool "Microblaze AXI (little endian)"
but:
Quoted 1 line
bool "Microblaze non-AXI (big-endian)"
So I guess you want to change this one to "big endian". Probably not needed to send a new version just for this, I guess Peter can fix this up will committing.
Thomas
Signature · 4 lines
Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com
PATCH 1/1 Config.in.arch: add help and less cryptic names to architecture menu
Yep, I missed that.This little things are worst!
2012/3/20 Thomas Petazzoni <[email protected]>
Quoted 34 lines
Le Mon, 19 Mar 2012 22:56:06 +0100,
"Alvaro G. M" <[email protected]> a ?crit :Quoted 3 lines
From: "Alvaro G. M" <[email protected]>
Signed-off-by Alvaro G. M <[email protected]>Thanks!
One minor nitpick, below.
target/Config.in.arch choice · line 57
Quoted 4 lines
target/Config.in.arch +3
-1+ bool "ARM (little endian)" + bool "ARM (big endian)" - bool "Microblaze AXI (little-endian)" + bool "Microblaze AXI (little endian)"but:
Quoted 1 line
bool "Microblaze non-AXI (big-endian)"
So I guess you want to change this one to "big endian". Probably not needed to send a new version just for this, I guess Peter can fix this up will committing.
Thomas
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
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Signature · 4 lines
?lvaro G?mez Machado -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.busybox.net/pipermail/buildroot/attachments/20120320/d4e46065/attachment.html>
PATCH 1/1 Config.in.arch: add help and less cryptic names to architecture menu
In reply to Alvaro G. MQuoted 1 line
Quoted 1 line
Quoted 1 line
Quoted 1 line
Quoted 1 line
"Alvaro" == Alvaro G M <[email protected]> writes:
Alvaro> From: "Alvaro G. M" <[email protected]>
Committed, thanks.
Signature · 1 line
Bye, Peter Korsgaard