Various patches - debug help, xend fixes and S3 resume fixes (v1).

linux-xencommons: Load xen-acpi-processor

Quoted 1 line

Quoted 1 line · Konrad Rzeszutek Wilk

# HG changeset patch
# User Konrad Rzeszutek Wilk <[email protected]>
# Date 1332608052 14400
# Node ID d097c3ba42f601af65b53a0c84973855aab64aa9
# Parent 708bf485e5d4baaf1c6272bd4fb1895a3c355d3e
xen/vga: Add 'vga_delay' parameter to delay screen output by 2 second per screen output.

This is useful if you find yourself on machine that has no serial console, nor any PCI, PCIe to put in a serial card. Nothing really fancy except it allows
to capture the screenshot of the screen using a camera.

Signed-off-by Konrad Rzeszutek Wilk <[email protected]>

diff -r 708bf485e5d4 -r d097c3ba42f6 xen/drivers/video/vga.c

xen/drivers/video/vga.c +3 -1

@@ -10,7 +10,7 @@
 #include <xen/mm.h>
 #include <xen/vga.h>
 #include <asm/io.h>
-
+#include <xen/delay.h>
 /* Filled in by arch boot code. */
 struct xen_vga_console_info vga_console_info;
 

@@ -49,6 +49,8 @@ void (*vga_puts)(const char *) = vga_noo
 static char __initdata opt_vga[30] = "";
 string_param("vga", opt_vga);
 
+static bool_t __read_mostly vga_delay;
+boolean_param("vga_delay", vga_delay);
 /* VGA text-mode definitions. */
 static unsigned int columns, lines;
 #define ATTRIBUTE   7

xen/drivers/video/vga.c +1 -0

+
         if ( (c == '\n') || (xpos >= columns) )
         {
             if ( ++ypos >= lines )

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xen/vga: Add 'vga_delay' parameter to delay screen output by 2 second per screen output.

Quoted 1 line

Quoted 1 line · Konrad Rzeszutek Wilk

# HG changeset patch
# User Simon Graham <[email protected]> # Date 1332610898 14400
# Node ID 75798a472b1a9121adda166b6fd05ba8473a44f0 # Parent d097c3ba42f601af65b53a0c84973855aab64aa9 xen/pat: After suspend re-write PAT if BIOS changed it.

Certain AMD machines (this was a MSI or GigaBYTE BIOS) after resume would reset the PAT MSR causing rather weird issues - where the pages would (say they would be set to WC) would end up with the wrong type (as they would use the BIOS PAT instead of the one set by the hypervisor).

Signed-off-by Simon Graham <[email protected]>

Signed-off-by Konrad Rzeszutek Wilk <[email protected]>

diff -r d097c3ba42f6 -r 75798a472b1a xen/arch/x86/acpi/power.c

xen/arch/x86/acpi/power.c +4 -0

@@ -41,8 +41,25 @@ static DEFINE_SPINLOCK(pm_lock);
 
 struct acpi_sleep_info acpi_sinfo;
 
+static void pat_resume(void);
 void do_suspend_lowlevel(void);
 
+static void
+pat_resume()
+{

xen/arch/x86/acpi/power.c +4 -0

+    }
+}
+
 static int device_power_down(void)
 {
     console_suspend();

@@ -194,6 +211,7 @@ static int enter_state(u32 state)
     if ( cpu_has_efer )
         write_efer(read_efer());
 
+    pat_resume();
     device_power_up();
 
     mcheck_init(&boot_cpu_data, 0);

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Quoted 8 lines

Quoted 1 line

Quoted 1 line · Konrad Rzeszutek Wilk

# HG changeset patch
# User Simon Graham <[email protected]> # Date 1332610898 14400
# Node ID 75798a472b1a9121adda166b6fd05ba8473a44f0 # Parent d097c3ba42f601af65b53a0c84973855aab64aa9 xen/pat: After suspend re-write PAT if BIOS changed it.

Quoted 5 lines

Certain AMD machines (this was a MSI or GigaBYTE BIOS) after resume would reset the PAT MSR causing rather weird issues - where the pages would (say they would be set to WC) would end up with the wrong type (as they would use the BIOS PAT instead of the one set by the hypervisor).

There's a write of the PAT MSR already at the end of restore_rest_processor_state() - are you saying this doesn't do what is needed? Also note that this is properly gated by a check of cpu_has_pat (other than the patch here does).

Quoted 23 lines

Signed-off-by Simon Graham <[email protected]>

Signed-off-by Konrad Rzeszutek Wilk <[email protected]>

diff -r d097c3ba42f6 -r 75798a472b1a xen/arch/x86/acpi/power.c

xen/arch/x86/acpi/power.c +10 -0

@@ -41,8 +41,25 @@ static DEFINE_SPINLOCK(pm_lock);
 
 struct acpi_sleep_info acpi_sinfo;
 
+static void pat_resume(void);
 void do_suspend_lowlevel(void);
 
+static void
+pat_resume()
+{
+    u64 pat;
+
+    rdmsrl(MSR_IA32_CR_PAT, pat);
+    if (pat != host_pat) {
+	printk(KERN_INFO PREFIX "Found PAT MSR: 0x%lx\n", pat);
+	printk(KERN_INFO PREFIX "reseting to 0x%lx\n", host_pat);

xen/arch/x86/acpi/power.c static DEFINE_SPINLOCK(pm_lock); · line 59

Quoted 4 lines

xen/arch/x86/acpi/power.c +4 -0

+	wrmsrl(MSR_IA32_CR_PAT, host_pat);
+	rdmsrl(MSR_IA32_CR_PAT, pat);
+	if (pat != host_pat)
+	    printk(KERN_WARNING PREFIX "PAT MSR stuck on: 0x%lx\n", pat);

All the %lx format specifiers here would break the 32-bit build afaict. Further (if this code really is needed at all), please use %# instead of 0x%.

Quoted 14 lines · Jan Beulich

Quoted 13 lines

Quoted 1 line

Quoted 1 line · Konrad Rzeszutek Wilk

# HG changeset patch
# User Simon Graham <[email protected]> # Date 1332610898 14400
# Node ID 75798a472b1a9121adda166b6fd05ba8473a44f0 # Parent d097c3ba42f601af65b53a0c84973855aab64aa9 xen/pat: After suspend re-write PAT if BIOS changed it.

Certain AMD machines (this was a MSI or GigaBYTE BIOS) after resume would reset the PAT MSR causing rather weird issues - where the pages would (say they would be set to WC) would end up with the wrong type (as they would use the BIOS PAT instead of the one set by the hypervisor).

Quoted 4 lines

There's a write of the PAT MSR already at the end of restore_rest_processor_state() - are you saying this doesn't do what is needed? Also note that this is properly gated by a check of cpu_has_pat (other than the patch here does).

Let me double-check with folks at VirtualComputer - but they had experienced this with Xen 4.0 (I think) and the c/s 19167 certainly was in there.

xend: Don't crash due to weird PCI devices

# HG changeset patch
# User Konrad Rzeszutek Wilk <[email protected]>
# Date 1332610898 14400
# Node ID 95eda76084314aa8a5cfd4b5e83969823492deda
# Parent d42921da3931026ecf5da7c0e5bb86074e77cf71
xend/xc: Implement a domain_set_e820_hole function to be used by python code

Signed-off-by Konrad Rzeszutek Wilk <[email protected]>

diff -r d42921da3931 -r 95eda7608431 tools/python/xen/lowlevel/xc/xc.c

tools/python/xen/lowlevel/xc/xc.c +1 -0

@@ -16,6 +16,7 @@
 #include <sys/mman.h>
 #include <netdb.h>
 #include <arpa/inet.h>
+#include <stdio.h>
 
 #include "xenctrl.h"
 #include <xen/elfnote.h>

tools/python/xen/lowlevel/xc/xc.c +8 -0

+static const char *e820_names(int type)
+{
+    switch (type) {
+        case E820_RAM: return "RAM";
+        case E820_RESERVED: return "Reserved";
+        case E820_ACPI: return "ACPI";
+        case E820_NVS: return "ACPI NVS";
+        case E820_UNUSABLE: return "Unusable";

tools/python/xen/lowlevel/xc/xc.c +39 -0

+}
+
+static PyObject *pyxc_domain_set_e820_hole(XcObject *self, PyObject *args)
+{
+    uint32_t dom, nr;
+    unsigned int target_kb;
+    unsigned int balloon_kb;
+    int rc;
+    struct e820entry map[E820MAX];
+
+    if ( !PyArg_ParseTuple(args, "iii", &dom, &target_kb, &balloon_kb) )
+        return NULL;
+
+    rc = xc_get_machine_memory_map(self->xc_handle, map, E820MAX);
+	if (rc < 0)
+        return pyxc_error_to_exception(self->xc_handle);
+
+	nr = rc;
+	rc = e820_sanitize(map, &nr, target_kb, balloon_kb);
+	if (rc)
+        return pyxc_error_to_exception(self->xc_handle);
+
+	rc = xc_domain_set_memory_map(self->xc_handle, dom, map, nr);
+	if (rc < 0)
+        return pyxc_error_to_exception(self->xc_handle);
+
+    Py_INCREF(zero);
+    return zero;
+}
+
 static PyObject *pyxc_domain_ioport_permission(XcObject *self,
                                                PyObject *args,
                                                PyObject *kwds)

@@ -2701,6 +2939,15 @@ static PyMethodDef pyxc_methods[] = {
       " map_limitkb [int]: .\n"
       "Returns: [int] 0 on success; -1 on error.\n" },
 
+    { "domain_set_e820_hole", 
+      (PyCFunction)pyxc_domain_set_e820_hole, 
+      METH_VARARGS, "\n"
+      "Set a domain's E820 memory map\n"
+      " dom [int]: Identifier of domain.\n"
+      " target_memkb [int]: .\n"
+      " balloon_kb [int]: .\n"
+      "Returns: [int] 0 on success; -1 on error.\n" },
+
 #ifdef __ia64__
     { "nvram_init",
       (PyCFunction)pyxc_nvram_init,

Quoted 24 lines · Konrad Rzeszutek Wilk

# HG changeset patch
# User Konrad Rzeszutek Wilk <[email protected]>
# Date 1332610898 14400
# Node ID 95eda76084314aa8a5cfd4b5e83969823492deda
# Parent d42921da3931026ecf5da7c0e5bb86074e77cf71
xend/xc: Implement a domain_set_e820_hole function to be used by python code

Signed-off-by Konrad Rzeszutek Wilk <[email protected]>

diff -r d42921da3931 -r 95eda7608431 tools/python/xen/lowlevel/xc/xc.c

tools/python/xen/lowlevel/xc/xc.c +1 -0

@@ -16,6 +16,7 @@
 #include <sys/mman.h>
 #include <netdb.h>
 #include <arpa/inet.h>
+#include <stdio.h>
 
 #include "xenctrl.h"
 #include <xen/elfnote.h>

@@ -1697,6 +1698,243 @@ static PyObject *pyxc_domain_set_memmap_
     return zero;
 }
 

tools/python/xen/lowlevel/xc/xc.c static PyObject *pyxc_domain_set_memmap_ · line 1701

Quoted 1 line

tools/python/xen/lowlevel/xc/xc.c +1 -0

+#ifdef PRIu64

This is a really weird condition -- when / where does this end up not defined?

Perhaps you see this depending on platform? In which case is this just a case of including the right header (stdint.h?) directly instead of implicitly via some arch dependent chain of includes?

Quoted 14 lines

tools/python/xen/lowlevel/xc/xc.c +13 -0

+static const char *e820_names(int type)
+{
+    switch (type) {
+        case E820_RAM: return "RAM";
+        case E820_RESERVED: return "Reserved";
+        case E820_ACPI: return "ACPI";
+        case E820_NVS: return "ACPI NVS";
+        case E820_UNUSABLE: return "Unusable";
+        default: break;
+    }
+    return "Unknown";
+}
+#endif

tools/python/xen/lowlevel/xc/xc.c static PyObject *pyxc_domain_set_memmap_ · line 1719

Quoted 5 lines

tools/python/xen/lowlevel/xc/xc.c +5 -0

+static int e820_sanitize(struct e820entry src[],
+                         uint32_t *nr_entries,
+                         unsigned long map_limitkb,
+                         unsigned long balloon_kb)
+{

Seems odd to do this in the C bindings, can this be done either in the python layer or in the libxc layer (in which case libxl can use it too?)

Quoted 14 lines · Ian Campbell

Quoted 14 lines

tools/python/xen/lowlevel/xc/xc.c +13 -0

+static const char *e820_names(int type)
+{
+    switch (type) {
+        case E820_RAM: return "RAM";
+        case E820_RESERVED: return "Reserved";
+        case E820_ACPI: return "ACPI";
+        case E820_NVS: return "ACPI NVS";
+        case E820_UNUSABLE: return "Unusable";
+        default: break;
+    }
+    return "Unknown";
+}
+#endif

Quoted 8 lines

tools/python/xen/lowlevel/xc/xc.c static PyObject *pyxc_domain_set_memmap_ · line 1719

Quoted 5 lines

tools/python/xen/lowlevel/xc/xc.c +5 -0

+static int e820_sanitize(struct e820entry src[],
+                         uint32_t *nr_entries,
+                         unsigned long map_limitkb,
+                         unsigned long balloon_kb)
+{

Seems odd to do this in the C bindings, can this be done either in the python layer or in the libxc layer (in which case libxl can use it too?)

So this is copied from the libxl layer (With the removal of the libxl_ctx). I was hoping you could shed some ideas of how to "export" that function (e820_sanitize) from the libxl_pci.c so that the tools/python/xen/lowlevel/xc/xc.c can also use it?

xend: Add support for passing in the host's E820 for PCI passthrough

The code that populates E820 is unconditionally triggered by the guest configuration having 'e820_hole=1'.

Konrad Rzeszutek Wilk writes ("[PATCH 6 of 6] xend: Add support for passing in the host's E820 for PCI passthrough"):

Quoted 1 line

xend: Add support for passing in the host's E820 for PCI passthrough

...>

Quoted 2 lines

The code that populates E820 is unconditionally triggered by the guest configuration having 'e820_hole=1'.

Isn't this similar to some xl/libxl features ? "e820_host" maybe.

We certainly don't want to add any new features to xend with incompatible config settings to xl.

Ian.

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