i.MX6: mx6q_sabrelite: add SATA bindings

PATCH Superseded Eric Nelson 3 participants 10 messages May 1, 2012 – May 6, 2012 1 message not in the archive

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Eric Nelson

author

2012-05-01 19:24 UTC #1 lore raw

PATCH v4 1/1 i.MX6: mx6q_sabrelite: add SATA bindings

Signed-off-by Eric Nelson <[email protected]>

---
V2 has been stripped of the board-independent changes and uses clrsetbits_le32() instead of twiddling bits by hand.

V3 returns immediately from setup_sata() if enable_sata_clock() returns an error.

V4 removes extra #include and addresses a style issue as discussed on the ML.

 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   31 +++++++++++++++++++++++++
 include/configs/mx6qsabrelite.h               |   13 ++++++++++
 2 files changed, 44 insertions(+), 0 deletions(-)

board/freescale/mx6qsabrelite/mx6qsabrelite.c +31 -0

index 1d09a72..cdd2f15 100644
@@ -25,6 +25,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6x_pins.h>
 #include <asm/arch/iomux-v3.h>
+#include <asm/arch/clock.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <mmc.h>

@@ -267,6 +268,32 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
+#ifdef CONFIG_CMD_SATA
+
+int setup_sata(void)
+{
+	struct iomuxc_base_regs *const iomuxc_regs
+		= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
+	int ret = enable_sata_clock();
+	if (ret)
+		return ret;
+
+	clrsetbits_le32(&iomuxc_regs->gpr[13],
+			IOMUXC_GPR13_SATA_MASK,
+			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
+			|IOMUXC_GPR13_SATA_SPEED_3G
+			|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+	return 0 ;
+}
+#endif
+
 int board_early_init_f(void)
 {
        setup_iomux_uart();

@@ -283,6 +310,10 @@ int board_init(void)
 	setup_spi();
 #endif
 
+#ifdef CONFIG_CMD_SATA
+	setup_sata();
+#endif
+
        return 0;
 }

include/configs/mx6qsabrelite.h +13 -0

index f52c3c7..1d92dd0 100644
@@ -71,6 +71,19 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
+#define CONFIG_CMD_SATA
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII

Signature · 1 line

1.7.9

Marek Vasut

2012-05-01 19:25 UTC #2 lore raw

PATCH v4 1/1 i.MX6: mx6q_sabrelite: add SATA bindings

Dear Eric Nelson,

Quoted 10 lines

Signed-off-by Eric Nelson <[email protected]>
---
V2 has been stripped of the board-independent changes and uses clrsetbits_le32() instead of twiddling bits by hand.
V3 returns immediately from setup_sata() if enable_sata_clock() returns an error.
V4 removes extra #include and addresses a style issue as discussed on the ML.

It's still there ;-)

Quoted 93 lines

 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   31
+++++++++++++++++++++++++ include/configs/mx6qsabrelite.h               | 
 13 ++++++++++
 2 files changed, 44 insertions(+), 0 deletions(-)

(quoted diff) +0 -0

b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 1d09a72..cdd2f15 100644

board/freescale/mx6qsabrelite/mx6qsabrelite.c +31 -0

@@ -25,6 +25,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6x_pins.h>
 #include <asm/arch/iomux-v3.h>
+#include <asm/arch/clock.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <mmc.h>

@@ -267,6 +268,32 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
+#ifdef CONFIG_CMD_SATA
+
+int setup_sata(void)
+{
+	struct iomuxc_base_regs *const iomuxc_regs
+		= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
+	int ret = enable_sata_clock();
+	if (ret)
+		return ret;
+
+	clrsetbits_le32(&iomuxc_regs->gpr[13],
+			IOMUXC_GPR13_SATA_MASK,
+			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
+			|IOMUXC_GPR13_SATA_SPEED_3G
+			|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
 
 
 
+	return 0 ; <---- here :-)
 
 
 
+}
+#endif
+
 int board_early_init_f(void)
 {
        setup_iomux_uart();

@@ -283,6 +310,10 @@ int board_init(void)
 	setup_spi();
 #endif
 
+#ifdef CONFIG_CMD_SATA
+	setup_sata();
+#endif
+
        return 0;
 }

(quoted diff) +0 -0

b/include/configs/mx6qsabrelite.h index f52c3c7..1d92dd0 100644

include/configs/mx6qsabrelite.h +13 -0

@@ -71,6 +71,19 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
+#define CONFIG_CMD_SATA
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII

Eric Nelson

author

2012-05-01 19:53 UTC #3 lore raw

PATCH v4 1/1 i.MX6: mx6q_sabrelite: add SATA bindings

Quoted 15 lines · Marek Vasut

Dear Eric Nelson,
Quoted 10 lines
Signed-off-by Eric Nelson<[email protected]>
---
V2 has been stripped of the board-independent changes and uses clrsetbits_le32() instead of twiddling bits by hand.
V3 returns immediately from setup_sata() if enable_sata_clock() returns an error.
V4 removes extra #include and addresses a style issue as discussed on the ML.
It's still there ;-)
Quoted 1 line

Quoted 8 lines

board/freescale/mx6qsabrelite/mx6qsabrelite.c int board_eth_init(bd_t *bis)
Quoted 7 lines
<snip>
board/freescale/mx6qsabrelite/mx6qsabrelite.c +4 -0
+			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
 
+	return 0 ;<---- here :-)

My eyes are clearly not as finely tuned as yours...

<thought to self>
What are the odd that I could tweak checkpatch.pl
without introducing another style issue?
</thought to self>

V5 forthcoming...

Marek Vasut

2012-05-01 21:11 UTC #4 lore raw

PATCH v4 1/1 i.MX6: mx6q_sabrelite: add SATA bindings

Dear Eric Nelson,

Quoted 18 lines · Marek Vasut

Quoted 17 lines
Dear Eric Nelson,
Quoted 10 lines
Signed-off-by Eric Nelson<[email protected]>
---
V2 has been stripped of the board-independent changes and uses clrsetbits_le32() instead of twiddling bits by hand.
V3 returns immediately from setup_sata() if enable_sata_clock() returns an error.
V4 removes extra #include and addresses a style issue as discussed on the ML.
It's still there ;-)
Quoted 2 lines
<snip>

Quoted 7 lines

Quoted 5 lines
board/freescale/mx6qsabrelite/mx6qsabrelite.c int board_eth_init(bd_t *bis)
Quoted 5 lines
board/freescale/mx6qsabrelite/mx6qsabrelite.c +4 -0
+			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
 
+	return 0 ;<---- here :-)
My eyes are clearly not as finely tuned as yours...

1 dioptry on left eye, lazy-eye blindness on the right one ;-)

Quoted 4 lines

<thought to self>
What are the odd that I could tweak checkpatch.pl
without introducing another style issue?
</thought to self>

That'd be awesome.

Quoted 1 line

V5 forthcoming...

Thanks :)

Best regards,
Marek Vasut

Eric Nelson

author

2012-05-01 21:58 UTC #5 lore raw

PATCH v4 1/1 i.MX6: mx6q_sabrelite: add SATA bindings

Quoted 24 lines · Marek Vasut

Dear Eric Nelson,
Quoted 22 lines · Marek Vasut
Quoted 21 lines
Dear Eric Nelson,
Quoted 10 lines
Signed-off-by Eric Nelson<[email protected]>
---
V2 has been stripped of the board-independent changes and uses clrsetbits_le32() instead of twiddling bits by hand.
V3 returns immediately from setup_sata() if enable_sata_clock() returns an error.
V4 removes extra #include and addresses a style issue as discussed on the ML.
It's still there ;-)
Quoted 6 lines
<snip>
board/freescale/mx6qsabrelite/mx6qsabrelite.c +3 -0
+			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
+

Quoted 6 lines

Quoted 3 lines
Quoted 1 line
Review
Quoted 1 line
(quoted diff) +1 -0
+	return 0 ;<---- here :-)
My eyes are clearly not as finely tuned as yours...
1 dioptry on left eye, lazy-eye blindness on the right one ;-)

For all that, you seem to see quite well!

Quoted 7 lines

Quoted 4 lines
<thought to self>
What are the odd that I could tweak checkpatch.pl
without introducing another style issue?
</thought to self>
That'd be awesome.

Forthcoming...

Eric Nelson

author

2012-05-01 19:55 UTC #6 lore raw

PATCH v5 1/1 i.MX6: mx6q_sabrelite: add SATA bindings

In reply to a message not in the archive

Signed-off-by Eric Nelson <[email protected]>

---
V2 has been stripped of the board-independent changes and uses clrsetbits_le32() instead of twiddling bits by hand.

V3 returns immediately from setup_sata() if enable_sata_clock() returns an error.

V4 removes extra #include and addresses a style issue as discussed on the ML.

V5 addresses another (hopefully last) style issue.

 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   31 +++++++++++++++++++++++++
 include/configs/mx6qsabrelite.h               |   13 ++++++++++
 2 files changed, 44 insertions(+), 0 deletions(-)

board/freescale/mx6qsabrelite/mx6qsabrelite.c +31 -0

index 1d09a72..cdd2f15 100644
@@ -25,6 +25,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6x_pins.h>
 #include <asm/arch/iomux-v3.h>
+#include <asm/arch/clock.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <mmc.h>

@@ -267,6 +268,32 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
+#ifdef CONFIG_CMD_SATA
+
+int setup_sata(void)
+{
+	struct iomuxc_base_regs *const iomuxc_regs
+		= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
+	int ret = enable_sata_clock();
+	if (ret)
+		return ret;
+
+	clrsetbits_le32(&iomuxc_regs->gpr[13],
+			IOMUXC_GPR13_SATA_MASK,
+			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
+			|IOMUXC_GPR13_SATA_SPEED_3G
+			|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+	return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
        setup_iomux_uart();

@@ -283,6 +310,10 @@ int board_init(void)
 	setup_spi();
 #endif
 
+#ifdef CONFIG_CMD_SATA
+	setup_sata();
+#endif
+
        return 0;
 }

include/configs/mx6qsabrelite.h +13 -0

index f52c3c7..1d92dd0 100644
@@ -71,6 +71,19 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
+#define CONFIG_CMD_SATA
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII

Signature · 1 line

1.7.9

Marek Vasut

2012-05-01 20:09 UTC #7 lore raw

PATCH v5 1/1 i.MX6: mx6q_sabrelite: add SATA bindings

Dear Eric Nelson,

Quoted 5 lines

Signed-off-by Eric Nelson <[email protected]>
---
V2 has been stripped of the board-independent changes and uses clrsetbits_le32() instead of twiddling bits by hand.

Quoted 7 lines

V3 returns immediately from setup_sata() if enable_sata_clock() returns an error.
V4 removes extra #include and addresses a style issue as discussed on the ML.
V5 addresses another (hopefully last) style issue.

Sorry for torturing you so much :-)

Acked-by Marek Vasut <[email protected]>

Quoted 87 lines

 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   31
+++++++++++++++++++++++++ include/configs/mx6qsabrelite.h               | 
 13 ++++++++++
 2 files changed, 44 insertions(+), 0 deletions(-)

(quoted diff) +0 -0

b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 1d09a72..cdd2f15 100644

board/freescale/mx6qsabrelite/mx6qsabrelite.c +31 -0

@@ -25,6 +25,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6x_pins.h>
 #include <asm/arch/iomux-v3.h>
+#include <asm/arch/clock.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <mmc.h>

@@ -267,6 +268,32 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
+#ifdef CONFIG_CMD_SATA
+
+int setup_sata(void)
+{
+	struct iomuxc_base_regs *const iomuxc_regs
+		= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
+	int ret = enable_sata_clock();
+	if (ret)
+		return ret;
+
+	clrsetbits_le32(&iomuxc_regs->gpr[13],
+			IOMUXC_GPR13_SATA_MASK,
+			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
+			|IOMUXC_GPR13_SATA_SPEED_3G
+			|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+	return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
        setup_iomux_uart();

@@ -283,6 +310,10 @@ int board_init(void)
 	setup_spi();
 #endif
 
+#ifdef CONFIG_CMD_SATA
+	setup_sata();
+#endif
+
        return 0;
 }

(quoted diff) +0 -0

b/include/configs/mx6qsabrelite.h index f52c3c7..1d92dd0 100644

include/configs/mx6qsabrelite.h +13 -0

@@ -71,6 +71,19 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
+#define CONFIG_CMD_SATA
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII

Eric Nelson

author

2012-05-01 20:23 UTC #8 lore raw

PATCH v5 1/1 i.MX6: mx6q_sabrelite: add SATA bindings

Quoted 10 lines · Marek Vasut

Dear Eric Nelson,
Quoted 8 lines
Signed-off-by Eric Nelson<[email protected]>
---
V2 has been stripped of the board-independent changes and uses clrsetbits_le32() instead of twiddling bits by hand.
V3 returns immediately from setup_sata() if enable_sata_clock() returns an error.

Quoted 7 lines

Quoted 4 lines
V4 removes extra #include and addresses a style issue as discussed on the ML.
V5 addresses another (hopefully last) style issue.
Sorry for torturing you so much :-)

No worries. I think I have a high threshold...

Quoted 2 lines

Acked-by Marek Vasut<[email protected]>

Thanks for the ack.

Stefano Babic

2012-05-06 17:06 UTC #9 lore raw

PATCH v5 1/1 i.MX6: mx6q_sabrelite: add SATA bindings

In reply to Eric Nelson

Quoted 87 lines · Eric Nelson

Signed-off-by Eric Nelson <[email protected]>

---
V2 has been stripped of the board-independent changes and uses clrsetbits_le32() instead of twiddling bits by hand.

V3 returns immediately from setup_sata() if enable_sata_clock() returns an error.

V4 removes extra #include and addresses a style issue as discussed on the ML.

V5 addresses another (hopefully last) style issue.

 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   31 +++++++++++++++++++++++++
 include/configs/mx6qsabrelite.h               |   13 ++++++++++
 2 files changed, 44 insertions(+), 0 deletions(-)

board/freescale/mx6qsabrelite/mx6qsabrelite.c +31 -0

index 1d09a72..cdd2f15 100644
@@ -25,6 +25,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6x_pins.h>
 #include <asm/arch/iomux-v3.h>
+#include <asm/arch/clock.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <mmc.h>

@@ -267,6 +268,32 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
+#ifdef CONFIG_CMD_SATA
+
+int setup_sata(void)
+{
+	struct iomuxc_base_regs *const iomuxc_regs
+		= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
+	int ret = enable_sata_clock();
+	if (ret)
+		return ret;
+
+	clrsetbits_le32(&iomuxc_regs->gpr[13],
+			IOMUXC_GPR13_SATA_MASK,
+			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
+			|IOMUXC_GPR13_SATA_SPEED_3G
+			|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+	return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
        setup_iomux_uart();

@@ -283,6 +310,10 @@ int board_init(void)
 	setup_spi();
 #endif
 
+#ifdef CONFIG_CMD_SATA
+	setup_sata();
+#endif
+
        return 0;
 }

include/configs/mx6qsabrelite.h +6 -0

index f52c3c7..1d92dd0 100644
@@ -71,6 +71,19 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
+#define CONFIG_CMD_SATA
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA

include/configs/mx6qsabrelite.h line 89

Quoted 10 lines

include/configs/mx6qsabrelite.h +7 -0

+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII

Acked-by stefano Babic <[email protected]>

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

2012-05-06 17:10 UTC #10 lore raw

PATCH v5 1/1 i.MX6: mx6q_sabrelite: add SATA bindings

In reply to Eric Nelson

Quoted 5 lines · Eric Nelson

Signed-off-by Eric Nelson <[email protected]>
---
V2 has been stripped of the board-independent changes and uses clrsetbits_le32() instead of twiddling bits by hand.

Quoted 8 lines

V3 returns immediately from setup_sata() if enable_sata_clock() returns an error.
V4 removes extra #include and addresses a style issue as discussed on the ML.
V5 addresses another (hopefully last) style issue.

Hi Eric,

applied after rebasing on current u-boot-imx.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================