USB: S5P: Add ehci support

This patch adds ehci driver support for s5p.

Signed-off-by Vivek Gautam <[email protected]>

Signed-off-by Rajeshwari Shinde <[email protected]>

---
 arch/arm/include/asm/arch-exynos/ehci-s5p.h |   66 ++++++++++++++++
 drivers/usb/host/Makefile                   |    1 +
 drivers/usb/host/ehci-s5p.c                 |  113
+++++++++++++++++++++++++++ 3 files changed, 180 insertions(+), 0
deletions(-)
 create mode 100755 arch/arm/include/asm/arch-exynos/ehci-s5p.h
 create mode 100644 drivers/usb/host/ehci-s5p.c

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-exynos/ehci-s5p.h new file mode 100755 index 0000000..68feb85

arch/arm/include/asm/arch-exynos/ehci-s5p.h new file +66 -0

@@ -0,0 +1,66 @@
+/*
+ * SAMSUNG S5P USB HOST EHCI Controller
+ *
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ *	Vivek Gautam <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
+#define __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
+
+#define CLK_24MHZ		5
+
+#define HOST_CTRL0_PHYSWRSTALL			(1 << 31)
+#define HOST_CTRL0_COMMONON_N			(1 << 9)
+#define HOST_CTRL0_SIDDQ			(1 << 6)
+#define HOST_CTRL0_FORCESLEEP			(1 << 5)
+#define HOST_CTRL0_FORCESUSPEND			(1 << 4)
+#define HOST_CTRL0_WORDINTERFACE		(1 << 3)
+#define HOST_CTRL0_UTMISWRST			(1 << 2)
+#define HOST_CTRL0_LINKSWRST			(1 << 1)
+#define HOST_CTRL0_PHYSWRST			(1 << 0)
+
+#define HOST_CTRL0_FSEL_MASK			(7 << 16)
+
+#define EHCICTRL_ENAINCRXALIGN			(1 << 29)
+#define EHCICTRL_ENAINCR4			(1 << 28)
+#define EHCICTRL_ENAINCR8			(1 << 27)
+#define EHCICTRL_ENAINCR16			(1 << 26)
+
+/* Register map for PHY control */
+struct s5p_usb_phy {
+	unsigned int usbphyctrl0;
+	unsigned int usbphytune0;
+	unsigned int reserved1[2];
+	unsigned int hsicphyctrl1;
+	unsigned int hsicphytune1;
+	unsigned int reserved2[2];
+	unsigned int hsicphyctrl2;
+	unsigned int hsicphytune2;
+	unsigned int reserved3[2];
+	unsigned int ehcictrl;
+	unsigned int ohcictrl;
+	unsigned int usbotgsys;
+	unsigned int reserved4;
+	unsigned int usbotgtune;
+};
+
+/* Switch on the VBUS power. */
+int board_usb_vbus_init(void);
+
+#endif /* __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ */

drivers/usb/host/Makefile +1 -0

index 0d4657e..59c3e57 100644
@@ -50,6 +50,7 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
 COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
 COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
 COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
+COBJS-$(CONFIG_USB_EHCI_S5P) += ehci-s5p.o
 COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 

drivers/usb/host/ehci-s5p.c new file +36 -0

new file mode 100644
index 0000000..ac9f061
@@ -0,0 +1,113 @@
+/*
+ * SAMSUNG S5P USB HOST EHCI Controller
+ *
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ *	Vivek Gautam <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ehci-s5p.h>
+#include "ehci.h"
+#include "ehci-core.h"
+
+/* Setup the EHCI host controller. */
+static void setup_usb_phy(struct s5p_usb_phy *usb)
+{
+	unsigned int hostphy_ctrl0;
+
+	/* Setting up host and device simultaneously */
+	hostphy_ctrl0 = readl(&usb->usbphyctrl0);

drivers/usb/host/ehci-s5p.c new file +33 -0

+	udelay(10);
+	clrbits_le32(&usb->usbphyctrl0,
+			HOST_CTRL0_LINKSWRST |
+			HOST_CTRL0_UTMISWRST);
+	udelay(20);
+
+	/* EHCI Ctrl setting */
+	setbits_le32(&usb->ehcictrl,
+			EHCICTRL_ENAINCRXALIGN |
+			EHCICTRL_ENAINCR4 |
+			EHCICTRL_ENAINCR8 |
+			EHCICTRL_ENAINCR16);
+}
+
+/* Reset the EHCI host controller. */
+static void reset_usb_phy(struct s5p_usb_phy *usb)
+{
+	/* HOST_PHY reset */
+	setbits_le32(&usb->usbphyctrl0,
+			HOST_CTRL0_PHYSWRST |
+			HOST_CTRL0_PHYSWRSTALL |
+			HOST_CTRL0_SIDDQ |
+			HOST_CTRL0_FORCESUSPEND |
+			HOST_CTRL0_FORCESLEEP);
+}
+
+/*
+ * EHCI-initialization
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(void)
+{

drivers/usb/host/ehci-s5p.c new file +7 -0

+	debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
+		(uint32_t)hccr, (uint32_t)hcor,
+		(uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+	return 0;
+}
+

drivers/usb/host/ehci-s5p.c new file +3 -0

+
+	return 0;
+}

Dear Rajeshwari Shinde,

This patch adds ehci driver support ?for s5p.

It'd be awesome if you CCed me ;-)
Also, it might be worth CCing Lukasz?

Signed-off-by Vivek Gautam <[email protected]>

Signed-off-by Rajeshwari Shinde <[email protected]>

---

?arch/arm/include/asm/arch-exynos/ehci-s5p.h | ? 66 ++++++++++++++++
?drivers/usb/host/Makefile ? ? ? ? ? ? ? ? ? | ? ?1 +
?drivers/usb/host/ehci-s5p.c ? ? ? ? ? ? ? ? | ?113

+++++++++++++++++++++++++++ 3 files changed, 180 insertions(+), 0 deletions(-)
?create mode 100755 arch/arm/include/asm/arch-exynos/ehci-s5p.h ?create mode 100644 drivers/usb/host/ehci-s5p.c

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-exynos/ehci-s5p.h new file mode 100755 index 0000000..68feb85

arch/arm/include/asm/arch-exynos/ehci-s5p.h new file +66 -0

@@ -0,0 +1,66 @@
+/*
+ * SAMSUNG S5P USB HOST EHCI Controller
+ *
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ * ? Vivek Gautam <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
+#define __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
+
+#define CLK_24MHZ ? ? ? ? ? ?5
+
+#define HOST_CTRL0_PHYSWRSTALL ? ? ? ? ? ? ? ? ? ? ? (1 << 31)
+#define HOST_CTRL0_COMMONON_N ? ? ? ? ? ? ? ? ? ? ? ?(1 << 9)
+#define HOST_CTRL0_SIDDQ ? ? ? ? ? ? ? ? ? ? (1 << 6)
+#define HOST_CTRL0_FORCESLEEP ? ? ? ? ? ? ? ? ? ? ? ?(1 << 5)
+#define HOST_CTRL0_FORCESUSPEND ? ? ? ? ? ? ? ? ? ? ?(1 << 4)
+#define HOST_CTRL0_WORDINTERFACE ? ? ? ? ? ? (1 << 3)
+#define HOST_CTRL0_UTMISWRST ? ? ? ? ? ? ? ? (1 << 2)
+#define HOST_CTRL0_LINKSWRST ? ? ? ? ? ? ? ? (1 << 1)
+#define HOST_CTRL0_PHYSWRST ? ? ? ? ? ? ? ? ?(1 << 0)
+
+#define HOST_CTRL0_FSEL_MASK ? ? ? ? ? ? ? ? (7 << 16)
+
+#define EHCICTRL_ENAINCRXALIGN ? ? ? ? ? ? ? ? ? ? ? (1 << 29)
+#define EHCICTRL_ENAINCR4 ? ? ? ? ? ? ? ? ? ?(1 << 28)
+#define EHCICTRL_ENAINCR8 ? ? ? ? ? ? ? ? ? ?(1 << 27)
+#define EHCICTRL_ENAINCR16 ? ? ? ? ? ? ? ? ? (1 << 26)
+
+/* Register map for PHY control */
+struct s5p_usb_phy {
+ ? ? unsigned int usbphyctrl0;
+ ? ? unsigned int usbphytune0;
+ ? ? unsigned int reserved1[2];
+ ? ? unsigned int hsicphyctrl1;
+ ? ? unsigned int hsicphytune1;
+ ? ? unsigned int reserved2[2];
+ ? ? unsigned int hsicphyctrl2;
+ ? ? unsigned int hsicphytune2;
+ ? ? unsigned int reserved3[2];
+ ? ? unsigned int ehcictrl;
+ ? ? unsigned int ohcictrl;
+ ? ? unsigned int usbotgsys;
+ ? ? unsigned int reserved4;
+ ? ? unsigned int usbotgtune;
+};
+
+/* Switch on the VBUS power. */
+int board_usb_vbus_init(void);
+
+#endif /* __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ */

drivers/usb/host/Makefile +0 -0

index 0d4657e..59c3e57 100644
@@ -50,6 +50,7 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o

?COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o ?COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o ?COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o +COBJS-$(CONFIG_USB_EHCI_S5P) += ehci-s5p.o ?COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o ?COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o

drivers/usb/host/ehci-s5p.c new file +46 -0

new file mode 100644
index 0000000..ac9f061
@@ -0,0 +1,113 @@
+/*
+ * SAMSUNG S5P USB HOST EHCI Controller
+ *
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ * ? Vivek Gautam <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ehci-s5p.h>
+#include "ehci.h"
+#include "ehci-core.h"
+
+/* Setup the EHCI host controller. */
+static void setup_usb_phy(struct s5p_usb_phy *usb)
+{
+ ? ? unsigned int hostphy_ctrl0;
+
+ ? ? /* Setting up host and device simultaneously */
+ ? ? hostphy_ctrl0 = readl(&usb->usbphyctrl0);
+ ? ? hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK |
+ ? ? ? ? ? ? ? ? ? ? ? ?HOST_CTRL0_COMMONON_N |
+ ? ? ? ? ? ? ? ? ? ? ? ?/* HOST Phy setting */
+ ? ? ? ? ? ? ? ? ? ? ? ?HOST_CTRL0_PHYSWRST |
+ ? ? ? ? ? ? ? ? ? ? ? ?HOST_CTRL0_PHYSWRSTALL |
+ ? ? ? ? ? ? ? ? ? ? ? ?HOST_CTRL0_SIDDQ |
+ ? ? ? ? ? ? ? ? ? ? ? ?HOST_CTRL0_FORCESUSPEND |
+ ? ? ? ? ? ? ? ? ? ? ? ?HOST_CTRL0_FORCESLEEP);
+ ? ? hostphy_ctrl0 |= (/* Setting up the ref freq */
+ ? ? ? ? ? ? ? ? ? ? ? CLK_24MHZ << 16 |

Parens around (CLK << 16).

+ ? ? ? ? ? ? ? ? ? ? ? /* HOST Phy setting */
+ ? ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_LINKSWRST |
+ ? ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_UTMISWRST);
+ ? ? writel(hostphy_ctrl0, &usb->usbphyctrl0);

Use clrsetbits_le32() please.

+ ? ? udelay(10);
+ ? ? clrbits_le32(&usb->usbphyctrl0,
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_LINKSWRST |
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_UTMISWRST);
+ ? ? udelay(20);

drivers/usb/host/ehci-s5p.c new file +38 -0

+
+ ? ? /* EHCI Ctrl setting */
+ ? ? setbits_le32(&usb->ehcictrl,
+ ? ? ? ? ? ? ? ? ? ? EHCICTRL_ENAINCRXALIGN |
+ ? ? ? ? ? ? ? ? ? ? EHCICTRL_ENAINCR4 |
+ ? ? ? ? ? ? ? ? ? ? EHCICTRL_ENAINCR8 |
+ ? ? ? ? ? ? ? ? ? ? EHCICTRL_ENAINCR16);
+}
+
+/* Reset the EHCI host controller. */
+static void reset_usb_phy(struct s5p_usb_phy *usb)
+{
+ ? ? /* HOST_PHY reset */
+ ? ? setbits_le32(&usb->usbphyctrl0,
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_PHYSWRST |
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_PHYSWRSTALL |
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_SIDDQ |
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_FORCESUSPEND |
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_FORCESLEEP);
+}
+
+/*
+ * EHCI-initialization
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(void)
+{
+ ? ? struct s5p_usb_phy *usb;
+
+ ? ? usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy();
+ ? ? setup_usb_phy(usb);
+
+ ? ? hccr = (struct ehci_hccr *)(EXYNOS5_USB_HOST_EHCI_BASE);
+ ? ? hcor = (struct ehci_hcor *)((uint32_t) hccr
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ ? ? printf("\n usb cmd addr = %x", &hcor->or_usbcmd);

Either debug() or remove the above ;-)

+ ? ? debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
+ ? ? ? ? ? ? (uint32_t)hccr, (uint32_t)hcor,
+ ? ? ? ? ? ? (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));

drivers/usb/host/ehci-s5p.c new file +14 -0

+
+ ? ? return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding
+ * the EHCI host controller.
+ */
+int ehci_hcd_stop()
+{
+ ? ? struct s5p_usb_phy *usb;
+
+ ? ? usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy();
+ ? ? reset_usb_phy(usb);

Well ... if reseting the PHY is enough to stop the controller, I won't object ;-)

This patch gives a good impression, I see V2 and then mainline acceptance :)

drivers/usb/host/ehci-s5p.c new file +3 -0

+
+ ? ? return 0;
+}

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