Incorrect Register Offsets in OMAP Mailbox

PATCH Henry Chan 2 participants 4 messages Feb 7, 2012 – May 4, 2012

Subsystems (3)

Arm (32-bit) Arm sub-architectures OMAP2+ support

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Henry Chan

author

2012-02-07 17:56 UTC #0 lore raw

Hi,

Looks like the register offsets are incorrect in the OMAP mailbox code (arch/arm/mach-omap2/mailbox.c) for the OMAP4_MAILBOX_IRQ* macros. The discrepancy is with p.224 of TI document SPRUGX9 and p3891 of SWPU231K. Patch attached.

My hardware hasn't come in yet, so I would appreciate it if anyone can share their experience using this code.

Thanks.
-H

Signature · 1 line

Henry Chan

 arch/arm/mach-omap2/mailbox.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

arch/arm/mach-omap2/mailbox.c +3 -3

index 609ea2d..4801e01 100644
@@ -26,9 +26,9 @@
 #define MAILBOX_IRQSTATUS(u)		(0x100 + 8 * (u))
 #define MAILBOX_IRQENABLE(u)		(0x104 + 8 * (u))
 
-#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 10 * (u))
+#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 0x10 * (u))
 
 #define MAILBOX_IRQ_NEWMSG(m)		(1 << (2 * (m)))
 #define MAILBOX_IRQ_NOTFULL(m)		(1 << (2 * (m) + 1))

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Tony Lindgren

maintainer

2012-03-05 19:34 UTC #1 lore raw

Hi Henry,

Quoted 9 lines · Henry Chan

Hi,
Looks like the register offsets are incorrect in the OMAP mailbox code (arch/arm/mach-omap2/mailbox.c) for the OMAP4_MAILBOX_IRQ* macros. The discrepancy is with p.224 of TI document SPRUGX9 and p3891 of SWPU231K. Patch attached.
My hardware hasn't come in yet, so I would appreciate it if anyone can share their experience using this code.

Can you please reply with your Signed-off-by, it's missing from the patch.

Thanks,

Tony

Quoted 16 lines

arch/arm/mach-omap2/mailbox.c +3 -3

@@ -26,9 +26,9 @@
 #define MAILBOX_IRQSTATUS(u)		(0x100 + 8 * (u))
 #define MAILBOX_IRQENABLE(u)		(0x104 + 8 * (u))
 
-#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 10 * (u))
+#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 0x10 * (u))
 
 #define MAILBOX_IRQ_NEWMSG(m)		(1 << (2 * (m)))
 #define MAILBOX_IRQ_NOTFULL(m)		(1 << (2 * (m) + 1))

Henry Chan

author

2012-03-08 08:04 UTC #2 lore raw

Sorry about that. Kind of new at this.
-H

Signed-off-by Henry Chan <[email protected]>

Quoted 37 lines · Tony Lindgren

Hi Henry,
Quoted 9 lines · Henry Chan
Hi,
Looks like the register offsets are incorrect in the OMAP mailbox code (arch/arm/mach-omap2/mailbox.c) for the OMAP4_MAILBOX_IRQ* macros. The discrepancy is with p.224 of TI document SPRUGX9 and p3891 of SWPU231K. Patch attached.
My hardware hasn't come in yet, so I would appreciate it if anyone can share their experience using this code.
Can you please reply with your Signed-off-by, it's missing from the patch.
Thanks,
Tony
Quoted 16 lines
arch/arm/mach-omap2/mailbox.c +3 -3
@@ -26,9 +26,9 @@
 #define MAILBOX_IRQSTATUS(u)		(0x100 + 8 * (u))
 #define MAILBOX_IRQENABLE(u)		(0x104 + 8 * (u))
 
-#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 10 * (u))
+#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 0x10 * (u))
 
 #define MAILBOX_IRQ_NEWMSG(m)		(1 << (2 * (m)))
 #define MAILBOX_IRQ_NOTFULL(m)		(1 << (2 * (m) + 1))

Signature · 1 line

Henry Chan

Tony Lindgren

maintainer

2012-05-04 18:07 UTC #3 lore raw

Quoted 4 lines · Henry Chan

Sorry about that. Kind of new at this.
-H
Signed-off-by Henry Chan <[email protected]>

Thanks, applying this finally into fixes-non-critical.

Tony

Quoted 40 lines · Tony Lindgren

Quoted 37 lines
Hi Henry,
Quoted 9 lines · Henry Chan
Hi,
Looks like the register offsets are incorrect in the OMAP mailbox code (arch/arm/mach-omap2/mailbox.c) for the OMAP4_MAILBOX_IRQ* macros. The discrepancy is with p.224 of TI document SPRUGX9 and p3891 of SWPU231K. Patch attached.
My hardware hasn't come in yet, so I would appreciate it if anyone can share their experience using this code.
Can you please reply with your Signed-off-by, it's missing from the patch.
Thanks,
Tony
Quoted 16 lines
arch/arm/mach-omap2/mailbox.c +3 -3
@@ -26,9 +26,9 @@
 #define MAILBOX_IRQSTATUS(u)		(0x100 + 8 * (u))
 #define MAILBOX_IRQENABLE(u)		(0x104 + 8 * (u))
 
-#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 10 * (u))
+#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 0x10 * (u))
 
 #define MAILBOX_IRQ_NEWMSG(m)		(1 << (2 * (m)))
 #define MAILBOX_IRQ_NOTFULL(m)		(1 << (2 * (m) + 1))
Signature · 1 line
Henry Chan