ARM: OMAP5: Add minimal OMAP5 SOC support

Adding the OMAP5 ES1.0, 2.0 and OMAP5432 cpu revision detection support.

Signed-off-by R Sricharan <[email protected]>

Signed-off-by Santosh Shilimkar <[email protected]>

---
 arch/arm/mach-omap2/control.h         |    4 +++
 arch/arm/mach-omap2/id.c              |   47 +++++++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/cpu.h |   23 ++++++++++++++-
 3 files changed, 72 insertions(+), 2 deletions(-)

arch/arm/mach-omap2/control.h +4 -0

index a406fd0..9daac6f 100644
@@ -246,6 +246,10 @@
 /* TI81XX CONTROL_DEVCONF register offsets */
 #define TI81XX_CONTROL_DEVICE_ID	(TI81XX_CONTROL_DEVCONF + 0x000)
 
+/* OMAP54XX CONTROL STATUS register */
+#define OMAP5XXX_CONTROL_STATUS                0x134
+#define OMAP5_DEVICETYPE_MASK          (0x7 << 6)
+
 /*
  * REVISIT: This list of registers is not comprehensive - there are more
  * that should be added.

arch/arm/mach-omap2/id.c +15 -0

index 0e79b7b..d2ec323 100644
@@ -50,6 +50,11 @@ int omap_type(void)
 		val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
 	} else if (cpu_is_omap44xx()) {
 		val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
+	} else if (cpu_is_omap54xx()) {
+		val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
+		val &= OMAP5_DEVICETYPE_MASK;
+		val >>= 6;
+		goto out;
 	} else {
 		pr_err("Cannot detect omap type!\n");
 		goto out;

@@ -500,6 +505,48 @@ void __init omap4xxx_check_revision(void)
 		((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
 }
 
+void __init omap5xxx_check_revision(void)
+{
+	u32 idcode;
+	u16 hawkeye;
+	u8 rev;
+
+	idcode = read_tap_reg(OMAP_TAP_IDCODE);
+	hawkeye = (idcode >> 12) & 0xffff;
+	rev = (idcode >> 28) & 0xff;
+	switch (hawkeye) {

arch/arm/mach-omap2/id.c +12 -0

+		}
+		break;
+
+	case 0xb998:
+		switch (rev) {
+		case 0:
+			omap_revision = OMAP5432_REV_ES1_0;
+			break;
+		default:
+			omap_revision = OMAP5432_REV_ES1_0;
+		}
+		break;

Quoted 15 lines

(quoted diff) +15 -0

+void __init omap5xxx_check_revision(void)
+{
+ ? ? u32 idcode;
+ ? ? u16 hawkeye;
+ ? ? u8 rev;
+
+ ? ? idcode = read_tap_reg(OMAP_TAP_IDCODE);
+ ? ? hawkeye = (idcode >> 12) & 0xffff;
+ ? ? rev = (idcode >> 28) & 0xff;
+ ? ? switch (hawkeye) {
+ ? ? case 0xb942:
+ ? ? ? ? ? ? switch (rev) {
+ ? ? ? ? ? ? case 0:
+ ? ? ? ? ? ? ? ? ? ? omap_revision = OMAP5430_REV_ES1_0;
+ ? ? ? ? ? ? ? ? ? ? break;

Quoted 5 lines

+ ? ? ? ? ? ? case 1:
+ ? ? ? ? ? ? ? ? ? ? omap_revision = OMAP5430_REV_ES2_0;
+ ? ? ? ? ? ? ? ? ? ? break;
+ ? ? ? ? ? ? default:
+ ? ? ? ? ? ? ? ? ? ? omap_revision = OMAP5430_REV_ES1_0;

Default should always be the latest version supported. i.e. in this case it should be OMAP5430_REV_ES2_0

Adding the OMAP5 ES1.0, 2.0 and OMAP5432 cpu revision detection support.

Signed-off-by R Sricharan <[email protected]>

Signed-off-by Santosh Shilimkar <[email protected]>

---
 arch/arm/mach-omap2/control.h         |    4 +++
 arch/arm/mach-omap2/id.c              |   47 +++++++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/cpu.h |   23 ++++++++++++++-
 3 files changed, 72 insertions(+), 2 deletions(-)

arch/arm/mach-omap2/control.h +4 -0

index a406fd0..9daac6f 100644
@@ -246,6 +246,10 @@
 /* TI81XX CONTROL_DEVCONF register offsets */
 #define TI81XX_CONTROL_DEVICE_ID	(TI81XX_CONTROL_DEVCONF + 0x000)
 
+/* OMAP54XX CONTROL STATUS register */
+#define OMAP5XXX_CONTROL_STATUS                0x134
+#define OMAP5_DEVICETYPE_MASK          (0x7 << 6)
+
 /*
  * REVISIT: This list of registers is not comprehensive - there are more
  * that should be added.

arch/arm/mach-omap2/id.c +9 -0

index 0e79b7b..d2ec323 100644
@@ -50,6 +50,11 @@ int omap_type(void)
 		val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
 	} else if (cpu_is_omap44xx()) {
 		val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
+	} else if (cpu_is_omap54xx()) {
+		val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
+		val &= OMAP5_DEVICETYPE_MASK;
+		val >>= 6;
+		goto out;
 	} else {
 		pr_err("Cannot detect omap type!\n");
 		goto out;

@@ -500,6 +505,48 @@ void __init omap4xxx_check_revision(void)
 		((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
 }
 
+void __init omap5xxx_check_revision(void)
+{
+	u32 idcode;
+	u16 hawkeye;

why do you duplicate this

Quoted 4 lines

+ ? ? ? ? ? ? ? ? ? ? break;
+ ? ? ? ? ? ? case 1:
+ ? ? ? ? ? ? ? ? ? ? omap_revision = OMAP5430_REV_ES2_0;
+ ? ? ? ? ? ? ? ? ? ? break;

do this

? ? ? ? ? ? ? ?case 0:

Quoted 11 lines

+ ? ? ? ? ? ? default:
+ ? ? ? ? ? ? ? ? ? ? omap_revision = OMAP5430_REV_ES1_0;
+ ? ? ? ? ? ? }
+ ? ? ? ? ? ? break;
+
+ ? ? case 0xb998:
+ ? ? ? ? ? ? switch (rev) {
+ ? ? ? ? ? ? case 0:
+ ? ? ? ? ? ? ? ? ? ? omap_revision = OMAP5432_REV_ES1_0;
+ ? ? ? ? ? ? ? ? ? ? break;
+ ? ? ? ? ? ? default:

ditto here

arch/arm/mach-omap2/Makefile +17 -7

@@ -16,6 +16,7 @@ secure-common				= omap-smc.o omap-secure.o
 obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
 obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
+obj-$(CONFIG_ARCH_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
 
 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
 obj-y += mcbsp.o

@@ -27,8 +28,10 @@ obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
 
 obj-$(CONFIG_SMP)			+= omap-smp.o omap-headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)		+= omap-hotplug.o
-obj-$(CONFIG_ARCH_OMAP4)		+= omap4-common.o omap-wakeupgen.o
-obj-$(CONFIG_ARCH_OMAP4)		+= sleep44xx.o
+omap-4-5-common				=  omap4-common.o omap-wakeupgen.o \
+					   sleep44xx.o		
+obj-$(CONFIG_ARCH_OMAP4)		+= $(omap-4-5-common)
+obj-$(CONFIG_ARCH_OMAP5)                += $(omap-4-5-common)
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o			:=-Wa,-march=armv7-a$(plus_sec)

@@ -68,6 +71,7 @@ obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= cpuidle34xx.o
 obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o omap-mpuss-lowpower.o
+obj-$(CONFIG_ARCH_OMAP5)		+= omap-mpuss-lowpower.o
 obj-$(CONFIG_ARCH_OMAP4)		+= cpuidle44xx.o
 obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
 obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o

@@ -87,9 +91,11 @@ obj-y					+= prm_common.o
 obj-$(CONFIG_ARCH_OMAP2)		+= prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= vc3xxx_data.o vp3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)		+= prcm.o cminst44xx.o cm44xx.o
-obj-$(CONFIG_ARCH_OMAP4)		+= prcm_mpu44xx.o prminst44xx.o
-obj-$(CONFIG_ARCH_OMAP4)		+= vc44xx_data.o vp44xx_data.o prm44xx.o
+omap-prcm-4-5-common			=  prcm.o cminst44xx.o cm44xx.o \
+					   prcm_mpu44xx.o prminst44xx.o \
+					   vc44xx_data.o vp44xx_data.o
+obj-$(CONFIG_ARCH_OMAP4)		+= $(omap-prcm-4-5-common) prm44xx.o
+obj-$(CONFIG_ARCH_OMAP5)                += $(omap-prcm-4-5-common)
 
 # OMAP voltage domains
 voltagedomain-common			:= voltage.o vc.o vp.o

@@ -99,6 +105,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP3)		+= voltagedomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP4)		+= voltagedomains44xx_data.o
+obj-$(CONFIG_ARCH_OMAP5)		+= $(voltagedomain-common)
 
 # OMAP powerdomain framework
 powerdomain-common			+= powerdomain.o powerdomain-common.o

@@ -113,6 +120,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= powerdomains2xxx_3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)		+= powerdomain44xx.o
 obj-$(CONFIG_ARCH_OMAP4)		+= powerdomains44xx_data.o
+obj-$(CONFIG_ARCH_OMAP5)                += $(powerdomain-common) powerdomain44xx.o
 
 # PRCM clockdomain control
 obj-$(CONFIG_ARCH_OMAP2)		+= clockdomain.o

@@ -124,9 +132,11 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clockdomain.o
 obj-$(CONFIG_ARCH_OMAP3)		+= clockdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= clockdomains2xxx_3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)		+= clockdomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)		+= clockdomain.o
-obj-$(CONFIG_ARCH_OMAP4)		+= clockdomain44xx.o
+omap-clock-4-5-common			= clockdomain.o \
+					  clockdomain44xx.o
+obj-$(CONFIG_ARCH_OMAP4)		+= $(omap-clock-4-5-common)
 obj-$(CONFIG_ARCH_OMAP4)		+= clockdomains44xx_data.o
+obj-$(CONFIG_ARCH_OMAP5)		+= $(omap-clock-4-5-common)
 
 # Clock framework
 obj-$(CONFIG_ARCH_OMAP2)		+= $(clock-common) clock2xxx.o

arch/arm/mach-omap2/common.h +0 -0

index 0672fc5..797dda7 100644
@@ -78,6 +78,14 @@ static inline void omap44xx_map_common_io(void)
 }
 #endif

arch/arm/mach-omap2/prm2xxx_3xxx.h +0 -0

@@ -232,8 +232,9 @@
  * Stub omap2xxx/omap3xxx functions so that common files

arch/arm/mach-omap2/clock.c int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) · line 405

Quoted 10 lines

arch/arm/mach-omap2/clock.c +2 -1

@@ -400,7 +400,8 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 
 /* OMAP3/4 non-CORE DPLL clkops */
 
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
+				defined(CONFIG_ARCH_OMAP5)
 

How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series? Then this becomes just:

#ifdef CONFIG_SOC_OMAP3PLUS

Quoted 6 lines

arch/arm/mach-omap2/cminst44xx.h +0 -0

@@ -19,7 +19,7 @@ extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
 
 extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
 

arch/arm/mach-omap2/cminst44xx.h extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs); · line 24

Quoted 4 lines

arch/arm/mach-omap2/cminst44xx.h +1 -1

-# ifdef CONFIG_ARCH_OMAP4
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
 extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
 					 u16 clkctrl_offs);

And this would be:

#ifdef CONFIG_SOC_OMAP4PLUS

OK this seems to be based on Santosh' Makefile cleanup.

arch/arm/mach-omap2/clock.c int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)

Quoted 5 lines

arch/arm/mach-omap2/clock.c +2 -1

-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? defined(CONFIG_ARCH_OMAP5)

How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series? Then this becomes just:

#ifdef CONFIG_SOC_OMAP3PLUS

Quoted 4 lines

arch/arm/mach-omap2/cminst44xx.h +1 -1

-# ifdef CONFIG_ARCH_OMAP4
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)

?extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?u16 clkctrl_offs);

And this would be:

#ifdef CONFIG_SOC_OMAP4PLUS

Also, please change the whole series to use CONFIG_SOC_OMAP5 instead of CONFIG_ARCH_OMAP5. CONFIG_ARCH_OMAPXXXX stuff will go away except for CONFIG_ARCH_OMAP2PLUS. Sorry forgot to mention that earlier.

Quoted 8 lines

(quoted diff) +3 -2

-#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || ? ?\
- ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? defined(CONFIG_ARCH_OMAP3))
+#if (defined(CONFIG_ARCH_OMAP5) || defined(CONFIG_ARCH_OMAP4)) && \
+ ? ? ? ? ? ? !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
+

?static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx) ?{
? ? ? WARN(1, "prm: omap2xxx/omap3xxx specific function and "

Maybe these functions could be just set up as __weak to avoid the ifdeffery?

Quoted 7 lines

?#define CK_443X ? ? ? ? ? ? ?(1 << 11)
?#define CK_TI816X ? ?(1 << 12)
?#define CK_446X ? ? ? ? ? ? ?(1 << 13)
+#define CK_54XX ? ? ? ? ? ? ?(1 << 14)
?#define CK_1710 ? ? ? ? ? ? ?(1 << 15) ? ? ? /* 1710 extra for rate selection */

Are we going to have to patch tons of existing clocks just to add CK_54XX? If so, we should init clocks using SoC specific lists instead.

arch/arm/plat-omap/include/plat/clock.h struct clkops { · line 64

Quoted 9 lines

arch/arm/plat-omap/include/plat/clock.h +1 -0

index d0ef57c..41858f4 100644
@@ -61,6 +61,7 @@ struct clkops {
 ?#define RATE_IN_4460 ? ? ? ? (1 << 7)
 ?#define RATE_IN_AM33XX ? ? ? ? ? ? ? (1 << 8)
 ?#define RATE_IN_TI814X ? ? ? ? ? ? ? (1 << 9)
+#define RATE_IN_54XX ? ? ? ? (1 << 10)

This too may have similar issues, but I guess that's really a different patch series to sort out..

Quoted 6 lines

arch/arm/plat-omap/include/plat/clock.h +2 -1

-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) \
+ ? ? ? ? ? ? || defined(CONFIG_ARCH_OMAP5)
 ? ? ? void __iomem ? ? ? ? ? ?*autoidle_reg;

? ? ? void __iomem ? ? ? ? ? ?*idlest_reg;
? ? ? u32 ? ? ? ? ? ? ? ? ? ? autoidle_mask;

#ifdef CONFIG_SOC_OMAP3PLUS could be used here too

Quoted 5 lines

Also, please change the whole series to use CONFIG_SOC_OMAP5 instead of CONFIG_ARCH_OMAP5. CONFIG_ARCH_OMAPXXXX stuff will go away except for CONFIG_ARCH_OMAP2PLUS. Sorry forgot to mention that earlier.

ok. sure. will change this.

Quoted 12 lines

Quoted 8 lines

(quoted diff) +3 -2

-#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || ? ?\
- ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? defined(CONFIG_ARCH_OMAP3))
+#if (defined(CONFIG_ARCH_OMAP5) || defined(CONFIG_ARCH_OMAP4)) && \
+ ? ? ? ? ? ? !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
+

?static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx) ?{
? ? ? WARN(1, "prm: omap2xxx/omap3xxx specific function and "

Maybe these functions could be just set up as __weak to avoid the ifdeffery?

sorry to understand,
you mean make this weak and have a strong override for OMAP2 ?

Quoted 12 lines

Quoted 12 lines

Quoted 8 lines

(quoted diff) +3 -2

-#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || ? ?\
- ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? defined(CONFIG_ARCH_OMAP3))
+#if (defined(CONFIG_ARCH_OMAP5) || defined(CONFIG_ARCH_OMAP4)) && \
+ ? ? ? ? ? ? !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
+

?static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx) ?{
? ? ? WARN(1, "prm: omap2xxx/omap3xxx specific function and "

Maybe these functions could be just set up as __weak to avoid the ifdeffery?

Quoted 2 lines

?sorry to understand,
?you mean make this weak and have a strong override for OMAP2 ?

Yeah that should do the trick, right?

Tony,

[snip]

Quoted 15 lines

Quoted 14 lines

Quoted 12 lines

Quoted 8 lines

(quoted diff) +3 -2

-#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || ? ?\
- ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? defined(CONFIG_ARCH_OMAP3))
+#if (defined(CONFIG_ARCH_OMAP5) || defined(CONFIG_ARCH_OMAP4)) && \
+ ? ? ? ? ? ? !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
+

?static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx) ?{
? ? ? WARN(1, "prm: omap2xxx/omap3xxx specific function and "

Maybe these functions could be just set up as __weak to avoid the ifdeffery?

?sorry to understand,
?you mean make this weak and have a strong override for OMAP2 ?

Quoted 1 line

Yeah that should do the trick, right?

Ok, There are multiple functions under that #ifdef.
Also i see that __weak cannot be used for inline functions.
So should those functions should be moved to .c file and qualify them
__weak. There is already a strong override for OMAP2 and 3 which
should not be a problem.

[OR]

So after the cleanup patch introducing CONFIG_SOC_OMAP4PLUS it can be changed as
#ifdef (CONFIG_SOC_OMAP4PLUS) && !(defined(CONFIG_ARCH_OMAP2) ||
defined(CONFIG_ARCH_OMAP3))

So this will avoid patching this for the future socs. ?

Quoted 6 lines

?So after the cleanup patch introducing CONFIG_SOC_OMAP4PLUS ?it can be changed as
?#ifdef (CONFIG_SOC_OMAP4PLUS) && !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))

So this will avoid patching this for the future socs. ?

Well it seems that we've come to a conclusion that if we introduce new config options, they should be based on features instead. So CONFIG_SOC_HAS_OMAPXYZ_BLAH rather than CONFIG_SOC_OMAP4PLUS.

How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series? Then this becomes just:

#ifdef CONFIG_SOC_OMAP3PLUS

Hi,

On Fri, 4 May 2012, Tony Lindgren wrote:

Quoted 4 lines

How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series? Then this becomes just:

#ifdef CONFIG_SOC_OMAP3PLUS

We might want to consider having separate CONFIG_SOC_* values for each SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430, CONFIG_SOC_OMAP3630, etc.

This would be for two main reasons. One is that Kconfig options like CONFIG_SOC_OMAP3PLUS don't have much meaning. It is really unclear to me what SoCs would be included in CONFIG_SOC_OMAP3PLUS, since some of them differ so radically -- different interconnects, different power and system management IP blocks, different CPU subsystems, different RAM controllers, etc. The advantage of using SoC-specific Kconfig options, from this point of view, is that it is easy to know what they mean. Then those SoC-specific Kconfig options can select the appropriate SoC-independent interconnect driver, PRCM drivers, CPU options, etc.

The other motivation would be to support device manufacturers who only wish to build a kernel for the single device that they are shipping. In terms of kernels shipped, this is probably the most popular use-case. With something like CONFIG_SOC_OMAPAM33XX, they can avoid building quite a bit of code and data (and potentially bugs) that are not needed for their specific device.

Quoted 4 lines · Paul Walmsley

Hi,

On Fri, 4 May 2012, Tony Lindgren wrote:

Quoted 8 lines

Quoted 4 lines

How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series? Then this becomes just:

#ifdef CONFIG_SOC_OMAP3PLUS

We might want to consider having separate CONFIG_SOC_* values for each SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430, CONFIG_SOC_OMAP3630, etc.

Hmm but this would be in addition to the SOC specific options. The goal is to cut down the ifdeffery needed all over the place to add new SoCs, see the experimental patch I posted:

http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67938.html

Of course we could make this finer grained based on features like SOC_HAS_XYZ or SOC_HAS_OMAP3PLUS_PRMXYZBITS if you have some grouping like that in mind.

Quoted 18 lines · Tony Lindgren

Quoted 4 lines · Paul Walmsley

Hi,

On Fri, 4 May 2012, Tony Lindgren wrote:

Quoted 8 lines

Quoted 4 lines

How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series? Then this becomes just:

#ifdef CONFIG_SOC_OMAP3PLUS

We might want to consider having separate CONFIG_SOC_* values for each SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430, CONFIG_SOC_OMAP3630, etc.

Hmm but this would be in addition to the SOC specific options. The goal is to cut down the ifdeffery needed all over the place to add new SoCs, see the experimental patch I posted:

Quoted 1 line

http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67938.html

Of course we could make this finer grained based on features like SOC_HAS_XYZ or SOC_HAS_OMAP3PLUS_PRMXYZBITS if you have some grouping like that in mind.

Quoted 19 lines · Tony Lindgren

Quoted 18 lines · Tony Lindgren

Quoted 4 lines · Paul Walmsley

Hi,

On Fri, 4 May 2012, Tony Lindgren wrote:

Quoted 8 lines

Quoted 4 lines

How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series? Then this becomes just:

#ifdef CONFIG_SOC_OMAP3PLUS

We might want to consider having separate CONFIG_SOC_* values for each SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430, CONFIG_SOC_OMAP3630, etc.

Hmm but this would be in addition to the SOC specific options. The goal is to cut down the ifdeffery needed all over the place to add new SoCs, see the experimental patch I posted:

Quoted 6 lines

Quoted 1 line

http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67938.html

Of course we could make this finer grained based on features like SOC_HAS_XYZ or SOC_HAS_OMAP3PLUS_PRMXYZBITS if you have some grouping like that in mind.

This is much better approach than both ARCH_OMAPx and SOC_OMAPxxxx.

Quoted 27 lines · Hiremath, Vaibhav

Quoted 25 lines · Tony Lindgren

Quoted 14 lines · Tony Lindgren

Quoted 4 lines · Paul Walmsley

Hi,

On Fri, 4 May 2012, Tony Lindgren wrote:

Quoted 8 lines

Quoted 4 lines

How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series? Then this becomes just:

#ifdef CONFIG_SOC_OMAP3PLUS

We might want to consider having separate CONFIG_SOC_* values for each SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430, CONFIG_SOC_OMAP3630, etc.

Quoted 5 lines

Hmm but this would be in addition to the SOC specific options. The goal is to cut down the ifdeffery needed all over the place to add new SoCs, see the experimental patch I posted:

http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67938.html

Of course we could make this finer grained based on features like SOC_HAS_XYZ or SOC_HAS_OMAP3PLUS_PRMXYZBITS if you have some grouping like that in mind.

Quoted 1 line

This is much better approach than both ARCH_OMAPx and SOC_OMAPxxxx.

OK good, so now the question is just what groupings we need.. Got any suggestions?

Quoted 28 lines · Tony Lindgren

Quoted 27 lines · Hiremath, Vaibhav

Quoted 25 lines · Tony Lindgren

Quoted 14 lines · Tony Lindgren

Quoted 4 lines · Paul Walmsley

Hi,

On Fri, 4 May 2012, Tony Lindgren wrote:

Quoted 8 lines

Quoted 4 lines

How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series? Then this becomes just:

#ifdef CONFIG_SOC_OMAP3PLUS

We might want to consider having separate CONFIG_SOC_* values for each SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430, CONFIG_SOC_OMAP3630, etc.

Quoted 5 lines

Hmm but this would be in addition to the SOC specific options. The goal is to cut down the ifdeffery needed all over the place to add new SoCs, see the experimental patch I posted:

http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67938.html

Of course we could make this finer grained based on features like SOC_HAS_XYZ or SOC_HAS_OMAP3PLUS_PRMXYZBITS if you have some grouping like that in mind.

Quoted 5 lines

Quoted 1 line

This is much better approach than both ARCH_OMAPx and SOC_OMAPxxxx.

OK good, so now the question is just what groupings we need.. Got any suggestions?

Tony

I have submitted first round of cleanup patches in the same direction, can you please take a look at them? Most of them are trivial and should be considered for upstream.

I am trying to take cleanup thing one-by-one, and keep submitting them. Please let me know if you have any suggestions or pointers for me.

Quoted 10 lines · Paul Walmsley

Quoted 4 lines · Tony Lindgren

How about we add CONFIG_SOC_OMAP3PLUS in the clean-up series? Then this becomes just:

#ifdef CONFIG_SOC_OMAP3PLUS

We might want to consider having separate CONFIG_SOC_* values for each SoC. So rather than CONFIG_SOC_OMAP3PLUS, we'd have CONFIG_SOC_OMAP3430, CONFIG_SOC_OMAP3630, etc.

Hmm but this would be in addition to the SOC specific options. The goal is to cut down the ifdeffery needed all over the place to add new SoCs, see the experimental patch I posted:

http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67938.html

Just to continue exploring just using the SoC specific options, we would currently end up with more of this kind of nastiness:

#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) || \
defined(CONFIG_ARCH_OMAP3))

Quoted 6 lines

The other motivation would be to support device manufacturers who only wish to build a kernel for the single device that they are shipping. In terms of kernels shipped, this is probably the most popular use-case. With something like CONFIG_SOC_OMAPAM33XX, they can avoid building quite a bit of code and data (and potentially bugs) that are not needed for their specific device.

Sure, but I think you're missing the point: This would be in addition to the SoC specific options. Do you still see issues with that?

Quoted 2 lines · Tony Lindgren

http://www.mail-archive.com/linux-omap at vger.kernel.org/msg67938.html

I see. Yeah, the problem is that it's hard to figure out which SoCs should go into SOC_OMAP3PLUS. AM33xx? TI81xx? etc. Some of these chips draw some aspects from chips that we've historically considered part of OMAP3, and other aspects from OMAP4-style chips.

What seems better to me would be to use a more specific, IP block-focused macro as needed. So to pick a random example, in mach-omap2/control.c, we currently skip compilation of the scratchpad functions unless CONFIG_ARCH_OMAP3 is defined. Instead of making this SOC_OMAP3PLUS-dependent, or dependent on a mess of CONFIG_SOC_* macros, maybe something like CONFIG_OMAP3430_SCM_SCRATCHPAD_FORMAT?

Of course, for some of these cases, maybe it makes more sense to move the code out into a separate file, control-omap3-scratchpad.c or something, and just conditionally compile it to avoid the #ifdefs.

OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and with an integrated L2 cache controller.

OMAP5432 is another variant of OMAP5430, with a
memory controller supporting DDR3 and SATA.

Patch includes:
- The machine specific headers and sources updates.
- Platform header updates.
- Minimum initialisation support for serial.
- IO table init

Signed-off-by R Sricharan <[email protected]>

Signed-off-by Santosh Shilimkar <[email protected]>

---
 arch/arm/mach-omap2/Makefile                   |   26 ++++++++++----
 arch/arm/mach-omap2/clock.c                    |    3 +-
 arch/arm/mach-omap2/cminst44xx.h               |    2 +-
 arch/arm/mach-omap2/common.c                   |   24 +++++++++++++
 arch/arm/mach-omap2/common.h                   |   11 ++++++
 arch/arm/mach-omap2/include/mach/debug-macro.S |    8 ++--
 arch/arm/mach-omap2/io.c                       |   44 ++++++++++++++++++++++++
 arch/arm/mach-omap2/iomap.h                    |   27 ++++++++++++++
 arch/arm/mach-omap2/prcm.c                     |    2 +-
 arch/arm/mach-omap2/prm2xxx_3xxx.h             |    5 ++-
 arch/arm/plat-omap/Makefile                    |    4 +--
 arch/arm/plat-omap/include/plat/clkdev_omap.h  |    1 +
 arch/arm/plat-omap/include/plat/clock.h        |    4 ++-
 arch/arm/plat-omap/include/plat/hardware.h     |    1 +
 arch/arm/plat-omap/include/plat/multi.h        |    9 +++++
 arch/arm/plat-omap/include/plat/omap54xx.h     |   32 +++++++++++++++++
 arch/arm/plat-omap/include/plat/serial.h       |   10 +++++
 arch/arm/plat-omap/include/plat/uncompress.h   |    6 +++
 arch/arm/plat-omap/sram.c                      |   11 +++++-
 19 files changed, 208 insertions(+), 22 deletions(-)
 create mode 100644 arch/arm/plat-omap/include/plat/omap54xx.h

arch/arm/mach-omap2/Makefile +19 -7

index 669e2b1..fbb6b3d 100644
@@ -16,6 +16,7 @@ secure-common				= omap-smc.o omap-secure.o
 obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
 obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
+obj-$(CONFIG_ARCH_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
 
 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
 obj-y += mcbsp.o

@@ -27,8 +28,10 @@ obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
 
 obj-$(CONFIG_SMP)			+= omap-smp.o omap-headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)		+= omap-hotplug.o
-obj-$(CONFIG_ARCH_OMAP4)		+= omap4-common.o omap-wakeupgen.o
-obj-$(CONFIG_ARCH_OMAP4)		+= sleep44xx.o
+omap-4-5-common				=  omap4-common.o omap-wakeupgen.o \
+					   sleep44xx.o		
+obj-$(CONFIG_ARCH_OMAP4)		+= $(omap-4-5-common)
+obj-$(CONFIG_ARCH_OMAP5)                += $(omap-4-5-common)
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o			:=-Wa,-march=armv7-a$(plus_sec)

@@ -68,6 +71,7 @@ obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= cpuidle34xx.o
 obj-$(CONFIG_ARCH_OMAP4)		+= pm44xx.o omap-mpuss-lowpower.o
+obj-$(CONFIG_ARCH_OMAP5)		+= omap-mpuss-lowpower.o
 obj-$(CONFIG_ARCH_OMAP4)		+= cpuidle44xx.o
 obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
 obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o

@@ -87,9 +91,11 @@ obj-y					+= prm_common.o
 obj-$(CONFIG_ARCH_OMAP2)		+= prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= vc3xxx_data.o vp3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)		+= prcm.o cminst44xx.o cm44xx.o
-obj-$(CONFIG_ARCH_OMAP4)		+= prcm_mpu44xx.o prminst44xx.o
-obj-$(CONFIG_ARCH_OMAP4)		+= vc44xx_data.o vp44xx_data.o prm44xx.o
+omap-prcm-4-5-common			=  prcm.o cminst44xx.o cm44xx.o \
+					   prcm_mpu44xx.o prminst44xx.o \
+					   vc44xx_data.o vp44xx_data.o
+obj-$(CONFIG_ARCH_OMAP4)		+= $(omap-prcm-4-5-common) prm44xx.o
+obj-$(CONFIG_ARCH_OMAP5)                += $(omap-prcm-4-5-common)
 
 # OMAP voltage domains
 voltagedomain-common			:= voltage.o vc.o vp.o

@@ -99,6 +105,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP3)		+= voltagedomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP4)		+= voltagedomains44xx_data.o
+obj-$(CONFIG_ARCH_OMAP5)		+= $(voltagedomain-common)
 
 # OMAP powerdomain framework
 powerdomain-common			+= powerdomain.o powerdomain-common.o

@@ -113,6 +120,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= powerdomains2xxx_3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)		+= powerdomain44xx.o
 obj-$(CONFIG_ARCH_OMAP4)		+= powerdomains44xx_data.o
+obj-$(CONFIG_ARCH_OMAP5)                += $(powerdomain-common) powerdomain44xx.o
 
 # PRCM clockdomain control
 obj-$(CONFIG_ARCH_OMAP2)		+= clockdomain.o

@@ -124,9 +132,11 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clockdomain.o
 obj-$(CONFIG_ARCH_OMAP3)		+= clockdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)		+= clockdomains2xxx_3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)		+= clockdomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)		+= clockdomain.o
-obj-$(CONFIG_ARCH_OMAP4)		+= clockdomain44xx.o
+omap-clock-4-5-common			= clockdomain.o \
+					  clockdomain44xx.o
+obj-$(CONFIG_ARCH_OMAP4)		+= $(omap-clock-4-5-common)
 obj-$(CONFIG_ARCH_OMAP4)		+= clockdomains44xx_data.o
+obj-$(CONFIG_ARCH_OMAP5)		+= $(omap-clock-4-5-common)
 
 # Clock framework
 obj-$(CONFIG_ARCH_OMAP2)		+= $(clock-common) clock2xxx.o

@@ -144,6 +154,8 @@ obj-$(CONFIG_ARCH_OMAP3)		+= dpll3xxx.o clock3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)		+= clkt_iclk.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common) clock44xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)		+= dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_ARCH_OMAP5)		+= $(clock-common)
+obj-$(CONFIG_ARCH_OMAP5)		+= dpll3xxx.o dpll44xx.o
 
 # OMAP2 clock rate set data (old "OPP" data)
 obj-$(CONFIG_SOC_OMAP2420)		+= opp2420_data.o

arch/arm/mach-omap2/clock.c +2 -1

index d9f4931..c589bb8 100644
@@ -400,7 +400,8 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 
 /* OMAP3/4 non-CORE DPLL clkops */
 
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
+				defined(CONFIG_ARCH_OMAP5)
 
 const struct clkops clkops_omap3_noncore_dpll_ops = {
 	.enable		= omap3_noncore_dpll_enable,

arch/arm/mach-omap2/cminst44xx.h +1 -1

index a018a73..da67e08 100644
@@ -19,7 +19,7 @@ extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
 
 extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
 
-# ifdef CONFIG_ARCH_OMAP4
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
 extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
 					 u16 clkctrl_offs);
 

arch/arm/mach-omap2/common.c +0 -0

index 8a6953a..a0e74b9 100644
@@ -182,3 +182,27 @@ void __init omap4_map_io(void)
 }
 #endif
 

arch/arm/mach-omap2/common.c +14 -0

+};
+
+void __init omap2_set_globals_543x(void)
+{
+	omap2_set_globals_tap(&omap5_globals);
+	omap2_set_globals_control(&omap5_globals);
+	omap2_set_globals_prcm(&omap5_globals);
+}
+
+void __init omap5_map_io(void)
+{
+	omap5_map_common_io();
+}
+#endif

arch/arm/mach-omap2/common.h +0 -0

index 0672fc5..797dda7 100644

arch/arm/mach-omap2/common.h +3 -0

+#endif
+
 extern void omap2_init_common_infrastructure(void);
 
 extern struct sys_timer omap2_timer;

@@ -94,6 +102,7 @@ void omap3_init_early(void);	/* Do not use this one */
 void am35xx_init_early(void);
 void ti81xx_init_early(void);
 void omap4430_init_early(void);
+void omap5_init_early(void);
 void omap_prcm_restart(char, const char *);
 
 /*

Quoted 5 lines

- ? ? if (!(cpu_is_omap44xx()))
+ ? ? if ((!(cpu_is_omap44xx())) && (!cpu_is_omap54xx())) ? ? ? ? ? ? ? return -ENODEV;

? ? ? for (i = 0; i < L3_MODULES; i++) {

Isn't there some unnecessary parens here?

Hi Tony,

Quoted 4 lines

Quoted 4 lines

- ? ? if (!(cpu_is_omap44xx()))
+ ? ? if ((!(cpu_is_omap44xx())) && (!cpu_is_omap54xx())) ? ? ? ? ? ? ? return -ENODEV;

Quoted 3 lines

Quoted 1 line

? ? ? for (i = 0; i < L3_MODULES; i++) {

Isn't there some unnecessary parens here?

You mean in this above for loop?.
There are multiple statements .

Quoted 6 lines · R, Sricharan

Hi Tony,

Quoted 4 lines

Quoted 4 lines

- ? ? if (!(cpu_is_omap44xx()))
+ ? ? if ((!(cpu_is_omap44xx())) && (!cpu_is_omap54xx())) ? ? ? ? ? ? ? return -ENODEV;

Quoted 6 lines

Quoted 3 lines

Quoted 1 line

? ? ? for (i = 0; i < L3_MODULES; i++) {

Isn't there some unnecessary parens here?

?You mean in this above for loop?.
?There are multiple statements .

No, both the old (!(cpu_is_omap44xx())) and the added one.

arch/arm/mach-omap2/omap-hotplug.c +12 -5

@@ -17,8 +17,10 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
+#include <linux/io.h>
 
 #include <asm/cacheflush.h>
+#include <mach/omap-wakeupgen.h>
 
 #include "common.h"
 

@@ -35,7 +37,8 @@ int platform_cpu_kill(unsigned int cpu)
  */
 void __ref platform_cpu_die(unsigned int cpu)
 {
-	unsigned int this_cpu;
+	unsigned int boot_cpu = 0;
+	void __iomem *base = omap_get_wakeupgen_base();
 
 	flush_cache_all();
 	dsb();

@@ -43,16 +46,27 @@ void __ref platform_cpu_die(unsigned int cpu)
 	/*
 	 * we're ready for shutdown now, so do it
 	 */
-	if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
-		pr_err("Secure clear status failed\n");
+	if (cpu_is_omap44xx()) {
+		if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
+			pr_err("Secure clear status failed\n");
+	} else {
+		__raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
+	}
+
 
 	for (;;) {
 		/*
 		 * Enter into low power state
 		 */
 		omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
-		this_cpu = smp_processor_id();
-		if (omap_read_auxcoreboot0() == this_cpu) {
+

arch/arm/mach-omap2/omap-hotplug.c +7 -1

@@ -85,7 +89,11 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 	 * the AuxCoreBoot1 register is updated with cpu state
 	 * A barrier is added to ensure that write buffer is drained
 	 */
-	omap_modify_auxcoreboot0(0x200, 0xfffffdff);
+	if (cpu_is_omap44xx())
+		omap_modify_auxcoreboot0(0x200, 0xfffffdff);
+	else
+		__raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
+
 	flush_cache_all();
 	smp_wmb();
 

@@ -124,13 +132,20 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 
 static void __init wakeup_secondary(void)
 {
+	void __iomem *base = omap_get_wakeupgen_base();
+
 	/*
 	 * Write the address of secondary startup routine into the
 	 * AuxCoreBoot1 where ROM code will jump and start executing
 	 * on secondary core once out of WFE
 	 * A barrier is added to ensure that write buffer is drained
 	 */

Quoted 50 lines · R Sricharan

arch/arm/mach-omap2/omap-hotplug.c +17 -5

@@ -17,8 +17,10 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
+#include <linux/io.h>
 
 #include <asm/cacheflush.h>
+#include <mach/omap-wakeupgen.h>
 
 #include "common.h"
 

@@ -35,7 +37,8 @@ int platform_cpu_kill(unsigned int cpu)
  */
 void __ref platform_cpu_die(unsigned int cpu)
 {
-	unsigned int this_cpu;
+	unsigned int boot_cpu = 0;
+	void __iomem *base = omap_get_wakeupgen_base();
 
 	flush_cache_all();
 	dsb();

@@ -43,16 +46,27 @@ void __ref platform_cpu_die(unsigned int cpu)
 	/*
 	 * we're ready for shutdown now, so do it
 	 */
-	if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
-		pr_err("Secure clear status failed\n");
+	if (cpu_is_omap44xx()) {
+		if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
+			pr_err("Secure clear status failed\n");
+	} else {
+		__raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
+	}
+
 
 	for (;;) {
 		/*
 		 * Enter into low power state
 		 */
 		omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
-		this_cpu = smp_processor_id();
-		if (omap_read_auxcoreboot0() == this_cpu) {
+
+		if (cpu_is_omap44xx())
+			boot_cpu = omap_read_auxcoreboot0();
+		else
+			boot_cpu =
+				__raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;

arch/arm/mach-omap2/omap-hotplug.c void __ref platform_cpu_die(unsigned int cpu) · line 72

Quoted 5 lines

arch/arm/mach-omap2/omap-hotplug.c +2 -0

+
+		if (boot_cpu == smp_processor_id()) {
 			/*
 			 * OK, proper wakeup, we're done
 			 */

These should use variables set up during init instead of cpu_is_omapxxx checks.

From: Santosh Shilimkar <[email protected]>

OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
- Additional 32 interrupt support is added w.r.t OMAP4 design.
- The AUX CORE boot registers are now made accessible from non-secure SW.
- SAR offset are changed and PTMSYNC* registers are removed from SAR.

Patch updates the WakeupGen code accordingly.

Signed-off-by Santosh Shilimkar <[email protected]>

Signed-off-by R Sricharan <[email protected]>

---
 arch/arm/mach-omap2/include/mach/omap-wakeupgen.h |    6 +
 arch/arm/mach-omap2/omap-hotplug.c                |   24 ++++-
 arch/arm/mach-omap2/omap-smp.c                    |   19 +++-
 arch/arm/mach-omap2/omap-wakeupgen.c              |  110 +++++++++++++++-----
 arch/arm/mach-omap2/omap4-sar-layout.h            |   12 ++-
 5 files changed, 135 insertions(+), 36 deletions(-)

arch/arm/mach-omap2/include/mach/omap-wakeupgen.h +0 -0

index 548de90..4d700bc 100644

arch/arm/mach-omap2/include/mach/omap-wakeupgen.h +4 -0

+
 #define OMAP_WKG_CONTROL_0			0x00
 #define OMAP_WKG_ENB_A_0			0x10
 #define OMAP_WKG_ENB_B_0			0x14
 #define OMAP_WKG_ENB_C_0			0x18
 #define OMAP_WKG_ENB_D_0			0x1c
+#define OMAP_WKG_ENB_E_0			0x20
 #define OMAP_WKG_ENB_A_1			0x410
 #define OMAP_WKG_ENB_B_1			0x414
 #define OMAP_WKG_ENB_C_1			0x418
 #define OMAP_WKG_ENB_D_1			0x41c
+#define OMAP_WKG_ENB_E_1			0x420
 #define OMAP_AUX_CORE_BOOT_0			0x800
 #define OMAP_AUX_CORE_BOOT_1			0x804
 #define OMAP_PTMSYNCREQ_MASK			0xc00

@@ -28,4 +33,5 @@
 #define OMAP_TIMESTAMPCYCLEHI			0xc0c
 
 extern int __init omap_wakeupgen_init(void);
+extern void __iomem *omap_get_wakeupgen_base(void);
 #endif

arch/arm/mach-omap2/omap-hotplug.c +2 -0

index 56c345b..052303c 100644
@@ -17,8 +17,10 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
+#include <linux/io.h>
 
 #include <asm/cacheflush.h>
+#include <mach/omap-wakeupgen.h>
 
 #include "common.h"
 

arch/arm/mach-omap2/omap-hotplug.c +11 -2

+		__raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
+	}
+
 
 	for (;;) {
 		/*
 		 * Enter into low power state
 		 */
 		omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
-		this_cpu = smp_processor_id();
-		if (omap_read_auxcoreboot0() == this_cpu) {
+
+		if (cpu_is_omap44xx())
+			boot_cpu = omap_read_auxcoreboot0();
+		else
+			boot_cpu =
+				__raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;
+
+		if (boot_cpu == smp_processor_id()) {
 			/*
 			 * OK, proper wakeup, we're done
 			 */

arch/arm/mach-omap2/omap-smp.c +2 -0

index deffbf1..151fd5b 100644
@@ -26,6 +26,8 @@
 
 #include <mach/hardware.h>
 #include <mach/omap-secure.h>
+#include <mach/omap-wakeupgen.h>
+#include <asm/cputype.h>
 
 #include "iomap.h"
 #include "common.h"

arch/arm/mach-omap2/omap-smp.c +6 -1

 	/*
 	 * Write the address of secondary startup routine into the
 	 * AuxCoreBoot1 where ROM code will jump and start executing
 	 * on secondary core once out of WFE
 	 * A barrier is added to ensure that write buffer is drained
 	 */
-	omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
+	if (cpu_is_omap44xx())
+		omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
+	else
+		__raw_writel(virt_to_phys(omap5_secondary_startup),
+						base + OMAP_AUX_CORE_BOOT_1);
+
 	smp_wmb();
 
 	/*

arch/arm/mach-omap2/omap-wakeupgen.c +10 -11

index 42cd7fb..444cf12 100644
@@ -33,18 +33,22 @@
 #include "omap4-sar-layout.h"
 #include "common.h"
 
-#define NR_REG_BANKS		4
-#define MAX_IRQS		128
+#define MAX_NR_REG_BANKS	5
+#define MAX_IRQS		160
 #define WKG_MASK_ALL		0x00000000
 #define WKG_UNMASK_ALL		0xffffffff
 #define CPU_ENA_OFFSET		0x400
 #define CPU0_ID			0x0
 #define CPU1_ID			0x1
+#define OMAP4_NR_BANKS		4
+#define OMAP4_NR_IRQS		128
 
 static void __iomem *wakeupgen_base;
 static void __iomem *sar_base;
 static DEFINE_SPINLOCK(wakeupgen_lock);
 static unsigned int irq_target_cpu[NR_IRQS];
+static unsigned int irq_banks = MAX_NR_REG_BANKS;
+static unsigned int max_irqs = MAX_IRQS;
 
 /*
  * Static helper functions.

@@ -146,13 +150,13 @@ static void wakeupgen_unmask(struct irq_data *d)
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
-static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
+static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
 
 static void _wakeupgen_save_masks(unsigned int cpu)
 {
 	u8 i;
 
-	for (i = 0; i < NR_REG_BANKS; i++)
+	for (i = 0; i < irq_banks; i++)
 		per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
 }
 

@@ -160,7 +164,7 @@ static void _wakeupgen_restore_masks(unsigned int cpu)
 {
 	u8 i;
 
-	for (i = 0; i < NR_REG_BANKS; i++)
+	for (i = 0; i < irq_banks; i++)
 		wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
 }
 

@@ -168,7 +172,7 @@ static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
 {
 	u8 i;
 
-	for (i = 0; i < NR_REG_BANKS; i++)
+	for (i = 0; i < irq_banks; i++)
 		wakeupgen_writel(reg, i, cpu);
 }
 

@@ -196,25 +200,11 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
 #endif
 
 #ifdef CONFIG_CPU_PM
-/*
- * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
- * ROM code. WakeupGen IP is integrated along with GIC to manage the
- * interrupt wakeups from CPU low power states. It manages
- * masking/unmasking of Shared peripheral interrupts(SPI). So the

arch/arm/mach-omap2/omap-wakeupgen.c +31 -5

-
-	if (!sar_base)
-		sar_base = omap4_get_sar_ram_base();
-
-	for (i = 0; i < NR_REG_BANKS; i++) {
+	for (i = 0; i < irq_banks; i++) {
 		/* Save the CPUx interrupt mask for IRQ 0 to 127 */
 		val = wakeupgen_readl(i, 0);
 		sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);

@@ -254,6 +244,53 @@ static void irq_save_context(void)
 	val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
 	val |= SAR_BACKUP_STATUS_WAKEUPGEN;
 	__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+
+}
+
+static inline void omap5_irq_save_context(void)
+{
+	u32 i, val;
+
+	for (i = 0; i < irq_banks; i++) {
+		/* Save the CPUx interrupt mask for IRQ 0 to 159 */
+		val = wakeupgen_readl(i, 0);
+		sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
+		val = wakeupgen_readl(i, 1);
+		sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
+		sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
+		sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
+	}
+
+	/* Save AuxBoot* registers */
+	val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+	__raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
+	val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+	__raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
+
+	/* Set the Backup Bit Mask status */
+	val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
+	val |= SAR_BACKUP_STATUS_WAKEUPGEN;
+	__raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
+
+}
+

arch/arm/mach-omap2/omap-wakeupgen.c +22 -3

+	if (!sar_base)
+		sar_base = omap4_get_sar_ram_base();
+
+	if (cpu_is_omap54xx())
+		omap5_irq_save_context();
+	else
+		omap4_irq_save_context();
 }
 
 /*

@@ -262,9 +299,14 @@ static void irq_save_context(void)
 void irq_sar_clear(void)
 {
 	u32 val;
-	val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
+	u32 offset = SAR_BACKUP_STATUS_OFFSET;
+
+	if (cpu_is_omap54xx())
+		offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
+
+	val = __raw_readl(sar_base + offset);
 	val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
-	__raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+	__raw_writel(val, sar_base + offset);
 }
 
 /*

@@ -336,13 +378,20 @@ static struct notifier_block irq_notifier_block = {
 
 static void __init irq_pm_init(void)
 {
-	cpu_pm_register_notifier(&irq_notifier_block);
+	/* FIXME: Remove this when MPU OSWR support is added */
+	if (!cpu_is_omap54xx())
+		cpu_pm_register_notifier(&irq_notifier_block);
 }
 #else
 static void __init irq_pm_init(void)
 {}
 #endif
 
+void __iomem *omap_get_wakeupgen_base(void)
+{
+	return wakeupgen_base;
+}
+
 /*
  * Initialise the wakeupgen module.
  */

arch/arm/mach-omap2/omap-wakeupgen.c +7 -2

 	if (WARN_ON(!wakeupgen_base))
 		return -ENOMEM;
 
+	if (cpu_is_omap44xx()) {
+		irq_banks = OMAP4_NR_BANKS;
+		max_irqs = OMAP4_NR_IRQS;
+	}
+
 	/* Clear all IRQ bitmasks at wakeupGen level */
-	for (i = 0; i < NR_REG_BANKS; i++) {
+	for (i = 0; i < irq_banks; i++) {
 		wakeupgen_writel(0, i, CPU0_ID);
 		wakeupgen_writel(0, i, CPU1_ID);
 	}

@@ -382,7 +436,7 @@ int __init omap_wakeupgen_init(void)
 	 */
 
 	/* Associate all the IRQs to boot CPU like GIC init does. */
-	for (i = 0; i < NR_IRQS; i++)
+	for (i = 0; i < max_irqs; i++)
 		irq_target_cpu[i] = boot_cpu;
 
 	irq_hotplug_init();

arch/arm/mach-omap2/omap4-sar-layout.h +2 -1

index fe5b545..e170fe8 100644
@@ -12,7 +12,7 @@
 #define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
 
 /*
- * SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE
+ * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE
  */
 #define SAR_BANK1_OFFSET		0x0000
 #define SAR_BANK2_OFFSET		0x1000

@@ -47,4 +47,14 @@
 #define PTMSYNCREQ_EN_OFFSET			(SAR_BANK3_OFFSET + 0x6d0)
 #define SAR_BACKUP_STATUS_WAKEUPGEN		0x10
 
+/* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */

Hi,

Quoted 27 lines · R Sricharan

From: Santosh Shilimkar <[email protected]>

OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
- Additional 32 interrupt support is added w.r.t OMAP4 design.
- The AUX CORE boot registers are now made accessible from non-secure SW.
- SAR offset are changed and PTMSYNC* registers are removed from SAR.

Patch updates the WakeupGen code accordingly.

Signed-off-by Santosh Shilimkar <[email protected]>

Signed-off-by R Sricharan <[email protected]>

---

?arch/arm/mach-omap2/include/mach/omap-wakeupgen.h | ? ?6 +
?arch/arm/mach-omap2/omap-hotplug.c ? ? ? ? ? ? ? ?| ? 24 ++++-
?arch/arm/mach-omap2/omap-smp.c ? ? ? ? ? ? ? ? ? ?| ? 19 +++-
?arch/arm/mach-omap2/omap-wakeupgen.c ? ? ? ? ? ? ?| ?110 +++++++++++++++-----
?arch/arm/mach-omap2/omap4-sar-layout.h ? ? ? ? ? ?| ? 12 ++-

?5 files changed, 135 insertions(+), 36 deletions(-)

arch/arm/mach-omap2/include/mach/omap-wakeupgen.h +0 -0

index 548de90..4d700bc 100644
@@ -11,15 +11,20 @@

?#ifndef OMAP_ARCH_WAKEUPGEN_H
?#define OMAP_ARCH_WAKEUPGEN_H

arch/arm/mach-omap2/include/mach/omap-wakeupgen.h

Quoted 2 lines

arch/arm/mach-omap2/include/mach/omap-wakeupgen.h +2 -0

+/* OMAP4 and OMAP5 has same base address */
+#define OMAP_WKUPGEN_BASE ? ? ? ? ? ? ? ? ? ?0x48281000

unnecessary change, why don't you just use OMAP44XX_WKUPGEN_BASE or define this in the same header as OMAP44XX_WKUPGEN_BASE?

Quoted 30 lines · Roger Quadros

Hi,

Quoted 27 lines · R Sricharan

From: Santosh Shilimkar <[email protected]>

OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
- Additional 32 interrupt support is added w.r.t OMAP4 design.
- The AUX CORE boot registers are now made accessible from non-secure SW.
- SAR offset are changed and PTMSYNC* registers are removed from SAR.

Patch updates the WakeupGen code accordingly.

Signed-off-by Santosh Shilimkar <[email protected]>

Signed-off-by R Sricharan <[email protected]>

---
 arch/arm/mach-omap2/include/mach/omap-wakeupgen.h |    6 +
 arch/arm/mach-omap2/omap-hotplug.c                |   24 ++++-
 arch/arm/mach-omap2/omap-smp.c                    |   19 +++-
 arch/arm/mach-omap2/omap-wakeupgen.c              |  110 +++++++++++++++-----
 arch/arm/mach-omap2/omap4-sar-layout.h            |   12 ++-
 5 files changed, 135 insertions(+), 36 deletions(-)

arch/arm/mach-omap2/include/mach/omap-wakeupgen.h +0 -0

index 548de90..4d700bc 100644
@@ -11,15 +11,20 @@
 #ifndef OMAP_ARCH_WAKEUPGEN_H
 #define OMAP_ARCH_WAKEUPGEN_H
 

Quoted 6 lines

arch/arm/mach-omap2/include/mach/omap-wakeupgen.h line 15

Quoted 2 lines

arch/arm/mach-omap2/include/mach/omap-wakeupgen.h +2 -0

+/* OMAP4 and OMAP5 has same base address */
+#define OMAP_WKUPGEN_BASE                    0x48281000

unnecessary change, why don't you just use OMAP44XX_WKUPGEN_BASE or define this in the same header as OMAP44XX_WKUPGEN_BASE?

Just to avoid confusion about OMAP44XX and OMAP54XX. It's cleaner to remove the OMAP44XX reference if the base is generic and not depend on OMAP4/5.

It's not un-necessary change as such.

Quoted 41 lines · Santosh

Quoted 30 lines · Roger Quadros

Hi,

Quoted 27 lines · R Sricharan

From: Santosh Shilimkar <[email protected]>

OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
- Additional 32 interrupt support is added w.r.t OMAP4 design.
- The AUX CORE boot registers are now made accessible from non-secure SW.
- SAR offset are changed and PTMSYNC* registers are removed from SAR.

Patch updates the WakeupGen code accordingly.

Signed-off-by Santosh Shilimkar <[email protected]>

Signed-off-by R Sricharan <[email protected]>

---
 arch/arm/mach-omap2/include/mach/omap-wakeupgen.h |    6 +
 arch/arm/mach-omap2/omap-hotplug.c                |   24 ++++-
 arch/arm/mach-omap2/omap-smp.c                    |   19 +++-
 arch/arm/mach-omap2/omap-wakeupgen.c              |  110 +++++++++++++++-----
 arch/arm/mach-omap2/omap4-sar-layout.h            |   12 ++-
 5 files changed, 135 insertions(+), 36 deletions(-)

arch/arm/mach-omap2/include/mach/omap-wakeupgen.h +0 -0

index 548de90..4d700bc 100644
@@ -11,15 +11,20 @@
 #ifndef OMAP_ARCH_WAKEUPGEN_H
 #define OMAP_ARCH_WAKEUPGEN_H
 

Quoted 6 lines

arch/arm/mach-omap2/include/mach/omap-wakeupgen.h line 15

Quoted 2 lines

arch/arm/mach-omap2/include/mach/omap-wakeupgen.h +2 -0

+/* OMAP4 and OMAP5 has same base address */
+#define OMAP_WKUPGEN_BASE                    0x48281000

unnecessary change, why don't you just use OMAP44XX_WKUPGEN_BASE or define this in the same header as OMAP44XX_WKUPGEN_BASE?

Just to avoid confusion about OMAP44XX and OMAP54XX. It's cleaner to remove the OMAP44XX reference if the base is generic and not depend on OMAP4/5.

Quoted 2 lines

It's not un-necessary change as such.

OK, is OMAP_WKUPGEN_BASE applicable for OMAPs prior to OMAP4? If not the naming scheme does not look appropriate.

From: Santosh Shilimkar <[email protected]>

Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths are runtime checked using cpu id

Signed-off-by Santosh Shilimkar <[email protected]>

Signed-off-by R Sricharan <[email protected]>

---
 arch/arm/mach-omap2/common.h       |    1 +
 arch/arm/mach-omap2/omap-headsmp.S |   21 ++++++++++++++++++
 arch/arm/mach-omap2/omap-smp.c     |   41 +++++++++++++++++++++++++----------
 3 files changed, 51 insertions(+), 12 deletions(-)

arch/arm/mach-omap2/omap-smp.c +4 -0

index 151fd5b..9424bb6 100644
@@ -33,6 +33,10 @@
 #include "common.h"
 #include "clockdomain.h"
 
+#define CPU_MASK		0xff0ffff0
+#define CPU_CORTEX_A9		0x410FC090
+#define CPU_CORTEX_A15		0x410FC0F0
+
 /* SCU base address */
 static void __iomem *scu_base;
 

Hello,

Quoted 12 lines · R Sricharan

From: Santosh Shilimkar <[email protected]>

Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths are runtime checked using cpu id

Signed-off-by Santosh Shilimkar <[email protected]>

Signed-off-by R Sricharan <[email protected]>

---
 arch/arm/mach-omap2/common.h       |    1 +
 arch/arm/mach-omap2/omap-headsmp.S |   21 ++++++++++++++++++
 arch/arm/mach-omap2/omap-smp.c     |   41 +++++++++++++++++++++++++----------
 3 files changed, 51 insertions(+), 12 deletions(-)

[...]

Quoted 19 lines

arch/arm/mach-omap2/omap-smp.c +4 -0

index 151fd5b..9424bb6 100644
@@ -33,6 +33,10 @@
 #include "common.h"
 #include "clockdomain.h"
 
+#define CPU_MASK		0xff0ffff0
+#define CPU_CORTEX_A9		0x410FC090
+#define CPU_CORTEX_A15		0x410FC0F0
+
 /* SCU base address */
 static void __iomem *scu_base;
 

@@ -43,6 +47,14 @@ void __iomem *omap4_get_scu_base(void)
 	return scu_base;
 }
 

arch/arm/mach-omap2/omap-smp.c void __iomem *omap4_get_scu_base(void) · line 56

Quoted 7 lines

arch/arm/mach-omap2/omap-smp.c +7 -0

+static inline unsigned int get_a15_core_count(void)
+{
+	unsigned int ncores;
+
+	asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (ncores));
+	return ((ncores >> 24) & 3) + 1;
+}

This register (L2 control) only tells you how many cores you have hanging off the L2 cache, which isn't really viable for future multi-cluster configurations. You're probably better off either reading the number of CPU nodes out of the DT (ppc, vexpress) or returning a constant for now (exynos5).

Adding the minimal support for OMAP5 soc with device tree.

Signed-off-by R Sricharan<[email protected]>

---
  arch/arm/mach-omap2/board-generic.c |   39 +++++++++++++++++++++-------------
  arch/arm/mach-omap2/common.h        |    2 +
  arch/arm/mach-omap2/irq.c           |   11 +++++++++
  arch/arm/mach-omap2/omap4-common.c  |   14 ++++++++++++
  4 files changed, 51 insertions(+), 15 deletions(-)

arch/arm/mach-omap2/board-generic.c +24 -15

index 098d183..0dd9e3f 100644
@@ -20,6 +20,7 @@
  #include<mach/hardware.h>
  #include<asm/hardware/gic.h>
  #include<asm/mach/arch.h>
+#include<mach/omap-wakeupgen.h>
 
  #include<plat/board.h>
  #include "common.h"

@@ -32,17 +33,6 @@
  #define gic_of_init		NULL
  #endif
 
-static struct of_device_id irq_match[] __initdata = {
-	{ .compatible = "ti,omap2-intc", .data = omap_intc_of_init, },
-	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-	{ }
-};
-
-static void __init omap_init_irq(void)
-{
-	of_irq_init(irq_match);
-}
-
  static struct of_device_id omap_dt_match_table[] __initdata = {
  	{ .compatible = "simple-bus", },
  	{ .compatible = "ti,omap-infra", },

@@ -66,7 +56,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
  	.reserve	= omap_reserve,
  	.map_io		= omap242x_map_io,
  	.init_early	= omap2420_init_early,
-	.init_irq	= omap_init_irq,
+	.init_irq	= omap_of_init_irq,
  	.handle_irq	= omap2_intc_handle_irq,
  	.init_machine	= omap_generic_init,
  	.timer		=&omap2_timer,

@@ -85,7 +75,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
  	.reserve	= omap_reserve,
  	.map_io		= omap243x_map_io,
  	.init_early	= omap2430_init_early,
-	.init_irq	= omap_init_irq,
+	.init_irq	= omap_of_init_irq,
  	.handle_irq	= omap2_intc_handle_irq,
  	.init_machine	= omap_generic_init,
  	.timer		=&omap2_timer,

@@ -120,7 +110,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
  	.reserve	= omap_reserve,
  	.map_io		= omap3_map_io,
  	.init_early	= omap3430_init_early,
-	.init_irq	= omap_init_irq,
+	.init_irq	= omap_of_init_irq,
  	.handle_irq	= omap3_intc_handle_irq,
  	.init_machine	= omap3_init,
  	.timer		=&omap3_timer,

@@ -155,7 +145,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
  	.reserve	= omap_reserve,
  	.map_io		= omap4_map_io,
  	.init_early	= omap4430_init_early,
-	.init_irq	= omap_init_irq,
+	.init_irq	= omap_gic_of_init,
  	.handle_irq	= gic_handle_irq,
  	.init_machine	= omap4_init,
  	.timer		=&omap4_timer,

@@ -163,3 +153,22 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
  	.restart	= omap_prcm_restart,
  MACHINE_END
  #endif
+
+#ifdef CONFIG_ARCH_OMAP5
+static const char *omap5_boards_compat[] __initdata = {
+	"ti,omap5",
+	NULL,
+};
+
+DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
+	.reserve	= omap_reserve,
+	.map_io		= omap5_map_io,
+	.init_early	= omap5_init_early,
+	.init_irq	= omap_gic_of_init,
+	.handle_irq	= gic_handle_irq,
+	.init_machine	= omap_generic_init,
+	.timer		=&omap5_timer,
+	.dt_compat	= omap5_boards_compat,
+	.restart	= omap_prcm_restart,
+MACHINE_END
+#endif

arch/arm/mach-omap2/common.h +0 -0

index 0771d22..e66859d 100644