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ARM: OMAP2+: remove incorrect irq_chip ack field

PATCH New Grazvydas Ignotas 2 participants 2 messages May 5, 2012 – May 9, 2012

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Arm (32-bit) Arm sub-architectures OMAP2+ support
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Grazvydas Ignotas

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#0 lore raw

PATCH 1/1 ARM: OMAP2+: remove incorrect irq_chip ack field

Each irq_chip for the main interrupt controller has offsets set for irq masking registers, which added to respective base results in a pointer to appropriate hardware register. However this is not correct for INTC_CONTROL as there is only one INTC_CONTROL register. This does not cause problems because generic ack code is never called, but remove this assignment to avoid confusion.

Signed-off-by Grazvydas Ignotas <[email protected]>
---
 arch/arm/mach-omap2/irq.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)
arch/arm/mach-omap2/irq.c +0 -1
index 65f0d25..c11e8a8 100644
@@ -149,7 +149,6 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
 	ct->chip.irq_mask = irq_gc_mask_disable_reg;
 	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
 
-	ct->regs.ack = INTC_CONTROL;
 	ct->regs.enable = INTC_MIR_CLEAR0;
 	ct->regs.disable = INTC_MIR_SET0;
 	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
Signature · 1 line
1.7.0.4
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#1 lore raw

PATCH 1/1 ARM: OMAP2+: remove incorrect irq_chip ack field

Quoted 6 lines · Grazvydas Ignotas

Each irq_chip for the main interrupt controller has offsets set for irq masking registers, which added to respective base results in a pointer to appropriate hardware register. However this is not correct for INTC_CONTROL as there is only one INTC_CONTROL register. This does not cause problems because generic ack code is never called, but remove this assignment to avoid confusion.

Thanks applying into fixes-non-critical.

Regards,

Tony

Quoted 20 lines
Signed-off-by Grazvydas Ignotas <[email protected]>
---
 arch/arm/mach-omap2/irq.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)
arch/arm/mach-omap2/irq.c +0 -1
index 65f0d25..c11e8a8 100644
@@ -149,7 +149,6 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
 	ct->chip.irq_mask = irq_gc_mask_disable_reg;
 	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
 
-	ct->regs.ack = INTC_CONTROL;
 	ct->regs.enable = INTC_MIR_CLEAR0;
 	ct->regs.disable = INTC_MIR_SET0;
 	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
Signature · 1 line
1.7.0.4