arm: Add basic support for new Marvell Armada SoC family

From: Gregory CLEMENT <[email protected]>

This patch adds basic header files for Armada SoCs.

Signed-off-by Gregory CLEMENT <[email protected]>

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Lior Amsalem <[email protected]>

---
 arch/arm/mach-armada/include/mach/armada.h      |  234 +++++++++++++++++++++++
 arch/arm/mach-armada/include/mach/bridge-regs.h |   28 +++
 arch/arm/mach-armada/include/mach/debug-macro.S |   23 +++
 arch/arm/mach-armada/include/mach/gpio.h        |   13 ++
 arch/arm/mach-armada/include/mach/hardware.h    |   18 ++
 arch/arm/mach-armada/include/mach/io.h          |   24 +++
 arch/arm/mach-armada/include/mach/irqs.h        |   96 ++++++++++
 arch/arm/mach-armada/include/mach/system.h      |   21 ++
 arch/arm/mach-armada/include/mach/timex.h       |   13 ++
 arch/arm/mach-armada/include/mach/uncompress.h  |   41 ++++
 10 files changed, 511 insertions(+)
 create mode 100644 arch/arm/mach-armada/include/mach/armada.h
 create mode 100644 arch/arm/mach-armada/include/mach/bridge-regs.h
 create mode 100644 arch/arm/mach-armada/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-armada/include/mach/gpio.h
 create mode 100644 arch/arm/mach-armada/include/mach/hardware.h
 create mode 100644 arch/arm/mach-armada/include/mach/io.h
 create mode 100644 arch/arm/mach-armada/include/mach/irqs.h
 create mode 100644 arch/arm/mach-armada/include/mach/system.h
 create mode 100644 arch/arm/mach-armada/include/mach/timex.h
 create mode 100644 arch/arm/mach-armada/include/mach/uncompress.h

arch/arm/mach-armada/include/mach/armada.h new file +211 -0

new file mode 100644
index 0000000..be12667
@@ -0,0 +1,234 @@
+/*
+ * Generic definitions for Marvell Armada SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_ARMADA_H
+#define __MACH_ARMADA_H
+
+/*
+ * Marvell ARMADA address maps.
+ *
+ * phys		virt		size
+ * d0000000	feb00000	1M	internal registers
+ * d0100000	@runtime	1M	uart
+ * d0200000	fec00000	1M	PCIe-0 I/O (port 0.0)
+ * d0300000	fed00000	1M	PCIe-1 I/O (port 1.0)
+ * d0400000	fee00000	1M	PCIe-2 I/O (port 2.0)
+ * d0500000	fef00000	1M	PCIe-3 I/O (port 3.0)
+ * d0600000	@runtime	1M	cryptographic sram-0
+ * d0700000	@runtime	1M	cryptographic sram-1
+ * d0800000	reserved	8M	reserved for future
+ * d1000000	@runtime	16M	device bus cs-0
+ * d2000000	@runtime	16M	device bus cs-0
+ * d3000000	@runtime	16M	device bus cs-0
+ * d4000000	@runtime	16M	device bus cs-0
+ * d5000000	@runtime	16M	device bus boot cs
+ * d6000000	@runtime	16M	spi-0 flash
+ * d7000000	@runtime	16M	spi-1 flash
+ * d8000000	@runtime	64M	PCIe-0 Memory (port 0.0)
+ * dc000000	@runtime	64M	PCIe-1 Memory (port 1.0)
+ * e0000000	@runtime	64M	PCIe-2 Memory (port 2.0)
+ * e4000000	@runtime	64M	PCIe-3 Memory (port 3.0)
+ * fff00000	@runtime	1M	internal bootrom
+ */
+
+#define ARMADA_REGS_PHYS_BASE		0xd0000000
+#define ARMADA_REGS_VIRT_BASE		0xfeb00000
+#define ARMADA_REGS_SIZE		SZ_1M
+
+#define ARMADA_UART_REGS_BASE		0xd0100000
+#define ARMADA_UART_SIZE		_1M
+
+#define ARMADA_PCIE0_IO_PHYS_BASE	0xd0200000
+#define ARMADA_PCIE0_IO_VIRT_BASE	0xfec00000
+#define ARMADA_PCIE0_IO_BUS_BASE	0x00100000
+#define ARMADA_PCIE0_IO_SIZE		SZ_1M
+
+#define ARMADA_PCIE1_IO_PHYS_BASE	0xd0300000
+#define ARMADA_PCIE1_IO_VIRT_BASE	0xfed00000
+#define ARMADA_PCIE1_IO_BUS_BASE	0x00200000
+#define ARMADA_PCIE1_IO_SIZE		SZ_1M
+
+#define ARMADA_PCIE2_IO_PHYS_BASE	0xd0400000
+#define ARMADA_PCIE2_IO_VIRT_BASE	0xfee00000
+#define ARMADA_PCIE2_IO_BUS_BASE	0x00300000
+#define ARMADA_PCIE2_IO_SIZE		SZ_1M
+
+#define ARMADA_PCIE3_IO_PHYS_BASE	0xd0500000
+#define ARMADA_PCIE3_IO_VIRT_BASE	0xfef00000
+#define ARMADA_PCIE3_IO_BUS_BASE	0x00400000
+#define ARMADA_PCIE3_IO_SIZE		SZ_1M
+
+#define ARMADA_CESA0_PHYS_BASE		0xd0600000
+#define ARMADA_CESA0_SIZE		SZ_1M
+
+#define ARMADA_CESA1_PHYS_BASE		0xd0700000
+#define ARMADA_CESA1_SIZE		SZ_1M
+
+#define ARMADA_DEVICE_CS0_PHYS_BASE	0xd1000000
+#define ARMADA_DEVICE_CS0_SIZE		SZ_16M
+
+#define ARMADA_DEVICE_CS1_PHYS_BASE	0xd2000000
+#define ARMADA_DEVICE_CS1_SIZE		SZ_16M
+
+#define ARMADA_DEVICE_CS2_PHYS_BASE	0xd3000000
+#define ARMADA_DEVICE_CS2_SIZE		SZ_16M
+
+#define ARMADA_DEVICE_CS3_PHYS_BASE	0xd4000000
+#define ARMADA_DEVICE_CS3_SIZE		SZ_16M
+
+#define ARMADA_DEVICE_BOOT_CS_PHYS_BASE	0xd5000000
+#define ARMADA_DEVICE_BOOT_CS_SIZE	SZ_16M
+
+#define ARMADA_SPI0_CS0_PHYS_BASE	0xd6000000
+#define ARMADA_SPI0_CS0_SIZE		SZ_16M
+
+#define ARMADA_SPI1_CS0_PHYS_BASE	0xd7000000
+#define ARMADA_SPI1_CS0_SIZE		SZ_16M
+
+#define ARMADA_PCIE0_MEM_PHYS_BASE	0xd8000000
+#define ARMADA_PCIE0_MEM_SIZE		SZ_64M
+
+#define ARMADA_PCIE1_MEM_PHYS_BASE	0xdc000000
+#define ARMADA_PCIE1_MEM_SIZE		SZ_64M
+
+#define ARMADA_PCIE2_MEM_PHYS_BASE	0xe0000000
+#define ARMADA_PCIE2_MEM_SIZE		SZ_64M
+
+#define ARMADA_PCIE3_MEM_PHYS_BASE	0xe4000000
+#define ARMADA_PCIE3_MEM_SIZE		SZ_64M
+
+#define ARMADA_BOOTROM_PHYS_BASE	0xFFF00000
+#define ARMADA_BOOTROM_SIZE		SZ_1M
+
+/*
+ * Core Registers Map
+ */
+
+/* DRAM */
+#define ARMADA_DRAM_PHYS_BASE     (ARMADA_REGS_PHYS_BASE | 0x0)
+#define ARMADA_DRAM_VIRT_BASE     (ARMADA_REGS_VIRT_BASE | 0x0)
+
+/* L2 Cache */
+#define ARMADA_L2_CACHE_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x8000)
+#define ARMADA_L2_CACHE_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x8000)
+
+/* RTC */
+#define ARMADA_RTC_PHYS_BASE      (ARMADA_REGS_PHYS_BASE | 0x10300)
+#define ARMADA_RTC_VIRT_BASE      (ARMADA_REGS_VIRT_BASE | 0x10300)
+
+/* SPI */
+#define ARMADA_SPI0_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x10600)
+#define ARMADA_SPI0_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x10600)
+#define ARMADA_SPI1_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x10680)
+#define ARMADA_SPI1_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x10680)
+
+/* I2C */
+#define ARMADA_I2C0_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x11000)
+#define ARMADA_I2C0_VIRT_BASE     (ARMADA_REGS_VIRT_BASE | 0x11000)
+#define ARMADA_I2C1_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x11100)
+#define ARMADA_I2C1_VIRT_BASE	(ARMADA_REGS_PHYS_BASE | 0x11100)
+
+/* UART */
+#define ARMADA_UART0_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x12000)
+#define ARMADA_UART0_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x12000)
+#define ARMADA_UART1_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x12100)
+#define ARMADA_UART1_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x12100)
+
+/* MPP (pin muxing) */
+#define ARMADA_MPP_PHYS_BASE      (ARMADA_REGS_PHYS_BASE | 0x18000)
+#define ARMADA_MPP_VIRT_BASE      (ARMADA_REGS_VIRT_BASE | 0x18000)
+
+/* GPIO */
+#define ARMADA_GPIO_PHYS_BASE     (ARMADA_REGS_PHYS_BASE | 0x18100)
+#define ARMADA_GPIO_VIRT_BASE     (ARMADA_REGS_VIRT_BASE | 0x18100)
+
+/* Misc registers */
+#define ARMADA_SYSTEM_PHYS_BASE     (ARMADA_REGS_PHYS_BASE | 0x18200)
+#define ARMADA_SYSTEM_VIRT_BASE     (ARMADA_REGS_VIRT_BASE | 0x18200)
+
+/* CPU */
+#define ARMADA_CPU_PHYS_BASE      (ARMADA_REGS_PHYS_BASE | 0x20000)
+#define ARMADA_CPU_VIRT_BASE      (ARMADA_REGS_VIRT_BASE | 0x20000)
+
+/* Audio */
+#define ARMADA_AUDIO_PHYS_BASE    (ARMADA_REGS_PHYS_BASE | 0x30000)
+#define ARMADA_AUDIO_VIRT_BASE    (ARMADA_REGS_VIRT_BASE | 0x30000)
+
+/* PCIe */
+#define ARMADA_PCIE0_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x40000)
+#define ARMADA_PCIE0_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x40000)
+#define ARMADA_PCIE1_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x80000)
+#define ARMADA_PCIE1_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x80000)
+#define ARMADA_PCIE2_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x42000)
+#define ARMADA_PCIE2_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x42000)
+#define ARMADA_PCIE3_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x82000)
+#define ARMADA_PCIE3_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x82000)
+
+/* USB */
+#define ARMADA_USB0_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x50000)
+#define ARMADA_USB0_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x50000)
+#define ARMADA_USB1_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x51000)
+#define ARMADA_USB1_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x51000)
+
+/* XOR Engines */
+#define ARMADA_XOR0_PHYS_BASE        (ARMADA_REGS_PHYS_BASE | 0x60900)
+#define ARMADA_XOR0_HIGH_PHYS_BASE   (ARMADA_REGS_PHYS_BASE | 0x60B00)
+#define ARMADA_XOR1_PHYS_BASE        (ARMADA_REGS_PHYS_BASE | 0xF0900)
+#define ARMADA_XOR1_HIGH_PHYS_BASE   (ARMADA_REGS_PHYS_BASE | 0xF0B00)
+
+/* Cryptographic Engine */
+#define ARMADA_CRYPT_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x30000)
+
+/* Gigabit Ethernet */
+#define ARMADA_GE00_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x70000)
+#define ARMADA_GE01_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x74000)
+#define ARMADA_GE10_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x30000)
+#define ARMADA_GE11_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x34000)
+
+/* SDIO */
+#define ARMADA_SDIO0_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x92000)
+
+/* SATA */
+#define ARMADA_SATA_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0xa0000)
+
+/* NAND Flash Controller */
+#define ARMADA_NFC_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0xd0000)
+
+/* MPP, GPIO, Reset Sampling */
+#define ARMADA_MPP_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x18000)
+#define ARMADA_GPIO0_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x18100)
+#define ARMADA_GPIO1_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x18140)

arch/arm/mach-armada/include/mach/bridge-regs.h new file +28 -0

new file mode 100644
index 0000000..0eaefbd
@@ -0,0 +1,28 @@
+/*
+ * Mbus-L to Mbus Bridge Registers
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_BRIDGE_REGS_H
+#define __ASM_ARCH_BRIDGE_REGS_H
+
+#include <mach/armada.h>
+
+#define RSTOUTn_MASK		(ARMADA_SYSTEM_VIRT_BASE | 0x60)
+#define  SOFT_RESET_OUT_EN	0x00000001
+
+#define SYSTEM_SOFT_RESET	(ARMADA_SYSTEM_VIRT_BASE | 0x64)
+#define  SOFT_RESET		0x00000001
+
+#define SOC_ID                  (ARMADA_MISC_VIRT_BASE | 0x3C)
+
+#endif

arch/arm/mach-armada/include/mach/debug-macro.S new file +9 -0

new file mode 100644
index 0000000..1c7c52f
@@ -0,0 +1,23 @@
+/*
+ * Early serial output macro for Marvell Armada SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as

arch/arm/mach-armada/include/mach/debug-macro.S new file +4 -0

+	.endm
+
+#define UART_SHIFT	2
+#include <asm/hardware/debug-8250.S>

arch/arm/mach-armada/include/mach/gpio.h new file +13 -0

new file mode 100644
index 0000000..e62f38a
@@ -0,0 +1,13 @@
+/*
+ * Marvell Armada SoC GPIO definitions
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <plat/gpio.h>

arch/arm/mach-armada/include/mach/hardware.h new file +8 -0

new file mode 100644
index 0000000..829111b
@@ -0,0 +1,18 @@
+/*
+ * Marvell Armada SoC hardware definitions
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public

arch/arm/mach-armada/include/mach/io.h new file +24 -0

new file mode 100644
index 0000000..48716c1
@@ -0,0 +1,24 @@
+/*
+ * Basic I/O macros
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include <mach/armada.h>
+
+#define IO_SPACE_LIMIT		0xffffffff
+
+#define __io(a)		((void __iomem *)(((a) - ARMADA_PCIE0_IO_BUS_BASE) + \
+						 ARMADA_PCIE0_IO_VIRT_BASE))
+#define __mem_pci(a)	(a)
+
+#endif

arch/arm/mach-armada/include/mach/irqs.h new file +86 -0

new file mode 100644
index 0000000..48844a4
@@ -0,0 +1,96 @@
+/*
+ * IRQ definitions for Marvell Armada SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+/*
+ * Per-cpu Interrupts
+ */
+#define IRQ_ARMADA_DRBL_LOW	0
+#define IRQ_ARMADA_DRBL_HI	1
+#define IRQ_ARMADA_DRBL_SUM	2
+#define IRQ_ARMADA_FABRIC	3
+#define IRQ_ARMADA_SOC_ERR	4
+#define IRQ_ARMADA_LCL_TIMER0	5
+#define IRQ_ARMADA_LCL_TIMER1	6
+#define IRQ_ARMADA_LCL_WD	7
+#define IRQ_ARMADA_GE0_TH_RXTX	8
+#define IRQ_ARMADA_GE0_RXTX	9
+#define IRQ_ARMADA_GE1_TH_RXTX	10
+#define IRQ_ARMADA_GE1_RXTX	11
+#define IRQ_ARMADA_GE2_TH_RXTX	12
+#define IRQ_ARMADA_GE2_RXTX	13
+#define IRQ_ARMADA_GE3_TH_RXTX	14
+#define IRQ_ARMADA_GE3_RXTX	15
+
+/*
+ * Global interrupts
+ */
+#define IRQ_ARMADA_LCD		29
+#define IRQ_ARMADA_SPI0		30
+#define IRQ_ARMADA_I2C0		31
+#define IRQ_ARMADA_I2C1		32
+#define IRQ_ARMADA_GLBL_TIMER0	37
+#define IRQ_ARMADA_GLBL_TIMER1	38
+#define IRQ_ARMADA_GLBL_TIMER2	39
+#define IRQ_ARMADA_GLBL_TIMER3	40
+#define IRQ_ARMADA_UART0	41
+#define IRQ_ARMADA_UART1	42
+#define IRQ_ARMADA_UART2	43
+#define IRQ_ARMADA_UART3	44
+#define IRQ_ARMADA_USB0		45
+#define IRQ_ARMADA_USB1		46
+#define IRQ_ARMADA_USB2		47
+#define IRQ_ARMADA_CESA0	48
+#define IRQ_ARMADA_CESA1	49
+#define IRQ_ARMADA_RTC		50
+#define IRQ_ARMADA_XOR0_CH0	51
+#define IRQ_ARMADA_XOR0_CH1	52
+#define IRQ_ARMADA_SDIO		54
+#define IRQ_ARMADA_SATA0	55
+#define IRQ_ARMADA_TDM		56
+#define IRQ_ARMADA_SATA1	57
+#define IRQ_ARMADA_PCIE0	61
+#define IRQ_ARMADA_PCIE1	62
+#define IRQ_ARMADA_GPIO_0_7	82
+#define IRQ_ARMADA_GPIO_8_15	83
+#define IRQ_ARMADA_GPIO_16_23	84
+#define IRQ_ARMADA_GPIO_24_31	85
+#define IRQ_ARMADA_GPIO_32_39	87
+#define IRQ_ARMADA_GPIO_40_47	88
+#define IRQ_ARMADA_GPIO_48_55	89
+#define IRQ_ARMADA_GPIO_56_63	90
+#define IRQ_ARMADA_GPIO_64_66	91
+#define IRQ_ARMADA_SPI1		92
+#define IRQ_ARMADA_WD		93
+#define IRQ_ARMADA_XOR1_CH0	94
+#define IRQ_ARMADA_XOR1_CH1	95
+#define IRQ_ARMADA_PCIE2	99
+#define IRQ_ARMADA_PCIE3	103
+#define IRQ_ARMADA_DRAM		108
+#define IRQ_ARMADA_GE0_WKUP	109
+#define IRQ_ARMADA_GE1_WKUP	110
+#define IRQ_ARMADA_GE2_WKUP	111
+#define IRQ_ARMADA_GE3_WKUP	112
+#define IRQ_ARMADA_NFC		113
+

new file mode 100644
index 0000000..f920ef0

arch/arm/mach-armada/include/mach/system.h new file +21 -0

@@ -0,0 +1,21 @@
+/*
+ * Marvell Armada SoC system defines
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static inline void arch_idle(void)
+{
+	cpu_do_idle();
+}
+
+#endif

arch/arm/mach-armada/include/mach/timex.h new file +13 -0

new file mode 100644
index 0000000..ab324a3
@@ -0,0 +1,13 @@
+/*
+ * Marvell Armada SoC time definitions
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE		(100 * HZ)

arch/arm/mach-armada/include/mach/uncompress.h new file +6 -0

new file mode 100644
index 0000000..611ebf3
@@ -0,0 +1,41 @@
+/*
+ * Marvell Armada SoC kernel uncompression UART routines
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>

arch/arm/mach-armada/include/mach/uncompress.h new file +13 -0

+
+	*UART_THR = c;
+}
+
+static void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()

Signature · 1 line

1.7.9.5

Quoted 71 lines · Thomas Petazzoni

From: Gregory CLEMENT<[email protected]>

This patch adds basic header files for Armada SoCs.

Signed-off-by Gregory CLEMENT<[email protected]>

Signed-off-by Thomas Petazzoni<[email protected]>

Signed-off-by Lior Amsalem<[email protected]>

---
  arch/arm/mach-armada/include/mach/armada.h      |  234 +++++++++++++++++++++++
  arch/arm/mach-armada/include/mach/bridge-regs.h |   28 +++
  arch/arm/mach-armada/include/mach/debug-macro.S |   23 +++
  arch/arm/mach-armada/include/mach/gpio.h        |   13 ++
  arch/arm/mach-armada/include/mach/hardware.h    |   18 ++
  arch/arm/mach-armada/include/mach/io.h          |   24 +++
  arch/arm/mach-armada/include/mach/irqs.h        |   96 ++++++++++
  arch/arm/mach-armada/include/mach/system.h      |   21 ++
  arch/arm/mach-armada/include/mach/timex.h       |   13 ++
  arch/arm/mach-armada/include/mach/uncompress.h  |   41 ++++
  10 files changed, 511 insertions(+)

create mode 100644 arch/arm/mach-armada/include/mach/armada.h create mode 100644 arch/arm/mach-armada/include/mach/bridge-regs.h create mode 100644 arch/arm/mach-armada/include/mach/debug-macro.S create mode 100644 arch/arm/mach-armada/include/mach/gpio.h create mode 100644 arch/arm/mach-armada/include/mach/hardware.h create mode 100644 arch/arm/mach-armada/include/mach/io.h create mode 100644 arch/arm/mach-armada/include/mach/irqs.h create mode 100644 arch/arm/mach-armada/include/mach/system.h create mode 100644 arch/arm/mach-armada/include/mach/timex.h create mode 100644 arch/arm/mach-armada/include/mach/uncompress.h

arch/arm/mach-armada/include/mach/armada.h new file +35 -0

new file mode 100644
index 0000000..be12667
@@ -0,0 +1,234 @@
+/*
+ * Generic definitions for Marvell Armada SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem<[email protected]>
+ * Gregory CLEMENT<[email protected]>
+ * Thomas Petazzoni<[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_ARMADA_H
+#define __MACH_ARMADA_H
+
+/*
+ * Marvell ARMADA address maps.
+ *
+ * phys		virt		size
+ * d0000000	feb00000	1M	internal registers
+ * d0100000	@runtime	1M	uart
+ * d0200000	fec00000	1M	PCIe-0 I/O (port 0.0)
+ * d0300000	fed00000	1M	PCIe-1 I/O (port 1.0)
+ * d0400000	fee00000	1M	PCIe-2 I/O (port 2.0)
+ * d0500000	fef00000	1M	PCIe-3 I/O (port 3.0)
+ * d0600000	@runtime	1M	cryptographic sram-0
+ * d0700000	@runtime	1M	cryptographic sram-1
+ * d0800000	reserved	8M	reserved for future
+ * d1000000	@runtime	16M	device bus cs-0
+ * d2000000	@runtime	16M	device bus cs-0
+ * d3000000	@runtime	16M	device bus cs-0
+ * d4000000	@runtime	16M	device bus cs-0
+ * d5000000	@runtime	16M	device bus boot cs

arch/arm/mach-armada/include/mach/armada.h line 43

Quoted 8 lines

arch/arm/mach-armada/include/mach/armada.h new file +8 -0

+ * d6000000	@runtime	16M	spi-0 flash
+ * d7000000	@runtime	16M	spi-1 flash
+ * d8000000	@runtime	64M	PCIe-0 Memory (port 0.0)
+ * dc000000	@runtime	64M	PCIe-1 Memory (port 1.0)
+ * e0000000	@runtime	64M	PCIe-2 Memory (port 2.0)
+ * e4000000	@runtime	64M	PCIe-3 Memory (port 3.0)
+ * fff00000	@runtime	1M	internal bootrom
+ */

From: Gregory CLEMENT <[email protected]>

This patch adds basic header files for Armada SoCs.

Signed-off-by Gregory CLEMENT <[email protected]>

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Lior Amsalem <[email protected]>

---
 arch/arm/mach-armada/include/mach/armada.h      |  234 +++++++++++++++++++++++
 arch/arm/mach-armada/include/mach/bridge-regs.h |   28 +++
 arch/arm/mach-armada/include/mach/debug-macro.S |   23 +++
 arch/arm/mach-armada/include/mach/gpio.h        |   13 ++
 arch/arm/mach-armada/include/mach/hardware.h    |   18 ++
 arch/arm/mach-armada/include/mach/io.h          |   24 +++
 arch/arm/mach-armada/include/mach/irqs.h        |   96 ++++++++++
 arch/arm/mach-armada/include/mach/system.h      |   21 ++
 arch/arm/mach-armada/include/mach/timex.h       |   13 ++
 arch/arm/mach-armada/include/mach/uncompress.h  |   41 ++++
 10 files changed, 511 insertions(+)
 create mode 100644 arch/arm/mach-armada/include/mach/armada.h
 create mode 100644 arch/arm/mach-armada/include/mach/bridge-regs.h
 create mode 100644 arch/arm/mach-armada/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-armada/include/mach/gpio.h
 create mode 100644 arch/arm/mach-armada/include/mach/hardware.h
 create mode 100644 arch/arm/mach-armada/include/mach/io.h
 create mode 100644 arch/arm/mach-armada/include/mach/irqs.h
 create mode 100644 arch/arm/mach-armada/include/mach/system.h
 create mode 100644 arch/arm/mach-armada/include/mach/timex.h
 create mode 100644 arch/arm/mach-armada/include/mach/uncompress.h

arch/arm/mach-armada/include/mach/armada.h new file +223 -0

new file mode 100644
index 0000000..be12667
@@ -0,0 +1,234 @@
+/*
+ * Generic definitions for Marvell Armada SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_ARMADA_H
+#define __MACH_ARMADA_H
+
+/*
+ * Marvell ARMADA address maps.
+ *
+ * phys		virt		size
+ * d0000000	feb00000	1M	internal registers
+ * d0100000	@runtime	1M	uart
+ * d0200000	fec00000	1M	PCIe-0 I/O (port 0.0)
+ * d0300000	fed00000	1M	PCIe-1 I/O (port 1.0)
+ * d0400000	fee00000	1M	PCIe-2 I/O (port 2.0)
+ * d0500000	fef00000	1M	PCIe-3 I/O (port 3.0)
+ * d0600000	@runtime	1M	cryptographic sram-0
+ * d0700000	@runtime	1M	cryptographic sram-1
+ * d0800000	reserved	8M	reserved for future
+ * d1000000	@runtime	16M	device bus cs-0
+ * d2000000	@runtime	16M	device bus cs-0
+ * d3000000	@runtime	16M	device bus cs-0
+ * d4000000	@runtime	16M	device bus cs-0
+ * d5000000	@runtime	16M	device bus boot cs
+ * d6000000	@runtime	16M	spi-0 flash
+ * d7000000	@runtime	16M	spi-1 flash
+ * d8000000	@runtime	64M	PCIe-0 Memory (port 0.0)
+ * dc000000	@runtime	64M	PCIe-1 Memory (port 1.0)
+ * e0000000	@runtime	64M	PCIe-2 Memory (port 2.0)
+ * e4000000	@runtime	64M	PCIe-3 Memory (port 3.0)
+ * fff00000	@runtime	1M	internal bootrom
+ */
+
+#define ARMADA_REGS_PHYS_BASE		0xd0000000
+#define ARMADA_REGS_VIRT_BASE		0xfeb00000
+#define ARMADA_REGS_SIZE		SZ_1M
+
+#define ARMADA_UART_REGS_BASE		0xd0100000
+#define ARMADA_UART_SIZE		_1M
+
+#define ARMADA_PCIE0_IO_PHYS_BASE	0xd0200000
+#define ARMADA_PCIE0_IO_VIRT_BASE	0xfec00000
+#define ARMADA_PCIE0_IO_BUS_BASE	0x00100000
+#define ARMADA_PCIE0_IO_SIZE		SZ_1M
+
+#define ARMADA_PCIE1_IO_PHYS_BASE	0xd0300000
+#define ARMADA_PCIE1_IO_VIRT_BASE	0xfed00000
+#define ARMADA_PCIE1_IO_BUS_BASE	0x00200000
+#define ARMADA_PCIE1_IO_SIZE		SZ_1M
+
+#define ARMADA_PCIE2_IO_PHYS_BASE	0xd0400000
+#define ARMADA_PCIE2_IO_VIRT_BASE	0xfee00000
+#define ARMADA_PCIE2_IO_BUS_BASE	0x00300000
+#define ARMADA_PCIE2_IO_SIZE		SZ_1M
+
+#define ARMADA_PCIE3_IO_PHYS_BASE	0xd0500000
+#define ARMADA_PCIE3_IO_VIRT_BASE	0xfef00000
+#define ARMADA_PCIE3_IO_BUS_BASE	0x00400000
+#define ARMADA_PCIE3_IO_SIZE		SZ_1M
+
+#define ARMADA_CESA0_PHYS_BASE		0xd0600000
+#define ARMADA_CESA0_SIZE		SZ_1M
+
+#define ARMADA_CESA1_PHYS_BASE		0xd0700000
+#define ARMADA_CESA1_SIZE		SZ_1M
+
+#define ARMADA_DEVICE_CS0_PHYS_BASE	0xd1000000
+#define ARMADA_DEVICE_CS0_SIZE		SZ_16M
+
+#define ARMADA_DEVICE_CS1_PHYS_BASE	0xd2000000
+#define ARMADA_DEVICE_CS1_SIZE		SZ_16M
+
+#define ARMADA_DEVICE_CS2_PHYS_BASE	0xd3000000
+#define ARMADA_DEVICE_CS2_SIZE		SZ_16M
+
+#define ARMADA_DEVICE_CS3_PHYS_BASE	0xd4000000
+#define ARMADA_DEVICE_CS3_SIZE		SZ_16M
+
+#define ARMADA_DEVICE_BOOT_CS_PHYS_BASE	0xd5000000
+#define ARMADA_DEVICE_BOOT_CS_SIZE	SZ_16M
+
+#define ARMADA_SPI0_CS0_PHYS_BASE	0xd6000000
+#define ARMADA_SPI0_CS0_SIZE		SZ_16M
+
+#define ARMADA_SPI1_CS0_PHYS_BASE	0xd7000000
+#define ARMADA_SPI1_CS0_SIZE		SZ_16M
+
+#define ARMADA_PCIE0_MEM_PHYS_BASE	0xd8000000
+#define ARMADA_PCIE0_MEM_SIZE		SZ_64M
+
+#define ARMADA_PCIE1_MEM_PHYS_BASE	0xdc000000
+#define ARMADA_PCIE1_MEM_SIZE		SZ_64M
+
+#define ARMADA_PCIE2_MEM_PHYS_BASE	0xe0000000
+#define ARMADA_PCIE2_MEM_SIZE		SZ_64M
+
+#define ARMADA_PCIE3_MEM_PHYS_BASE	0xe4000000
+#define ARMADA_PCIE3_MEM_SIZE		SZ_64M
+
+#define ARMADA_BOOTROM_PHYS_BASE	0xFFF00000
+#define ARMADA_BOOTROM_SIZE		SZ_1M
+
+/*
+ * Core Registers Map
+ */
+
+/* DRAM */
+#define ARMADA_DRAM_PHYS_BASE     (ARMADA_REGS_PHYS_BASE | 0x0)
+#define ARMADA_DRAM_VIRT_BASE     (ARMADA_REGS_VIRT_BASE | 0x0)
+
+/* L2 Cache */
+#define ARMADA_L2_CACHE_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x8000)
+#define ARMADA_L2_CACHE_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x8000)
+
+/* RTC */
+#define ARMADA_RTC_PHYS_BASE      (ARMADA_REGS_PHYS_BASE | 0x10300)
+#define ARMADA_RTC_VIRT_BASE      (ARMADA_REGS_VIRT_BASE | 0x10300)
+
+/* SPI */
+#define ARMADA_SPI0_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x10600)
+#define ARMADA_SPI0_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x10600)
+#define ARMADA_SPI1_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x10680)
+#define ARMADA_SPI1_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x10680)
+
+/* I2C */
+#define ARMADA_I2C0_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x11000)
+#define ARMADA_I2C0_VIRT_BASE     (ARMADA_REGS_VIRT_BASE | 0x11000)
+#define ARMADA_I2C1_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x11100)
+#define ARMADA_I2C1_VIRT_BASE	(ARMADA_REGS_PHYS_BASE | 0x11100)
+
+/* UART */
+#define ARMADA_UART0_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x12000)
+#define ARMADA_UART0_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x12000)
+#define ARMADA_UART1_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x12100)
+#define ARMADA_UART1_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x12100)
+
+/* MPP (pin muxing) */
+#define ARMADA_MPP_PHYS_BASE      (ARMADA_REGS_PHYS_BASE | 0x18000)
+#define ARMADA_MPP_VIRT_BASE      (ARMADA_REGS_VIRT_BASE | 0x18000)
+
+/* GPIO */
+#define ARMADA_GPIO_PHYS_BASE     (ARMADA_REGS_PHYS_BASE | 0x18100)
+#define ARMADA_GPIO_VIRT_BASE     (ARMADA_REGS_VIRT_BASE | 0x18100)
+
+/* Misc registers */
+#define ARMADA_SYSTEM_PHYS_BASE     (ARMADA_REGS_PHYS_BASE | 0x18200)
+#define ARMADA_SYSTEM_VIRT_BASE     (ARMADA_REGS_VIRT_BASE | 0x18200)
+
+/* CPU */
+#define ARMADA_CPU_PHYS_BASE      (ARMADA_REGS_PHYS_BASE | 0x20000)
+#define ARMADA_CPU_VIRT_BASE      (ARMADA_REGS_VIRT_BASE | 0x20000)
+
+/* Audio */
+#define ARMADA_AUDIO_PHYS_BASE    (ARMADA_REGS_PHYS_BASE | 0x30000)
+#define ARMADA_AUDIO_VIRT_BASE    (ARMADA_REGS_VIRT_BASE | 0x30000)
+
+/* PCIe */
+#define ARMADA_PCIE0_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x40000)
+#define ARMADA_PCIE0_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x40000)
+#define ARMADA_PCIE1_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x80000)
+#define ARMADA_PCIE1_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x80000)
+#define ARMADA_PCIE2_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x42000)
+#define ARMADA_PCIE2_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x42000)
+#define ARMADA_PCIE3_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x82000)
+#define ARMADA_PCIE3_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x82000)
+
+/* USB */
+#define ARMADA_USB0_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x50000)
+#define ARMADA_USB0_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x50000)
+#define ARMADA_USB1_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x51000)
+#define ARMADA_USB1_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x51000)
+
+/* XOR Engines */
+#define ARMADA_XOR0_PHYS_BASE        (ARMADA_REGS_PHYS_BASE | 0x60900)
+#define ARMADA_XOR0_HIGH_PHYS_BASE   (ARMADA_REGS_PHYS_BASE | 0x60B00)
+#define ARMADA_XOR1_PHYS_BASE        (ARMADA_REGS_PHYS_BASE | 0xF0900)
+#define ARMADA_XOR1_HIGH_PHYS_BASE   (ARMADA_REGS_PHYS_BASE | 0xF0B00)
+
+/* Cryptographic Engine */
+#define ARMADA_CRYPT_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x30000)
+
+/* Gigabit Ethernet */
+#define ARMADA_GE00_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x70000)
+#define ARMADA_GE01_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x74000)
+#define ARMADA_GE10_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x30000)
+#define ARMADA_GE11_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x34000)
+
+/* SDIO */
+#define ARMADA_SDIO0_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x92000)
+
+/* SATA */
+#define ARMADA_SATA_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0xa0000)
+
+/* NAND Flash Controller */
+#define ARMADA_NFC_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0xd0000)
+
+/* MPP, GPIO, Reset Sampling */
+#define ARMADA_MPP_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x18000)
+#define ARMADA_GPIO0_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x18100)
+#define ARMADA_GPIO1_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x18140)
+#define ARMADA_GPIO2_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x18180)
+
+/* Power Management */
+#define ARMADA_PMU_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x1c000)
+
+/* Real Time Clock */
+#define ARMADA_RTC_PHYS_BASE	(ARMADA_REGS_PHYS_BASE | 0x10300)
+
+/* Memory Controller */
+#define ARMADA_MC_VIRT_BASE	(ARMADA_REGS_VIRT_BASE | 0x20180)
+
+/* Timers */

arch/arm/mach-armada/include/mach/armada.h new file +1 -0

+#endif /* __MACH_ARMADA_H */

arch/arm/mach-armada/include/mach/bridge-regs.h new file +28 -0

new file mode 100644
index 0000000..0eaefbd
@@ -0,0 +1,28 @@
+/*
+ * Mbus-L to Mbus Bridge Registers
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_BRIDGE_REGS_H
+#define __ASM_ARCH_BRIDGE_REGS_H
+
+#include <mach/armada.h>
+
+#define RSTOUTn_MASK		(ARMADA_SYSTEM_VIRT_BASE | 0x60)
+#define  SOFT_RESET_OUT_EN	0x00000001
+
+#define SYSTEM_SOFT_RESET	(ARMADA_SYSTEM_VIRT_BASE | 0x64)
+#define  SOFT_RESET		0x00000001
+
+#define SOC_ID                  (ARMADA_MISC_VIRT_BASE | 0x3C)
+
+#endif

arch/arm/mach-armada/include/mach/debug-macro.S new file +23 -0

new file mode 100644
index 0000000..1c7c52f
@@ -0,0 +1,23 @@
+/*
+ * Early serial output macro for Marvell Armada SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <mach/armada.h>
+
+	.macro	addruart, rp, rv, tmp
+	ldr	\rp, =ARMADA_REGS_PHYS_BASE
+	ldr	\rv, =ARMADA_REGS_VIRT_BASE
+	orr	\rp, \rp, #0x00012000
+	orr	\rv, \rv, #0x00012000
+	.endm
+
+#define UART_SHIFT	2
+#include <asm/hardware/debug-8250.S>

arch/arm/mach-armada/include/mach/gpio.h new file +3 -0

new file mode 100644
index 0000000..e62f38a
@@ -0,0 +1,13 @@
+/*
+ * Marvell Armada SoC GPIO definitions
+ *

arch/arm/mach-armada/include/mach/hardware.h new file +18 -0

@@ -0,0 +1,18 @@
+/*
+ * Marvell Armada SoC hardware definitions
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <mach/armada.h>
+
+#endif

arch/arm/mach-armada/include/mach/io.h new file +8 -0

new file mode 100644
index 0000000..48716c1
@@ -0,0 +1,24 @@
+/*
+ * Basic I/O macros
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public

arch/arm/mach-armada/include/mach/io.h new file +2 -0

+
+#endif

arch/arm/mach-armada/include/mach/irqs.h new file +84 -0

new file mode 100644
index 0000000..48844a4
@@ -0,0 +1,96 @@
+/*
+ * IRQ definitions for Marvell Armada SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+/*
+ * Per-cpu Interrupts
+ */
+#define IRQ_ARMADA_DRBL_LOW	0
+#define IRQ_ARMADA_DRBL_HI	1
+#define IRQ_ARMADA_DRBL_SUM	2
+#define IRQ_ARMADA_FABRIC	3
+#define IRQ_ARMADA_SOC_ERR	4
+#define IRQ_ARMADA_LCL_TIMER0	5
+#define IRQ_ARMADA_LCL_TIMER1	6
+#define IRQ_ARMADA_LCL_WD	7
+#define IRQ_ARMADA_GE0_TH_RXTX	8
+#define IRQ_ARMADA_GE0_RXTX	9
+#define IRQ_ARMADA_GE1_TH_RXTX	10
+#define IRQ_ARMADA_GE1_RXTX	11
+#define IRQ_ARMADA_GE2_TH_RXTX	12
+#define IRQ_ARMADA_GE2_RXTX	13
+#define IRQ_ARMADA_GE3_TH_RXTX	14
+#define IRQ_ARMADA_GE3_RXTX	15
+
+/*
+ * Global interrupts
+ */
+#define IRQ_ARMADA_LCD		29
+#define IRQ_ARMADA_SPI0		30
+#define IRQ_ARMADA_I2C0		31
+#define IRQ_ARMADA_I2C1		32
+#define IRQ_ARMADA_GLBL_TIMER0	37
+#define IRQ_ARMADA_GLBL_TIMER1	38
+#define IRQ_ARMADA_GLBL_TIMER2	39
+#define IRQ_ARMADA_GLBL_TIMER3	40
+#define IRQ_ARMADA_UART0	41
+#define IRQ_ARMADA_UART1	42
+#define IRQ_ARMADA_UART2	43
+#define IRQ_ARMADA_UART3	44
+#define IRQ_ARMADA_USB0		45
+#define IRQ_ARMADA_USB1		46
+#define IRQ_ARMADA_USB2		47
+#define IRQ_ARMADA_CESA0	48
+#define IRQ_ARMADA_CESA1	49
+#define IRQ_ARMADA_RTC		50
+#define IRQ_ARMADA_XOR0_CH0	51
+#define IRQ_ARMADA_XOR0_CH1	52
+#define IRQ_ARMADA_SDIO		54
+#define IRQ_ARMADA_SATA0	55
+#define IRQ_ARMADA_TDM		56
+#define IRQ_ARMADA_SATA1	57
+#define IRQ_ARMADA_PCIE0	61
+#define IRQ_ARMADA_PCIE1	62
+#define IRQ_ARMADA_GPIO_0_7	82
+#define IRQ_ARMADA_GPIO_8_15	83
+#define IRQ_ARMADA_GPIO_16_23	84
+#define IRQ_ARMADA_GPIO_24_31	85
+#define IRQ_ARMADA_GPIO_32_39	87
+#define IRQ_ARMADA_GPIO_40_47	88
+#define IRQ_ARMADA_GPIO_48_55	89
+#define IRQ_ARMADA_GPIO_56_63	90
+#define IRQ_ARMADA_GPIO_64_66	91
+#define IRQ_ARMADA_SPI1		92
+#define IRQ_ARMADA_WD		93
+#define IRQ_ARMADA_XOR1_CH0	94
+#define IRQ_ARMADA_XOR1_CH1	95
+#define IRQ_ARMADA_PCIE2	99
+#define IRQ_ARMADA_PCIE3	103
+#define IRQ_ARMADA_DRAM		108
+#define IRQ_ARMADA_GE0_WKUP	109
+#define IRQ_ARMADA_GE1_WKUP	110
+#define IRQ_ARMADA_GE2_WKUP	111
+#define IRQ_ARMADA_GE3_WKUP	112

arch/arm/mach-armada/include/mach/system.h new file +21 -0

@@ -0,0 +1,21 @@
+/*
+ * Marvell Armada SoC system defines
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static inline void arch_idle(void)
+{
+	cpu_do_idle();
+}
+
+#endif

arch/arm/mach-armada/include/mach/timex.h new file +13 -0

new file mode 100644
index 0000000..ab324a3
@@ -0,0 +1,13 @@
+/*
+ * Marvell Armada SoC time definitions
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE		(100 * HZ)

arch/arm/mach-armada/include/mach/uncompress.h new file +41 -0

new file mode 100644
index 0000000..611ebf3
@@ -0,0 +1,41 @@
+/*
+ * Marvell Armada SoC kernel uncompression UART routines
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/armada.h>
+
+#define UART_THR ((volatile unsigned char *)(ARMADA_UART0_PHYS_BASE + 0x0))
+#define UART_LSR ((volatile unsigned char *)(ARMADA_UART0_PHYS_BASE + 0x14))
+
+#define LSR_THRE	0x20
+
+static void putc(const char c)
+{
+	int i;
+
+	for (i = 0; i < 0x1000; i++) {
+		/* Transmit fifo not full? */
+		if (*UART_LSR & LSR_THRE)
+			break;
+	}
+
+	*UART_THR = c;
+}
+
+static void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()

From: Gregory CLEMENT <[email protected]>

This patch adds basic header files for Armada SoCs.

This patch adds basic source files for Marvell Armada SoCs.

Signed-off-by Gregory CLEMENT <[email protected]>

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Lior Amsalem <[email protected]>

---
 arch/arm/boot/dts/a370.dtsi        |   23 ++++
 arch/arm/boot/dts/armada.dtsi      |   67 ++++++++++
 arch/arm/boot/dts/axp.dtsi         |   43 +++++++
 arch/arm/mach-armada/Kconfig       |    5 +
 arch/arm/mach-armada/Makefile      |    2 +
 arch/arm/mach-armada/Makefile.boot |    1 +
 arch/arm/mach-armada/common.c      |   56 +++++++++
 arch/arm/mach-armada/common.h      |   27 ++++
 arch/arm/mach-armada/irq.c         |  116 +++++++++++++++++
 arch/arm/mach-armada/time.c        |  243 ++++++++++++++++++++++++++++++++++++
 10 files changed, 583 insertions(+)
 create mode 100644 arch/arm/boot/dts/a370.dtsi
 create mode 100644 arch/arm/boot/dts/armada.dtsi
 create mode 100644 arch/arm/boot/dts/axp.dtsi
 create mode 100644 arch/arm/mach-armada/Kconfig
 create mode 100644 arch/arm/mach-armada/Makefile
 create mode 100644 arch/arm/mach-armada/Makefile.boot
 create mode 100644 arch/arm/mach-armada/common.c
 create mode 100644 arch/arm/mach-armada/common.h
 create mode 100644 arch/arm/mach-armada/irq.c
 create mode 100644 arch/arm/mach-armada/time.c

arch/arm/boot/dts/a370.dtsi new file +12 -0

new file mode 100644
index 0000000..f11e56a
@@ -0,0 +1,23 @@
+/*
+ * Device Tree Include file for Marvell Armada 370 family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.

arch/arm/boot/dts/a370.dtsi new file +4 -0

+void armada_restart(char mode, const char *cmd)
+{
+	/*
+	 * Enable soft reset to assert RSTOUTn.

arch/arm/boot/dts/a370.dtsi line 22

Quoted 5 lines

arch/arm/boot/dts/a370.dtsi new file +5 -0

+/include/ "armada.dtsi"
+
+/ {
+	model = "Marvell Armada 370 family SoC";
+	compatible = "marvell,armada370", "marvell,armada";

It should be mrvl, not marvell, in all the compatibility strings.

Also, we need to be careful with armada. kirkwood is an armada for example. It maybe be better to not actually use armada without postfix.

This chunk of code comes up multiple times in various orion devices. Could it be refactored into plat-orion?

Hello Andrew,

Thanks for the quick feedback!

Le Tue, 15 May 2012 11:12:18 +0200,
Andrew Lunn<[email protected]> a ?crit :

Quoted 7 lines

arch/arm/boot/dts/a370.dtsi line 22

Quoted 5 lines

arch/arm/boot/dts/a370.dtsi new file +5 -0

+/include/ "armada.dtsi"
+
+/ {
+	model = "Marvell Armada 370 family SoC";
+	compatible = "marvell,armada370", "marvell,armada";

It should be mrvl, not marvell, in all the compatibility strings.

Ok, we will change that.

Quoted 3 lines

Also, we need to be careful with armada. kirkwood is an armada for example. It maybe be better to not actually use armada without postfix.

Do you have a recommendation for this? We support both Armada 370 and Armada XP, so the obvious common prefix for these two platforms is "armada". Since kirkwood are ARMv5 and those new Armada are ARMv7, would armadav7 be a better prefix? Then we could have armadav7-370 and armadav7-xp? Other suggestions?

Hello Andrew,

Thanks for the quick feedback!

Le Tue, 15 May 2012 11:12:18 +0200,
Andrew Lunn <[email protected]> a ?crit :

Quoted 7 lines

arch/arm/boot/dts/a370.dtsi line 22

Quoted 5 lines

arch/arm/boot/dts/a370.dtsi new file +5 -0

+/include/ "armada.dtsi"
+
+/ {
+	model = "Marvell Armada 370 family SoC";
+	compatible = "marvell,armada370", "marvell,armada";

It should be mrvl, not marvell, in all the compatibility strings.

Ok, we will change that.

Quoted 3 lines

Also, we need to be careful with armada. kirkwood is an armada for example. It maybe be better to not actually use armada without postfix.

Do you have a recommendation for this? We support both Armada 370 and Armada XP, so the obvious common prefix for these two platforms is "armada". Since kirkwood are ARMv5 and those new Armada are ARMv7, would armadav7 be a better prefix? Then we could have armadav7-370 and armadav7-xp? Other suggestions?

Thomas Petazzoni<[email protected]> writes:

Hi,

Quoted 21 lines

Hello Andrew,

Thanks for the quick feedback!

Le Tue, 15 May 2012 11:12:18 +0200,
Andrew Lunn<[email protected]> a ?crit :

Quoted 7 lines

arch/arm/boot/dts/a370.dtsi line 22

Quoted 5 lines

arch/arm/boot/dts/a370.dtsi new file +5 -0

+/include/ "armada.dtsi"
+
+/ {
+	model = "Marvell Armada 370 family SoC";
+	compatible = "marvell,armada370", "marvell,armada";

It should be mrvl, not marvell, in all the compatibility strings.

Ok, we will change that.

Quoted 3 lines

Also, we need to be careful with armada. kirkwood is an armada for example. It maybe be better to not actually use armada without postfix.

Quoted 5 lines

Do you have a recommendation for this? We support both Armada 370 and Armada XP, so the obvious common prefix for these two platforms is "armada". Since kirkwood are ARMv5 and those new Armada are ARMv7, would armadav7 be a better prefix? Then we could have armadav7-370 and armadav7-xp? Other suggestions?

Please be carefull with what you'll choose. There's also Dove SoCs which are v7 too (88AP510 / armada 510 in Marvell namings). I would be tempted to use "mrvl,dove" like was what was used for kirkwood so this won't conflict but still, can be quite confusing.

arch/arm/mach-armada/irq.c new file +37 -0

new file mode 100644
index 0000000..7006429
@@ -0,0 +1,116 @@
+/*
+ * Marvall Armada SoC IRQ handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <asm/mach/arch.h>
+#include <asm/exception.h>
+
+/* Interrupt Controller Registers Map */
+#define ARMADA_INT_SET_MASK_OFFS             (0xBC)
+#define ARMADA_INT_CLEAR_MASK_OFFS           (0xB8)
+
+#define ARMADA_INT_SET_ENABLE_OFFS           (0xA30)
+#define ARMADA_INT_CLEAR_ENABLE_OFFS         (0xA34)
+
+#define ARMADA_CPU_INTACK_OFFS               (0xB4)
+
+static void __iomem *per_cpu_int_base;
+static void __iomem *main_int_base;
+static struct irq_domain *armada_mpic_domain;

Quoted 50 lines

arch/arm/mach-armada/irq.c new file +43 -0

new file mode 100644
index 0000000..7006429
@@ -0,0 +1,116 @@
+/*
+ * Marvall Armada SoC IRQ handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem<[email protected]>
+ * Gregory CLEMENT<[email protected]>
+ * Thomas Petazzoni<[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include<linux/kernel.h>
+#include<linux/init.h>
+#include<linux/irq.h>
+#include<linux/interrupt.h>
+#include<linux/io.h>
+#include<linux/of_address.h>
+#include<linux/of_irq.h>
+#include<linux/irqdomain.h>
+#include<asm/mach/arch.h>
+#include<asm/exception.h>
+
+/* Interrupt Controller Registers Map */
+#define ARMADA_INT_SET_MASK_OFFS             (0xBC)
+#define ARMADA_INT_CLEAR_MASK_OFFS           (0xB8)
+
+#define ARMADA_INT_SET_ENABLE_OFFS           (0xA30)
+#define ARMADA_INT_CLEAR_ENABLE_OFFS         (0xA34)
+
+#define ARMADA_CPU_INTACK_OFFS               (0xB4)
+
+static void __iomem *per_cpu_int_base;
+static void __iomem *main_int_base;
+static struct irq_domain *armada_mpic_domain;
+
+static void armada_irq_mask(struct irq_data *d)
+{
+	writel(d->irq, per_cpu_int_base + ARMADA_INT_CLEAR_MASK_OFFS);
+}
+

arch/arm/mach-armada/irq.c line 47

Quoted 4 lines

arch/arm/mach-armada/irq.c new file +4 -0

+static void armada_irq_unmask(struct irq_data *d)
+{
+	writel(d->irq, per_cpu_int_base + ARMADA_INT_SET_MASK_OFFS);
+}

All the other orion's use the generic-chip interrupt routines. Can this device also use it? It would also allow you to use the generic DT bindings.

-----Original Message-----
From: Ben Dooks [mailto:ben.dooks at codethink.co.uk]
Sent: Tuesday, May 15, 2012 12:54 PM
To: Thomas Petazzoni; Arnd Bergmann; Olof Johansson; Ben Dooks; Jason Cooper; Andrew Lunn; Nicolas Pitre; Lior Amsalem; Maen Suleiman; linux- arm-kernel at lists.infradead.org; Gregory CLEMENT
Subject: Re: [PATCH 2/8] arm: mach-armada: add source files

Quoted 37 lines · Andrew Lunn

Quoted 37 lines

arch/arm/mach-armada/irq.c new file +31 -0

new file mode 100644 index 0000000..7006429
@@ -0,0 +1,116 @@
+/*
+ * Marvall Armada SoC IRQ handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem<[email protected]>
+ * Gregory CLEMENT<[email protected]>
+ * Thomas Petazzoni<[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include<linux/kernel.h>
+#include<linux/init.h>
+#include<linux/irq.h>
+#include<linux/interrupt.h>
+#include<linux/io.h>
+#include<linux/of_address.h>
+#include<linux/of_irq.h>
+#include<linux/irqdomain.h>
+#include<asm/mach/arch.h>
+#include<asm/exception.h>
+
+/* Interrupt Controller Registers Map */
+#define ARMADA_INT_SET_MASK_OFFS             (0xBC)
+#define ARMADA_INT_CLEAR_MASK_OFFS           (0xB8)
+
+#define ARMADA_INT_SET_ENABLE_OFFS           (0xA30)
+#define ARMADA_INT_CLEAR_ENABLE_OFFS         (0xA34)

Quoted 8 lines

arch/arm/mach-armada/irq.c

Quoted 8 lines

arch/arm/mach-armada/irq.c new file +8 -0

+
+#define ARMADA_CPU_INTACK_OFFS               (0xB4)
+
+static void __iomem *per_cpu_int_base; static void __iomem
+*main_int_base; static struct irq_domain *armada_mpic_domain;
+
+static void armada_irq_mask(struct irq_data *d) {
+	writel(d->irq, per_cpu_int_base +

ARMADA_INT_CLEAR_MASK_OFFS); }

Quoted 3 lines

arch/arm/mach-armada/irq.c line 46

Quoted 3 lines

arch/arm/mach-armada/irq.c new file +3 -0

+
+static void armada_irq_unmask(struct irq_data *d) {
+	writel(d->irq, per_cpu_int_base + ARMADA_INT_SET_MASK_OFFS);

}

Quoted 1 line

Quoted 3 lines

All the other orion's use the generic-chip interrupt routines. Can this device also use it? It would also allow you to use the generic DT bindings.

Possibly, but there'll need to be support for setting interrupt affinity added at some point, as this is used on multi-core systems.

--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius

This patch adds basic source files for Marvell Armada SoCs.

Signed-off-by Gregory CLEMENT<[email protected]>

Signed-off-by Thomas Petazzoni<[email protected]>

Signed-off-by Lior Amsalem<[email protected]>

---
  arch/arm/boot/dts/a370.dtsi        |   23 ++++
  arch/arm/boot/dts/armada.dtsi      |   67 ++++++++++
  arch/arm/boot/dts/axp.dtsi         |   43 +++++++
  arch/arm/mach-armada/Kconfig       |    5 +
  arch/arm/mach-armada/Makefile      |    2 +
  arch/arm/mach-armada/Makefile.boot |    1 +
  arch/arm/mach-armada/common.c      |   56 +++++++++
  arch/arm/mach-armada/common.h      |   27 ++++
  arch/arm/mach-armada/irq.c         |  116 +++++++++++++++++
  arch/arm/mach-armada/time.c        |  243 ++++++++++++++++++++++++++++++++++++
  10 files changed, 583 insertions(+)

create mode 100644 arch/arm/boot/dts/a370.dtsi create mode 100644 arch/arm/boot/dts/armada.dtsi create mode 100644 arch/arm/boot/dts/axp.dtsi create mode 100644 arch/arm/mach-armada/Kconfig create mode 100644 arch/arm/mach-armada/Makefile create mode 100644 arch/arm/mach-armada/Makefile.boot create mode 100644 arch/arm/mach-armada/common.c create mode 100644 arch/arm/mach-armada/common.h create mode 100644 arch/arm/mach-armada/irq.c create mode 100644 arch/arm/mach-armada/time.c

arch/arm/boot/dts/a370.dtsi new file +8 -0

new file mode 100644
index 0000000..f11e56a
@@ -0,0 +1,23 @@
+/*
+ * Device Tree Include file for Marvell Armada 370 family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem<[email protected]>
+ * Gregory CLEMENT<[email protected]>
+ * Thomas Petazzoni<[email protected]>

arch/arm/boot/dts/armada.dtsi new file +5 -0

new file mode 100644
index 0000000..3c99c30
@@ -0,0 +1,67 @@
+/*
+ * Device Tree Include file for Marvell Armada family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *

arch/arm/boot/dts/armada.dtsi new file +6 -0

+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "Marvell Armada family SoC";

arch/arm/boot/dts/armada.dtsi new file +7 -0

+	      #interrupt-cells =<1>;
+	      #address-cells =<1>;
+	      #size-cells =<1>;
+	      interrupt-controller;
+	      reg =<0xd0020000 0x1000>,
+		<0xd0021000 0x1000>;
+	};

arch/arm/mach-armada/Kconfig new file +5 -0

new file mode 100644
index 0000000..010a6a3
@@ -0,0 +1,5 @@
+if ARCH_ARMADA
+
+menu "Marvell Armada Implementations"
+
+endif

arch/arm/mach-armada/Makefile new file +2 -0

new file mode 100644
index 0000000..6765961
@@ -0,0 +1,2 @@
+obj-y += common.o irq.o time.o
+

arch/arm/mach-armada/Makefile.boot new file +1 -0

new file mode 100644
index 0000000..b327175
@@ -0,0 +1 @@
+zreladdr-y := 0x00008000

arch/arm/mach-armada/common.c new file +17 -0

new file mode 100644
index 0000000..92d9ec2
@@ -0,0 +1,56 @@
+/*
+ * Core functions for Marvell Armada System On Chip
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem<[email protected]>
+ * Gregory CLEMENT<[email protected]>
+ * Thomas Petazzoni<[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include<linux/kernel.h>
+#include<linux/delay.h>
+#include<linux/init.h>

arch/arm/mach-armada/common.c new file +29 -0

+
+static struct map_desc armada_io_desc[] __initdata = {
+	{
+		.virtual	= ARMADA_REGS_VIRT_BASE,
+		.pfn		= __phys_to_pfn(ARMADA_REGS_PHYS_BASE),
+		.length		= ARMADA_REGS_SIZE,
+		.type		= MT_DEVICE,
+	},
+};
+
+void __init armada_map_io(void)
+{
+	iotable_init(armada_io_desc, ARRAY_SIZE(armada_io_desc));
+}
+
+void armada_restart(char mode, const char *cmd)
+{
+	/*
+	 * Enable soft reset to assert RSTOUTn.
+	 */
+	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+
+	/*
+	 * Assert soft reset.
+	 */
+	writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+	while (1)
+		;
+}

arch/arm/mach-armada/common.h new file +27 -0

new file mode 100644
index 0000000..e453161
@@ -0,0 +1,27 @@
+/*
+ * Core functions for Marvell Armada System On Chip
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem<[email protected]>
+ * Gregory CLEMENT<[email protected]>
+ * Thomas Petazzoni<[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARCH_ARMADA_COMMON_H
+#define __ARCH_ARMADA_COMMON_H
+
+#include<asm/exception.h>
+
+extern struct sys_timer armada_timer;
+
+void armada_map_io(void);
+void armada_init_irq(void);
+void armada_restart(char, const char *);
+asmlinkage void __exception_irq_entry armada_handle_irq(struct pt_regs *regs);
+
+#endif

arch/arm/mach-armada/irq.c new file +23 -0

new file mode 100644
index 0000000..7006429
@@ -0,0 +1,116 @@
+/*
+ * Marvall Armada SoC IRQ handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem<[email protected]>
+ * Gregory CLEMENT<[email protected]>
+ * Thomas Petazzoni<[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include<linux/kernel.h>
+#include<linux/init.h>
+#include<linux/irq.h>
+#include<linux/interrupt.h>
+#include<linux/io.h>
+#include<linux/of_address.h>
+#include<linux/of_irq.h>
+#include<linux/irqdomain.h>
+#include<asm/mach/arch.h>

arch/arm/mach-armada/irq.c new file +24 -0

+
+static void __iomem *per_cpu_int_base;
+static void __iomem *main_int_base;
+static struct irq_domain *armada_mpic_domain;
+
+static void armada_irq_mask(struct irq_data *d)
+{
+	writel(d->irq, per_cpu_int_base + ARMADA_INT_CLEAR_MASK_OFFS);
+}
+
+static void armada_irq_unmask(struct irq_data *d)
+{
+	writel(d->irq, per_cpu_int_base + ARMADA_INT_SET_MASK_OFFS);
+}
+
+static struct irq_chip armada_irq_chip = {
+	.name		= "armada_irq",
+	.irq_mask       = armada_irq_mask,
+	.irq_mask_ack   = armada_irq_mask,
+	.irq_unmask     = armada_irq_unmask,
+};
+
+static int armada_mpic_irq_map(struct irq_domain *h,
+			       unsigned int virq,

arch/arm/mach-armada/irq.c new file +16 -0

+
+	armada_mpic_domain = irq_domain_add_linear(node, NR_IRQS,
+						&armada_mpic_irq_ops, NULL);
+	if (!armada_mpic_domain)
+		panic("Unable to add Armada MPIC irq domain (DT)\n");
+
+	irq_set_default_host(armada_mpic_domain);
+}
+
+asmlinkage void __exception_irq_entry armada_handle_irq(struct pt_regs *regs)
+{
+	u32 irqstat, irqnr;
+
+	do {
+		irqstat = readl_relaxed(per_cpu_int_base +
+					ARMADA_CPU_INTACK_OFFS);

arch/arm/mach-armada/irq.c new file +11 -0

+}
+
+static const struct of_device_id mpic_of_match[] __initconst = {
+	{ .compatible = "marvell,mpic", .data = armada_mpic_of_init },
+	{},
+};
+
+void __init armada_init_irq(void)
+{
+	of_irq_init(mpic_of_match);
+}

arch/arm/mach-armada/time.c new file +17 -0

new file mode 100644
index 0000000..73817ea
@@ -0,0 +1,243 @@
+/*
+ * Marvell Armada SoC timer handling.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem<[email protected]>
+ * Gregory CLEMENT<[email protected]>
+ * Thomas Petazzoni<[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Timer 0 is used as free-running clocksource, while timer 1 is
+ * used as clock_event_device.
+ */
+

arch/arm/mach-armada/time.c new file +67 -0

+
+/*
+ * Timer block registers.
+ */
+#define TIMER_CTRL_OFF		0x0000
+#define  TIMER0_EN		 0x0001
+#define  TIMER0_RELOAD_EN	 0x0002
+#define  TIMER0_25MHZ            0x0800
+#define  TIMER0_DIV(div)         ((div)<<  19)
+#define  TIMER1_EN		 0x0004
+#define  TIMER1_RELOAD_EN	 0x0008
+#define  TIMER1_25MHZ            0x1000
+#define  TIMER1_DIV(div)         ((div)<<  22)
+#define TIMER_EVENTS_STATUS	0x0004
+#define  TIMER0_CLR_MASK         (~0x1)
+#define  TIMER1_CLR_MASK         (~0x100)
+#define TIMER0_RELOAD_OFF	0x0010
+#define TIMER0_VAL_OFF		0x0014
+#define TIMER1_RELOAD_OFF	0x0018
+#define TIMER1_VAL_OFF		0x001c
+
+/* Global timers are connected to the coherency fabric clock, and the
+   below divider reduces their incrementing frequency. */
+#define TIMER_DIVIDER_SHIFT     5
+#define TIMER_DIVIDER           (1<<  TIMER_DIVIDER_SHIFT)
+
+/*
+ * SoC-specific data.
+ */
+static void __iomem *timer_base;
+static int timer_irq;
+
+/*
+ * Number of timer ticks per jiffy.
+ */
+static u32 ticks_per_jiffy;
+
+static u32 notrace armada_read_sched_clock(void)
+{
+	return ~readl(timer_base + TIMER0_VAL_OFF);
+}
+
+/*
+ * Clockevent handling.
+ */
+static int
+armada_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
+{
+	unsigned long flags;
+	u32 u;
+
+	if (delta == 0)
+		return -ETIME;
+
+	local_irq_save(flags);
+
+	/*
+	 * Clear clockevent timer interrupt.
+	 */
+	writel(TIMER1_CLR_MASK, timer_base + TIMER_EVENTS_STATUS);
+
+	/*
+	 * Setup new clockevent timer value.
+	 */
+	writel(delta, timer_base + TIMER1_VAL_OFF);
+
+	/*

arch/arm/mach-armada/time.c new file +28 -0

+}
+
+static void
+armada_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
+{
+	unsigned long flags;
+	u32 u;
+
+	local_irq_save(flags);
+	if (mode == CLOCK_EVT_MODE_PERIODIC) {
+		/*
+		 * Setup timer to fire at 1/HZ intervals.
+		 */
+		writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
+		writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
+
+		/*
+		 * Enable timer.
+		 */
+		u = readl(timer_base + TIMER_CTRL_OFF);
+
+		writel((u | TIMER1_EN | TIMER1_RELOAD_EN |
+			TIMER1_DIV(TIMER_DIVIDER_SHIFT)),
+		       timer_base + TIMER_CTRL_OFF);
+	} else {
+		/*
+		 * Disable timer.
+		 */

arch/arm/mach-armada/time.c new file +15 -0

+static void __init armada_time_init(void)
+{
+	u32 u;
+	struct device_node *np;
+	unsigned int timer_clk;
+
+	np = of_find_compatible_node(NULL, NULL, "marvell,timer");
+	timer_base = of_iomap(np, 0);
+	WARN_ON(!timer_base);
+
+	if (of_find_property(np, "marvell,timer-25Mhz", NULL)) {
+		/* The fixed 25MHz timer is available so let's use it*/
+		u = readl(timer_base + TIMER_CTRL_OFF);
+		writel(u | TIMER0_25MHZ | TIMER1_25MHZ,
+		       timer_base + TIMER_CTRL_OFF);

Quoted 42 lines · Thomas Petazzoni

This patch adds basic source files for Marvell Armada SoCs.

Signed-off-by Gregory CLEMENT<[email protected]>

Signed-off-by Thomas Petazzoni<[email protected]>

Signed-off-by Lior Amsalem<[email protected]>

---
  arch/arm/boot/dts/a370.dtsi        |   23 ++++
  arch/arm/boot/dts/armada.dtsi      |   67 ++++++++++
  arch/arm/boot/dts/axp.dtsi         |   43 +++++++
  arch/arm/mach-armada/Kconfig       |    5 +
  arch/arm/mach-armada/Makefile      |    2 +
  arch/arm/mach-armada/Makefile.boot |    1 +
  arch/arm/mach-armada/common.c      |   56 +++++++++
  arch/arm/mach-armada/common.h      |   27 ++++
  arch/arm/mach-armada/irq.c         |  116 +++++++++++++++++
  arch/arm/mach-armada/time.c        |  243 ++++++++++++++++++++++++++++++++++++
  10 files changed, 583 insertions(+)

create mode 100644 arch/arm/boot/dts/a370.dtsi create mode 100644 arch/arm/boot/dts/armada.dtsi create mode 100644 arch/arm/boot/dts/axp.dtsi create mode 100644 arch/arm/mach-armada/Kconfig create mode 100644 arch/arm/mach-armada/Makefile create mode 100644 arch/arm/mach-armada/Makefile.boot create mode 100644 arch/arm/mach-armada/common.c create mode 100644 arch/arm/mach-armada/common.h create mode 100644 arch/arm/mach-armada/irq.c create mode 100644 arch/arm/mach-armada/time.c

arch/arm/boot/dts/a370.dtsi new file +8 -0

new file mode 100644
index 0000000..f11e56a
@@ -0,0 +1,23 @@
+/*
+ * Device Tree Include file for Marvell Armada 370 family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem<[email protected]>
+ * Gregory CLEMENT<[email protected]>
+ * Thomas Petazzoni<[email protected]>

arch/arm/boot/dts/a370.dtsi line 18

Quoted 10 lines

arch/arm/boot/dts/a370.dtsi new file +10 -0

+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada 370 SoC that are not
+ * common to all Armada SoCs.
+ */
+
+/include/ "armada.dtsi"

I would use armada_xp.dtsi at the least, we've no way of knowing what further Armada devices are going to be produced and whether they will be compatible with.

arch/arm/boot/dts/a370.dtsi line 23

Quoted 4 lines

arch/arm/boot/dts/a370.dtsi new file +4 -0

+/ {
+	model = "Marvell Armada 370 family SoC";
+	compatible = "marvell,armada370", "marvell,armada";
+ };

Firstly, it is mrvl, not marvell everywhere else in the kernel (see MIPS and device tree documentation).

Secondly, I would strongly advise against using the generic marketing name for these devices in the compatible list, "marvell,armada" as we have no way of knowing what new devices will come along in the future and if they'll be compatible.

Quoted 11 lines

arch/arm/boot/dts/armada.dtsi new file +5 -0

new file mode 100644
index 0000000..3c99c30
@@ -0,0 +1,67 @@
+/*
+ * Device Tree Include file for Marvell Armada family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *

arch/arm/boot/dts/armada.dtsi line 15

Quoted 10 lines

arch/arm/boot/dts/armada.dtsi new file +10 -0

+ * Lior Amsalem<[email protected]>
+ * Gregory CLEMENT<[email protected]>
+ * Thomas Petazzoni<[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file contains the definitions that are common to the Armada
+ * 370 and Armada XP SoC.

I really do not want to see these files in the kernel, we where suppose to remove any specific manchine dependency by moving to device tree and not push the problem from a board.c to a .dts file.

Given these really should be part of the bootloader, I am not sure if a GPLv2 compliant license is really appropriate for these files. At best some form of dual-licensing to allow them to be moved out into a devtree repository elsewhere would be useful.

(Feedback from Grant here would be useful)

PS, given the amount of devtree related stuff, CC'ing Grant Likely may have been useful./

Quoted 6 lines

arch/arm/boot/dts/armada.dtsi new file +6 -0

+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "Marvell Armada family SoC";

arch/arm/boot/dts/armada.dtsi line 31

Quoted 10 lines

arch/arm/boot/dts/armada.dtsi new file +10 -0

+	compatible = "marvell,armada";
+
+	cpus {
+		cpu at 0 {
+			compatible = "marvell,sheeva-v7";
+		};
+	};
+
+	mpic: interrupt-controller at d0020000 {
+	      compatible = "marvell,mpic";

Should this be "mrvl,axp_mpic" ?

Quoted 7 lines

arch/arm/boot/dts/armada.dtsi new file +7 -0

+	      #interrupt-cells =<1>;
+	      #address-cells =<1>;
+	      #size-cells =<1>;
+	      interrupt-controller;
+	      reg =<0xd0020000 0x1000>,
+		<0xd0021000 0x1000>;
+	};

arch/arm/boot/dts/armada.dtsi line 48

Quoted 10 lines

arch/arm/boot/dts/armada.dtsi new file +10 -0

+
+	soc {
+		#address-cells =<1>;
+		#size-cells =<1>;
+		compatible = "simple-bus";
+		interrupt-parent =<&mpic>;
+		ranges;
+
+		serial at d0012000 {
+				compatible = "ns16550";

thought these where more akin to the designware uart blocks?

arch/arm/boot/dts/armada.dtsi line 61

Quoted 13 lines

arch/arm/boot/dts/armada.dtsi new file +13 -0

+				reg =<0xd0012000 0x100>;
+				reg-shift =<2>;
+				interrupts =<41>;
+		};
+		serial at d0012100 {
+				compatible = "ns16550";
+				reg =<0xd0012100 0x100>;
+				reg-shift =<2>;
+				interrupts =<42>;
+		};
+
+		timer at d0020300 {
+			       compatible = "marvell,timer";

Is this really a generic marvell timer block?

arch/arm/boot/dts/axp.dtsi

Quoted 10 lines

arch/arm/boot/dts/armada.dtsi new file +6 -0

+			       reg =<0xd0020300 0x30>;
+			       interrupts =<37>,<38>,<39>,<40>;
+		};
+	};
+};
+

arch/arm/boot/dts/axp.dtsi new file +0 -1

new file mode 100644
index 0000000..6427268
--- /dev/null

[snip, pretty much the same comments here.

Quoted 49 lines

arch/arm/mach-armada/Kconfig new file +5 -0

new file mode 100644
index 0000000..010a6a3
@@ -0,0 +1,5 @@
+if ARCH_ARMADA
+
+menu "Marvell Armada Implementations"
+
+endif

arch/arm/mach-armada/Makefile new file +2 -0

new file mode 100644
index 0000000..6765961
@@ -0,0 +1,2 @@
+obj-y += common.o irq.o time.o
+

arch/arm/mach-armada/Makefile.boot new file +1 -0

new file mode 100644
index 0000000..b327175
@@ -0,0 +1 @@
+zreladdr-y := 0x00008000

arch/arm/mach-armada/common.c new file +17 -0

new file mode 100644
index 0000000..92d9ec2
@@ -0,0 +1,56 @@
+/*
+ * Core functions for Marvell Armada System On Chip
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem<[email protected]>
+ * Gregory CLEMENT<[email protected]>
+ * Thomas Petazzoni<[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include<linux/kernel.h>
+#include<linux/delay.h>
+#include<linux/init.h>

arch/arm/mach-armada/common.c line 27

Quoted 10 lines

arch/arm/mach-armada/common.c new file +10 -0

+#include<linux/platform_device.h>
+#include<linux/irq.h>
+#include<linux/timex.h>
+#include<asm/page.h>
+#include<asm/setup.h>
+#include<asm/mach/map.h>
+#include<plat/addr-map.h>
+#include<mach/armada.h>
+#include<mach/bridge-regs.h>
+#include "common.h"

for some reason there are no spaces between #include and the rest of the code?

Quoted 91 lines

arch/arm/mach-armada/common.c new file +29 -0

+
+static struct map_desc armada_io_desc[] __initdata = {
+	{
+		.virtual	= ARMADA_REGS_VIRT_BASE,
+		.pfn		= __phys_to_pfn(ARMADA_REGS_PHYS_BASE),
+		.length		= ARMADA_REGS_SIZE,
+		.type		= MT_DEVICE,
+	},
+};
+
+void __init armada_map_io(void)
+{
+	iotable_init(armada_io_desc, ARRAY_SIZE(armada_io_desc));
+}
+
+void armada_restart(char mode, const char *cmd)
+{
+	/*
+	 * Enable soft reset to assert RSTOUTn.
+	 */
+	writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+
+	/*
+	 * Assert soft reset.
+	 */
+	writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+	while (1)
+		;
+}

arch/arm/mach-armada/common.h new file +27 -0

new file mode 100644
index 0000000..e453161
@@ -0,0 +1,27 @@
+/*
+ * Core functions for Marvell Armada System On Chip
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem<[email protected]>
+ * Gregory CLEMENT<[email protected]>
+ * Thomas Petazzoni<[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARCH_ARMADA_COMMON_H
+#define __ARCH_ARMADA_COMMON_H
+
+#include<asm/exception.h>
+
+extern struct sys_timer armada_timer;
+
+void armada_map_io(void);
+void armada_init_irq(void);
+void armada_restart(char, const char *);
+asmlinkage void __exception_irq_entry armada_handle_irq(struct pt_regs *regs);
+
+#endif

arch/arm/mach-armada/irq.c new file +23 -0

new file mode 100644
index 0000000..7006429
@@ -0,0 +1,116 @@
+/*
+ * Marvall Armada SoC IRQ handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem<[email protected]>
+ * Gregory CLEMENT<[email protected]>
+ * Thomas Petazzoni<[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include<linux/kernel.h>
+#include<linux/init.h>
+#include<linux/irq.h>
+#include<linux/interrupt.h>
+#include<linux/io.h>
+#include<linux/of_address.h>
+#include<linux/of_irq.h>
+#include<linux/irqdomain.h>
+#include<asm/mach/arch.h>

arch/arm/mach-armada/irq.c line 33

Quoted 10 lines

arch/arm/mach-armada/irq.c new file +10 -0

+#include<asm/exception.h>
+
+/* Interrupt Controller Registers Map */
+#define ARMADA_INT_SET_MASK_OFFS             (0xBC)
+#define ARMADA_INT_CLEAR_MASK_OFFS           (0xB8)
+
+#define ARMADA_INT_SET_ENABLE_OFFS           (0xA30)
+#define ARMADA_INT_CLEAR_ENABLE_OFFS         (0xA34)
+
+#define ARMADA_CPU_INTACK_OFFS               (0xB4)

MPIC_ since you indicated earlier that it is pretty generic.

Quoted 24 lines

arch/arm/mach-armada/irq.c new file +24 -0

+
+static void __iomem *per_cpu_int_base;
+static void __iomem *main_int_base;
+static struct irq_domain *armada_mpic_domain;
+
+static void armada_irq_mask(struct irq_data *d)
+{
+	writel(d->irq, per_cpu_int_base + ARMADA_INT_CLEAR_MASK_OFFS);
+}
+
+static void armada_irq_unmask(struct irq_data *d)
+{
+	writel(d->irq, per_cpu_int_base + ARMADA_INT_SET_MASK_OFFS);
+}
+
+static struct irq_chip armada_irq_chip = {
+	.name		= "armada_irq",
+	.irq_mask       = armada_irq_mask,
+	.irq_mask_ack   = armada_irq_mask,
+	.irq_unmask     = armada_irq_unmask,
+};
+
+static int armada_mpic_irq_map(struct irq_domain *h,
+			       unsigned int virq,

arch/arm/mach-armada/irq.c line 67

Quoted 10 lines

arch/arm/mach-armada/irq.c new file +10 -0

+			       irq_hw_number_t hw)
+{
+	armada_irq_mask(irq_get_irq_data(virq));
+	writel(virq, main_int_base + ARMADA_INT_SET_ENABLE_OFFS);
+
+	irq_set_chip_and_handler(virq,&armada_irq_chip,
+				 handle_level_irq);
+	irq_set_status_flags(virq, IRQ_LEVEL);
+	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+	return 0;

you could have used the per-irq driver private data to keep things like the base of controller in.

arch/arm/mach-armada/irq.c line 79

Quoted 12 lines

arch/arm/mach-armada/irq.c new file +12 -0

+}
+
+static struct irq_domain_ops armada_mpic_irq_ops = {
+	.map = armada_mpic_irq_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+static void __init armada_mpic_of_init(struct device_node *node,
+				       struct device_node *parent)
+{
+	main_int_base = of_iomap(node, 0);
+	per_cpu_int_base = of_iomap(node, 1);

Please verify the return values.

Quoted 16 lines

arch/arm/mach-armada/irq.c new file +16 -0

+
+	armada_mpic_domain = irq_domain_add_linear(node, NR_IRQS,
+						&armada_mpic_irq_ops, NULL);
+	if (!armada_mpic_domain)
+		panic("Unable to add Armada MPIC irq domain (DT)\n");
+
+	irq_set_default_host(armada_mpic_domain);
+}
+
+asmlinkage void __exception_irq_entry armada_handle_irq(struct pt_regs *regs)
+{
+	u32 irqstat, irqnr;
+
+	do {
+		irqstat = readl_relaxed(per_cpu_int_base +
+					ARMADA_CPU_INTACK_OFFS);

arch/arm/mach-armada/irq.c line 105

Quoted 10 lines

arch/arm/mach-armada/irq.c new file +10 -0

+		irqnr = irqstat&  0x3FF;
+
+		if (irqnr<  1023) {
+			irqnr = irq_find_mapping(armada_mpic_domain, irqnr);
+			handle_IRQ(irqnr, regs);
+			continue;
+		}
+
+		break;
+	} while (1);

no timeout to get out of handling many IRQs?

Quoted 34 lines

arch/arm/mach-armada/irq.c new file +11 -0

+}
+
+static const struct of_device_id mpic_of_match[] __initconst = {
+	{ .compatible = "marvell,mpic", .data = armada_mpic_of_init },
+	{},
+};
+
+void __init armada_init_irq(void)
+{
+	of_irq_init(mpic_of_match);
+}

arch/arm/mach-armada/time.c new file +17 -0

new file mode 100644
index 0000000..73817ea
@@ -0,0 +1,243 @@
+/*
+ * Marvell Armada SoC timer handling.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem<[email protected]>
+ * Gregory CLEMENT<[email protected]>
+ * Thomas Petazzoni<[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Timer 0 is used as free-running clocksource, while timer 1 is
+ * used as clock_event_device.
+ */
+

arch/arm/mach-armada/time.c line 27

Quoted 10 lines

arch/arm/mach-armada/time.c new file +10 -0

+#include<linux/kernel.h>
+#include<linux/timer.h>
+#include<linux/clockchips.h>
+#include<linux/interrupt.h>
+#include<linux/of.h>
+#include<linux/of_irq.h>
+#include<linux/of_address.h>
+#include<linux/irq.h>
+#include<asm/sched_clock.h>
+#include<asm/mach/time.h>

Style issue again.

Quoted 72 lines

arch/arm/mach-armada/time.c new file +72 -0

+
+/*
+ * Timer block registers.
+ */
+#define TIMER_CTRL_OFF		0x0000
+#define  TIMER0_EN		 0x0001
+#define  TIMER0_RELOAD_EN	 0x0002
+#define  TIMER0_25MHZ            0x0800
+#define  TIMER0_DIV(div)         ((div)<<  19)
+#define  TIMER1_EN		 0x0004
+#define  TIMER1_RELOAD_EN	 0x0008
+#define  TIMER1_25MHZ            0x1000
+#define  TIMER1_DIV(div)         ((div)<<  22)
+#define TIMER_EVENTS_STATUS	0x0004
+#define  TIMER0_CLR_MASK         (~0x1)
+#define  TIMER1_CLR_MASK         (~0x100)
+#define TIMER0_RELOAD_OFF	0x0010
+#define TIMER0_VAL_OFF		0x0014
+#define TIMER1_RELOAD_OFF	0x0018
+#define TIMER1_VAL_OFF		0x001c
+
+/* Global timers are connected to the coherency fabric clock, and the
+   below divider reduces their incrementing frequency. */
+#define TIMER_DIVIDER_SHIFT     5
+#define TIMER_DIVIDER           (1<<  TIMER_DIVIDER_SHIFT)
+
+/*
+ * SoC-specific data.
+ */
+static void __iomem *timer_base;
+static int timer_irq;
+
+/*
+ * Number of timer ticks per jiffy.
+ */
+static u32 ticks_per_jiffy;
+
+static u32 notrace armada_read_sched_clock(void)
+{
+	return ~readl(timer_base + TIMER0_VAL_OFF);
+}
+
+/*
+ * Clockevent handling.
+ */
+static int
+armada_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
+{
+	unsigned long flags;
+	u32 u;
+
+	if (delta == 0)
+		return -ETIME;
+
+	local_irq_save(flags);
+
+	/*
+	 * Clear clockevent timer interrupt.
+	 */
+	writel(TIMER1_CLR_MASK, timer_base + TIMER_EVENTS_STATUS);
+
+	/*
+	 * Setup new clockevent timer value.
+	 */
+	writel(delta, timer_base + TIMER1_VAL_OFF);
+
+	/*
+	 * Enable the timer.
+	 */
+	u = readl(timer_base + TIMER_CTRL_OFF);
+	u = ((u&  ~TIMER1_RELOAD_EN) | TIMER1_EN |
+	     TIMER1_DIV(TIMER_DIVIDER_SHIFT));