ARM: Samsung: Add support for Exynos5250 Rev1.0

From: Changhwan Youn <[email protected]>

Redefine IRQ_MCT_L0,1 irq definition as it is changed in rev1 of EXYNOS5.

Signed-off-by Changhwan Youn <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

Signed-off-by Kukjin Kim <[email protected]>

---
?arch/arm/mach-exynos/include/mach/irqs.h | ? ?4 ++-- ?arch/arm/mach-exynos/mct.c ? ? ? ? ? ? ? | ? 17 +++++++++++------ ?2 files changed, 13 insertions(+), 8 deletions(-)

arch/arm/mach-exynos/include/mach/irqs.h +2 -2

index 591e7852..ef52f61 100644
@@ -331,6 +331,8 @@
 ?#define EXYNOS5_IRQ_SATA ? ? ? ? ? ? ? IRQ_SPI(115)
 ?#define EXYNOS5_IRQ_NFCON ? ? ? ? ? ? ?IRQ_SPI(116)
 
+#define EXYNOS5_IRQ_MCT_L0 ? ? ? ? ? ? IRQ_SPI(120)
+#define EXYNOS5_IRQ_MCT_L1 ? ? ? ? ? ? IRQ_SPI(121)
 ?#define EXYNOS5_IRQ_MMC44 ? ? ? ? ? ? ?IRQ_SPI(123)
 ?#define EXYNOS5_IRQ_MDMA1 ? ? ? ? ? ? ?IRQ_SPI(124)
 ?#define EXYNOS5_IRQ_FIMC_LITE0 ? ? ? ? IRQ_SPI(125)

@@ -410,8 +412,6 @@
 ?#define EXYNOS5_IRQ_FIMD1_SYSTEM ? ? ? COMBINER_IRQ(18, 6)
 
 ?#define EXYNOS5_IRQ_EINT0 ? ? ? ? ? ? ?COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_L0 ? ? ? ? ? ? COMBINER_IRQ(23, 1)
-#define EXYNOS5_IRQ_MCT_L1 ? ? ? ? ? ? COMBINER_IRQ(23, 2)
 ?#define EXYNOS5_IRQ_MCT_G0 ? ? ? ? ? ? COMBINER_IRQ(23, 3)
 ?#define EXYNOS5_IRQ_MCT_G1 ? ? ? ? ? ? COMBINER_IRQ(23, 4)
 ?#define EXYNOS5_IRQ_MCT_G2 ? ? ? ? ? ? COMBINER_IRQ(23, 5)

arch/arm/mach-exynos/mct.c +1 -0

index 897d9a9..b601fb8 100644
@@ -388,6 +388,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 ?{
 ? ? ? ?struct mct_clock_event_device *mevt;
 ? ? ? ?unsigned int cpu = smp_processor_id();
+ ? ? ? int mct_lx_irq;
 
 ? ? ? ?mevt = this_cpu_ptr(&percpu_mct_tick);
 ? ? ? ?mevt->evt = evt;

arch/arm/mach-exynos/mct.c +4 -4

 ? ? ? ? ? ? ? ? ? ? ? ?mct_tick1_event_irq.dev_id = mevt;
- ? ? ? ? ? ? ? ? ? ? ? evt->irq = EXYNOS4_IRQ_MCT_L1;
- ? ? ? ? ? ? ? ? ? ? ? setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
- ? ? ? ? ? ? ? ? ? ? ? irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
+ ? ? ? ? ? ? ? ? ? ? ? evt->irq = mct_lx_irq;
+ ? ? ? ? ? ? ? ? ? ? ? setup_irq(mct_lx_irq, &mct_tick1_event_irq);
+ ? ? ? ? ? ? ? ? ? ? ? irq_set_affinity(mct_lx_irq, cpumask_of(1));
 ? ? ? ? ? ? ? ?}
 ? ? ? ?} else {
 ? ? ? ? ? ? ? ?enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);

@@ -473,7 +478,7 @@ static void __init exynos4_timer_resources(void)
 
 ?static void __init exynos4_timer_init(void)
 ?{
- ? ? ? if (soc_is_exynos4210())
+ ? ? ? if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
 ? ? ? ? ? ? ? ?mct_int_type = MCT_INT_SPI;

? ? ? ?else
? ? ? ? ? ? ? ?mct_int_type = MCT_INT_PPI;

--
1.7.5.4

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Hi,

Quoted 48 lines · Thomas Abraham

From: Changhwan Youn <[email protected]>

Redefine IRQ_MCT_L0,1 irq definition as it is changed in rev1 of EXYNOS5.

Signed-off-by Changhwan Youn <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

Signed-off-by Kukjin Kim <[email protected]>

---
?arch/arm/mach-exynos/include/mach/irqs.h | ? ?4 ++-- ?arch/arm/mach-exynos/mct.c ? ? ? ? ? ? ? | ? 17 +++++++++++------ ?2 files changed, 13 insertions(+), 8 deletions(-)

arch/arm/mach-exynos/include/mach/irqs.h +2 -2

index 591e7852..ef52f61 100644
@@ -331,6 +331,8 @@
 ?#define EXYNOS5_IRQ_SATA ? ? ? ? ? ? ? IRQ_SPI(115)
 ?#define EXYNOS5_IRQ_NFCON ? ? ? ? ? ? ?IRQ_SPI(116)
 
+#define EXYNOS5_IRQ_MCT_L0 ? ? ? ? ? ? IRQ_SPI(120)
+#define EXYNOS5_IRQ_MCT_L1 ? ? ? ? ? ? IRQ_SPI(121)
 ?#define EXYNOS5_IRQ_MMC44 ? ? ? ? ? ? ?IRQ_SPI(123)
 ?#define EXYNOS5_IRQ_MDMA1 ? ? ? ? ? ? ?IRQ_SPI(124)
 ?#define EXYNOS5_IRQ_FIMC_LITE0 ? ? ? ? IRQ_SPI(125)

@@ -410,8 +412,6 @@
 ?#define EXYNOS5_IRQ_FIMD1_SYSTEM ? ? ? COMBINER_IRQ(18, 6)
 
 ?#define EXYNOS5_IRQ_EINT0 ? ? ? ? ? ? ?COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_L0 ? ? ? ? ? ? COMBINER_IRQ(23, 1)
-#define EXYNOS5_IRQ_MCT_L1 ? ? ? ? ? ? COMBINER_IRQ(23, 2)
 ?#define EXYNOS5_IRQ_MCT_G0 ? ? ? ? ? ? COMBINER_IRQ(23, 3)
 ?#define EXYNOS5_IRQ_MCT_G1 ? ? ? ? ? ? COMBINER_IRQ(23, 4)
 ?#define EXYNOS5_IRQ_MCT_G2 ? ? ? ? ? ? COMBINER_IRQ(23, 5)

arch/arm/mach-exynos/mct.c +1 -0

index 897d9a9..b601fb8 100644
@@ -388,6 +388,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 ?{
 ? ? ? ?struct mct_clock_event_device *mevt;
 ? ? ? ?unsigned int cpu = smp_processor_id();
+ ? ? ? int mct_lx_irq;
 
 ? ? ? ?mevt = this_cpu_ptr(&percpu_mct_tick);
 ? ? ? ?mevt->evt = evt;

@@ -414,14 +415,18 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 

arch/arm/mach-exynos/mct.c static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) · line 419

Quoted 4 lines

arch/arm/mach-exynos/mct.c +2 -0

 ? ? ? ?if (mct_int_type == MCT_INT_SPI) {
 ? ? ? ? ? ? ? ?if (cpu == 0) {
+ ? ? ? ? ? ? ? ? ? ? ? mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? EXYNOS5_IRQ_MCT_L0;

Does it still valid for exynos4x12?. It means exynos4x12 uses EXYNOS5_IRQ_MCT_L0?

arch/arm/mach-exynos/mct.c static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) · line 425

Quoted 8 lines

arch/arm/mach-exynos/mct.c +4 -2

 ? ? ? ? ? ? ? ? ? ? ? ?mct_tick0_event_irq.dev_id = mevt;
- ? ? ? ? ? ? ? ? ? ? ? evt->irq = EXYNOS4_IRQ_MCT_L0;
- ? ? ? ? ? ? ? ? ? ? ? setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
+ ? ? ? ? ? ? ? ? ? ? ? evt->irq = mct_lx_irq;
+ ? ? ? ? ? ? ? ? ? ? ? setup_irq(mct_lx_irq, &mct_tick0_event_irq);
 ? ? ? ? ? ? ? ?} else {
+ ? ? ? ? ? ? ? ? ? ? ? mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? EXYNOS5_IRQ_MCT_L1;

ditto

Quoted 10 lines

arch/arm/mach-exynos/mct.c +3 -3

 ? ? ? ? ? ? ? ? ? ? ? ?mct_tick1_event_irq.dev_id = mevt;
- ? ? ? ? ? ? ? ? ? ? ? evt->irq = EXYNOS4_IRQ_MCT_L1;
- ? ? ? ? ? ? ? ? ? ? ? setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
- ? ? ? ? ? ? ? ? ? ? ? irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
+ ? ? ? ? ? ? ? ? ? ? ? evt->irq = mct_lx_irq;
+ ? ? ? ? ? ? ? ? ? ? ? setup_irq(mct_lx_irq, &mct_tick1_event_irq);
+ ? ? ? ? ? ? ? ? ? ? ? irq_set_affinity(mct_lx_irq, cpumask_of(1));
 ? ? ? ? ? ? ? ?}
 ? ? ? ?} else {
 ? ? ? ? ? ? ? ?enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);

Quoted 9 lines

arch/arm/mach-exynos/mct.c +1 -1

@@ -473,7 +478,7 @@ static void __init exynos4_timer_resources(void)
 
 ?static void __init exynos4_timer_init(void)
 ?{
- ? ? ? if (soc_is_exynos4210())
+ ? ? ? if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
 ? ? ? ? ? ? ? ?mct_int_type = MCT_INT_SPI;

? ? ? ?else
? ? ? ? ? ? ? ?mct_int_type = MCT_INT_PPI;

BTW exynos4x12 uses MCT_INT_PPI?

From: Sangsu Park <[email protected]>

Add GPC4 bank instance which is included in rev1 of EXYNOS5.

Cc Grant Likely <[email protected]>

Signed-off-by Sangsu Park <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

[kgene.kim at samsung.com: re-worked on top of v3.4-rc3]

Signed-off-by Kukjin Kim <[email protected]>

---
 arch/arm/mach-exynos/include/mach/gpio.h |    9 ++++++---
 arch/arm/mach-exynos/include/mach/irqs.h |    2 +-
 drivers/gpio/gpio-samsung.c              |   11 ++++++++++-
 3 files changed, 17 insertions(+), 5 deletions(-)

arch/arm/mach-exynos/include/mach/gpio.h +6 -3

index d7498af..eb24f1e 100644
@@ -153,10 +153,11 @@ enum exynos4_gpio_number {
 #define EXYNOS5_GPIO_B2_NR	(4)
 #define EXYNOS5_GPIO_B3_NR	(4)
 #define EXYNOS5_GPIO_C0_NR	(7)
-#define EXYNOS5_GPIO_C1_NR	(7)
+#define EXYNOS5_GPIO_C1_NR	(4)
 #define EXYNOS5_GPIO_C2_NR	(7)
 #define EXYNOS5_GPIO_C3_NR	(7)
-#define EXYNOS5_GPIO_D0_NR	(8)
+#define EXYNOS5_GPIO_C4_NR	(7)
+#define EXYNOS5_GPIO_D0_NR	(4)
 #define EXYNOS5_GPIO_D1_NR	(8)
 #define EXYNOS5_GPIO_Y0_NR	(6)
 #define EXYNOS5_GPIO_Y1_NR	(4)

@@ -199,7 +200,8 @@ enum exynos5_gpio_number {
 	EXYNOS5_GPIO_C1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
 	EXYNOS5_GPIO_C2_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
 	EXYNOS5_GPIO_C3_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
-	EXYNOS5_GPIO_D0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+	EXYNOS5_GPIO_C4_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+	EXYNOS5_GPIO_D0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
 	EXYNOS5_GPIO_D1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
 	EXYNOS5_GPIO_Y0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
 	EXYNOS5_GPIO_Y1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),

@@ -242,6 +244,7 @@ enum exynos5_gpio_number {
 #define EXYNOS5_GPC1(_nr)	(EXYNOS5_GPIO_C1_START + (_nr))
 #define EXYNOS5_GPC2(_nr)	(EXYNOS5_GPIO_C2_START + (_nr))
 #define EXYNOS5_GPC3(_nr)	(EXYNOS5_GPIO_C3_START + (_nr))
+#define EXYNOS5_GPC4(_nr)	(EXYNOS5_GPIO_C4_START + (_nr))
 #define EXYNOS5_GPD0(_nr)	(EXYNOS5_GPIO_D0_START + (_nr))
 #define EXYNOS5_GPD1(_nr)	(EXYNOS5_GPIO_D1_START + (_nr))
 #define EXYNOS5_GPY0(_nr)	(EXYNOS5_GPIO_Y0_START + (_nr))

arch/arm/mach-exynos/include/mach/irqs.h +1 -1

index ef52f61..ece5624 100644
@@ -446,7 +446,7 @@
 
 #define EXYNOS5_MAX_COMBINER_NR		32
 
-#define EXYNOS5_IRQ_GPIO1_NR_GROUPS	13
+#define EXYNOS5_IRQ_GPIO1_NR_GROUPS	14
 #define EXYNOS5_IRQ_GPIO2_NR_GROUPS	9
 #define EXYNOS5_IRQ_GPIO3_NR_GROUPS	5
 #define EXYNOS5_IRQ_GPIO4_NR_GROUPS	1

drivers/gpio/gpio-samsung.c +10 -1

index 19d6fc0..0a2087b 100644
@@ -2452,6 +2452,12 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
 		},
 	}, {
 		.chip	= {
+			.base	= EXYNOS5_GPC4(0),
+			.ngpio	= EXYNOS5_GPIO_C4_NR,
+			.label	= "GPC4",
+		},
+	}, {
+		.chip	= {
 			.base	= EXYNOS5_GPD0(0),
 			.ngpio	= EXYNOS5_GPIO_D0_NR,
 			.label	= "GPD0",

@@ -2874,8 +2880,11 @@ static __init int samsung_gpiolib_init(void)
 			goto err_ioremap1;
 		}
 
+		/* need to set base address for gpc4 */
+		exynos5_gpios_1[11].base = gpio_base1 + 0x2E0;
+
 		/* need to set base address for gpx */
-		chip = &exynos5_gpios_1[20];
+		chip = &exynos5_gpios_1[21];
 		gpx_base = gpio_base1 + 0xC00;
 		for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
 			chip->base = gpx_base;

Signature · 1 line

1.7.5.4

From: Kisoo Yu <[email protected]>

The fout clock of BPLL and MPLL have a selectable source in rev1 of EXYNOS5. The clock options are a fixed divided by 2 clock and the output of the PLL itself. Add support for these new clock instances.

Signed-off-by Kisoo Yu <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

[kgene.kim at samsung.com: temporary apply this because I don't want to add pll stuff in each clock not commonly]

Temporary-Signed-off-by Kukjin Kim <[email protected]>

Signed-off-by Kukjin Kim <[email protected]>

---
 arch/arm/mach-exynos/clock-exynos5.c           |   73
+++++++++++++++++++++++-
 arch/arm/mach-exynos/include/mach/regs-clock.h |    2 +
 arch/arm/plat-s5p/clock.c                      |   11 ----
 3 files changed, 74 insertions(+), 12 deletions(-)

arch/arm/mach- renamed from arch/arm/mach-exynos/clock-exynos5.c +0 -0

exynos/clock-exynos5.c
index 846741e..7c0f810 100644

arch/arm/mach-exynos/clock-exynos5.c +72 -1

@@ -145,6 +145,39 @@ static struct clksrc_clk exynos5_clk_sclk_apll = {
 	.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
 };
 
+static struct clk clk_fout_bpll_div2 = {
+	.name	= "fout_bpll_div2",
+};
+
+static struct clk *exynos5_clkset_mout_bpll_fout_list[] = {
+	[0] = &clk_fout_bpll_div2,
+	[1] = &clk_fout_bpll,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_bpll_fout = {
+	.sources	= exynos5_clkset_mout_bpll_fout_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_bpll_fout_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
+	.clk	= {
+		.name		= "mout_bpll_fout",
+	},
+	.sources = &exynos5_clkset_mout_bpll_fout,
+	.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
+};
+
+/* Possible clock sources for BPLL Mux */
+static struct clk *clk_src_bpll_list[] = {
+	[0] = &clk_fin_bpll,
+	[1] = &exynos5_clk_mout_bpll_fout.clk,
+};
+
+struct clksrc_sources clk_src_bpll = {
+	.sources	= clk_src_bpll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_bpll_list),
+};
+
 static struct clksrc_clk exynos5_clk_mout_bpll = {
 	.clk	= {
 		.name		= "mout_bpll",

@@ -187,11 +220,43 @@ static struct clksrc_clk exynos5_clk_mout_epll = {
 	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
 };
 
+static struct clk clk_fout_mpll_div2 = {
+	.name	= "fout_mpll_div2",
+};
+
+static struct clk *exynos5_clkset_mout_mpll_fout_list[] = {
+	[0] = &clk_fout_mpll_div2,
+	[1] = &clk_fout_mpll,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_mpll_fout = {
+	.sources	= exynos5_clkset_mout_mpll_fout_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_mpll_fout_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
+	.clk	= {
+		.name		= "mout_mpll_fout",
+	},
+	.sources = &exynos5_clkset_mout_mpll_fout,
+	.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_mpll_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &exynos5_clk_mout_mpll_fout.clk,
+};
+
+struct clksrc_sources exynos5_clk_src_mpll = {
+	.sources	= exynos5_clk_src_mpll_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clk_src_mpll_list),
+};
+
 struct clksrc_clk exynos5_clk_mout_mpll = {
 	.clk = {
 		.name		= "mout_mpll",
 	},
-	.sources = &clk_src_mpll,
+	.sources = &exynos5_clk_src_mpll,
 	.reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
 };
 

@@ -946,10 +1011,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
 	&exynos5_clk_mout_apll,
 	&exynos5_clk_sclk_apll,
 	&exynos5_clk_mout_bpll,
+	&exynos5_clk_mout_bpll_fout,
 	&exynos5_clk_mout_bpll_user,
 	&exynos5_clk_mout_cpll,
 	&exynos5_clk_mout_epll,
 	&exynos5_clk_mout_mpll,
+	&exynos5_clk_mout_mpll_fout,
 	&exynos5_clk_mout_mpll_user,
 	&exynos5_clk_vpllsrc,
 	&exynos5_clk_sclk_vpll,

@@ -1013,6 +1080,8 @@ static struct clk *exynos5_clks[] __initdata = {
 	&exynos5_clk_sclk_hdmi27m,
 	&exynos5_clk_sclk_hdmiphy,
 	&clk_fout_bpll,
+	&clk_fout_bpll_div2,
+	&clk_fout_mpll_div2,
 	&clk_fout_cpll,
 	&exynos5_clk_armclk,
 };

@@ -1178,8 +1247,10 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
 
 	clk_fout_apll.ops = &exynos5_fout_apll_ops;
 	clk_fout_bpll.rate = bpll;
+	clk_fout_bpll_div2.rate = bpll >> 1;
 	clk_fout_cpll.rate = cpll;
 	clk_fout_mpll.rate = mpll;
+	clk_fout_mpll_div2.rate = mpll >> 1;
 	clk_fout_epll.rate = epll;
 	clk_fout_vpll.rate = vpll;
 

arch/arm/mach-exynos/include/mach/regs-clock.h +0 -0

index d9578a5..130034d 100644

arch/arm/mach-exynos/include/mach/regs-clock.h +2 -0

+#define EXYNOS5_PLL_DIV2_SEL			EXYNOS_CLKREG(0x20A24)
+
 #define EXYNOS5_BPLL_CON0			EXYNOS_CLKREG(0x20110)
 #define EXYNOS5_CLKSRC_CDREX			EXYNOS_CLKREG(0x20200)
 #define EXYNOS5_CLKDIV_CDREX			EXYNOS_CLKREG(0x20500)

arch/arm/plat-s5p/clock.c +0 -12

index f68a9bb..bea0907 100644
@@ -115,17 +115,6 @@ struct clksrc_sources clk_src_apll = {
 	.nr_sources	= ARRAY_SIZE(clk_src_apll_list),
 };
 
-/* Possible clock sources for BPLL Mux */
-static struct clk *clk_src_bpll_list[] = {
-	[0] = &clk_fin_bpll,
-	[1] = &clk_fout_bpll,
-};
-
-struct clksrc_sources clk_src_bpll = {
-	.sources	= clk_src_bpll_list,
-	.nr_sources	= ARRAY_SIZE(clk_src_bpll_list),
-};
-
 /* Possible clock sources for CPLL Mux */
 static struct clk *clk_src_cpll_list[] = {
 	[0] = &clk_fin_cpll,
--

1.7.5.4

Quoted 7 lines · Thomas Abraham

From: Kisoo Yu <[email protected]>

The fout clock of BPLL and MPLL have a selectable source in rev1 of EXYNOS5. The clock options are a fixed divided by 2 clock and the output of the PLL itself. Add support for these new clock instances.

Quoted 4 lines

Signed-off-by Kisoo Yu <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

[kgene.kim at samsung.com: temporary apply this because I don't want to add pll stuff in each clock not commonly]

As I commented, I won't apply this because pll stuff should be added in common file such as plat-s5p/clock.c even though the plat-s5p files moved into plat-samsung.

The interrupt parent lookup fails for a node that is a interrupt-controller but does not have an explict interrupt-parent property and instead inherits this property from the root node.

Consider the nodes listed below.

    / {
        interrupt-parent = <&intc_level1>;

        intc_level1: interrupt-controller at xxx {
                interrupt-controller;
                #interrupt-cells = <3>;
                <rest of the properties here>;
        };

        intc_level2: interrupt-controller at yyy {
                interrupt-controller;
                #interrupt-cells = <2>;
                <rest of the properties here>;
        };
    };

The interrupt parent lookup for interrupt-controller at yyy fails. It inherits the interrupt-parent property from the root node and the root node ('/') specifies a 'interrupt-parent' property which represents the default interrupt root controller. But, the property '#interrupt-cells' might not be specified in the root node.

In case a interrupt controller node does not include a 'interrupt-parent' property but inherits that property from the root node, the check for 'interrupt-cells' property in the root node fails. Fix this removing the check for 'interrupt-cells' property.

Signed-off-by Thomas Abraham <[email protected]>

---
 drivers/of/irq.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

drivers/of/irq.c +3 -2

index 9cf0060..a520363 100644
@@ -66,14 +66,16 @@ struct device_node *of_irq_find_parent(struct device_node *child)
 		if (parp == NULL)
 			p = of_get_parent(child);
 		else {
+			of_node_put(child);
 			if (of_irq_workarounds & OF_IMAP_NO_PHANDLE)
 				p = of_node_get(of_irq_dflt_pic);
 			else
 				p = of_find_node_by_phandle(be32_to_cpup(parp));
+			return p;
 		}
 		of_node_put(child);
 		child = p;
-	} while (p && of_get_property(p, "#interrupt-cells", NULL) == NULL);
+	} while (p);
 
 	return p;
 }
--

1.7.5.4

Quoted 29 lines · Thomas Abraham

The interrupt parent lookup fails for a node that is a interrupt-controller but does not have an explict interrupt-parent property and instead inherits this property from the root node.

Consider the nodes listed below.

    / {
        interrupt-parent = <&intc_level1>;

        intc_level1: interrupt-controller at xxx {
                interrupt-controller;
                #interrupt-cells = <3>;
                <rest of the properties here>;
        };

        intc_level2: interrupt-controller at yyy {
                interrupt-controller;
                #interrupt-cells = <2>;
                <rest of the properties here>;
        };
    };

The interrupt parent lookup for interrupt-controller at yyy fails. It inherits the interrupt-parent property from the root node and the root node ('/') specifies a 'interrupt-parent' property which represents the default interrupt root controller. But, the property '#interrupt-cells' might not be specified in the root node.

Quoted 4 lines

In case a interrupt controller node does not include a 'interrupt-parent' property but inherits that property from the root node, the check for 'interrupt-cells' property in the root node fails. Fix this removing the check for 'interrupt-cells' property.

Quoted 17 lines

Signed-off-by Thomas Abraham <[email protected]>

---
 drivers/of/irq.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

drivers/of/irq.c +1 -0

index 9cf0060..a520363 100644
@@ -66,14 +66,16 @@ struct device_node *of_irq_find_parent(struct device_node *child)
 		if (parp == NULL)
 			p = of_get_parent(child);
 		else {
+			of_node_put(child);
 			if (of_irq_workarounds & OF_IMAP_NO_PHANDLE)
 				p = of_node_get(of_irq_dflt_pic);

drivers/of/irq.c struct device_node *of_irq_find_parent(struct device_node *child) · line 78

Quoted 8 lines

drivers/of/irq.c +2 -1

 			else
 				p = of_find_node_by_phandle(be32_to_cpup(parp));
+			return p;
 		}
 		of_node_put(child);
 		child = p;
-	} while (p && of_get_property(p, "#interrupt-cells", NULL) == NULL);
+	} while (p);

Quoted 5 lines

drivers/of/irq.c +0 -1

 	return p;
 }
--

1.7.5.4

Hi Grant and Rob,

I'm ok on this and this patch and #11 patch in this series are required for patches that add device tree based support for wakeup interrupts on EXYNOS5250.

So could you have a look at this patch and let us know if this is okay or any rework is required.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Quoted 30 lines · Kukjin Kim

Quoted 29 lines · Thomas Abraham

The interrupt parent lookup fails for a node that is a interrupt-controller but does not have an explict interrupt-parent property and instead inherits this property from the root node.

Consider the nodes listed below.

? ? / {
? ? ? ? interrupt-parent = <&intc_level1>;

? ? ? ? intc_level1: interrupt-controller at xxx { ? ? ? ? ? ? ? ? interrupt-controller;
? ? ? ? ? ? ? ? #interrupt-cells = <3>;
? ? ? ? ? ? ? ? <rest of the properties here>; ? ? ? ? };

? ? ? ? intc_level2: interrupt-controller at yyy { ? ? ? ? ? ? ? ? interrupt-controller;
? ? ? ? ? ? ? ? #interrupt-cells = <2>;
? ? ? ? ? ? ? ? <rest of the properties here>; ? ? ? ? };
? ? };

The interrupt parent lookup for interrupt-controller at yyy fails. It inherits the interrupt-parent property from the root node and the root node ('/') specifies a 'interrupt-parent' property which represents the default interrupt root controller. But, the property '#interrupt-cells' might not be specified in the root node.

Quoted 4 lines

Quoted 4 lines

In case a interrupt controller node does not include a 'interrupt-parent' property but inherits that property from the root node, the check for 'interrupt-cells' property in the root node fails. Fix this removing the check for 'interrupt-cells' property.

Hmmm... I dont see the bug... ?From your description above, I see the following sequence.

First iteration:
? ? ? ?child = &ic at yyy;
? ? ? ?cannot find "interrupt-parent" so take 'if' clause
? ? ? ? ? ? ? ?p = of_get_parent(child); ?(root)
? ? ? ?iteration continues because #interrupt-cells not found in 'p'(root) Second iteration:
? ? ? ?child = root;
? ? ? ?found "interrupt-parent", so take 'else' clause
? ? ? ? ? ? ? ?p = of_find_node_by_phandle(); ?(ic at xxx)
? ? ? ?iteration stops because #interrupt-cells is found in 'p'(ic at xxx)

What am I missing in my admittedly short look at the code?

g.

Quoted 20 lines

Quoted 20 lines

Signed-off-by Thomas Abraham <[email protected]>

---
?drivers/of/irq.c | ? ?4 +++-
?1 files changed, 3 insertions(+), 1 deletions(-)

drivers/of/irq.c +1 -0

index 9cf0060..a520363 100644
@@ -66,14 +66,16 @@ struct device_node *of_irq_find_parent(struct device_node *child)
 ? ? ? ? ? ? if (parp == NULL)
 ? ? ? ? ? ? ? ? ? ? p = of_get_parent(child);
 ? ? ? ? ? ? else {
+ ? ? ? ? ? ? ? ? ? of_node_put(child);
 ? ? ? ? ? ? ? ? ? ? if (of_irq_workarounds & OF_IMAP_NO_PHANDLE)
 ? ? ? ? ? ? ? ? ? ? ? ? ? ? p = of_node_get(of_irq_dflt_pic);

? ? ? ? ? ? ? ? ? ? else
? ? ? ? ? ? ? ? ? ? ? ? ? ? p = of_find_node_by_phandle(be32_to_cpup(parp));
+ ? ? ? ? ? ? ? ? ? return p;

Quoted 5 lines

Quoted 5 lines

? ? ? ? ? ? }
? ? ? ? ? ? of_node_put(child);
? ? ? ? ? ? child = p;
- ? } while (p && of_get_property(p, "#interrupt-cells", NULL) == NULL);
+ ? } while (p);

This does break one use-case. ?Sometimes the interrupt-parent is the same node when an

Quoted 30 lines · Kukjin Kim

Quoted 29 lines · Thomas Abraham

The interrupt parent lookup fails for a node that is a interrupt-controller but does not have an explict interrupt-parent property and instead inherits this property from the root node.

Consider the nodes listed below.

? ? / {
? ? ? ? interrupt-parent = <&intc_level1>;

? ? ? ? intc_level1: interrupt-controller at xxx { ? ? ? ? ? ? ? ? interrupt-controller;
? ? ? ? ? ? ? ? #interrupt-cells = <3>;
? ? ? ? ? ? ? ? <rest of the properties here>; ? ? ? ? };

? ? ? ? intc_level2: interrupt-controller at yyy { ? ? ? ? ? ? ? ? interrupt-controller;
? ? ? ? ? ? ? ? #interrupt-cells = <2>;
? ? ? ? ? ? ? ? <rest of the properties here>; ? ? ? ? };
? ? };

The interrupt parent lookup for interrupt-controller at yyy fails. It inherits the interrupt-parent property from the root node and the root node ('/') specifies a 'interrupt-parent' property which represents the default interrupt root controller. But, the property '#interrupt-cells' might not be specified in the root node.

Quoted 4 lines

Quoted 4 lines

In case a interrupt controller node does not include a 'interrupt-parent' property but inherits that property from the root node, the check for 'interrupt-cells' property in the root node fails. Fix this removing the check for 'interrupt-cells' property.

Hmmm... I dont see the bug... ?From your description above, I see the following sequence.

First iteration:
? ? ? ?child = &ic at yyy;
? ? ? ?cannot find "interrupt-parent" so take 'if' clause
? ? ? ? ? ? ? ?p = of_get_parent(child); ?(root)
? ? ? ?iteration continues because #interrupt-cells not found in 'p'(root) Second iteration:
? ? ? ?child = root;
? ? ? ?found "interrupt-parent", so take 'else' clause
? ? ? ? ? ? ? ?p = of_find_node_by_phandle(); ?(ic at xxx)
? ? ? ?iteration stops because #interrupt-cells is found in 'p'(ic at xxx)

What am I missing in my admittedly short look at the code?

Add a irq_domain for all the 32 gpio external wakeup interrupt sources. Since there are users of fixed linux irq numbers of the external wakeup interrupts, the legacy mapping is used for the irq domain. The fixups required to use irq domain based interrupt mapping is also included.

Cc Grant Likely <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

Acked-by Rob Herring <[email protected]>

---
 arch/arm/mach-exynos/common.c                 |   67 +++++++++++++++++--------
 arch/arm/mach-exynos/include/mach/regs-gpio.h |    4 +-
 2 files changed, 48 insertions(+), 23 deletions(-)

arch/arm/mach-exynos/common.c +46 -21

index 810f804..0d69412 100644
@@ -752,6 +752,9 @@ static DEFINE_SPINLOCK(eint_lock);
 
 static unsigned int eint0_15_data[16];
 
+#define EXYNOS_EINT_NR 32
+static struct irq_domain *irq_domain;
+
 static inline int exynos4_irq_to_gpio(unsigned int irq)
 {
 	if (irq < IRQ_EINT(0))

@@ -842,9 +845,9 @@ static inline void exynos_irq_eint_mask(struct irq_data *data)
 	u32 mask;
 
 	spin_lock(&eint_lock);
-	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
-	mask |= EINT_OFFSET_BIT(data->irq);
-	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
+	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->hwirq));
+	mask |= EINT_OFFSET_BIT(data->hwirq);
+	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->hwirq));
 	spin_unlock(&eint_lock);
 }
 

@@ -853,16 +856,16 @@ static void exynos_irq_eint_unmask(struct irq_data *data)
 	u32 mask;
 
 	spin_lock(&eint_lock);
-	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
-	mask &= ~(EINT_OFFSET_BIT(data->irq));
-	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
+	mask = __raw_readl(EINT_MASK(exynos_eint_base, data->hwirq));
+	mask &= ~(EINT_OFFSET_BIT(data->hwirq));
+	__raw_writel(mask, EINT_MASK(exynos_eint_base, data->hwirq));
 	spin_unlock(&eint_lock);
 }
 
 static inline void exynos_irq_eint_ack(struct irq_data *data)
 {
-	__raw_writel(EINT_OFFSET_BIT(data->irq),
-		     EINT_PEND(exynos_eint_base, data->irq));
+	__raw_writel(EINT_OFFSET_BIT(data->hwirq),
+		     EINT_PEND(exynos_eint_base, data->hwirq));
 }
 
 static void exynos_irq_eint_maskack(struct irq_data *data)

@@ -873,7 +876,7 @@ static void exynos_irq_eint_maskack(struct irq_data *data)
 
 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 {
-	int offs = EINT_OFFSET(data->irq);
+	int offs = data->hwirq;
 	int shift;
 	u32 ctrl, mask;
 	u32 newvalue = 0;

@@ -908,10 +911,10 @@ static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 	mask = 0x7 << shift;
 
 	spin_lock(&eint_lock);
-	ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
+	ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->hwirq));
 	ctrl &= ~mask;
 	ctrl |= newvalue << shift;
-	__raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
+	__raw_writel(ctrl, EINT_CON(exynos_eint_base, data->hwirq));
 	spin_unlock(&eint_lock);
 
 	if (soc_is_exynos5250())

@@ -955,7 +958,7 @@ static inline void exynos_irq_demux_eint(unsigned int start)
 
 	while (status) {
 		irq = fls(status) - 1;
-		generic_handle_irq(irq + start);
+		generic_handle_irq(irq_find_mapping(irq_domain, irq + start));
 		status &= ~(1 << irq);
 	}
 }

@@ -964,8 +967,8 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 {
 	struct irq_chip *chip = irq_get_chip(irq);
 	chained_irq_enter(chip, desc);
-	exynos_irq_demux_eint(IRQ_EINT(16));
-	exynos_irq_demux_eint(IRQ_EINT(24));
+	exynos_irq_demux_eint(16);
+	exynos_irq_demux_eint(24);
 	chained_irq_exit(chip, desc);
 }
 

@@ -973,6 +976,7 @@ static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 {
 	u32 *irq_data = irq_get_handler_data(irq);
 	struct irq_chip *chip = irq_get_chip(irq);
+	int eint_irq;
 
 	chained_irq_enter(chip, desc);
 	chip->irq_mask(&desc->irq_data);

@@ -980,15 +984,28 @@ static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 	if (chip->irq_ack)
 		chip->irq_ack(&desc->irq_data);
 
-	generic_handle_irq(*irq_data);
+	eint_irq = irq_find_mapping(irq_domain, *irq_data);
+	generic_handle_irq(eint_irq);
 
 	chip->irq_unmask(&desc->irq_data);
 	chained_irq_exit(chip, desc);
 }
 
+static int exynos_eint_irq_domain_map(struct irq_domain *d, unsigned int irq,
+					irq_hw_number_t hw)
+{
+	irq_set_chip_and_handler(irq, &exynos_irq_eint, handle_level_irq);
+	set_irq_flags(irq, IRQF_VALID);
+	return 0;
+}
+
+static struct irq_domain_ops exynos_eint_irq_domain_ops = {
+	.map = exynos_eint_irq_domain_map,
+};
+
 static int __init exynos_init_irq_eint(void)
 {
-	int irq, *src_int;
+	int irq, *src_int, irq_base;
 	unsigned int paddr;
 
 	paddr = soc_is_exynos5250() ? EXYNOS5_PA_GPIO1 : EXYNOS4_PA_GPIO2;

@@ -998,16 +1015,24 @@ static int __init exynos_init_irq_eint(void)
 		return -ENXIO;
 	}
 
-	for (irq = 0 ; irq <= 31 ; irq++) {
-		irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
-					 handle_level_irq);
-		set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
+	irq_base = irq_alloc_descs(IRQ_EINT(0), 1, EXYNOS_EINT_NR, 0);
+	if (IS_ERR_VALUE(irq_base)) {
+		irq_base = IRQ_EINT(0);
+		pr_warning("%s: irq desc alloc failed. Continuing with %d as "
+				"linux irq base\n", __func__, irq_base);
+	}
+
+	irq_domain = irq_domain_add_legacy(NULL, EXYNOS_EINT_NR, irq_base, 0,
+					 &exynos_eint_irq_domain_ops, NULL);
+	if (WARN_ON(!irq_domain)) {
+		pr_warning("%s: irq domain init failed\n", __func__);
+		return 0;
 	}
 
 	irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 
 	for (irq = 0 ; irq <= 15; irq++) {
-		eint0_15_data[irq] = IRQ_EINT(irq);
+		eint0_15_data[irq] = irq;
 		src_int = soc_is_exynos5250() ? exynos5_eint0_15_src_int :
 						exynos4_eint0_15_src_int;
 		irq_set_handler_data(src_int[irq], &eint0_15_data[irq]);

arch/arm/mach-exynos/include/mach/regs-gpio.h +2 -2

index e4b5b60..24bf4ec 100644
@@ -16,13 +16,13 @@
 #include <mach/map.h>
 #include <mach/irqs.h>
 
-#define EINT_REG_NR(x)			(EINT_OFFSET(x) >> 3)
+#define EINT_REG_NR(x)			((x) >> 3)
 #define EINT_CON(b, x)			(b + 0xE00 + (EINT_REG_NR(x) * 4))
 #define EINT_FLTCON(b, x)		(b + 0xE80 + (EINT_REG_NR(x) * 4))
 #define EINT_MASK(b, x)			(b + 0xF00 + (EINT_REG_NR(x) * 4))
 #define EINT_PEND(b, x)			(b + 0xF40 + (EINT_REG_NR(x) * 4))
 
-#define EINT_OFFSET_BIT(x)		(1 << (EINT_OFFSET(x) & 0x7))
+#define EINT_OFFSET_BIT(x)		(1 << ((x) & 0x7))
 
 /* compatibility for plat-s5p/irq-pm.c */
 #define EXYNOS4_EINT40CON		(S5P_VA_GPIO2 + 0xE00)

Signature · 1 line

1.7.5.4

Add device tree support for gpio wakeup source interrupt controller for Exynos platforms.

Cc Rob Herring <[email protected]>

Cc Grant Likely <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/mach-exynos/common.c |   92 +++++++++++++++++++++++++++++++++++------
 1 files changed, 79 insertions(+), 13 deletions(-)

arch/arm/mach-exynos/common.c +28 -4

index 544f8b5..074508f 100644
@@ -64,7 +64,8 @@ static void exynos4_init_clocks(int xtal);
 static void exynos5_init_clocks(int xtal);
 static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
-static int exynos_init_irq_eint(void);
+static int exynos_init_irq_eint(struct device_node *np,
+				struct device_node *parent);
 
 static struct cpu_table cpu_ids[] __initdata = {
 	{

@@ -589,6 +590,8 @@ static const struct of_device_id exynos4_dt_irq_match[] = {
 	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
 	{ .compatible = "samsung,exynos4210-combiner",
 			.data = combiner_of_init, },
+	{ .compatible = "samsung,exynos5210-wakeup-eint-map",
+			.data = exynos_init_irq_eint, },
 	{},
 };
 #endif

@@ -606,8 +609,10 @@ void __init exynos4_init_irq(void)
 		of_irq_init(exynos4_dt_irq_match);
 #endif
 
-	if (!of_have_populated_dt())
+	if (!of_have_populated_dt()) {
 		combiner_init(S5P_VA_COMBINER_BASE, NULL);
+		exynos_init_irq_eint(NULL, NULL);
+	}
 
 	/*
 	 * The parameters of s5p_init_irq() are for VIC init.

@@ -615,7 +620,6 @@ void __init exynos4_init_irq(void)
 	 * uses GIC instead of VIC.
 	 */
 	s5p_init_irq(NULL, 0);
-	exynos_init_irq_eint();
 }
 
 void __init exynos5_init_irq(void)

@@ -629,7 +633,6 @@ void __init exynos5_init_irq(void)
 	 * uses GIC instead of VIC.
 	 */
 	s5p_init_irq(NULL, 0);
-	exynos_init_irq_eint();
 }
 
 struct bus_type exynos_subsys = {

@@ -1002,17 +1005,72 @@ static int exynos_eint_irq_domain_map(struct irq_domain *d, unsigned int irq,
 	return 0;
 }
 
+#ifdef CONFIG_OF
+static int exynos_eint_irq_domain_xlate(struct irq_domain *d,
+		struct device_node *controller, const u32 *intspec,
+		unsigned int intsize, unsigned long *out_hwirq,
+		unsigned int *out_type)
+{
+	if (d->of_node != controller)
+		return -EINVAL;
+	if (intsize < 2)
+		return -EINVAL;
+	*out_hwirq = intspec[0];
+
+	switch (intspec[1]) {
+	case S5P_IRQ_TYPE_LEVEL_LOW:
+		*out_type = IRQ_TYPE_LEVEL_LOW;
+		break;
+	case S5P_IRQ_TYPE_LEVEL_HIGH:
+		*out_type = IRQ_TYPE_LEVEL_HIGH;
+		break;
+	case S5P_IRQ_TYPE_EDGE_FALLING:
+		*out_type = IRQ_TYPE_EDGE_FALLING;

arch/arm/mach-exynos/common.c +33 -7

+}
+#else
+static int exynos_eint_irq_domain_xlate(struct irq_domain *d,
+		struct device_node *controller, const u32 *intspec,
+		unsigned int intsize, unsigned long *out_hwirq,
+		unsigned int *out_type)
+{
+	return -EINVAL;
+}
+#endif
+
 static struct irq_domain_ops exynos_eint_irq_domain_ops = {
+	.xlate = exynos_eint_irq_domain_xlate,
 	.map = exynos_eint_irq_domain_map,
 };
 
-static int __init exynos_init_irq_eint(void)
+static int __init exynos_init_irq_eint(struct device_node *eint_np,
+					struct device_node *parent)
 {
-	int irq, *src_int, irq_base;
+	int irq, *src_int, irq_base, irq_eint;
 	unsigned int paddr;
+	static unsigned int retry = 0;
+	static struct device_node *np;
 
-	paddr = soc_is_exynos5250() ? EXYNOS5_PA_GPIO1 : EXYNOS4_PA_GPIO2;
-	exynos_eint_base = ioremap(paddr, SZ_4K);
+	if (retry)
+		goto retry_init;
+
+	if (!eint_np) {
+		paddr = soc_is_exynos5250() ? EXYNOS5_PA_GPIO1 :
+						EXYNOS4_PA_GPIO2;
+		exynos_eint_base = ioremap(paddr, SZ_4K);
+	} else {
+		np = of_get_parent(eint_np);
+		exynos_eint_base = of_iomap(np, 0);
+	}
 	if (!exynos_eint_base) {
 		pr_err("unable to ioremap for EINT base address\n");
 		return -ENXIO;

@@ -1025,21 +1083,29 @@ static int __init exynos_init_irq_eint(void)
 				"linux irq base\n", __func__, irq_base);
 	}
 
-	irq_domain = irq_domain_add_legacy(NULL, EXYNOS_EINT_NR, irq_base, 0,
+	irq_domain = irq_domain_add_legacy(np, EXYNOS_EINT_NR, irq_base, 0,
 					 &exynos_eint_irq_domain_ops, NULL);
 	if (WARN_ON(!irq_domain)) {
 		pr_warning("%s: irq domain init failed\n", __func__);
 		return 0;
 	}
 
-	irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
+	irq_eint = eint_np ? irq_of_parse_and_map(np, 16) : EXYNOS_IRQ_EINT16_31;
+	irq_set_chained_handler(irq_eint, exynos_irq_demux_eint16_31);
 
-	for (irq = 0 ; irq <= 15; irq++) {
+retry_init:
+	for (irq = 0; irq <= 15; irq++) {
 		eint0_15_data[irq] = irq;
 		src_int = soc_is_exynos5250() ? exynos5_eint0_15_src_int :
 						exynos4_eint0_15_src_int;

Updated EXYNOS5 device tree source files to reflect changes in rev1 of EXYNOS5 SoC. This includes new additions to the EXYNOS5 dtsi and SMDK5250 dts files and few minor fixes.

Signed-off-by Thomas Abraham <[email protected]>

Signed-off-by Kukjin Kim <[email protected]>

---
?arch/arm/boot/dts/exynos5250-smdk5250.dts | ? 52 +++++++++++++++++++++++++++++ ?arch/arm/boot/dts/exynos5250.dtsi ? ? ? ? | ? 44 +++++++----------------- ?2 files changed, 65 insertions(+), 31 deletions(-)

arch/arm/boot/dts/exynos5250-smdk5250.dts +0 -0

index 399d17b..bcc4b89 100644

Hi,

Quoted 16 lines · Thomas Abraham

Updated EXYNOS5 device tree source files to reflect changes in rev1 of EXYNOS5 SoC. This includes new additions to the EXYNOS5 dtsi and SMDK5250 dts files and few minor fixes.

Signed-off-by Thomas Abraham <[email protected]>

Signed-off-by Kukjin Kim <[email protected]>

---
?arch/arm/boot/dts/exynos5250-smdk5250.dts | ? 52 +++++++++++++++++++++++++++++ ?arch/arm/boot/dts/exynos5250.dtsi ? ? ? ? | ? 44 +++++++----------------- ?2 files changed, 65 insertions(+), 31 deletions(-)

arch/arm/boot/dts/exynos5250-smdk5250.dts +0 -0

index 399d17b..bcc4b89 100644

arch/arm/boot/dts/exynos5250-smdk5250.dts line 29

Quoted 7 lines

arch/arm/boot/dts/exynos5250-smdk5250.dts +4 -0

@@ -23,4 +23,56 @@
 ? ? ? ?chosen {
 ? ? ? ? ? ? ? ?bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
 ? ? ? ?};
+
+ ? ? ? i2c at 12C60000 {
+ ? ? ? ? ? ? ? #address-cells = <1>;
+ ? ? ? ? ? ? ? #size-cells = <0>;

Two nits:

#a-c and #s-c is likely to always be 1/0, so you might as well move these to the dtsi file for the SoC.

Also, we tend to use non-caps here and in other locations (so it should be 12c60000 here).

-Olof

And interrupt combiner, external interrupt wakeup interrupt controller and smsc9215 lan controller nodes.

Signed-off-by Thomas Abraham <[email protected]>

---
?arch/arm/boot/dts/exynos5250-smdk5250.dts | ? 11 ++++++ ?arch/arm/boot/dts/exynos5250.dtsi ? ? ? ? | ? 55 +++++++++++++++++++++++++++++ ?2 files changed, 66 insertions(+), 0 deletions(-)

arch/arm/boot/dts/exynos5250-smdk5250.dts +1 -0

index bcc4b89..dbc4bdb 100644
@@ -24,6 +24,17 @@
 ? ? ? ? ? ? ? ?bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
 ? ? ? ?};
 
+ ? ? ? lan9215 at 0x05000000 {

Hi,

[adding devicetree-discuss]

Quoted 18 lines · Thomas Abraham

And interrupt combiner, external interrupt wakeup interrupt controller and smsc9215 lan controller nodes.

Signed-off-by Thomas Abraham <[email protected]>

---
??arch/arm/boot/dts/exynos5250-smdk5250.dts | ?? 11 ++++++ ??arch/arm/boot/dts/exynos5250.dtsi ?? ?? ?? ?? | ?? 55 +++++++++++++++++++++++++++++ ??2 files changed, 66 insertions(+), 0 deletions(-)

arch/arm/boot/dts/exynos5250-smdk5250.dts +1 -0

index bcc4b89..dbc4bdb 100644
@@ -24,6 +24,17 @@
 ?? ?? ?? ?? ?? ?? ?? ??bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
 ?? ?? ?? ??};
 
+ ?? ?? ?? lan9215 at 0x05000000 {

arch/arm/boot/dts/exynos5250-smdk5250.dts line 37

Quoted 10 lines

arch/arm/boot/dts/exynos5250-smdk5250.dts +10 -0

+ ?? ?? ?? ?? ?? ?? ?? compatible = "smsc,lan9215", "smsc,lan9115";
+ ?? ?? ?? ?? ?? ?? ?? reg = <0x05000000 0x20000>;
+ ?? ?? ?? ?? ?? ?? ?? interrupts = <5 0>;
+ ?? ?? ?? ?? ?? ?? ?? interrupt-parent = <&wakeup_eint>;
+ ?? ?? ?? ?? ?? ?? ?? phy-mode = "mii";
+ ?? ?? ?? ?? ?? ?? ?? smsc,irq-push-pull;
+ ?? ?? ?? ?? ?? ?? ?? smsc,force-internal-phy;
+ ?? ?? ?? ?? ?? ?? ?? local-mac-address = [00 80 00 23 45 67];
+ ?? ?? ?? };
+

since the 911x sits on a chipselect bus, you should instead add that bus to the dtsi and define this on that bus.

Something like this in the dtsi:

       sromc-bus {
               #address-cells = <2>;
               #size-cells = <1>;
               ranges = < 0 0 0x04000000 0x20000
                          1 0 0x05000000 0x20000
                          2 0 0x06000000 0x20000
                          3 0 0x07000000 0x20000>;
       };

and in the dts:

       sromc-bus {
               lan9215 at 1,0 {
                       compatible = "smsc,lan9215", "smsc,lan9115";
                       reg = <1 0 0x20000>;
                       interrupts = <5 0>;
                       interrupt-parent = <&wakeup_eint>;
                       phy-mode = "mii";
                       smsc,irq-push-pull;
                       smsc,force-internal-phy;
                       local-mac-address = [00 80 00 23 45 67];
               };
        };

(You might be able to do just fine with one address cell, I'm not 100% sure why Grant's example uses two, but I used the same above for consistency).

Also, I don't think it's a good idea to hardcode the mac address in the dts like this; have u-boot fill it in from the environment variable there instead, if needed.

Quoted 65 lines · Olof Johansson

Hi,

[adding devicetree-discuss]

Quoted 18 lines · Thomas Abraham

And interrupt combiner, external interrupt wakeup interrupt controller and smsc9215 lan controller nodes.

Signed-off-by Thomas Abraham <[email protected]>

---
?arch/arm/boot/dts/exynos5250-smdk5250.dts | ? 11 ++++++ ?arch/arm/boot/dts/exynos5250.dtsi ? ? ? ? | ? 55 +++++++++++++++++++++++++++++ ?2 files changed, 66 insertions(+), 0 deletions(-)

arch/arm/boot/dts/exynos5250-smdk5250.dts +1 -0

index bcc4b89..dbc4bdb 100644
@@ -24,6 +24,17 @@
 ? ? ? ? ? ? ? ?bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
 ? ? ? ?};
 
+ ? ? ? lan9215 at 0x05000000 {

arch/arm/boot/dts/exynos5250-smdk5250.dts line 37

Quoted 10 lines

arch/arm/boot/dts/exynos5250-smdk5250.dts +10 -0

+ ? ? ? ? ? ? ? compatible = "smsc,lan9215", "smsc,lan9115";
+ ? ? ? ? ? ? ? reg = <0x05000000 0x20000>;
+ ? ? ? ? ? ? ? interrupts = <5 0>;
+ ? ? ? ? ? ? ? interrupt-parent = <&wakeup_eint>;
+ ? ? ? ? ? ? ? phy-mode = "mii";
+ ? ? ? ? ? ? ? smsc,irq-push-pull;
+ ? ? ? ? ? ? ? smsc,force-internal-phy;
+ ? ? ? ? ? ? ? local-mac-address = [00 80 00 23 45 67];
+ ? ? ? };
+

since the 911x sits on a chipselect bus, you should instead add that bus to the dtsi and define this on that bus.

Something like this in the dtsi:

? ? ? ?sromc-bus {
? ? ? ? ? ? ? ?#address-cells = <2>;
? ? ? ? ? ? ? ?#size-cells = <1>;
? ? ? ? ? ? ? ?ranges = < 0 0 0x04000000 0x20000 ? ? ? ? ? ? ? ? ? ? ? ? ? 1 0 0x05000000 0x20000 ? ? ? ? ? ? ? ? ? ? ? ? ? 2 0 0x06000000 0x20000 ? ? ? ? ? ? ? ? ? ? ? ? ? 3 0 0x07000000 0x20000>; ? ? ? ?};

and in the dts:

? ? ? ?sromc-bus {
? ? ? ? ? ? ? ?lan9215 at 1,0 {
? ? ? ? ? ? ? ? ? ? ? ?compatible = "smsc,lan9215", "smsc,lan9115"; ? ? ? ? ? ? ? ? ? ? ? ?reg = <1 0 0x20000>;
? ? ? ? ? ? ? ? ? ? ? ?interrupts = <5 0>;
? ? ? ? ? ? ? ? ? ? ? ?interrupt-parent = <&wakeup_eint>; ? ? ? ? ? ? ? ? ? ? ? ?phy-mode = "mii";
? ? ? ? ? ? ? ? ? ? ? ?smsc,irq-push-pull;
? ? ? ? ? ? ? ? ? ? ? ?smsc,force-internal-phy;
? ? ? ? ? ? ? ? ? ? ? ?local-mac-address = [00 80 00 23 45 67]; ? ? ? ? ? ? ? ?};
? ? ? ? };

Quoted 3 lines

(You might be able to do just fine with one address cell, I'm not 100% sure why Grant's example uses two, but I used the same above for consistency).

Because otherwise there is no way to describe an offset from the base of the chipselect base value, and the core code will try to apply the size to the cs part of the address specifier. (so in the example above the address range described by:

? ? ? ?reg = <1 0x20000>;

would mean cs values 1 to 0x20001; which is definitely wrong.

This patch series adds support for Samsung's Exynos5250 Rev1.0. It includes
fixes for device tree support, updates for rev1.0 silicon and device tree discovery for combiner and wakeup interrupt controller. This patch series depricates the existing support for Exynos5250 Rev0.0.

This patchset is based and tested on top of v3.4-rc5.

Boojin Kim (1):
ARM: EXYNOS: Support DMA for EXYNOS5250 SoC

Changhwan Youn (2):
ARM: EXYNOS: Modify the GIC physical address for static io-mapping
ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition

Kisoo Yu (1):
ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll

Kukjin Kim (2):
ARM: EXYNOS: fix ctrlbit for exynos5_clk_pdma1
ARM: EXYNOS: update irqs for EXYNOS5250 evt1

Sangsu Park (1):
ARM: EXYNOS: add GPC4 bank instance

Thomas Abraham (13):
ARM: EXYNOS: Add watchdog timer clock instance
ARM: Exynos: Remove a new bus_type instance for Exynos5 of/irq: fix interrupt parent lookup procedure
of/irq: add retry support for interrupt controller tree initialization
ARM: Exynos: Add irq_domain support for interrupt combiner
ARM: Exynos: Add device tree support for interrupt combiner
ARM: Exynos: Simplify the wakeup interrupt setup code
ARM: Exynos: Add irq_domain support for gpio wakeup interrupts
ARM: Exynos: Remove arch_initcall for wakeup interrupt initialization
ARM: Exynos: Add device tree support for gpio wakeup interrupt
controller
ARM: dts: Update device tree source files for EXYNOS5250
ARM: Exynos5: Add combiner, wakeup interrupt controller and ethernet
nodes
ARM: Exynos5: Add AUXDATA for i2c controllers

 .../bindings/arm/samsung/interrupt-combiner.txt    |   52 +++
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |   63 ++++
 arch/arm/boot/dts/exynos5250.dtsi                  |   99 ++++--
 arch/arm/mach-exynos/Kconfig                       |    7 +-
 arch/arm/mach-exynos/Makefile                      |    2 +-
 arch/arm/mach-exynos/clock-exynos5.c               |   80 +++++-
 arch/arm/mach-exynos/common.c                      |  338

 arch/arm/mach-exynos/dma.c                         |  129 +++++++--
 arch/arm/mach-exynos/include/mach/gpio.h           |    9 +-
 arch/arm/mach-exynos/include/mach/irqs.h           |   40 ++-
 arch/arm/mach-exynos/include/mach/map.h            |    4 +-
 arch/arm/mach-exynos/include/mach/regs-clock.h     |    2 +
 arch/arm/mach-exynos/include/mach/regs-gpio.h      |    4 +-
 arch/arm/mach-exynos/mach-exynos5-dt.c             |    4 +
 arch/arm/mach-exynos/mct.c                         |   17 +-
 arch/arm/mach-exynos/pm.c                          |    2 +-
 arch/arm/plat-s5p/clock.c                          |   11 -
 arch/arm/plat-samsung/Kconfig                      |    2 +-
 arch/arm/plat-samsung/include/plat/cpu.h           |    2 +-
 arch/arm/plat-samsung/include/plat/dma-pl330.h     |    1 +
 drivers/gpio/gpio-samsung.c                        |   11 +-
 drivers/of/irq.c                                   |   29 ++-
 22 files changed, 698 insertions(+), 210 deletions(-)
 create mode 100644

Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt

--
1.7.5.4

Quoted 69 lines · Thomas Abraham

This patch series adds support for Samsung's Exynos5250 Rev1.0. It includes
fixes for device tree support, updates for rev1.0 silicon and device tree discovery for combiner and wakeup interrupt controller. This patch series depricates the existing support for Exynos5250 Rev0.0.

This patchset is based and tested on top of v3.4-rc5.

Boojin Kim (1):
ARM: EXYNOS: Support DMA for EXYNOS5250 SoC

Changhwan Youn (2):
ARM: EXYNOS: Modify the GIC physical address for static io-mapping
ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition

Kisoo Yu (1):
ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll

Kukjin Kim (2):
ARM: EXYNOS: fix ctrlbit for exynos5_clk_pdma1
ARM: EXYNOS: update irqs for EXYNOS5250 evt1

Sangsu Park (1):
ARM: EXYNOS: add GPC4 bank instance

Thomas Abraham (13):
ARM: EXYNOS: Add watchdog timer clock instance
ARM: Exynos: Remove a new bus_type instance for Exynos5 of/irq: fix interrupt parent lookup procedure
of/irq: add retry support for interrupt controller tree initialization
ARM: Exynos: Add irq_domain support for interrupt combiner
ARM: Exynos: Add device tree support for interrupt combiner
ARM: Exynos: Simplify the wakeup interrupt setup code
ARM: Exynos: Add irq_domain support for gpio wakeup interrupts
ARM: Exynos: Remove arch_initcall for wakeup interrupt initialization
ARM: Exynos: Add device tree support for gpio wakeup interrupt
controller
ARM: dts: Update device tree source files for EXYNOS5250
ARM: Exynos5: Add combiner, wakeup interrupt controller and ethernet
nodes
ARM: Exynos5: Add AUXDATA for i2c controllers

 .../bindings/arm/samsung/interrupt-combiner.txt    |   52 +++
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |   63 ++++
 arch/arm/boot/dts/exynos5250.dtsi                  |   99 ++++--
 arch/arm/mach-exynos/Kconfig                       |    7 +-
 arch/arm/mach-exynos/Makefile                      |    2 +-
 arch/arm/mach-exynos/clock-exynos5.c               |   80 +++++-
 arch/arm/mach-exynos/common.c                      |  338 ++++++++++++++------
 arch/arm/mach-exynos/dma.c                         |  129 +++++++--
 arch/arm/mach-exynos/include/mach/gpio.h           |    9 +-
 arch/arm/mach-exynos/include/mach/irqs.h           |   40 ++-
 arch/arm/mach-exynos/include/mach/map.h            |    4 +-
 arch/arm/mach-exynos/include/mach/regs-clock.h     |    2 +
 arch/arm/mach-exynos/include/mach/regs-gpio.h      |    4 +-
 arch/arm/mach-exynos/mach-exynos5-dt.c             |    4 +
 arch/arm/mach-exynos/mct.c                         |   17 +-
 arch/arm/mach-exynos/pm.c                          |    2 +-
 arch/arm/plat-s5p/clock.c                          |   11 -
 arch/arm/plat-samsung/Kconfig                      |    2 +-
 arch/arm/plat-samsung/include/plat/cpu.h           |    2 +-
 arch/arm/plat-samsung/include/plat/dma-pl330.h     |    1 +
 drivers/gpio/gpio-samsung.c                        |   11 +-
 drivers/of/irq.c                                   |   29 ++-
 22 files changed, 698 insertions(+), 210 deletions(-)
 create mode 100644

Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt

Quoted 2 lines

--
1.7.5.4

Hi,

Basically, it's ok to me on 1st~9th patches except #7 as I commented. Will apply them but need to update #7. And I will look at the others again. If any comments, let you know.

Hi,

Looks ok to me but some patches, #10 and #11 patches need to get the ack from Grant. And the #14 to #17 and #19 patches have a dependency on that. However now other patches which are including my re-work can be applied, so I will.

Thomas, please address comments from Olof on 18th patch.