spi: s3c64xx: add support for device tree

The macro S3C64XX_SPI_ST_TRLCNTZ is not used and hence it is removed.

Signed-off-by Thomas Abraham <[email protected]>

Acked-by Jaswinder Singh <[email protected]>

---
 drivers/spi/spi-s3c64xx.c |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

drivers/spi/spi-s3c64xx.c +0 -4

index 972a94c..6a3d51a 100644
@@ -113,10 +113,6 @@
 
 #define S3C64XX_SPI_FBCLK_MSK		(3<<0)
 
-#define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \
-					(((i)->fifo_lvl_mask + 1))) \
-					? 1 : 0)
-
 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0)
 #define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
 #define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)

Signature · 1 line

1.6.6.rc2

Platform data is used to specify controller hardware specific information such as the tx/rx fifo level mask and bit offset of rx fifo level. Such information is not suitable to be supplied from device tree. Instead, it can be moved into the driver data and removed from platform data.

Signed-off-by Thomas Abraham <[email protected]>

Acked-by Jaswinder Singh <[email protected]>

---
 arch/arm/mach-exynos/clock-exynos4.c             |   18 +-
 arch/arm/mach-exynos/setup-spi.c                 |   25 ---
 arch/arm/mach-s3c24xx/clock-s3c2416.c            |    2 +-
 arch/arm/mach-s3c24xx/clock-s3c2443.c            |    2 +-
 arch/arm/mach-s3c24xx/common-s3c2443.c           |    4 +-
 arch/arm/mach-s3c24xx/setup-spi.c                |    8 -
 arch/arm/mach-s3c64xx/clock.c                    |   20 ++--
 arch/arm/mach-s3c64xx/setup-spi.c                |   13 --
 arch/arm/mach-s5p64x0/clock-s5p6440.c            |   12 +-
 arch/arm/mach-s5p64x0/clock-s5p6450.c            |   12 +-
 arch/arm/mach-s5p64x0/setup-spi.c                |   16 --
 arch/arm/mach-s5pc100/clock.c                    |   30 ++--
 arch/arm/mach-s5pc100/setup-spi.c                |   22 ---
 arch/arm/mach-s5pv210/clock.c                    |   14 +-
 arch/arm/mach-s5pv210/setup-spi.c                |   15 --
 arch/arm/plat-samsung/include/plat/s3c64xx-spi.h |   15 --
 drivers/spi/spi-s3c64xx.c                        |  180 ++++++++++++++++++----
 17 files changed, 210 insertions(+), 198 deletions(-)

arch/arm/mach-exynos/clock-exynos4.c +9 -9

index bcb7db4..10a46a9 100644
@@ -586,17 +586,17 @@ static struct clk exynos4_init_clocks_off[] = {
 		.ctrlbit	= (1 << 13),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "exynos4210-spi.0",
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 16),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "exynos4210-spi.1",
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 17),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.2",
+		.devname	= "exynos4210-spi.2",
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 18),
 	}, {

@@ -1245,7 +1245,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
 static struct clksrc_clk exynos4_clk_sclk_spi0 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "exynos4210-spi.0",
 		.enable		= exynos4_clksrc_mask_peril1_ctrl,
 		.ctrlbit	= (1 << 16),
 	},

@@ -1257,7 +1257,7 @@ static struct clksrc_clk exynos4_clk_sclk_spi0 = {
 static struct clksrc_clk exynos4_clk_sclk_spi1 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "exynos4210-spi.1",
 		.enable		= exynos4_clksrc_mask_peril1_ctrl,
 		.ctrlbit	= (1 << 20),
 	},

@@ -1269,7 +1269,7 @@ static struct clksrc_clk exynos4_clk_sclk_spi1 = {
 static struct clksrc_clk exynos4_clk_sclk_spi2 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.2",
+		.devname	= "exynos4210-spi.2",
 		.enable		= exynos4_clksrc_mask_peril1_ctrl,
 		.ctrlbit	= (1 << 24),
 	},

@@ -1347,9 +1347,9 @@ static struct clk_lookup exynos4_clk_lookup[] = {
 	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
 	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
 	CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
-	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
-	CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
+	CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
+	CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
+	CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
 };
 
 static int xtal_rate;

arch/arm/mach-exynos/setup-spi.c +0 -25

index 833ff40..a71ec4d 100644
@@ -12,17 +12,8 @@
 #include <linux/platform_device.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-	.fifo_lvl_mask	= 0x1ff,
-	.rx_lvl_offset	= 15,
-	.high_speed	= 1,
-	.clk_from_cmu	= true,
-	.tx_st_done	= 25,
-};
-
 int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));

@@ -34,14 +25,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 15,
-	.high_speed	= 1,
-	.clk_from_cmu	= true,
-	.tx_st_done	= 25,
-};
-
 int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));

@@ -53,14 +36,6 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI2
-struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 15,
-	.high_speed	= 1,
-	.clk_from_cmu	= true,
-	.tx_st_done	= 25,
-};
-
 int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));

arch/arm/mach-s3c24xx/clock-s3c2416.c +1 -1

index 8702ecf..a582ba1 100644
@@ -144,7 +144,7 @@ static struct clk_lookup s3c2416_clk_lookup[] = {
 	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
 	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk),
+	CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk),
 };
 
 void __init s3c2416_init_clocks(int xtal)

arch/arm/mach-s3c24xx/clock-s3c2443.c +1 -1

index a4c5a52..7f689ce 100644
@@ -181,7 +181,7 @@ static struct clk *clks[] __initdata = {
 
 static struct clk_lookup s3c2443_clk_lookup[] = {
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk),
+	CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &clk_hsspi.clk),
 };
 
 void __init s3c2443_init_clocks(int xtal)

arch/arm/mach-s3c24xx/common-s3c2443.c +2 -2

index aeeb2be..aeb4a24 100644
@@ -559,7 +559,7 @@ static struct clk hsmmc1_clk = {
 
 static struct clk hsspi_clk = {
 	.name		= "spi",
-	.devname	= "s3c64xx-spi.0",
+	.devname	= "s3c2443-spi.0",
 	.parent		= &clk_p,
 	.enable		= s3c2443_clkcon_enable_p,
 	.ctrlbit	= S3C2443_PCLKCON_HSSPI,

@@ -633,7 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
 	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
 	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk),
+	CLKDEV_INIT("s3c2443-spi.0", "spi_busclk0", &hsspi_clk),
 };
 
 void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,

arch/arm/mach-s3c24xx/setup-spi.c +0 -8

index 5712c85..42abe15 100644
@@ -13,19 +13,11 @@
 #include <linux/platform_device.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 13,
-	.tx_st_done	= 21,
-	.high_speed	= 1,
-};
-
 int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev)
 {
 	/* enable hsspi bit in misccr */

arch/arm/mach-s3c64xx/clock.c +10 -10

index 52f079a..28041e8 100644
@@ -178,13 +178,13 @@ static struct clk init_clocks_off[] = {
 		.ctrlbit	= S3C_CLKCON_PCLK_KEYPAD,
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s3c6410-spi.0",
 		.parent		= &clk_p,
 		.enable		= s3c64xx_pclk_ctrl,
 		.ctrlbit	= S3C_CLKCON_PCLK_SPI0,
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s3c6410-spi.1",
 		.parent		= &clk_p,
 		.enable		= s3c64xx_pclk_ctrl,
 		.ctrlbit	= S3C_CLKCON_PCLK_SPI1,

@@ -331,7 +331,7 @@ static struct clk init_clocks_off[] = {
 
 static struct clk clk_48m_spi0 = {
 	.name		= "spi_48m",
-	.devname	= "s3c64xx-spi.0",
+	.devname	= "s3c6410-spi.0",
 	.parent		= &clk_48m,
 	.enable		= s3c64xx_sclk_ctrl,
 	.ctrlbit	= S3C_CLKCON_SCLK_SPI0_48,

@@ -339,7 +339,7 @@ static struct clk clk_48m_spi0 = {
 
 static struct clk clk_48m_spi1 = {
 	.name		= "spi_48m",
-	.devname	= "s3c64xx-spi.1",
+	.devname	= "s3c6410-spi.1",
 	.parent		= &clk_48m,
 	.enable		= s3c64xx_sclk_ctrl,
 	.ctrlbit	= S3C_CLKCON_SCLK_SPI1_48,

@@ -802,7 +802,7 @@ static struct clksrc_clk clk_sclk_mmc2 = {
 static struct clksrc_clk clk_sclk_spi0 = {
 	.clk	= {
 		.name		= "spi-bus",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s3c6410-spi.0",
 		.ctrlbit	= S3C_CLKCON_SCLK_SPI0,
 		.enable		= s3c64xx_sclk_ctrl,
 	},

@@ -814,7 +814,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
 	.clk	= {
 		.name		= "spi-bus",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s3c6410-spi.1",
 		.ctrlbit	= S3C_CLKCON_SCLK_SPI1,
 		.enable		= s3c64xx_sclk_ctrl,
 	},

@@ -858,10 +858,10 @@ static struct clk_lookup s3c64xx_clk_lookup[] = {
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
 	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
 	CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
-	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
-	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
+	CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+	CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0),
+	CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+	CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1),
 };
 
 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)

arch/arm/mach-s3c64xx/setup-spi.c +0 -13

index d9592ad..ff999d9 100644
@@ -12,15 +12,8 @@
 #include <linux/platform_device.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 13,
-	.tx_st_done	= 21,
-};
-
 int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,

@@ -30,12 +23,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 13,
-	.tx_st_done	= 21,
-};
-
 int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,

arch/arm/mach-s5p64x0/clock-s5p6440.c +6 -6

index ee1e8e7..55ea3ab 100644
@@ -227,13 +227,13 @@ static struct clk init_clocks_off[] = {
 		.ctrlbit	= (1 << 17),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s5p64x0-spi.0",
 		.parent		= &clk_pclk_low.clk,
 		.enable		= s5p64x0_pclk_ctrl,
 		.ctrlbit	= (1 << 21),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s5p64x0-spi.1",
 		.parent		= &clk_pclk_low.clk,
 		.enable		= s5p64x0_pclk_ctrl,
 		.ctrlbit	= (1 << 22),

@@ -467,7 +467,7 @@ static struct clksrc_clk clk_sclk_uclk = {
 static struct clksrc_clk clk_sclk_spi0 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s5p64x0-spi.0",
 		.ctrlbit	= (1 << 20),
 		.enable		= s5p64x0_sclk_ctrl,
 	},

@@ -479,7 +479,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s5p64x0-spi.1",
 		.ctrlbit	= (1 << 21),
 		.enable		= s5p64x0_sclk_ctrl,
 	},

@@ -519,8 +519,8 @@ static struct clk_lookup s5p6440_clk_lookup[] = {
 	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
 	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
 	CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+	CLKDEV_INIT("s5p64x0.0", "spi_busclk1", &clk_sclk_spi0.clk),
+	CLKDEV_INIT("s5p64x0.1", "spi_busclk1", &clk_sclk_spi1.clk),
 	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
 	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),

arch/arm/mach-s5p64x0/clock-s5p6450.c +6 -6

index dae6a13..f3e0ef3 100644
@@ -236,13 +236,13 @@ static struct clk init_clocks_off[] = {
 		.ctrlbit	= (1 << 17),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s5p64x0-spi.0",
 		.parent		= &clk_pclk_low.clk,
 		.enable		= s5p64x0_pclk_ctrl,
 		.ctrlbit	= (1 << 21),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s5p64x0-spi.1",
 		.parent		= &clk_pclk_low.clk,
 		.enable		= s5p64x0_pclk_ctrl,
 		.ctrlbit	= (1 << 22),

@@ -528,7 +528,7 @@ static struct clksrc_clk clk_sclk_uclk = {
 static struct clksrc_clk clk_sclk_spi0 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s5p64x0-spi.0",
 		.ctrlbit	= (1 << 20),
 		.enable		= s5p64x0_sclk_ctrl,
 	},

@@ -540,7 +540,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s5p64x0-spi.1",
 		.ctrlbit	= (1 << 21),
 		.enable		= s5p64x0_sclk_ctrl,
 	},

@@ -562,8 +562,8 @@ static struct clk_lookup s5p6450_clk_lookup[] = {
 	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
 	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
 	CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+	CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+	CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
 	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
 	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),

arch/arm/mach-s5p64x0/setup-spi.c +0 -16

index e9b8412..1cf84b5 100644
@@ -10,19 +10,9 @@
 
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
-#include <linux/io.h>
-
 #include <plat/gpio-cfg.h>
-#include <plat/cpu.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-	.fifo_lvl_mask	= 0x1ff,
-	.rx_lvl_offset	= 15,
-	.tx_st_done	= 25,
-};
-
 int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 {
 	if (soc_is_s5p6450())

@@ -36,12 +26,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 15,
-	.tx_st_done	= 25,
-};
-
 int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 {
 	if (soc_is_s5p6450())

arch/arm/mach-s5pc100/clock.c +15 -15

index 16eca4e..9262197 100644
@@ -564,19 +564,19 @@ static struct clk init_clocks_off[] = {
 		.ctrlbit	= (1 << 5),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s5pc100-spi.0",
 		.parent		= &clk_div_d1_bus.clk,
 		.enable		= s5pc100_d1_4_ctrl,
 		.ctrlbit	= (1 << 6),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s5pc100-spi.1",
 		.parent		= &clk_div_d1_bus.clk,
 		.enable		= s5pc100_d1_4_ctrl,
 		.ctrlbit	= (1 << 7),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.2",
+		.devname	= "s5pc100-spi.2",
 		.parent		= &clk_div_d1_bus.clk,
 		.enable		= s5pc100_d1_4_ctrl,
 		.ctrlbit	= (1 << 8),

@@ -702,7 +702,7 @@ static struct clk clk_hsmmc0 = {
 
 static struct clk clk_48m_spi0 = {
 	.name		= "spi_48m",
-	.devname	= "s3c64xx-spi.0",
+	.devname	= "s5pc100-spi.0",
 	.parent		= &clk_mout_48m.clk,
 	.enable		= s5pc100_sclk0_ctrl,
 	.ctrlbit	= (1 << 7),

@@ -710,7 +710,7 @@ static struct clk clk_48m_spi0 = {
 
 static struct clk clk_48m_spi1 = {
 	.name		= "spi_48m",
-	.devname	= "s3c64xx-spi.1",
+	.devname	= "s5pc100-spi.1",
 	.parent		= &clk_mout_48m.clk,
 	.enable		= s5pc100_sclk0_ctrl,
 	.ctrlbit	= (1 << 8),

@@ -718,7 +718,7 @@ static struct clk clk_48m_spi1 = {
 
 static struct clk clk_48m_spi2 = {
 	.name		= "spi_48m",
-	.devname	= "s3c64xx-spi.2",
+	.devname	= "s5pc100-spi.2",
 	.parent		= &clk_mout_48m.clk,
 	.enable		= s5pc100_sclk0_ctrl,
 	.ctrlbit	= (1 << 9),

@@ -1085,7 +1085,7 @@ static struct clksrc_clk clk_sclk_mmc2 = {
 static struct clksrc_clk clk_sclk_spi0 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s5pc100-spi.0",
 		.ctrlbit	= (1 << 4),
 		.enable		= s5pc100_sclk0_ctrl,
 	},

@@ -1097,7 +1097,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s5pc100-spi.1",
 		.ctrlbit	= (1 << 5),
 		.enable		= s5pc100_sclk0_ctrl,
 	},

@@ -1109,7 +1109,7 @@ static struct clksrc_clk clk_sclk_spi1 = {
 static struct clksrc_clk clk_sclk_spi2 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.2",
+		.devname	= "s5pc100-spi.2",
 		.ctrlbit	= (1 << 6),
 		.enable		= s5pc100_sclk0_ctrl,
 	},

@@ -1315,12 +1315,12 @@ static struct clk_lookup s5pc100_clk_lookup[] = {
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
 	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
 	CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
-	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
-	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
-	CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2),
-	CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
+	CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0),
+	CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
+	CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1),
+	CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
+	CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2),
+	CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
 };
 
 void __init s5pc100_register_clocks(void)

arch/arm/mach-s5pc100/setup-spi.c +0 -22

index 431a6f7..4b42718 100644
@@ -12,16 +12,8 @@
 #include <linux/platform_device.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 13,
-	.high_speed	= 1,
-	.tx_st_done	= 21,
-};
-
 int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,

@@ -31,13 +23,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 13,
-	.high_speed	= 1,
-	.tx_st_done	= 21,
-};
-
 int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,

@@ -47,13 +32,6 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI2
-struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 13,
-	.high_speed	= 1,
-	.tx_st_done	= 21,
-};
-
 int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));

arch/arm/mach-s5pv210/clock.c +7 -7

index 09609d5..fcdf52d 100644
@@ -445,19 +445,19 @@ static struct clk init_clocks_off[] = {
 		.ctrlbit	= (1 << 11),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s5pv210-spi.0",
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
 		.ctrlbit	= (1<<12),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s5pv210-spi.1",
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
 		.ctrlbit	= (1<<13),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.2",
+		.devname	= "s5pv210-spi.2",
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
 		.ctrlbit	= (1<<14),

@@ -1035,7 +1035,7 @@ static struct clksrc_clk clk_sclk_mmc3 = {
 static struct clksrc_clk clk_sclk_spi0 = {
 	.clk		= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s5pv210-spi.0",
 		.enable		= s5pv210_clk_mask0_ctrl,
 		.ctrlbit	= (1 << 16),
 	},

@@ -1047,7 +1047,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
 	.clk		= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s5pv210-spi.1",
 		.enable		= s5pv210_clk_mask0_ctrl,
 		.ctrlbit	= (1 << 17),
 	},

@@ -1331,8 +1331,8 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
 	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
 	CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
 	CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+	CLKDEV_INIT("s5pv210-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+	CLKDEV_INIT("s5pv210-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
 };
 
 void __init s5pv210_register_clocks(void)

arch/arm/mach-s5pv210/setup-spi.c +0 -15

index f43c504..2cd66a6 100644
@@ -12,16 +12,8 @@
 #include <linux/platform_device.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
-	.fifo_lvl_mask	= 0x1ff,
-	.rx_lvl_offset	= 15,
-	.high_speed	= 1,
-	.tx_st_done	= 25,
-};
-
 int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));

@@ -33,13 +25,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 15,
-	.high_speed	= 1,
-	.tx_st_done	= 25,
-};
-
 int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));

arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +0 -15

index fa95e9a..4e9b9c3 100644
@@ -33,28 +33,13 @@ struct s3c64xx_spi_csinfo {
 /**
  * struct s3c64xx_spi_info - SPI Controller defining structure
  * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
- * @clk_from_cmu: If the SPI clock/prescalar control block is present
- *     by the platform's clock-management-unit and not in SPI controller.
  * @num_cs: Number of CS this controller emulates.
  * @cfg_gpio: Configure pins for this SPI controller.
- * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
- * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
- * @high_speed: If the controller supports HIGH_SPEED_EN bit
- * @tx_st_done: Depends on tx fifo_lvl field
  */
 struct s3c64xx_spi_info {
 	int src_clk_nr;
-	bool clk_from_cmu;
-
 	int num_cs;
-
 	int (*cfg_gpio)(struct platform_device *pdev);
-
-	/* Following two fields are for future compatibility */
-	int fifo_lvl_mask;
-	int rx_lvl_offset;
-	int high_speed;
-	int tx_st_done;
 };
 
 /**

drivers/spi/spi-s3c64xx.c +153 -27

index 6a3d51a..f6bc0e3 100644
@@ -31,6 +31,8 @@
 #include <mach/dma.h>
 #include <plat/s3c64xx-spi.h>
 
+#define MAX_SPI_PORTS		3
+
 /* Registers and bit-fields */
 
 #define S3C64XX_SPI_CH_CFG		0x00

@@ -113,9 +115,12 @@
 
 #define S3C64XX_SPI_FBCLK_MSK		(3<<0)
 
-#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0)
-#define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
-#define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
+#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
+#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
+				(1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
+#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
+#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
+					FIFO_LVL_MASK(i))
 
 #define S3C64XX_SPI_MAX_TRAILCNT	0x3ff
 #define S3C64XX_SPI_TRAILCNT_OFF	19

@@ -134,6 +139,28 @@ struct s3c64xx_spi_dma_data {
 };
 
 /**
+ * struct s3c64xx_spi_info - SPI Controller hardware info
+ * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
+ * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
+ * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
+ * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
+ * @clk_from_cmu: True, if the controller does not include a clock mux and
+ *	prescaler unit.
+ *
+ * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
+ * differ in some aspects such as the size of the fifo and spi bus clock
+ * setup. Such differences are specified to the driver using this structure
+ * which is provided as driver data to the driver.
+ */
+struct s3c64xx_spi_port_config {
+	int	fifo_lvl_mask[MAX_SPI_PORTS];
+	int	rx_lvl_offset;
+	int	tx_st_done;
+	bool	high_speed;
+	bool	clk_from_cmu;
+};
+
+/**
  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
  * @clk: Pointer to the spi clock.
  * @src_clk: Pointer to the clock used to generate SPI signals.

@@ -171,6 +198,8 @@ struct s3c64xx_spi_driver_data {
 	struct s3c64xx_spi_dma_data	rx_dma;
 	struct s3c64xx_spi_dma_data	tx_dma;
 	struct samsung_dma_ops		*ops;
+	struct s3c64xx_spi_port_config	*port_conf;
+	unsigned			port_id;
 };
 
 static struct s3c2410_dma_client s3c64xx_spi_dma_client = {

@@ -179,7 +208,6 @@ static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
 
 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 {
-	struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 	void __iomem *regs = sdd->regs;
 	unsigned long loops;
 	u32 val;

@@ -195,7 +223,7 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 	loops = msecs_to_loops(1);
 	do {
 		val = readl(regs + S3C64XX_SPI_STATUS);
-	} while (TX_FIFO_LVL(val, sci) && loops--);
+	} while (TX_FIFO_LVL(val, sdd) && loops--);
 
 	if (loops == 0)
 		dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");

@@ -204,7 +232,7 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 	loops = msecs_to_loops(1);
 	do {
 		val = readl(regs + S3C64XX_SPI_STATUS);
-		if (RX_FIFO_LVL(val, sci))
+		if (RX_FIFO_LVL(val, sdd))
 			readl(regs + S3C64XX_SPI_RX_DATA);
 		else
 			break;

@@ -302,7 +330,6 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 				struct spi_device *spi,
 				struct spi_transfer *xfer, int dma_mode)
 {
-	struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 	void __iomem *regs = sdd->regs;
 	u32 modecfg, chcfg;
 

@@ -352,7 +379,7 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 	if (xfer->rx_buf != NULL) {
 		sdd->state |= RXBUSY;
 
-		if (sci->high_speed && sdd->cur_speed >= 30000000UL
+		if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
 					&& !(sdd->cur_mode & SPI_CPHA))
 			chcfg |= S3C64XX_SPI_CH_HS_EN;
 

@@ -392,7 +419,6 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
 				struct spi_transfer *xfer, int dma_mode)
 {
-	struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 	void __iomem *regs = sdd->regs;
 	unsigned long val;
 	int ms;

@@ -409,7 +435,7 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
 		val = msecs_to_loops(ms);
 		do {
 			status = readl(regs + S3C64XX_SPI_STATUS);
-		} while (RX_FIFO_LVL(status, sci) < xfer->len && --val);
+		} while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 	}
 
 	if (!val)

@@ -428,8 +454,8 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
 		if (xfer->rx_buf == NULL) {
 			val = msecs_to_loops(10);
 			status = readl(regs + S3C64XX_SPI_STATUS);
-			while ((TX_FIFO_LVL(status, sci)
-				|| !S3C64XX_SPI_ST_TX_DONE(status, sci))
+			while ((TX_FIFO_LVL(status, sdd)
+				|| !S3C64XX_SPI_ST_TX_DONE(status, sdd))
 					&& --val) {
 				cpu_relax();
 				status = readl(regs + S3C64XX_SPI_STATUS);

@@ -478,12 +504,11 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
 
 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 {
-	struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 	void __iomem *regs = sdd->regs;
 	u32 val;
 
 	/* Disable Clock */
-	if (sci->clk_from_cmu) {
+	if (sdd->port_conf->clk_from_cmu) {
 		clk_disable(sdd->src_clk);
 	} else {
 		val = readl(regs + S3C64XX_SPI_CLK_CFG);

@@ -527,7 +552,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 
 	writel(val, regs + S3C64XX_SPI_MODE_CFG);
 
-	if (sci->clk_from_cmu) {
+	if (sdd->port_conf->clk_from_cmu) {
 		/* Configure Clock */
 		/* There is half-multiplier before the SPI */
 		clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);

@@ -553,7 +578,6 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
 						struct spi_message *msg)
 {
-	struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 	struct device *dev = &sdd->pdev->dev;
 	struct spi_transfer *xfer;
 

@@ -569,7 +593,7 @@ static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
 	/* Map until end or first fail */
 	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 
-		if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
+		if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 			continue;
 
 		if (xfer->tx_buf != NULL) {

@@ -603,7 +627,6 @@ static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
 						struct spi_message *msg)
 {
-	struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 	struct device *dev = &sdd->pdev->dev;
 	struct spi_transfer *xfer;
 

@@ -612,7 +635,7 @@ static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
 
 	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 
-		if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
+		if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 			continue;
 
 		if (xfer->rx_buf != NULL

@@ -631,7 +654,6 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
 					    struct spi_message *msg)
 {
 	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
-	struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 	struct spi_device *spi = msg->spi;
 	struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 	struct spi_transfer *xfer;

@@ -686,7 +708,7 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
 		}
 
 		/* Polling method for xfers not bigger than FIFO capacity */
-		if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
+		if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 			use_dma = 0;
 		else
 			use_dma = 1;

@@ -840,7 +862,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
 	pm_runtime_get_sync(&sdd->pdev->dev);
 
 	/* Check if we can provide the requested rate */
-	if (!sci->clk_from_cmu) {
+	if (!sdd->port_conf->clk_from_cmu) {
 		u32 psr, speed;
 
 		/* Max possible */

@@ -921,7 +943,7 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
 	/* Disable Interrupts - we use Polling if not DMA mode */
 	writel(0, regs + S3C64XX_SPI_INT_EN);
 
-	if (!sci->clk_from_cmu)
+	if (!sdd->port_conf->clk_from_cmu)
 		writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
 				regs + S3C64XX_SPI_CLK_CFG);
 	writel(0, regs + S3C64XX_SPI_MODE_CFG);

@@ -942,6 +964,13 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
 	flush_fifo(sdd);
 }
 
+static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
+						struct platform_device *pdev)
+{
+	return (struct s3c64xx_spi_port_config *)
+			 platform_get_device_id(pdev)->driver_data;
+}
+
 static int __init s3c64xx_spi_probe(struct platform_device *pdev)
 {
 	struct resource	*mem_res, *dmatx_res, *dmarx_res;

@@ -1000,6 +1029,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, master);
 
 	sdd = spi_master_get_devdata(master);
+	sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
 	sdd->master = master;
 	sdd->cntrlr_info = sci;
 	sdd->pdev = pdev;

@@ -1008,10 +1038,11 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
 	sdd->tx_dma.direction = DMA_MEM_TO_DEV;
 	sdd->rx_dma.dmach = dmarx_res->start;
 	sdd->rx_dma.direction = DMA_DEV_TO_MEM;
+	sdd->port_id = pdev->id;
 
 	sdd->cur_bpw = 8;
 
-	master->bus_num = pdev->id;
+	master->bus_num = sdd->port_id;
 	master->setup = s3c64xx_spi_setup;
 	master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
 	master->transfer_one_message = s3c64xx_spi_transfer_one_message;

@@ -1071,7 +1102,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
 	}
 
 	/* Setup Deufult Mode */
-	s3c64xx_spi_hwinit(sdd, pdev->id);
+	s3c64xx_spi_hwinit(sdd, sdd->port_id);
 
 	spin_lock_init(&sdd->lock);
 	init_completion(&sdd->xfer_completion);

@@ -1096,7 +1127,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
 
 	dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d "
 					"with %d Slaves attached\n",
-					pdev->id, master->num_chipselect);
+					sdd->port_id, master->num_chipselect);
 	dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
 					mem_res->end, mem_res->start,
 					sdd->rx_dma.dmach, sdd->tx_dma.dmach);

@@ -1189,7 +1220,7 @@ static int s3c64xx_spi_resume(struct device *dev)
 	clk_enable(sdd->src_clk);
 	clk_enable(sdd->clk);
 
-	s3c64xx_spi_hwinit(sdd, pdev->id);
+	s3c64xx_spi_hwinit(sdd, sdd->port_id);
 
 	spi_master_resume(master);
 

@@ -1227,6 +1258,100 @@ static const struct dev_pm_ops s3c64xx_spi_pm = {
 			   s3c64xx_spi_runtime_resume, NULL)
 };
 
+#if defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2443)
+struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
+	.fifo_lvl_mask	= { 0x7f },
+	.rx_lvl_offset	= 13,
+	.tx_st_done	= 21,
+	.high_speed	= true,
+};
+#define S3C2443_SPI_PORT_CONFIG ((kernel_ulong_t)&s3c2443_spi_port_config)
+#else
+#define S3C2443_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif
+
+#ifdef CONFIG_ARCH_S3C64XX
+struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
+	.fifo_lvl_mask	= { 0x7f, 0x7F },
+	.rx_lvl_offset	= 13,
+	.tx_st_done	= 21,
+};
+#define S3C6410_SPI_PORT_CONFIG ((kernel_ulong_t)&s3c6410_spi_port_config)
+#else
+#define S3C6410_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif /* CONFIG_ARCH_S3C64XX */
+
+#ifdef CONFIG_ARCH_S5P64X0
+struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
+	.fifo_lvl_mask	= { 0x1ff, 0x7F },
+	.rx_lvl_offset	= 15,
+	.tx_st_done	= 25,
+};
+#define S5P64X0_SPI_PORT_CONFIG ((kernel_ulong_t)&s5p64x0_spi_port_config)
+#else
+#define S5P64X0_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif /* CONFIG_ARCH_S5P64X0 */
+
+#ifdef CONFIG_ARCH_S5PC100
+struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
+	.fifo_lvl_mask	= { 0x7f, 0x7F },
+	.rx_lvl_offset	= 13,
+	.tx_st_done	= 21,
+	.high_speed	= true,
+};
+#define S5PC100_SPI_PORT_CONFIG ((kernel_ulong_t)&s5pc100_spi_port_config)
+#else
+#define S5PC100_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif /* CONFIG_ARCH_S5PC100 */
+
+#ifdef CONFIG_ARCH_S5PV210
+struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
+	.fifo_lvl_mask	= { 0x1ff, 0x7F },
+	.rx_lvl_offset	= 15,
+	.tx_st_done	= 25,
+	.high_speed	= 1,
+};
+#define S5PV210_SPI_PORT_CONFIG ((kernel_ulong_t)&s5pv210_spi_port_config)
+#else
+#define S5PV210_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif /* CONFIG_ARCH_S5PV210 */
+
+#ifdef CONFIG_ARCH_EXYNOS4
+struct s3c64xx_spi_port_config exynos4_spi_port_config = {
+	.fifo_lvl_mask	= { 0x1ff, 0x7F, 0x7F },
+	.rx_lvl_offset	= 15,
+	.tx_st_done	= 25,
+	.high_speed	= 1,
+	.clk_from_cmu	= true,
+};
+#define EXYNOS4_SPI_PORT_CONFIG ((kernel_ulong_t)&exynos4_spi_port_config)
+#else
+#define EXYNOS4_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif /* CONFIG_ARCH_EXYNOS4 */
+
+static struct platform_device_id s3c64xx_spi_driver_ids[] = {
+	{
+		.name		= "s3c2443-spi",
+		.driver_data	= S3C2443_SPI_PORT_CONFIG,
+	}, {
+		.name		= "s3c6410-spi",
+		.driver_data	= S3C6410_SPI_PORT_CONFIG,
+	}, {
+		.name		= "s5p64x0-spi",
+		.driver_data	= S5P64X0_SPI_PORT_CONFIG,
+	}, {
+		.name		= "s5pc100-spi",
+		.driver_data	= S5PC100_SPI_PORT_CONFIG,
+	}, {
+		.name		= "s5pv210-spi",
+		.driver_data	= S5PV210_SPI_PORT_CONFIG,
+	}, {
+		.name		= "exynos4210-spi",
+		.driver_data	= EXYNOS4_SPI_PORT_CONFIG,
+	},
+	{ },
+};
+
 static struct platform_driver s3c64xx_spi_driver = {
 	.driver = {
 		.name	= "s3c64xx-spi",

@@ -1234,6 +1359,7 @@ static struct platform_driver s3c64xx_spi_driver = {
 		.pm = &s3c64xx_spi_pm,
 	},
 	.remove = s3c64xx_spi_remove,
+	.id_table = s3c64xx_spi_driver_ids,
 };
 MODULE_ALIAS("platform:s3c64xx-spi");
 

Signature · 1 line

1.6.6.rc2

Platform data is used to specify controller hardware specific information such as the tx/rx fifo level mask and bit offset of rx fifo level. Such information is not suitable to be supplied from device tree. Instead, it can be moved into the driver data and removed from platform data.

Signed-off-by Thomas Abraham <[email protected]>

Acked-by Jaswinder Singh <[email protected]>

---
 arch/arm/mach-exynos/clock-exynos4.c             |   18 +-
 arch/arm/mach-exynos/setup-spi.c                 |   25 ---
 arch/arm/mach-s3c24xx/clock-s3c2416.c            |    2 +-
 arch/arm/mach-s3c24xx/clock-s3c2443.c            |    2 +-
 arch/arm/mach-s3c24xx/common-s3c2443.c           |    4 +-
 arch/arm/mach-s3c24xx/setup-spi.c                |    8 -
 arch/arm/mach-s3c64xx/clock.c                    |   20 ++--
 arch/arm/mach-s3c64xx/setup-spi.c                |   13 --
 arch/arm/mach-s5p64x0/clock-s5p6440.c            |   12 +-

 arch/arm/mach-s5p64x0/clock-s5p6450.c            |   12 +-
 arch/arm/mach-s5p64x0/setup-spi.c                |   16 --
 arch/arm/mach-s5pc100/clock.c                    |   30 ++--
 arch/arm/mach-s5pc100/setup-spi.c                |   22 ---
 arch/arm/mach-s5pv210/clock.c                    |   14 +-
 arch/arm/mach-s5pv210/setup-spi.c                |   15 --
 arch/arm/plat-samsung/include/plat/s3c64xx-spi.h |   15 --
 drivers/spi/spi-s3c64xx.c                        |  180

 17 files changed, 210 insertions(+), 198 deletions(-)

arch/arm/mach- renamed from arch/arm/mach-s5p64x0/clock-s5p6440.c +0 -0

s5p64x0/clock-s5p6440.c
index ee1e8e7..55ea3ab 100644

arch/arm/mach-s5p64x0/clock-s5p6440.c +0 -0

arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +0 -0

index fa95e9a..4e9b9c3 100644

drivers/spi/spi-s3c64xx.c +2 -0

 /**
+ * struct s3c64xx_spi_info - SPI Controller hardware info
+ * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS

register.
+ * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
+ * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
+ * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
+ * @clk_from_cmu: True, if the controller does not include a clock mux and
+ * prescaler unit.
+ *
+ * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
+ * differ in some aspects such as the size of the fifo and spi bus clock
+ * setup. Such differences are specified to the driver using this structure
+ * which is provided as driver data to the driver.
+ */

drivers/spi/spi-s3c64xx.c +1 -0

@@ -1000,6 +1029,7 @@ static int __init s3c64xx_spi_probe(struct
 platform_device *pdev)
 	platform_set_drvdata(pdev, master);
 
 	sdd = spi_master_get_devdata(master);
+	sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
 	sdd->master = master;
 	sdd->cntrlr_info = sci;

drivers/spi/spi-s3c64xx.c +2 -1

 	sdd->pdev = pdev;

@@ -1008,10 +1038,11 @@ static int __init s3c64xx_spi_probe(struct
 platform_device *pdev)
 	sdd->tx_dma.direction = DMA_MEM_TO_DEV;
 	sdd->rx_dma.dmach = dmarx_res->start;
 	sdd->rx_dma.direction = DMA_DEV_TO_MEM;
+	sdd->port_id = pdev->id;
 
 	sdd->cur_bpw = 8;
 
-	master->bus_num = pdev->id;
+	master->bus_num = sdd->port_id;

drivers/spi/spi-s3c64xx.c +0 -0

 	dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
 					mem_res->end, mem_res->start,

sdd->rx_dma.dmach,

drivers/spi/spi-s3c64xx.c +10 -0

+
+static struct platform_device_id s3c64xx_spi_driver_ids[] = {
+	{
+		.name		= "s3c2443-spi",
+		.driver_data	= S3C2443_SPI_PORT_CONFIG,
+	}, {
+		.name		= "s3c6410-spi",
+		.driver_data	= S3C6410_SPI_PORT_CONFIG,
+	}, {
+		.name		= "s5p64x0-spi",

Quoted 18 lines · Thomas Abraham

Platform data is used to specify controller hardware specific information such as the tx/rx fifo level mask and bit offset of rx fifo level. Such information is not suitable to be supplied from device tree. Instead, it can be moved into the driver data and removed from platform data.

Signed-off-by Thomas Abraham <[email protected]>

Acked-by Jaswinder Singh <[email protected]>

---

?arch/arm/mach-exynos/clock-exynos4.c ? ? ? ? ? ? | ? 18 +-
?arch/arm/mach-exynos/setup-spi.c ? ? ? ? ? ? ? ? | ? 25 ---
?arch/arm/mach-s3c24xx/clock-s3c2416.c ? ? ? ? ? ?| ? ?2 +-
?arch/arm/mach-s3c24xx/clock-s3c2443.c ? ? ? ? ? ?| ? ?2 +-
?arch/arm/mach-s3c24xx/common-s3c2443.c ? ? ? ? ? | ? ?4 +-
?arch/arm/mach-s3c24xx/setup-spi.c ? ? ? ? ? ? ? ?| ? ?8 -
?arch/arm/mach-s3c64xx/clock.c ? ? ? ? ? ? ? ? ? ?| ? 20 ++--
?arch/arm/mach-s3c64xx/setup-spi.c ? ? ? ? ? ? ? ?| ? 13 --
?arch/arm/mach-s5p64x0/clock-s5p6440.c ? ? ? ? ? ?| ? 12 +-

Quoted 8 lines

?arch/arm/mach-s5p64x0/clock-s5p6450.c ? ? ? ? ? ?| ? 12 +-
?arch/arm/mach-s5p64x0/setup-spi.c ? ? ? ? ? ? ? ?| ? 16 --
?arch/arm/mach-s5pc100/clock.c ? ? ? ? ? ? ? ? ? ?| ? 30 ++--
?arch/arm/mach-s5pc100/setup-spi.c ? ? ? ? ? ? ? ?| ? 22 ---
?arch/arm/mach-s5pv210/clock.c ? ? ? ? ? ? ? ? ? ?| ? 14 +-
?arch/arm/mach-s5pv210/setup-spi.c ? ? ? ? ? ? ? ?| ? 15 --
?arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | ? 15 --
?drivers/spi/spi-s3c64xx.c ? ? ? ? ? ? ? ? ? ? ? ?| ?180

++++++++++++++++++----

Quoted 2 lines

?17 files changed, 210 insertions(+), 198 deletions(-)

Basically, looks ok to me and there are small comments.

arch/arm/mach-exynos/clock-exynos4.c static struct clk exynos4_init_clocks_off[] = { · line 589

Quoted 11 lines

arch/arm/mach- renamed from arch/arm/mach-exynos/clock-exynos4.c +0 -0

exynos/clock-exynos4.c
index bcb7db4..10a46a9 100644

arch/arm/mach-exynos/clock-exynos4.c +1 -1

@@ -586,17 +586,17 @@ static struct clk exynos4_init_clocks_off[] = {
 ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 13),
 ? ? ? }, {
 ? ? ? ? ? ? ? .name ? ? ? ? ? = "spi",
- ? ? ? ? ? ? .devname ? ? ? ?= "s3c64xx-spi.0",
+ ? ? ? ? ? ? .devname ? ? ? ?= "exynos4210-spi.0",

Please consider that this can be used only for exynos4210 or all of exynos4 Socs. We need to keep the consistency for the naming.

[...]

arch/arm/mach-s3c24xx/clock-s3c2416.c static struct clk_lookup s3c2416_clk_lookup[] = { · line 147

Quoted 11 lines

arch/arm/mach- renamed from arch/arm/mach-s3c24xx/clock-s3c2416.c +0 -0

s3c24xx/clock-s3c2416.c
index 8702ecf..a582ba1 100644

arch/arm/mach-s3c24xx/clock-s3c2416.c +1 -1

@@ -144,7 +144,7 @@ static struct clk_lookup s3c2416_clk_lookup[] = {
 ? ? ? CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
 ? ? ? CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
 ? ? ? CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
- ? ? CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk),
+ ? ? CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk),

I think, in this case, some comment helps to know that 's3c2443-spi' can support s3c2416/s3c2450 together.

[...]

Quoted 5 lines

arch/arm/mach- renamed from arch/arm/mach-s5p64x0/clock-s5p6440.c +0 -0

s5p64x0/clock-s5p6440.c
index ee1e8e7..55ea3ab 100644

arch/arm/mach-s5p64x0/clock-s5p6440.c +0 -0

[...]

arch/arm/mach-s5p64x0/clock-s5p6440.c static struct clk_lookup s5p6440_clk_lookup[] = { · line 523

Quoted 8 lines

arch/arm/mach-s5p64x0/clock-s5p6440.c +2 -2

@@ -519,8 +519,8 @@ static struct clk_lookup s5p6440_clk_lookup[] = {
 ? ? ? CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
 ? ? ? CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
 ? ? ? CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
- ? ? CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
- ? ? CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+ ? ? CLKDEV_INIT("s5p64x0.0", "spi_busclk1", &clk_sclk_spi0.clk),
+ ? ? CLKDEV_INIT("s5p64x0.1", "spi_busclk1", &clk_sclk_spi1.clk),

Should be s5p64x0-spi.0 and s5p64x0-spi.1 ?

[...]

Quoted 5 lines

arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +0 -0

index fa95e9a..4e9b9c3 100644

[...]

Quoted 8 lines

drivers/spi/spi-s3c64xx.c +0 -0

index 6a3d51a..f6bc0e3 100644
@@ -31,6 +31,8 @@

?#include <mach/dma.h>
?#include <plat/s3c64xx-spi.h>

Quoted 1 line

+#define MAX_SPI_PORTS ? ? ? ? ? ? ? ?3

As you know, if spi_isp is used, this can be 5 for latest SoCs later. Just note.

[...]

Quoted 21 lines

?/**
+ * struct s3c64xx_spi_info - SPI Controller hardware info
+ * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
+ * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
+ * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
+ * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
+ * @clk_from_cmu: True, if the controller does not include a clock mux and
+ * ? prescaler unit.
+ *
+ * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
+ * differ in some aspects such as the size of the fifo and spi bus clock
+ * setup. Such differences are specified to the driver using this structure
+ * which is provided as driver data to the driver.
+ */
+struct s3c64xx_spi_port_config {
+ ? ? int ? ? fifo_lvl_mask[MAX_SPI_PORTS];
+ ? ? int ? ? rx_lvl_offset;

Quoted 4 lines

+ ? ? int ? ? tx_st_done;
+ ? ? bool ? ?high_speed;
+ ? ? bool ? ?clk_from_cmu;
+};

When I saw this, I thought this will be used for each SPI port. But I know, above structure is used for each SoC not each SPI port. So I think, how about to change the structure name to avoid confusion?

[...]

Quoted 20 lines

drivers/spi/spi-s3c64xx.c +1 -0

@@ -1000,6 +1029,7 @@ static int __init s3c64xx_spi_probe(struct
 platform_device *pdev)
 ? ? ? platform_set_drvdata(pdev, master);
 
 ? ? ? sdd = spi_master_get_devdata(master);
+ ? ? sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
 ? ? ? sdd->master = master;
 ? ? ? sdd->cntrlr_info = sci;

? ? ? sdd->pdev = pdev;

drivers/spi/spi-s3c64xx.c +2 -1

@@ -1008,10 +1038,11 @@ static int __init s3c64xx_spi_probe(struct
 platform_device *pdev)
 ? ? ? sdd->tx_dma.direction = DMA_MEM_TO_DEV;
 ? ? ? sdd->rx_dma.dmach = dmarx_res->start;
 ? ? ? sdd->rx_dma.direction = DMA_DEV_TO_MEM;
+ ? ? sdd->port_id = pdev->id;
 
 ? ? ? sdd->cur_bpw = 8;
 
- ? ? master->bus_num = pdev->id;
+ ? ? master->bus_num = sdd->port_id;

[...]

Quoted 4 lines

drivers/spi/spi-s3c64xx.c +0 -0

@@ -1071,7 +1102,7 @@ static int __init s3c64xx_spi_probe(struct
 platform_device *pdev)
 ? ? ? }
 

Quoted 3 lines

? ? ? /* Setup Deufult Mode */
- ? ? s3c64xx_spi_hwinit(sdd, pdev->id);
+ ? ? s3c64xx_spi_hwinit(sdd, sdd->port_id);

Do we need this change?

Quoted 7 lines

? ? ? spin_lock_init(&sdd->lock);
? ? ? init_completion(&sdd->xfer_completion);

drivers/spi/spi-s3c64xx.c +0 -0

@@ -1096,7 +1127,7 @@ static int __init s3c64xx_spi_probe(struct
 platform_device *pdev)
 

Quoted 4 lines

? ? ? dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d " ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "with %d Slaves attached\n",
- ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pdev->id, master->num_chipselect);
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sdd->port_id,

master->num_chipselect);

Same as above.

Quoted 4 lines

? ? ? dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n", ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mem_res->end, mem_res->start, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sdd->rx_dma.dmach,

sdd->tx_dma.dmach);

drivers/spi/spi-s3c64xx.c static int s3c64xx_spi_resume(struct device *dev) · line 1223

Quoted 6 lines

drivers/spi/spi-s3c64xx.c +1 -1

@@ -1189,7 +1220,7 @@ static int s3c64xx_spi_resume(struct device *dev)
 ? ? ? clk_enable(sdd->src_clk);
 ? ? ? clk_enable(sdd->clk);
 
- ? ? s3c64xx_spi_hwinit(sdd, pdev->id);
+ ? ? s3c64xx_spi_hwinit(sdd, sdd->port_id);

Same as above.

[...]

drivers/spi/spi-s3c64xx.c static const struct dev_pm_ops s3c64xx_spi_pm = { · line 1320

Quoted 2 lines

drivers/spi/spi-s3c64xx.c +2 -0

+#ifdef CONFIG_ARCH_EXYNOS4
+struct s3c64xx_spi_port_config exynos4_spi_port_config = {

Is this available on exynos4212/exynos4412? If not, this should be 'exynos4210_spi_port_config' and ifdef CONFIG_CPU_EXYNOS4210.

drivers/spi/spi-s3c64xx.c

Quoted 7 lines

+ ? ? .fifo_lvl_mask ?= { 0x1ff, 0x7F, 0x7F },
+ ? ? .rx_lvl_offset ?= 15,
+ ? ? .tx_st_done ? ? = 25,
+ ? ? .high_speed ? ? = 1,
+ ? ? .clk_from_cmu ? = true,

drivers/spi/spi-s3c64xx.c +2 -0

+};
+#define EXYNOS4_SPI_PORT_CONFIG

((kernel_ulong_t)&exynos4_spi_port_config)

drivers/spi/spi-s3c64xx.c static const struct dev_pm_ops s3c64xx_spi_pm = { · line 1330

Quoted 3 lines

drivers/spi/spi-s3c64xx.c +3 -0

+#else
+#define EXYNOS4_SPI_PORT_CONFIG ((kernel_ulong_t)NULL)
+#endif /* CONFIG_ARCH_EXYNOS4 */

And let's think the name of ..._SPI_PORT_CONFIG again. How about just ..._SPI_CONFIG?

Quoted 16 lines

drivers/spi/spi-s3c64xx.c +15 -0

+
+static struct platform_device_id s3c64xx_spi_driver_ids[] = {
+ ? ? {
+ ? ? ? ? ? ? .name ? ? ? ? ? = "s3c2443-spi",
+ ? ? ? ? ? ? .driver_data ? ?= S3C2443_SPI_PORT_CONFIG,
+ ? ? }, {
+ ? ? ? ? ? ? .name ? ? ? ? ? = "s3c6410-spi",
+ ? ? ? ? ? ? .driver_data ? ?= S3C6410_SPI_PORT_CONFIG,
+ ? ? }, {
+ ? ? ? ? ? ? .name ? ? ? ? ? = "s5p64x0-spi",
+ ? ? ? ? ? ? .driver_data ? ?= S5P64X0_SPI_PORT_CONFIG,
+ ? ? }, {
+ ? ? ? ? ? ? .name ? ? ? ? ? = "s5pc100-spi",
+ ? ? ? ? ? ? .driver_data ? ?= S5PC100_SPI_PORT_CONFIG,
+ ? ? }, {

Quoted 5 lines

+ ? ? ? ? ? ? .name ? ? ? ? ? = "s5pv210-spi",
+ ? ? ? ? ? ? .driver_data ? ?= S5PV210_SPI_PORT_CONFIG,
+ ? ? }, {
+ ? ? ? ? ? ? .name ? ? ? ? ? = "exynos4210-spi",
+ ? ? ? ? ? ? .driver_data ? ?= EXYNOS4_SPI_PORT_CONFIG,

As I commented, if this is only for exynos4210, EXYNOS4210_SPI_CONFIG should be used here not EXYNOS4_SPI_.

[...]

And I think, it's time to change the name of spi driver to spi-samsung.c and samsung_spi as a prefix even though we have another s3c24xx spi driver now.

arch/arm/mach-s3c64xx/mach-crag6410.c +1 -1

-	s3c64xx_spi0_set_platdata(&s3c64xx_spi0_pdata, 0, 1);
+	s3c64xx_spi0_set_platdata("s3c6410-spi", NULL, 0, 1);

Quoted 2 lines · Thomas Abraham

- ? ? s3c64xx_spi0_set_platdata(&s3c64xx_spi0_pdata, 0, 1);
+ ? ? s3c64xx_spi0_set_platdata("s3c6410-spi", NULL, 0, 1);

...

Quoted 3 lines

+ ? ? pd.src_clk_nr = src_clk_nr;
+ ? ? pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
+ ? ? s3c64xx_device_spi0.name = dev_name;

This looks *really* strange. ?Why do we need to pass in a name to set in s3c64xx_device_spi0's name, why would we want to use a different name? This dev_name also isn't equivalent to dev_name() which makes matters more confusing than they need to be.

There was similar code for the I2C controllers which caused some really hard to debug brittleness.

Quoted 11 lines · Mark Brown

Quoted 2 lines · Thomas Abraham

- ? ? s3c64xx_spi0_set_platdata(&s3c64xx_spi0_pdata, 0, 1);
+ ? ? s3c64xx_spi0_set_platdata("s3c6410-spi", NULL, 0, 1);

...

Quoted 3 lines

+ ? ? pd.src_clk_nr = src_clk_nr;
+ ? ? pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
+ ? ? s3c64xx_device_spi0.name = dev_name;

Quoted 7 lines

This looks *really* strange. ?Why do we need to pass in a name to set in s3c64xx_device_spi0's name, why would we want to use a different name? This dev_name also isn't equivalent to dev_name() which makes matters more confusing than they need to be.

There was similar code for the I2C controllers which caused some really hard to debug brittleness.

Looks like they use the name as the magic string to pick initialization data.

I wonder if it makes more sense to keep the platform_data still around, and just fill it in with the table (from patch "spi: s3c64xx:
move controller information into driver data") based on the OF compatible field for the device-tree probe case, instead of trying to overload and having to change the name in this way.

-Olof

On Sun, May 20, 2012 at 2:21 AM, Mark Brown

Quoted 2 lines

This dev_name also isn't equivalent to dev_name() which makes matters more confusing than they need to be.

Looks like they use the name as the magic string to pick initialization data.

I wonder if it makes more sense to keep the platform_data still around, and just fill it in with the table (from patch "spi: s3c64xx:
move controller information into driver data") based on the OF compatible field for the device-tree probe case, instead of trying to overload and having to change the name in this way.

Quoted 4 lines · Olof Johansson

On Sun, May 20, 2012 at 2:21 AM, Mark Brown

Quoted 2 lines

This dev_name also isn't equivalent to dev_name() which makes matters more confusing than they need to be.

Quoted 1 line

Looks like they use the name as the magic string to pick initialization data.

Right, and there's no problem at all with using the name. ?The thing is that there's no need to set the name at runtime since the struct device being configured is always going to end up with the same name and doing so is just causing confusion. ?The device being registered is specific to the SoC already so setting the SoC name at runtime isn't needed.

Quoted 6 lines

I wonder if it makes more sense to keep the platform_data still around, and just fill it in with the table (from patch "spi: s3c64xx:
move controller information into driver data") based on the OF compatible field for the device-tree probe case, instead of trying to overload and having to change the name in this way.

We could do that, though it does seem nice to have everything be consistent.

Quoted 5 lines · Mark Brown

Right, and there's no problem at all with using the name. ?The thing is that there's no need to set the name at runtime since the struct device being configured is always going to end up with the same name and doing so is just causing confusion. ?The device being registered is specific to the SoC already so setting the SoC name at runtime isn't needed.

I think I did not understand your point. There is only one instance of spi platform device statically defined for all Samsung platforms. The

Quoted 10 lines · Thomas Abraham

Quoted 5 lines · Mark Brown

Right, and there's no problem at all with using the name. ?The thing is that there's no need to set the name at runtime since the struct device being configured is always going to end up with the same name and doing so is just causing confusion. ?The device being registered is specific to the SoC already so setting the SoC name at runtime isn't needed.

I think I did not understand your point. There is only one instance of spi platform device statically defined for all Samsung platforms. The

No there isn't. ?You've got things like s3c64xx_device_spi0 in arch/arm/plat-samsung/devs.c (which you'd expect since the resources that are passed in for memory mapping, DMA and interrupt vary with the SoC). ?The bit of code I was querying just changes "s3c64xx-spi" to "s3c6410-spi" at runtime in that structure which seems like a waste of time.

Quoted 6 lines · Mark Brown

No there isn't. ?You've got things like s3c64xx_device_spi0 in arch/arm/plat-samsung/devs.c (which you'd expect since the resources that are passed in for memory mapping, DMA and interrupt vary with the SoC). ?The bit of code I was querying just changes "s3c64xx-spi" to "s3c6410-spi" at runtime in that structure which seems like a waste of time.

So is the concern only with the change of device name from "s3c64xx-spi" to "s3c6410-spi"? Is there any concern with changing the name of the static spi platform device (s3c64xx_device_spi0/1/2) at runtime which then is used to select a driver data?

Quoted 9 lines · Thomas Abraham

Quoted 6 lines · Mark Brown

No there isn't. ?You've got things like s3c64xx_device_spi0 in arch/arm/plat-samsung/devs.c (which you'd expect since the resources that are passed in for memory mapping, DMA and interrupt vary with the SoC). ?The bit of code I was querying just changes "s3c64xx-spi" to "s3c6410-spi" at runtime in that structure which seems like a waste of time.

Quoted 4 lines

So is the concern only with the change of device name from "s3c64xx-spi" to "s3c6410-spi"? Is there any concern with changing the name of the static spi platform device (s3c64xx_device_spi0/1/2) at runtime which then is used to select a driver data?

No, you're not getting it at all. ?The changing at runtime is the problem, it's achieving nothing except making the code more fragile and obscure. ?Those devices will always come out with exactly the same name so we should just assign that name statically.

1. There is one instance of 'struct platform_device' for each of the spi controller instances (0/1/2) named "s3c64xx-spi" (in arch/arm/plat-samsung/devs.c).

5. If point 4 is not correct, the other option is to create a separate instances of 'struct platform_device' for each of the s3c, s5p and Exynos4/5 SoC's. Is this the correct way, and if yes, could you please help me understand the issues in setting the name of the platform device at runtime.

Quoted 3 lines · Thomas Abraham

1. There is one instance of 'struct platform_device' for each of the spi controller instances (0/1/2) named "s3c64xx-spi" (in arch/arm/plat-samsung/devs.c).

Right, which looks rather like it is specific to s3c64xx at least given the naming... ?there aren't any current in tree users, though I do have one out of tree user on s3c6410. ?If this is supposed to be used on the later SoCs too then I guess it ought to be renamed anyway since what's there looks wrong.

Quoted 6 lines

5. If point 4 is not correct, the other option is to create a separate instances of 'struct platform_device' for each of the s3c, s5p and Exynos4/5 SoC's. Is this the correct way, and if yes, could you please help me understand the issues in setting the name of the platform device at runtime.

That would seem less painful to me. ?The big problem I've found is with things like matching clocks up where if you look at the device that's being registered it has one name but at runtime it has another name, it makes everything much harder to follow. ?There was one of the devices where the .id also ended up getting changed which created even more confusion.

The set_level callback in the controller data, which is used to configure the slave select line, cannot be supported when migrating the driver to device tree based discovery. Since all the platforms currently use gpio as the slave select line, this callback can be removed from the controller data and replaced with call to gpio_set_value in the driver.

Signed-off-by Thomas Abraham <[email protected]>

Acked-by Jaswinder Singh <[email protected]>

---
 arch/arm/plat-samsung/include/plat/s3c64xx-spi.h |    2 --
 drivers/spi/spi-s3c64xx.c                        |    8 ++++----
 2 files changed, 4 insertions(+), 6 deletions(-)

arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +0 -2

index a733ce9..48a6495 100644
@@ -18,7 +18,6 @@ struct platform_device;
  * @fb_delay: Slave specific feedback delay.
  *            Refer to FB_CLK_SEL register definition in SPI chapter.
  * @line: Custom 'identity' of the CS line.
- * @set_level: CS line control.
  *
  * This is per SPI-Slave Chipselect information.
  * Allocate and initialize one in machine init code and make the

@@ -27,7 +26,6 @@ struct platform_device;
 struct s3c64xx_spi_csinfo {
 	u8 fb_delay;
 	unsigned line;
-	void (*set_level)(unsigned line_id, int lvl);
 };
 
 /**

drivers/spi/spi-s3c64xx.c +4 -4

index f6bc0e3..d84ce7f 100644
@@ -406,14 +406,14 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
 		if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
 			/* Deselect the last toggled device */
 			cs = sdd->tgl_spi->controller_data;
-			cs->set_level(cs->line,
-					spi->mode & SPI_CS_HIGH ? 0 : 1);
+			gpio_set_value(cs->line,
+				spi->mode & SPI_CS_HIGH ? 0 : 1);
 		}
 		sdd->tgl_spi = NULL;
 	}
 
 	cs = spi->controller_data;
-	cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
+	gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
 }
 
 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,

@@ -499,7 +499,7 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
 	if (sdd->tgl_spi == spi)
 		sdd->tgl_spi = NULL;
 
-	cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
+	gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
 }
 
 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)

Signature · 1 line

1.6.6.rc2

Add support for device based discovery.

Signed-off-by Thomas Abraham <[email protected]>

Acked-by Jaswinder Singh <[email protected]>

Changes since v1:

- Incorporated changes suggested by Mark Brown
- Merged 2nd, 3rd and 5th patch into one single patch.
- Listed the order of gpios in the device tree support documentation.
- Switched to generic property names for chip select gpio line and number of slave select lines.
- Moved the platform enablement patches for Exynos4 and Exynos5 into a different patch series.
- Included Ack from Jaswinder Singh <[email protected]>.

This patch series adds device tree based discovery support for Samsung's s3c64xx compatible spi controller. This is mainly tested for Exynos4210 and Exynos5250 with onboard spi nor flash device.

Thomas Abraham (6):
spi: s3c64xx: remove unused S3C64XX_SPI_ST_TRLCNTZ macro
spi: s3c64xx: move controller information into driver data
ARM: Samsung: Remove pdev pointer paremeter from spi gpio setup functions
ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function
spi: s3c64xx: Remove the 'set_level' callback from controller data
spi: s3c64xx: add device tree support

 .../devicetree/bindings/spi/spi-samsung.txt        |  113 +++++
 arch/arm/mach-exynos/clock-exynos4.c               |   18 +-
 arch/arm/mach-exynos/setup-spi.c                   |   33 +--
 arch/arm/mach-s3c24xx/clock-s3c2416.c              |    2 +-
 arch/arm/mach-s3c24xx/clock-s3c2443.c              |    2 +-
 arch/arm/mach-s3c24xx/common-s3c2443.c             |    4 +-
 arch/arm/mach-s3c24xx/setup-spi.c                  |   10 +-
 arch/arm/mach-s3c64xx/clock.c                      |   20 +-
 arch/arm/mach-s3c64xx/mach-crag6410.c              |    2 +-
 arch/arm/mach-s3c64xx/setup-spi.c                  |   19 +-
 arch/arm/mach-s5p64x0/clock-s5p6440.c              |   12 +-
 arch/arm/mach-s5p64x0/clock-s5p6450.c              |   12 +-
 arch/arm/mach-s5p64x0/setup-spi.c                  |   21 +-
 arch/arm/mach-s5pc100/clock.c                      |   30 +-
 arch/arm/mach-s5pc100/setup-spi.c                  |   30 +--
 arch/arm/mach-s5pv210/clock.c                      |   14 +-
 arch/arm/mach-s5pv210/setup-spi.c                  |   21 +-
 arch/arm/plat-samsung/devs.c                       |   50 +--
 arch/arm/plat-samsung/include/plat/s3c64xx-spi.h   |   31 +-
 drivers/spi/spi-s3c64xx.c                          |  467 +++++++++++++++++---
 20 files changed, 611 insertions(+), 300 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-samsung.txt