USB: EXYNOS: Incorporate EHCI review comments

This patch incorates the review comments given by Minkyu Kang for EHCI support on EXYNOS

Signed-off-by Rajeshwari Shinde <[email protected]>

---
 arch/arm/include/asm/arch-exynos/cpu.h      |    3 +
 arch/arm/include/asm/arch-exynos/ehci-s5p.h |   66 ----------------
 arch/arm/include/asm/arch-exynos/ehci.h     |   66 ++++++++++++++++
 drivers/usb/host/Makefile                   |    2 +-
 drivers/usb/host/ehci-exynos.c              |  110
+++++++++++++++++++++++++++ drivers/usb/host/ehci-s5p.c                 | 
110 --------------------------- 6 files changed, 180 insertions(+), 177
deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-exynos/ehci-s5p.h
 create mode 100644 arch/arm/include/asm/arch-exynos/ehci.h
 create mode 100644 drivers/usb/host/ehci-exynos.c
 delete mode 100644 drivers/usb/host/ehci-s5p.c

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-exynos/cpu.h index ac4ddc7..85d421d 100644

arch/arm/include/asm/arch-exynos/cpu.h +3 -0

@@ -45,6 +45,7 @@
 #define EXYNOS4_USBOTG_BASE		0x12480000
 #define EXYNOS4_MMC_BASE		0x12510000
 #define EXYNOS4_SROMC_BASE		0x12570000
+#define EXYNOS4_USB_HOST_EHCI_BASE	0x12580000
 #define EXYNOS4_USBPHY_BASE		0x125B0000
 #define EXYNOS4_UART_BASE		0x13800000
 #define EXYNOS4_ADC_BASE		0x13910000

@@ -68,6 +69,7 @@
 #define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE		0x11400000
 #define EXYNOS5_MIPI_DSIM_BASE		0x11D00000
+#define EXYNOS5_USB_HOST_EHCI_BASE	0x12110000
 #define EXYNOS5_MMC_BASE		0x12200000
 #define EXYNOS5_SROMC_BASE		0x12250000
 #define EXYNOS5_USBOTG_BASE		0x12480000

@@ -145,6 +147,7 @@ SAMSUNG_BASE(swreset, SWRESET)
 SAMSUNG_BASE(timer, PWMTIMER_BASE)
 SAMSUNG_BASE(uart, UART_BASE)
 SAMSUNG_BASE(usb_phy, USBPHY_BASE)
+SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
 SAMSUNG_BASE(usb_otg, USBOTG_BASE)
 SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 SAMSUNG_BASE(power, POWER_BASE)

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-exynos/ehci-s5p.h deleted file mode 100644 index 68feb85..0000000

arch/arm/include/asm/arch-exynos/ehci-s5p.h deleted +0 -66

@@ -1,66 +0,0 @@
-/*
- * SAMSUNG S5P USB HOST EHCI Controller
- *
- * Copyright (C) 2012 Samsung Electronics Co.Ltd
- *	Vivek Gautam <[email protected]>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
-#define __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
-
-#define CLK_24MHZ		5
-
-#define HOST_CTRL0_PHYSWRSTALL			(1 << 31)
-#define HOST_CTRL0_COMMONON_N			(1 << 9)
-#define HOST_CTRL0_SIDDQ			(1 << 6)
-#define HOST_CTRL0_FORCESLEEP			(1 << 5)
-#define HOST_CTRL0_FORCESUSPEND			(1 << 4)
-#define HOST_CTRL0_WORDINTERFACE		(1 << 3)
-#define HOST_CTRL0_UTMISWRST			(1 << 2)
-#define HOST_CTRL0_LINKSWRST			(1 << 1)
-#define HOST_CTRL0_PHYSWRST			(1 << 0)
-
-#define HOST_CTRL0_FSEL_MASK			(7 << 16)
-
-#define EHCICTRL_ENAINCRXALIGN			(1 << 29)
-#define EHCICTRL_ENAINCR4			(1 << 28)
-#define EHCICTRL_ENAINCR8			(1 << 27)
-#define EHCICTRL_ENAINCR16			(1 << 26)
-
-/* Register map for PHY control */
-struct s5p_usb_phy {
-	unsigned int usbphyctrl0;
-	unsigned int usbphytune0;
-	unsigned int reserved1[2];
-	unsigned int hsicphyctrl1;
-	unsigned int hsicphytune1;
-	unsigned int reserved2[2];
-	unsigned int hsicphyctrl2;
-	unsigned int hsicphytune2;
-	unsigned int reserved3[2];
-	unsigned int ehcictrl;
-	unsigned int ohcictrl;
-	unsigned int usbotgsys;
-	unsigned int reserved4;
-	unsigned int usbotgtune;
-};
-
-/* Switch on the VBUS power. */
-int board_usb_vbus_init(void);
-
-#endif /* __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ */

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-exynos/ehci.h new file mode 100644 index 0000000..8aeff8a

arch/arm/include/asm/arch-exynos/ehci.h new file +66 -0

@@ -0,0 +1,66 @@
+/*
+ * SAMSUNG EXYNOS USB HOST EHCI Controller
+ *
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ *	Vivek Gautam <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_EHCI_H__
+#define __ASM_ARM_ARCH_EHCI_H__
+
+#define CLK_24MHZ		5
+
+#define HOST_CTRL0_PHYSWRSTALL			(1 << 31)
+#define HOST_CTRL0_COMMONON_N			(1 << 9)
+#define HOST_CTRL0_SIDDQ			(1 << 6)
+#define HOST_CTRL0_FORCESLEEP			(1 << 5)
+#define HOST_CTRL0_FORCESUSPEND			(1 << 4)
+#define HOST_CTRL0_WORDINTERFACE		(1 << 3)
+#define HOST_CTRL0_UTMISWRST			(1 << 2)
+#define HOST_CTRL0_LINKSWRST			(1 << 1)
+#define HOST_CTRL0_PHYSWRST			(1 << 0)
+
+#define HOST_CTRL0_FSEL_MASK			(7 << 16)
+
+#define EHCICTRL_ENAINCRXALIGN			(1 << 29)
+#define EHCICTRL_ENAINCR4			(1 << 28)
+#define EHCICTRL_ENAINCR8			(1 << 27)
+#define EHCICTRL_ENAINCR16			(1 << 26)
+
+/* Register map for PHY control */
+struct exynos_usb_phy {
+	unsigned int usbphyctrl0;
+	unsigned int usbphytune0;
+	unsigned int reserved1[2];
+	unsigned int hsicphyctrl1;
+	unsigned int hsicphytune1;
+	unsigned int reserved2[2];
+	unsigned int hsicphyctrl2;
+	unsigned int hsicphytune2;
+	unsigned int reserved3[2];
+	unsigned int ehcictrl;
+	unsigned int ohcictrl;
+	unsigned int usbotgsys;
+	unsigned int reserved4;
+	unsigned int usbotgtune;
+};
+
+/* Switch on the VBUS power. */
+int board_usb_vbus_init(void);
+
+#endif /* __ASM_ARM_ARCH_EHCI_H__ */

drivers/usb/host/Makefile +1 -1

index 59c3e57..645bb58 100644
@@ -41,6 +41,7 @@ COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o
 else
 COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
 endif
+COBJS-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
 COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
 COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
 COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o

@@ -50,7 +51,6 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
 COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
 COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
 COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
-COBJS-$(CONFIG_USB_EHCI_S5P) += ehci-s5p.o
 COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 

(quoted diff) +0 -0

b/drivers/usb/host/ehci-exynos.c new file mode 100644 index 0000000..3830c43

drivers/usb/host/ehci-exynos.c new file +110 -0

@@ -0,0 +1,110 @@
+/*
+ * SAMSUNG EXYNOS USB HOST EHCI Controller
+ *
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ *	Vivek Gautam <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ehci.h>
+#include "ehci.h"
+#include "ehci-core.h"
+
+/* Setup the EHCI host controller. */
+static void setup_usb_phy(struct exynos_usb_phy *usb)
+{
+	clrbits_le32(&usb->usbphyctrl0,
+			HOST_CTRL0_FSEL_MASK |
+			HOST_CTRL0_COMMONON_N |
+			/* HOST Phy setting */
+			HOST_CTRL0_PHYSWRST |
+			HOST_CTRL0_PHYSWRSTALL |
+			HOST_CTRL0_SIDDQ |
+			HOST_CTRL0_FORCESUSPEND |
+			HOST_CTRL0_FORCESLEEP);
+
+	setbits_le32(&usb->usbphyctrl0,
+			/* Setting up the ref freq */
+			(CLK_24MHZ << 16) |
+			/* HOST Phy setting */
+			HOST_CTRL0_LINKSWRST |
+			HOST_CTRL0_UTMISWRST);
+	udelay(10);
+	clrbits_le32(&usb->usbphyctrl0,
+			HOST_CTRL0_LINKSWRST |
+			HOST_CTRL0_UTMISWRST);
+	udelay(20);
+
+	/* EHCI Ctrl setting */
+	setbits_le32(&usb->ehcictrl,
+			EHCICTRL_ENAINCRXALIGN |
+			EHCICTRL_ENAINCR4 |
+			EHCICTRL_ENAINCR8 |
+			EHCICTRL_ENAINCR16);
+}
+
+/* Reset the EHCI host controller. */
+static void reset_usb_phy(struct exynos_usb_phy *usb)
+{
+	/* HOST_PHY reset */
+	setbits_le32(&usb->usbphyctrl0,
+			HOST_CTRL0_PHYSWRST |
+			HOST_CTRL0_PHYSWRSTALL |
+			HOST_CTRL0_SIDDQ |
+			HOST_CTRL0_FORCESUSPEND |
+			HOST_CTRL0_FORCESLEEP);
+}
+
+/*
+ * EHCI-initialization
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(void)
+{
+	struct exynos_usb_phy *usb;
+
+	usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
+	setup_usb_phy(usb);
+
+	hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci();
+	hcor = (struct ehci_hcor *)((uint32_t) hccr
+				+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+	debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
+		(uint32_t)hccr, (uint32_t)hcor,
+		(uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+	return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding
+ * the EHCI host controller.
+ */
+int ehci_hcd_stop()
+{
+	struct exynos_usb_phy *usb;
+
+	usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
+	reset_usb_phy(usb);
+
+	return 0;
+}

drivers/usb/host/ehci-s5p.c deleted +0 -110

deleted file mode 100644
index 4dd4ec1..0000000
@@ -1,110 +0,0 @@
-/*
- * SAMSUNG S5P USB HOST EHCI Controller
- *
- * Copyright (C) 2012 Samsung Electronics Co.Ltd
- *	Vivek Gautam <[email protected]>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <usb.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/ehci-s5p.h>
-#include "ehci.h"
-#include "ehci-core.h"
-
-/* Setup the EHCI host controller. */
-static void setup_usb_phy(struct s5p_usb_phy *usb)
-{
-	clrbits_le32(&usb->usbphyctrl0,
-			HOST_CTRL0_FSEL_MASK |
-			HOST_CTRL0_COMMONON_N |
-			/* HOST Phy setting */
-			HOST_CTRL0_PHYSWRST |
-			HOST_CTRL0_PHYSWRSTALL |
-			HOST_CTRL0_SIDDQ |
-			HOST_CTRL0_FORCESUSPEND |
-			HOST_CTRL0_FORCESLEEP);
-
-	setbits_le32(&usb->usbphyctrl0,
-			/* Setting up the ref freq */
-			(CLK_24MHZ << 16) |
-			/* HOST Phy setting */
-			HOST_CTRL0_LINKSWRST |
-			HOST_CTRL0_UTMISWRST);
-	udelay(10);
-	clrbits_le32(&usb->usbphyctrl0,
-			HOST_CTRL0_LINKSWRST |
-			HOST_CTRL0_UTMISWRST);
-	udelay(20);
-
-	/* EHCI Ctrl setting */
-	setbits_le32(&usb->ehcictrl,
-			EHCICTRL_ENAINCRXALIGN |
-			EHCICTRL_ENAINCR4 |
-			EHCICTRL_ENAINCR8 |
-			EHCICTRL_ENAINCR16);
-}
-
-/* Reset the EHCI host controller. */
-static void reset_usb_phy(struct s5p_usb_phy *usb)
-{
-	/* HOST_PHY reset */
-	setbits_le32(&usb->usbphyctrl0,
-			HOST_CTRL0_PHYSWRST |
-			HOST_CTRL0_PHYSWRSTALL |
-			HOST_CTRL0_SIDDQ |
-			HOST_CTRL0_FORCESUSPEND |
-			HOST_CTRL0_FORCESLEEP);
-}
-
-/*
- * EHCI-initialization
- * Create the appropriate control structures to manage
- * a new EHCI host controller.
- */
-int ehci_hcd_init(void)
-{
-	struct s5p_usb_phy *usb;
-
-	usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy();
-	setup_usb_phy(usb);
-
-	hccr = (struct ehci_hccr *)(EXYNOS5_USB_HOST_EHCI_BASE);
-	hcor = (struct ehci_hcor *)((uint32_t) hccr
-				+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
-
-	debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
-		(uint32_t)hccr, (uint32_t)hcor,
-		(uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
-
-	return 0;
-}
-
-/*
- * Destroy the appropriate control structures corresponding
- * the EHCI host controller.
- */
-int ehci_hcd_stop()
-{
-	struct s5p_usb_phy *usb;
-
-	usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy();
-	reset_usb_phy(usb);
-
-	return 0;
-}

Dear Rajeshwari Shinde,

Quoted 4 lines

This patch incorates the review comments given by Minkyu Kang for EHCI support on EXYNOS

Signed-off-by Rajeshwari Shinde <[email protected]>

Perfect, applied and applied those 6 patches that were dangling. Now, I pushed out new usb/master branch, can you please verify if it's all you need from me before I submit another pull RQ?

Sorry I wasn't really a textbook example of a maintainer, I hope we I'll still see more code from you eventually.

Thank you very much for the work you put into these patches and all the additional (unnecessary) hassle!

Quoted 435 lines

---

?arch/arm/include/asm/arch-exynos/cpu.h ? ? ?| ? ?3 +
?arch/arm/include/asm/arch-exynos/ehci-s5p.h | ? 66 ----------------
?arch/arm/include/asm/arch-exynos/ehci.h ? ? | ? 66 ++++++++++++++++
?drivers/usb/host/Makefile ? ? ? ? ? ? ? ? ? | ? ?2 +-
?drivers/usb/host/ehci-exynos.c ? ? ? ? ? ? ?| ?110

+++++++++++++++++++++++++++ drivers/usb/host/ehci-s5p.c ? ? ? ? ? ? ? ? | 110 --------------------------- 6 files changed, 180 insertions(+), 177 deletions(-)
?delete mode 100644 arch/arm/include/asm/arch-exynos/ehci-s5p.h ?create mode 100644 arch/arm/include/asm/arch-exynos/ehci.h ?create mode 100644 drivers/usb/host/ehci-exynos.c
?delete mode 100644 drivers/usb/host/ehci-s5p.c

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-exynos/cpu.h index ac4ddc7..85d421d 100644

arch/arm/include/asm/arch-exynos/cpu.h +0 -0

@@ -45,6 +45,7 @@

?#define EXYNOS4_USBOTG_BASE ? ? ? ? ?0x12480000
?#define EXYNOS4_MMC_BASE ? ? ? ? ? ? 0x12510000
?#define EXYNOS4_SROMC_BASE ? ? ? ? ? 0x12570000
+#define EXYNOS4_USB_HOST_EHCI_BASE ? 0x12580000
?#define EXYNOS4_USBPHY_BASE ? ? ? ? ?0x125B0000
?#define EXYNOS4_UART_BASE ? ? ? ? ? ?0x13800000
?#define EXYNOS4_ADC_BASE ? ? ? ? ? ? 0x13910000

arch/arm/include/asm/arch-exynos/cpu.h +0 -0

@@ -68,6 +69,7 @@

?#define EXYNOS5_DMC_CTRL_BASE ? ? ? ? ? ? ? ?0x10DD0000 ?#define EXYNOS5_GPIO_PART1_BASE ? ? ? ? ? ? ?0x11400000 ?#define EXYNOS5_MIPI_DSIM_BASE ? ? ? ? ? ? ? 0x11D00000 +#define EXYNOS5_USB_HOST_EHCI_BASE ? 0x12110000 ?#define EXYNOS5_MMC_BASE ? ? ? ? ? ? 0x12200000 ?#define EXYNOS5_SROMC_BASE ? ? ? ? ? 0x12250000 ?#define EXYNOS5_USBOTG_BASE ? ? ? ? ?0x12480000

arch/arm/include/asm/arch-exynos/cpu.h +1 -0

@@ -145,6 +147,7 @@ SAMSUNG_BASE(swreset, SWRESET)
 ?SAMSUNG_BASE(timer, PWMTIMER_BASE)
 ?SAMSUNG_BASE(uart, UART_BASE)
 ?SAMSUNG_BASE(usb_phy, USBPHY_BASE)
+SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
 ?SAMSUNG_BASE(usb_otg, USBOTG_BASE)
 ?SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 ?SAMSUNG_BASE(power, POWER_BASE)

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-exynos/ehci-s5p.h deleted file mode 100644 index 68feb85..0000000

arch/arm/include/asm/arch-exynos/ehci-s5p.h deleted +0 -66

@@ -1,66 +0,0 @@
-/*
- * SAMSUNG S5P USB HOST EHCI Controller
- *
- * Copyright (C) 2012 Samsung Electronics Co.Ltd
- * ? Vivek Gautam <[email protected]>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
-#define __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
-
-#define CLK_24MHZ ? ? ? ? ? ?5
-
-#define HOST_CTRL0_PHYSWRSTALL ? ? ? ? ? ? ? ? ? ? ? (1 << 31)
-#define HOST_CTRL0_COMMONON_N ? ? ? ? ? ? ? ? ? ? ? ?(1 << 9)
-#define HOST_CTRL0_SIDDQ ? ? ? ? ? ? ? ? ? ? (1 << 6)
-#define HOST_CTRL0_FORCESLEEP ? ? ? ? ? ? ? ? ? ? ? ?(1 << 5)
-#define HOST_CTRL0_FORCESUSPEND ? ? ? ? ? ? ? ? ? ? ?(1 << 4)
-#define HOST_CTRL0_WORDINTERFACE ? ? ? ? ? ? (1 << 3)
-#define HOST_CTRL0_UTMISWRST ? ? ? ? ? ? ? ? (1 << 2)
-#define HOST_CTRL0_LINKSWRST ? ? ? ? ? ? ? ? (1 << 1)
-#define HOST_CTRL0_PHYSWRST ? ? ? ? ? ? ? ? ?(1 << 0)
-
-#define HOST_CTRL0_FSEL_MASK ? ? ? ? ? ? ? ? (7 << 16)
-
-#define EHCICTRL_ENAINCRXALIGN ? ? ? ? ? ? ? ? ? ? ? (1 << 29)
-#define EHCICTRL_ENAINCR4 ? ? ? ? ? ? ? ? ? ?(1 << 28)
-#define EHCICTRL_ENAINCR8 ? ? ? ? ? ? ? ? ? ?(1 << 27)
-#define EHCICTRL_ENAINCR16 ? ? ? ? ? ? ? ? ? (1 << 26)
-
-/* Register map for PHY control */
-struct s5p_usb_phy {
- ? ? unsigned int usbphyctrl0;
- ? ? unsigned int usbphytune0;
- ? ? unsigned int reserved1[2];
- ? ? unsigned int hsicphyctrl1;
- ? ? unsigned int hsicphytune1;
- ? ? unsigned int reserved2[2];
- ? ? unsigned int hsicphyctrl2;
- ? ? unsigned int hsicphytune2;
- ? ? unsigned int reserved3[2];
- ? ? unsigned int ehcictrl;
- ? ? unsigned int ohcictrl;
- ? ? unsigned int usbotgsys;
- ? ? unsigned int reserved4;
- ? ? unsigned int usbotgtune;
-};
-
-/* Switch on the VBUS power. */
-int board_usb_vbus_init(void);
-
-#endif /* __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ */

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-exynos/ehci.h new file mode 100644 index 0000000..8aeff8a

arch/arm/include/asm/arch-exynos/ehci.h new file +66 -0

@@ -0,0 +1,66 @@
+/*
+ * SAMSUNG EXYNOS USB HOST EHCI Controller
+ *
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ * ? Vivek Gautam <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_EHCI_H__
+#define __ASM_ARM_ARCH_EHCI_H__
+
+#define CLK_24MHZ ? ? ? ? ? ?5
+
+#define HOST_CTRL0_PHYSWRSTALL ? ? ? ? ? ? ? ? ? ? ? (1 << 31)
+#define HOST_CTRL0_COMMONON_N ? ? ? ? ? ? ? ? ? ? ? ?(1 << 9)
+#define HOST_CTRL0_SIDDQ ? ? ? ? ? ? ? ? ? ? (1 << 6)
+#define HOST_CTRL0_FORCESLEEP ? ? ? ? ? ? ? ? ? ? ? ?(1 << 5)
+#define HOST_CTRL0_FORCESUSPEND ? ? ? ? ? ? ? ? ? ? ?(1 << 4)
+#define HOST_CTRL0_WORDINTERFACE ? ? ? ? ? ? (1 << 3)
+#define HOST_CTRL0_UTMISWRST ? ? ? ? ? ? ? ? (1 << 2)
+#define HOST_CTRL0_LINKSWRST ? ? ? ? ? ? ? ? (1 << 1)
+#define HOST_CTRL0_PHYSWRST ? ? ? ? ? ? ? ? ?(1 << 0)
+
+#define HOST_CTRL0_FSEL_MASK ? ? ? ? ? ? ? ? (7 << 16)
+
+#define EHCICTRL_ENAINCRXALIGN ? ? ? ? ? ? ? ? ? ? ? (1 << 29)
+#define EHCICTRL_ENAINCR4 ? ? ? ? ? ? ? ? ? ?(1 << 28)
+#define EHCICTRL_ENAINCR8 ? ? ? ? ? ? ? ? ? ?(1 << 27)
+#define EHCICTRL_ENAINCR16 ? ? ? ? ? ? ? ? ? (1 << 26)
+
+/* Register map for PHY control */
+struct exynos_usb_phy {
+ ? ? unsigned int usbphyctrl0;
+ ? ? unsigned int usbphytune0;
+ ? ? unsigned int reserved1[2];
+ ? ? unsigned int hsicphyctrl1;
+ ? ? unsigned int hsicphytune1;
+ ? ? unsigned int reserved2[2];
+ ? ? unsigned int hsicphyctrl2;
+ ? ? unsigned int hsicphytune2;
+ ? ? unsigned int reserved3[2];
+ ? ? unsigned int ehcictrl;
+ ? ? unsigned int ohcictrl;
+ ? ? unsigned int usbotgsys;
+ ? ? unsigned int reserved4;
+ ? ? unsigned int usbotgtune;
+};
+
+/* Switch on the VBUS power. */
+int board_usb_vbus_init(void);
+
+#endif /* __ASM_ARM_ARCH_EHCI_H__ */

drivers/usb/host/Makefile +0 -0

index 59c3e57..645bb58 100644
@@ -41,6 +41,7 @@ COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o

?else
?COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
?endif
+COBJS-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
?COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
?COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
?COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o

drivers/usb/host/Makefile +0 -0

@@ -50,7 +51,6 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o

?COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o ?COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o ?COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o -COBJS-$(CONFIG_USB_EHCI_S5P) += ehci-s5p.o ?COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o ?COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o

(quoted diff) +0 -0

b/drivers/usb/host/ehci-exynos.c new file mode 100644 index 0000000..3830c43

drivers/usb/host/ehci-exynos.c new file +110 -0

@@ -0,0 +1,110 @@
+/*
+ * SAMSUNG EXYNOS USB HOST EHCI Controller
+ *
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ * ? Vivek Gautam <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ehci.h>
+#include "ehci.h"
+#include "ehci-core.h"
+
+/* Setup the EHCI host controller. */
+static void setup_usb_phy(struct exynos_usb_phy *usb)
+{
+ ? ? clrbits_le32(&usb->usbphyctrl0,
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_FSEL_MASK |
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_COMMONON_N |
+ ? ? ? ? ? ? ? ? ? ? /* HOST Phy setting */
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_PHYSWRST |
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_PHYSWRSTALL |
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_SIDDQ |
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_FORCESUSPEND |
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_FORCESLEEP);
+
+ ? ? setbits_le32(&usb->usbphyctrl0,
+ ? ? ? ? ? ? ? ? ? ? /* Setting up the ref freq */
+ ? ? ? ? ? ? ? ? ? ? (CLK_24MHZ << 16) |
+ ? ? ? ? ? ? ? ? ? ? /* HOST Phy setting */
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_LINKSWRST |
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_UTMISWRST);
+ ? ? udelay(10);
+ ? ? clrbits_le32(&usb->usbphyctrl0,
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_LINKSWRST |
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_UTMISWRST);
+ ? ? udelay(20);
+
+ ? ? /* EHCI Ctrl setting */
+ ? ? setbits_le32(&usb->ehcictrl,
+ ? ? ? ? ? ? ? ? ? ? EHCICTRL_ENAINCRXALIGN |
+ ? ? ? ? ? ? ? ? ? ? EHCICTRL_ENAINCR4 |
+ ? ? ? ? ? ? ? ? ? ? EHCICTRL_ENAINCR8 |
+ ? ? ? ? ? ? ? ? ? ? EHCICTRL_ENAINCR16);
+}
+
+/* Reset the EHCI host controller. */
+static void reset_usb_phy(struct exynos_usb_phy *usb)
+{
+ ? ? /* HOST_PHY reset */
+ ? ? setbits_le32(&usb->usbphyctrl0,
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_PHYSWRST |
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_PHYSWRSTALL |
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_SIDDQ |
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_FORCESUSPEND |
+ ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_FORCESLEEP);
+}
+
+/*
+ * EHCI-initialization
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(void)
+{
+ ? ? struct exynos_usb_phy *usb;
+
+ ? ? usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
+ ? ? setup_usb_phy(usb);
+
+ ? ? hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci();
+ ? ? hcor = (struct ehci_hcor *)((uint32_t) hccr
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ ? ? debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
+ ? ? ? ? ? ? (uint32_t)hccr, (uint32_t)hcor,
+ ? ? ? ? ? ? (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ ? ? return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding
+ * the EHCI host controller.
+ */
+int ehci_hcd_stop()
+{
+ ? ? struct exynos_usb_phy *usb;
+
+ ? ? usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
+ ? ? reset_usb_phy(usb);
+
+ ? ? return 0;
+}

drivers/usb/host/ehci-s5p.c deleted +0 -106

deleted file mode 100644
index 4dd4ec1..0000000
@@ -1,110 +0,0 @@
-/*
- * SAMSUNG S5P USB HOST EHCI Controller
- *
- * Copyright (C) 2012 Samsung Electronics Co.Ltd
- * ? Vivek Gautam <[email protected]>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <usb.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/ehci-s5p.h>
-#include "ehci.h"
-#include "ehci-core.h"
-
-/* Setup the EHCI host controller. */
-static void setup_usb_phy(struct s5p_usb_phy *usb)
-{
- ? ? clrbits_le32(&usb->usbphyctrl0,
- ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_FSEL_MASK |
- ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_COMMONON_N |
- ? ? ? ? ? ? ? ? ? ? /* HOST Phy setting */
- ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_PHYSWRST |
- ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_PHYSWRSTALL |
- ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_SIDDQ |
- ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_FORCESUSPEND |
- ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_FORCESLEEP);
-
- ? ? setbits_le32(&usb->usbphyctrl0,
- ? ? ? ? ? ? ? ? ? ? /* Setting up the ref freq */
- ? ? ? ? ? ? ? ? ? ? (CLK_24MHZ << 16) |
- ? ? ? ? ? ? ? ? ? ? /* HOST Phy setting */
- ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_LINKSWRST |
- ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_UTMISWRST);
- ? ? udelay(10);
- ? ? clrbits_le32(&usb->usbphyctrl0,
- ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_LINKSWRST |
- ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_UTMISWRST);
- ? ? udelay(20);
-
- ? ? /* EHCI Ctrl setting */
- ? ? setbits_le32(&usb->ehcictrl,
- ? ? ? ? ? ? ? ? ? ? EHCICTRL_ENAINCRXALIGN |
- ? ? ? ? ? ? ? ? ? ? EHCICTRL_ENAINCR4 |
- ? ? ? ? ? ? ? ? ? ? EHCICTRL_ENAINCR8 |
- ? ? ? ? ? ? ? ? ? ? EHCICTRL_ENAINCR16);
-}
-
-/* Reset the EHCI host controller. */
-static void reset_usb_phy(struct s5p_usb_phy *usb)
-{
- ? ? /* HOST_PHY reset */
- ? ? setbits_le32(&usb->usbphyctrl0,
- ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_PHYSWRST |
- ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_PHYSWRSTALL |
- ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_SIDDQ |
- ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_FORCESUSPEND |
- ? ? ? ? ? ? ? ? ? ? HOST_CTRL0_FORCESLEEP);
-}
-
-/*
- * EHCI-initialization
- * Create the appropriate control structures to manage
- * a new EHCI host controller.
- */
-int ehci_hcd_init(void)
-{
- ? ? struct s5p_usb_phy *usb;
-
- ? ? usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy();
- ? ? setup_usb_phy(usb);
-
- ? ? hccr = (struct ehci_hccr *)(EXYNOS5_USB_HOST_EHCI_BASE);
- ? ? hcor = (struct ehci_hcor *)((uint32_t) hccr
- ? ? ? ? ? ? ? ? ? ? ? ? ? ? + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
-
- ? ? debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
- ? ? ? ? ? ? (uint32_t)hccr, (uint32_t)hcor,
- ? ? ? ? ? ? (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
-
- ? ? return 0;
-}
-
-/*
- * Destroy the appropriate control structures corresponding
- * the EHCI host controller.
- */
-int ehci_hcd_stop()
-{
- ? ? struct s5p_usb_phy *usb;
-
- ? ? usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy();

drivers/usb/host/ehci-s5p.c line 61

Quoted 4 lines

drivers/usb/host/ehci-s5p.c deleted +0 -4

- ? ? reset_usb_phy(usb);
-
- ? ? return 0;
-}

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Hi Marek,

Quoted 10 lines · Marek Vasut

Dear Rajeshwari Shinde,

Quoted 4 lines

This patch incorates the review comments given by Minkyu Kang for EHCI support on EXYNOS

Signed-off-by Rajeshwari Shinde <[email protected]>

Perfect, applied and applied those 6 patches that were dangling. Now, I pushed out new usb/master branch, can you please verify if it's all you need from me before I submit another pull RQ?

Verified all patches there.

Quoted 5 lines

Sorry I wasn't really a textbook example of a maintainer, I hope we I'll still see more code from you eventually.

Thank you very much for the work you put into these patches and all the additional (unnecessary) hassle!

No problem. Thank you for incorporating them.

Regards,
Rajeshwari Shinde.