---
 arch/arm/boot/dts/imx28-m28.dts |  260 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 260 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx28-m28.dts

arch/arm/boot/dts/imx28-m28.dts new file +260 -0

new file mode 100644
index 0000000..7892020
@@ -0,0 +1,260 @@
+/*
+ * Copyright (C) 2012 Marek Vasut <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx28.dtsi"
+
+/ {
+	model = "DENX M28EVK";
+	compatible = "fsl,imx28-evk", "fsl,imx28";
+
+	memory {
+		reg = <0x40000000 0x08000000>;
+	};
+
+	apb at 80000000 {
+		apbh at 80000000 {
+			pinctrl at 80018000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx28-pinctrl", "simple-bus";
+				reg = <0x80018000 2000>;
+
+				gpmi_pins_data_m28: gpmi1 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x0000 0x0010 0x0020
+							  0x0030 0x0040 0x0050
+							  0x0060 0x0070 0x0100
+							  0x0140>;
+					fsl,drive-strength = <0>;
+					fsl,voltage = <0>;
+					fsl,pull-up = <0>;
+				};
+
+				gpmi_pins_ctrl_m28: gpmi1 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x180 0x0190
+							  0x01a0 0x01b0>;
+					fsl,drive-strength = <3>;
+					fsl,voltage = <0>;
+					fsl,pull-up = <1>;
+				};
+
+				mmc0_pins_data_m28: mmc0-8bit at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x2000 0x2010 0x2020
+							  0x2030 0x2040 0x2050
+							  0x2060 0x2070 0x2080>;
+					fsl,drive-strength = <1>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <1>;
+				};
+
+				mmc0_pins_ctrl_m28: mmc0-8bit at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x2090 0x20a0
+							  0x30a3 0x31c3>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
+
+				auart0_pins_m28: auart0 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x3000 0x3010>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
+
+				auart3_pins_m28: auart3 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x30c0 0x30d0
+							  0x30e0 0x30f0>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
+
+				mac_pin_reset: mac at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x30b3>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
+
+				flexcan0_pins_m28: flexcan0 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x0161 0x0162>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
+
+				flexcan1_pins_m28: flexcan1 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x0121 0x0122>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
+			};
+
+			ssp0: ssp at 80010000 {
+				compatible = "fsl,imx28-mmc";
+				pinctrl-names = "default";
+				pinctrl-0 = <&mmc0_pins_data_m28
+					     &mmc0_pins_ctrl_m28>;
+				bus-width = <8>;
+				wp-gpios = <&gpio3 10 1>;
+				status = "okay";
+			};
+
+			gpmi at 8000c000 {
+				compatible = "fsl,imx28-gpmi-nand";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x8000c000 2000>, <0x8000a000 2000>;
+				reg-names = "gpmi-nand", "bch";
+				pinctrl-names = "default";
+				pinctrl-0 = <&gpmi_pins_data_m28
+					     &gpmi_pins_ctrl_m28>;
+				interrupts = <88>, <41>;
+				interrupt-names = "gpmi-dma", "bch";
+				fsl,gpmi-dma-channel = <4>;
+				status = "okay";
+
+				partition at 0 {
+					label = "bootloader";
+					reg = <0x00000000 0x00300000>;
+					read-only;
+				};
+
+				partition at 1 {
+					label = "environment";
+					reg = <0x00300000 0x00080000>;
+				};
+
+				partition at 2 {
+					label = "redundant-environment";
+					reg = <0x00380000 0x00080000>;
+				};
+
+				partition at 3 {
+					label = "kernel";
+					reg = <0x00400000 0x00400000>;
+				};
+
+				partition at 4 {
+					label = "filesystem";
+					reg = <0x00800000 0x0f800000>;
+				};
+			};
+
+			can0: can at 80032000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&flexcan0_pins_m28>;
+				status = "okay";
+			};
+
+			can1: can at 80034000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&flexcan1_pins_m28>;
+				status = "okay";
+			};
+		};
+
+		apbx at 80040000 {
+			saif0: saif at 80042000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&saif0_pins_a>;
+				status = "okay";
+			};
+
+			saif1: saif at 80046000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&saif1_pins_a>;
+				fsl,saif-master = <&saif0>;
+				status = "okay";
+			};
+
+			i2c0: i2c at 80058000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&i2c0_pins_a>;
+				status = "okay";
+
+				sgtl5000: codec at 0a {
+					compatible = "fsl,sgtl5000";
+					reg = <0x0a>;
+					VDDA-supply = <&reg_3p3v>;
+					VDDIO-supply = <&reg_3p3v>;
+
+				};
+
+				eeprom: eeprom at 51 {
+					compatible = "atmel,24c128";
+					reg = <0x51>;
+					pagesize = <32>;
+				};
+
+				rtc: rtc at 68 {
+					compatible = "stm,mt41t62";
+					reg = <0x68>;
+				};
+			};
+
+			duart: serial at 80074000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&duart_pins_a>;
+				status = "okay";
+			};
+		};
+	};
+
+	ahb at 80080000 {
+		mac0: ethernet at 800f0000 {
+			phy-mode = "rmii";
+			pinctrl-names = "default";
+			pinctrl-0 = <&mac0_pins_a &mac_pin_reset>;
+			phy-reset-gpios = <&gpio3 11 0>;
+			status = "okay";
+		};
+
+		mac1: ethernet at 800f4000 {
+			phy-mode = "rmii";
+			pinctrl-names = "default";
+			pinctrl-0 = <&mac1_pins_a>;
+			phy-reset-gpios = <&gpio3 11 0>;
+			status = "okay";
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+
+		reg_3p3v: 3p3v {
+			compatible = "regulator-fixed";
+			regulator-name = "3P3V";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+	};
+
+	sound {
+		compatible = "fsl,imx28-evk-sgtl5000",
+			     "fsl,mxs-audio-sgtl5000";
+		model = "imx28-evk-sgtl5000";
+		saif-controllers = <&saif0 &saif1>;
+		audio-codec = <&sgtl5000>;
+	};
+};

Signature · 1 line

1.7.10

Fabio Estevam

reviewer

2012-05-28 15:27 UTC #1 lore raw

PATCH 1/1 MXS: Add DENX M28 dts file

Hi Marek,

Quoted 8 lines · Marek Vasut

+ ? ? ? sound {
+ ? ? ? ? ? ? ? compatible = "fsl,imx28-evk-sgtl5000",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ?"fsl,mxs-audio-sgtl5000";
+ ? ? ? ? ? ? ? model = "imx28-evk-sgtl5000";
+ ? ? ? ? ? ? ? saif-controllers = <&saif0 &saif1>;
+ ? ? ? ? ? ? ? audio-codec = <&sgtl5000>;
+ ? ? ? };
+};

Shouldn't this be:

sound {
	compatible = "fsl,imx28-m28-sgtl5000",
		     "fsl,mxs-audio-sgtl5000";
	model = "imx28-m28-sgtl5000";
	saif-controllers = <&saif0 &saif1>;
	audio-codec = <&sgtl5000>;
};

Fabio Estevam

reviewer

2012-05-29 12:57 UTC #4 lore raw

PATCH 1/1 MXS: Add DENX M28 dts file

Quoted 8 lines · Marek Vasut

Quoted 5 lines
Shouldn't this be:
sound {
? ? ? compatible = "fsl,imx28-m28-sgtl5000",
? ? ? ? ? ? ? ? ? ?"fsl,mxs-audio-sgtl5000";
Wait, no ... it should not, why should it? (I'm still very lame with this device tree stuff, so any advice is very welcome)

My understanding is that you need to reference your machine name in the compatible field instead of referencing another one (mx28evk). Maybe someone else can confirm this.

Shawn Guo

2012-06-06 05:54 UTC #5 lore raw

PATCH 1/1 MXS: Add DENX M28 dts file

In reply to Fabio Estevam

Quoted 15 lines · Fabio Estevam

Hi Marek,
Quoted 8 lines · Marek Vasut
+ ? ? ? sound {
+ ? ? ? ? ? ? ? compatible = "fsl,imx28-evk-sgtl5000",
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ?"fsl,mxs-audio-sgtl5000";
+ ? ? ? ? ? ? ? model = "imx28-evk-sgtl5000";
+ ? ? ? ? ? ? ? saif-controllers = <&saif0 &saif1>;
+ ? ? ? ? ? ? ? audio-codec = <&sgtl5000>;
+ ? ? ? };
+};
Shouldn't this be:

Quoted 7 lines

sound {
	compatible = "fsl,imx28-m28-sgtl5000",
		     "fsl,mxs-audio-sgtl5000";
	model = "imx28-m28-sgtl5000";
	saif-controllers = <&saif0 &saif1>;
	audio-codec = <&sgtl5000>;
};

Yes, this one looks sane to me.

Signature · 2 lines

Regards,
Shawn

Shawn Guo

2012-06-06 08:17 UTC #6 lore raw

PATCH 1/1 MXS: Add DENX M28 dts file

In reply to Marek Vasut

Quoted 30 lines · Marek Vasut

Missing:
AUART
LCDIF
Signed-off-by Marek Vasut <[email protected]>
Cc Detlev Zundel <[email protected]>
CC Dong Aisheng <[email protected]>
CC Fabio Estevam <[email protected]>
Cc Linux ARM kernel <[email protected]>
CC Shawn Guo <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Wolfgang Denk <[email protected]>
---
 arch/arm/boot/dts/imx28-m28.dts |  260 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 260 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx28-m28.dts
arch/arm/boot/dts/imx28-m28.dts new file +7 -0
new file mode 100644
index 0000000..7892020
@@ -0,0 +1,260 @@
+/*
+ * Copyright (C) 2012 Marek Vasut <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *

arch/arm/boot/dts/imx28-m28.dts line 17

Quoted 10 lines

arch/arm/boot/dts/imx28-m28.dts new file +10 -0

+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx28.dtsi"
+
+/ {
+	model = "DENX M28EVK";
+	compatible = "fsl,imx28-evk", "fsl,imx28";

"fsl,imx28-evk" shouldn't be used here. If you do not want to patch arch/arm/mach-mxs/mach-mxs.c to have "imx28-m28" added in imx28_dt_compat, you can just have compatible = "fsl,imx28"; here and the machine will still match DT_MACHINE_START(IMX28, ...).

arch/arm/boot/dts/imx28-m28.dts line 30

Quoted 13 lines

arch/arm/boot/dts/imx28-m28.dts new file +13 -0

+
+	memory {
+		reg = <0x40000000 0x08000000>;
+	};
+
+	apb at 80000000 {
+		apbh at 80000000 {
+			pinctrl at 80018000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx28-pinctrl", "simple-bus";
+				reg = <0x80018000 2000>;
+

The point of having "imx28.dtsi" is to define soc specific data in there and then those data do not have to be duplicated in every single <board>.dts.

Above pinctrl data have been defined in imx28.dtsi, so you do not need to define them here again.

Quoted 9 lines

arch/arm/boot/dts/imx28-m28.dts new file +9 -0

+				gpmi_pins_data_m28: gpmi1 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x0000 0x0010 0x0020
+							  0x0030 0x0040 0x0050
+							  0x0060 0x0070 0x0100
+							  0x0140>;
+					fsl,drive-strength = <0>;
+					fsl,voltage = <0>;
+					fsl,pull-up = <0>;

arch/arm/boot/dts/imx28-m28.dts line 49

Quoted 10 lines

arch/arm/boot/dts/imx28-m28.dts new file +10 -0

+				};
+
+				gpmi_pins_ctrl_m28: gpmi1 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x180 0x0190
+							  0x01a0 0x01b0>;
+					fsl,drive-strength = <3>;
+					fsl,voltage = <0>;
+					fsl,pull-up = <1>;
+				};

I just applied Huang's gpmi changes below. Can you please rebase the the patch on top of it? If you have the same pin setup as imx28-evk, we can save above data completely.

http://thread.gmane.org/gmane.linux.ports.arm.kernel/169351

Quoted 9 lines

arch/arm/boot/dts/imx28-m28.dts new file +9 -0

+
+				mmc0_pins_data_m28: mmc0-8bit at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x2000 0x2010 0x2020
+							  0x2030 0x2040 0x2050
+							  0x2060 0x2070 0x2080>;
+					fsl,drive-strength = <1>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <1>;

arch/arm/boot/dts/imx28-m28.dts line 68

Quoted 10 lines

arch/arm/boot/dts/imx28-m28.dts new file +10 -0

+				};
+
+				mmc0_pins_ctrl_m28: mmc0-8bit at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x2090 0x20a0
+							  0x30a3 0x31c3>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};

You did a couple of wrong things here (as well as gpmi above). First of all, there shouldn't be multiple pin group nodes for one device, supposing you are intending to set up pins for mmc0 in 2 groups nodes here. See the following copied from fsl,mxs-pinctrl.txt.

"On mxs, there is no hardware pin group. The pin group in this binding only means a group of pins put together for particular peripheral to work in particular function, like SSP0 functioning as mmc0-8bit. That said, the group node should include all the pins needed for one function rather than having these pins defined in several group nodes. It also means each of "pinctrl-*" phandle in client device node should only have one group node pointed in there, while the phandle can have multiple config node referenced there to adjust configurations for some pins in the group."

The reason I say above "if you are intending to ..." is you may just end up with having one "mmc0-8bit at 0" node in the dtb where only the data in the last occurrence get encoded in, because these two nodes are identical and thus the later one will overwrite the former one.

Secondly, the pin group node should be defined in imx28.dtsi, as the mux setting for particular device is determined by soc. That said, if the existing mmc0_8bit_pins_a works for you, you can just have your mmc0 device refer to it than define it over again in your board.dts. Otherwise, you should define mmc0_8bit_pins_b in imx28.dtsi, so that any other board use that mmc0 mux scheme can refer to it later as too.

Lastly, the gpio should currently stay away from here. There are some ongoing work at pinctrl core level to have gpio pin properly set up when gpio_request() gets called.

Quoted 7 lines

arch/arm/boot/dts/imx28-m28.dts new file +7 -0

+
+				auart0_pins_m28: auart0 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x3000 0x3010>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;

arch/arm/boot/dts/imx28-m28.dts line 85

Quoted 10 lines

arch/arm/boot/dts/imx28-m28.dts new file +10 -0

+				};
+
+				auart3_pins_m28: auart3 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x30c0 0x30d0
+							  0x30e0 0x30f0>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};

Should be defined in imx28.dtsi, so that other boards can refer to them too.

arch/arm/boot/dts/imx28-m28.dts line 93

Quoted 8 lines

arch/arm/boot/dts/imx28-m28.dts new file +8 -0

+
+				mac_pin_reset: mac at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x30b3>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};

gpio, let's wait for pinctrl core support.

Quoted 6 lines

arch/arm/boot/dts/imx28-m28.dts new file +6 -0

+
+				flexcan0_pins_m28: flexcan0 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x0161 0x0162>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;

arch/arm/boot/dts/imx28-m28.dts line 109

Quoted 10 lines

arch/arm/boot/dts/imx28-m28.dts new file +10 -0

+					fsl,pull-up = <0>;
+				};
+
+				flexcan1_pins_m28: flexcan1 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x0121 0x0122>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};

Put them into imx28.dtsi.

Quoted 15 lines

arch/arm/boot/dts/imx28-m28.dts new file +15 -0

+			};
+
+			ssp0: ssp at 80010000 {
+				compatible = "fsl,imx28-mmc";
+				pinctrl-names = "default";
+				pinctrl-0 = <&mmc0_pins_data_m28
+					     &mmc0_pins_ctrl_m28>;
+				bus-width = <8>;
+				wp-gpios = <&gpio3 10 1>;
+				status = "okay";
+			};
+
+			gpmi at 8000c000 {
+				compatible = "fsl,imx28-gpmi-nand";
+				#address-cells = <1>;

arch/arm/boot/dts/imx28-m28.dts line 134

Quoted 10 lines

arch/arm/boot/dts/imx28-m28.dts new file +10 -0

+				#size-cells = <1>;
+				reg = <0x8000c000 2000>, <0x8000a000 2000>;
+				reg-names = "gpmi-nand", "bch";
+				pinctrl-names = "default";
+				pinctrl-0 = <&gpmi_pins_data_m28
+					     &gpmi_pins_ctrl_m28>;
+				interrupts = <88>, <41>;
+				interrupt-names = "gpmi-dma", "bch";
+				fsl,gpmi-dma-channel = <4>;
+				status = "okay";

Please rebase on Huang's patches which are available on my for-next branch now. This gpmi controller node should be firstly defined in imx28.dtsi and only board specific data should be in <board>.dts.

Regards,
Shawn

Quoted 129 lines

arch/arm/boot/dts/imx28-m28.dts new file +126 -0

+
+				partition at 0 {
+					label = "bootloader";
+					reg = <0x00000000 0x00300000>;
+					read-only;
+				};
+
+				partition at 1 {
+					label = "environment";
+					reg = <0x00300000 0x00080000>;
+				};
+
+				partition at 2 {
+					label = "redundant-environment";
+					reg = <0x00380000 0x00080000>;
+				};
+
+				partition at 3 {
+					label = "kernel";
+					reg = <0x00400000 0x00400000>;
+				};
+
+				partition at 4 {
+					label = "filesystem";
+					reg = <0x00800000 0x0f800000>;
+				};
+			};
+
+			can0: can at 80032000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&flexcan0_pins_m28>;
+				status = "okay";
+			};
+
+			can1: can at 80034000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&flexcan1_pins_m28>;
+				status = "okay";
+			};
+		};
+
+		apbx at 80040000 {
+			saif0: saif at 80042000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&saif0_pins_a>;
+				status = "okay";
+			};
+
+			saif1: saif at 80046000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&saif1_pins_a>;
+				fsl,saif-master = <&saif0>;
+				status = "okay";
+			};
+
+			i2c0: i2c at 80058000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&i2c0_pins_a>;
+				status = "okay";
+
+				sgtl5000: codec at 0a {
+					compatible = "fsl,sgtl5000";
+					reg = <0x0a>;
+					VDDA-supply = <&reg_3p3v>;
+					VDDIO-supply = <&reg_3p3v>;
+
+				};
+
+				eeprom: eeprom at 51 {
+					compatible = "atmel,24c128";
+					reg = <0x51>;
+					pagesize = <32>;
+				};
+
+				rtc: rtc at 68 {
+					compatible = "stm,mt41t62";
+					reg = <0x68>;
+				};
+			};
+
+			duart: serial at 80074000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&duart_pins_a>;
+				status = "okay";
+			};
+		};
+	};
+
+	ahb at 80080000 {
+		mac0: ethernet at 800f0000 {
+			phy-mode = "rmii";
+			pinctrl-names = "default";
+			pinctrl-0 = <&mac0_pins_a &mac_pin_reset>;
+			phy-reset-gpios = <&gpio3 11 0>;
+			status = "okay";
+		};
+
+		mac1: ethernet at 800f4000 {
+			phy-mode = "rmii";
+			pinctrl-names = "default";
+			pinctrl-0 = <&mac1_pins_a>;
+			phy-reset-gpios = <&gpio3 11 0>;
+			status = "okay";
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+
+		reg_3p3v: 3p3v {
+			compatible = "regulator-fixed";
+			regulator-name = "3P3V";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+	};
+
+	sound {
+		compatible = "fsl,imx28-evk-sgtl5000",
+			     "fsl,mxs-audio-sgtl5000";
+		model = "imx28-evk-sgtl5000";
+		saif-controllers = <&saif0 &saif1>;
+		audio-codec = <&sgtl5000>;
+	};
+};

Signature · 1 line

1.7.10

Marek Vasut

author

2012-06-08 18:32 UTC #7 lore raw

PATCH 1/1 MXS: Add DENX M28 dts file

Dear Shawn Guo,

Quoted 4 lines · Marek Vasut

Quoted 3 lines
Missing:
AUART
LCDIF

[...]

Quoted 5 lines

I just applied Huang's gpmi changes below. Can you please rebase the the patch on top of it? If you have the same pin setup as imx28-evk, we can save above data completely.
http://thread.gmane.org/gmane.linux.ports.arm.kernel/169351

Ok, I see ... FSL patches get merged with priority?

Quoted 16 lines

arch/arm/boot/dts/imx28-m28.dts new file +16 -0

+
+				mmc0_pins_data_m28: mmc0-8bit at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x2000 0x2010 0x2020
+							  0x2030 0x2040 0x2050
+							  0x2060 0x2070 0x2080>;
+					fsl,drive-strength = <1>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <1>;
+				};
+
+				mmc0_pins_ctrl_m28: mmc0-8bit at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x2090 0x20a0
+							  0x30a3 0x31c3>;
+					fsl,drive-strength = <2>;

Quoted 8 lines

arch/arm/boot/dts/imx28-m28.dts line 68
Quoted 3 lines
arch/arm/boot/dts/imx28-m28.dts new file +3 -0
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
You did a couple of wrong things here (as well as gpmi above). First of all, there shouldn't be multiple pin group nodes for one device, supposing you are intending to set up pins for mmc0 in 2 groups nodes here. See the following copied from fsl,mxs-pinctrl.txt.

I see ... so if I need to configure two set of pins, how do I do that? Or it's not possible with DT too?

Quoted 37 lines

"On mxs, there is no hardware pin group. The pin group in this binding only means a group of pins put together for particular peripheral to work in particular function, like SSP0 functioning as mmc0-8bit. That said, the group node should include all the pins needed for one function rather than having these pins defined in several group nodes. It also means each of "pinctrl-*" phandle in client device node should only have one group node pointed in there, while the phandle can have multiple config node referenced there to adjust configurations for some pins in the group."
The reason I say above "if you are intending to ..." is you may just end up with having one "mmc0-8bit at 0" node in the dtb where only the data in the last occurrence get encoded in, because these two nodes are identical and thus the later one will overwrite the former one.
Secondly, the pin group node should be defined in imx28.dtsi, as the mux setting for particular device is determined by soc. That said, if the existing mmc0_8bit_pins_a works for you, you can just have your mmc0 device refer to it than define it over again in your board.dts. Otherwise, you should define mmc0_8bit_pins_b in imx28.dtsi, so that any other board use that mmc0 mux scheme can refer to it later as too.
Lastly, the gpio should currently stay away from here. There are some ongoing work at pinctrl core level to have gpio pin properly set up when gpio_request() gets called.
Quoted 12 lines
arch/arm/boot/dts/imx28-m28.dts new file +12 -0
+
+				auart0_pins_m28: auart0 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x3000 0x3010>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
+
+				auart3_pins_m28: auart3 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x30c0 0x30d0

Quoted 8 lines

arch/arm/boot/dts/imx28-m28.dts line 85
Quoted 5 lines
arch/arm/boot/dts/imx28-m28.dts new file +5 -0
+							  0x30e0 0x30f0>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
Should be defined in imx28.dtsi, so that other boards can refer to them too.

It's specific to our platform, why would it?

Quoted 10 lines

arch/arm/boot/dts/imx28-m28.dts line 93
Quoted 8 lines
arch/arm/boot/dts/imx28-m28.dts new file +8 -0
+
+				mac_pin_reset: mac at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x30b3>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
gpio, let's wait for pinctrl core support.

Hm, how long do you intend to block all possible platforms from mainline other than FSL EVK ones? I consider having stuff in mainline much better, as it helps testing it, but it seems you don't share this opinion.

[...]

Shawn Guo

2012-06-11 05:40 UTC #8 lore raw

PATCH 1/1 MXS: Add DENX M28 dts file

Quoted 2 lines · Marek Vasut

Ok, I see ... FSL patches get merged with priority?

If I'm not mistaken, Huang's patches hit list earlier than yours. That's the only reason I applied his patches with priority. Anything wrong with this approach?

Quoted 3 lines

I see ... so if I need to configure two set of pins, how do I do that? Or it's not possible with DT too?

It's possible. You already did that with ethernet pins, one set of mac function pins and another phy reset gpio, didn't you?

Quoted 21 lines

Quoted 12 lines
Quoted 12 lines
arch/arm/boot/dts/imx28-m28.dts new file +12 -0
+
+				auart0_pins_m28: auart0 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x3000 0x3010>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
+
+				auart3_pins_m28: auart3 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x30c0 0x30d0
Quoted 8 lines
arch/arm/boot/dts/imx28-m28.dts line 85
Quoted 5 lines
arch/arm/boot/dts/imx28-m28.dts new file +5 -0
+							  0x30e0 0x30f0>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
Should be defined in imx28.dtsi, so that other boards can refer to them too.

Quoted 2 lines

It's specific to our platform, why would it?

Which pins can be mux-ed on auart function is never specific to your platform, it's determined by SoC design. Different platforms may need different pad configuration though. That's can be done by defining config node in <board>.dts.

Quoted 11 lines

Quoted 10 lines
arch/arm/boot/dts/imx28-m28.dts line 93
Quoted 8 lines
arch/arm/boot/dts/imx28-m28.dts new file +8 -0
+
+				mac_pin_reset: mac at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x30b3>;
+					fsl,drive-strength = <2>;
+					fsl,voltage = <1>;
+					fsl,pull-up = <0>;
+				};
gpio, let's wait for pinctrl core support.

Quoted 2 lines

Hm, how long do you intend to block all possible platforms from mainline other than FSL EVK ones?

Would you mind giving an example that I block your platform support for some reason while give it pass on FSL EVK?

Quoted 3 lines

I consider having stuff in mainline much better, as it helps testing it, but it seems you don't share this opinion.

I do share this opinion. I was thinking that the gpio range support in pinctrl is close to get it. Now, it seems not the case and more importantly I just found one problem with that, the pad configuration for gpio is not covered by gpio range support. So we may not be able to use that support anyway, so go ahead with your approach.

Signature · 2 lines

Regards,
Shawn

Marek Vasut

author

2012-06-08 19:03 UTC #9 lore raw

PATCH 1/1 MXS: Add DENX M28 dts file

In reply to Shawn Guo

Dear Shawn Guo,

Quoted 4 lines · Marek Vasut

Quoted 3 lines
Missing:
AUART
LCDIF

[...]

Quoted 13 lines

arch/arm/boot/dts/imx28-m28.dts line 49
Quoted 8 lines
arch/arm/boot/dts/imx28-m28.dts new file +8 -0
+				gpmi_pins_ctrl_m28: gpmi1 at 0 {
+					reg = <0>;
+					fsl,pinmux-ids = <0x180 0x0190
+							  0x01a0 0x01b0>;
+					fsl,drive-strength = <3>;
+					fsl,voltage = <0>;
+					fsl,pull-up = <1>;
+				};
I just applied Huang's gpmi changes below. Can you please rebase the the patch on top of it? If you have the same pin setup as imx28-evk, we can save above data completely.

Quoted 1 line

http://thread.gmane.org/gmane.linux.ports.arm.kernel/169351

Well, GPMI NAND doens't work for me (AGAIN). Screw this, I'm not debuging it for the third damn time only to be told to rebase it again and that all I did was for naught. Sorry

Best regards,
Marek Vasut

Shawn Guo

2012-06-11 05:45 UTC #10 lore raw

PATCH 1/1 MXS: Add DENX M28 dts file

Quoted 10 lines · Marek Vasut

Quoted 5 lines
I just applied Huang's gpmi changes below. Can you please rebase the the patch on top of it? If you have the same pin setup as imx28-evk, we can save above data completely.
http://thread.gmane.org/gmane.linux.ports.arm.kernel/169351
Well, GPMI NAND doens't work for me (AGAIN). Screw this, I'm not debuging it for the third damn time only to be told to rebase it again and that all I did was for naught. Sorry

Hmm, I was told by Huang that GPMI NAND works for him. As I do not have NAND device to play, can you guys aligned here?

Signature · 2 lines

Regards,
Shawn

Huang Shijie

2012-06-11 05:56 UTC #11 lore raw

PATCH 1/1 MXS: Add DENX M28 dts file

? 2012?06?11? 13:45, Shawn Guo ??:

Quoted 11 lines · Marek Vasut

Quoted 9 lines
Quoted 5 lines
I just applied Huang's gpmi changes below. Can you please rebase the the patch on top of it? If you have the same pin setup as imx28-evk, we can save above data completely.
http://thread.gmane.org/gmane.linux.ports.arm.kernel/169351
Well, GPMI NAND doens't work for me (AGAIN). Screw this, I'm not debuging it for the third damn time only to be told to rebase it again and that all I did was for naught. Sorry
Hmm, I was told by Huang that GPMI NAND works for him. As I do not

sorry. It can not works now. :(

There is a bug in the GPMI-NAND driver( i guess).

The pinmux, clocks, IO resources are all correct.
And the ECC read page/ ECC write page are ok too.

But the UBIFS can not works.

I am debugging it now.

Huang Shijie

Quoted 2 lines

have NAND device to play, can you guys aligned here?

Marek Vasut

author

2012-06-11 10:59 UTC #12 lore raw

PATCH 1/1 MXS: Add DENX M28 dts file

Dear Huang Shijie,

Quoted 14 lines

? 2012?06?11? 13:45, Shawn Guo ??:
Quoted 5 lines · Marek Vasut
Quoted 4 lines
Quoted 4 lines
I just applied Huang's gpmi changes below. Can you please rebase the the patch on top of it? If you have the same pin setup as imx28-evk, we can save above data completely.
Quoted 7 lines
Quoted 5 lines
Quoted 1 line
http://thread.gmane.org/gmane.linux.ports.arm.kernel/169351
Well, GPMI NAND doens't work for me (AGAIN). Screw this, I'm not debuging it for the third damn time only to be told to rebase it again and that all I did was for naught. Sorry
Hmm, I was told by Huang that GPMI NAND works for him. As I do not

Quoted 8 lines

sorry. It can not works now. :(
There is a bug in the GPMI-NAND driver( i guess).
The pinmux, clocks, IO resources are all correct.
And the ECC read page/ ECC write page are ok too.
But the UBIFS can not works.

I sent you that link ... it might be the problem you're facing. And if it isn't, then you should fix that too, since you're depending on undefined behavior there.

Quoted 6 lines

I am debugging it now.
Huang Shijie
Quoted 1 line
have NAND device to play, can you guys aligned here?

Best regards,
Marek Vasut

Huang Shijie

2012-06-12 06:17 UTC #13 lore raw

PATCH 1/1 MXS: Add DENX M28 dts file

? 2012?06?11? 18:59, Marek Vasut ??:

Quoted 17 lines

Dear Huang Shijie,
Quoted 15 lines
? 2012?06?11? 13:45, Shawn Guo ??:
Quoted 10 lines · Marek Vasut
Quoted 8 lines
Quoted 5 lines
I just applied Huang's gpmi changes below. Can you please rebase the the patch on top of it? If you have the same pin setup as imx28-evk, we can save above data completely.
http://thread.gmane.org/gmane.linux.ports.arm.kernel/169351
Well, GPMI NAND doens't work for me (AGAIN). Screw this, I'm not debuging it for the third damn time only to be told to rebase it again and that all I did was for naught. Sorry
Hmm, I was told by Huang that GPMI NAND works for him. As I do not
sorry. It can not works now. :(
There is a bug in the GPMI-NAND driver( i guess).

Quoted 8 lines

Quoted 4 lines
The pinmux, clocks, IO resources are all correct.
And the ECC read page/ ECC write page are ok too.
But the UBIFS can not works.
I sent you that link ... it might be the problem you're facing. And if it isn't, then you should fix that too, since you're depending on undefined behavior there.

thanks for your link. But it's not the root cause.

The ECC read-page/write-page are _NOT_ stable. They can fail in some unknown cases.

Best Regards
Huang Shijie

Quoted 8 lines

Quoted 5 lines
I am debugging it now.
Huang Shijie
Quoted 1 line
have NAND device to play, can you guys aligned here?
Best regards,
Marek Vasut

Marek Vasut

author

2012-06-12 11:09 UTC #14 lore raw

PATCH 1/1 MXS: Add DENX M28 dts file

Dear Huang Shijie,

Quoted 24 lines

? 2012?06?11? 18:59, Marek Vasut ??:
Quoted 23 lines
Dear Huang Shijie,
Quoted 21 lines
? 2012?06?11? 13:45, Shawn Guo ??:
Quoted 5 lines · Marek Vasut
Quoted 4 lines
Quoted 4 lines
I just applied Huang's gpmi changes below. Can you please rebase the the patch on top of it? If you have the same pin setup as imx28-evk, we can save above data completely.
Quoted 7 lines
Quoted 5 lines
Quoted 1 line
http://thread.gmane.org/gmane.linux.ports.arm.kernel/169351
Well, GPMI NAND doens't work for me (AGAIN). Screw this, I'm not debuging it for the third damn time only to be told to rebase it again and that all I did was for naught. Sorry
Hmm, I was told by Huang that GPMI NAND works for him. As I do not
sorry. It can not works now. :(
There is a bug in the GPMI-NAND driver( i guess).
The pinmux, clocks, IO resources are all correct.
And the ECC read page/ ECC write page are ok too.

Quoted 7 lines

Quoted 5 lines
Quoted 1 line
But the UBIFS can not works.
I sent you that link ... it might be the problem you're facing. And if it isn't, then you should fix that too, since you're depending on undefined behavior there.
thanks for your link. But it's not the root cause.

But that doesn't quite change the fact that it is also a bug which should be fixed, right? Will you please investigate and fix it?

Quoted 2 lines

The ECC read-page/write-page are _NOT_ stable. They can fail in some unknown cases.

Rant: I think I've said it multiple times already, but Linux is a community effort. That's why the quality is so high and bug count so low. It was complete flub to have GPMI NAND driver in mainline linux for almost 6 months without merging the actual code that'd let anyone else test it and wait for the DT bindings. Maybe if you did merge it, this and many other bugs would already be fixed.

Quoted 11 lines

Best Regards
Huang Shijie
Quoted 8 lines
Quoted 5 lines
I am debugging it now.
Huang Shijie
Quoted 1 line
have NAND device to play, can you guys aligned here?
Best regards,
Marek Vasut

Best regards,
Marek Vasut