Add initial support for Altera's SOCFPGA hardward

+config ARCH_SOCFPGA

arch/arm/mach-socfpga/Kconfig new file +4 -0

+choice
+	prompt "Altera SOCFPGA Platform"
+	default MACH_SOCFPGA_CYCLONE5
+	depends on ARCH_SOCFPGA

arch/arm/mach-socfpga/Makefile.boot new file +31 -0

+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <mach/clkdev.h>
+
+int clk_enable(struct clk *clk)
+{
+	return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	long ret = -EIO;
+	if (clk->ops && clk->ops->round)
+		ret = clk->ops->round(clk, rate);
+	return ret;
+}

arch/arm/mach-socfpga/Makefile.boot new file +43 -0

+extern struct dw_mci_board sdmmc_platform_data;
+extern struct dma_pl330_platdata dma_platform_data;
+
+#define DW_APB_UART_OF_COMPATIBLE			"snps,dw-apb-uart"
+
+#define SOCFPGA_MPU_PERIHCLK_FREQ_HZ			(800000000 / 4)
+#define SOCFPGA_L4_MAIN_CLK					(400000000)
+
+static struct clk dummy_apb_pclk;
+static struct clk dummy_i2c_clk = {
+	.rate   = 100000000,
+};
+static struct clk dummy_spim_clk = {
+	.rate   = 100000000,
+};
+static struct clk mpu_periphclk = {
+	.rate   = SOCFPGA_MPU_PERIHCLK_FREQ_HZ,
+};
+
+static struct clk l4_main_clk = {
+	.rate   = SOCFPGA_L4_MAIN_CLK,
+};
+
+static struct clk_lookup lookups[] = {
+	{	/* Bus clock */
+		.con_id		= "apb_pclk",
+		.clk		= &dummy_apb_pclk,
+	},
+	{
+		.dev_id		= "ffc04000.i2c",
+		.clk		= &dummy_i2c_clk,
+	},
+	{
+		.dev_id		= "ffc05000.i2c",
+		.clk		= &dummy_i2c_clk,
+	},
+	{
+		.dev_id		= "dw-spi-mmio.0",
+		.clk		= &dummy_spim_clk,
+	},
+	{
+		.dev_id		= "dw-spi-mmio.1",
+		.clk		= &dummy_spim_clk,

arch/arm/mach-socfpga/Makefile.boot new file +5 -0

+/*
+ * Set up the clock source and clock events devices
+ */
+
+void __init socfpga_timer_init(void __iomem *src_timer_base,

+++ b/arch/arm/mach-socfpga/dw_apb_timer.c

arch/arm/mach-socfpga/Makefile.boot new file +266 -0

+/*
+ * SOCFPGA interrupt sources
+ */
+#define IRQ_SOCFPGA_CPU0_PARITY	(IRQ_SOCFPGA_GIC_START + 0)		/* CPU0 parity */
+#define IRQ_SOCFPGA_CPU0_PARITY_BTAG	(IRQ_SOCFPGA_GIC_START + 1)		/* CPU0 parity BTAG		*/
+#define IRQ_SOCFPGA_CPU0_PARITY_GHB		(IRQ_SOCFPGA_GIC_START + 2)		/* CPU0 parity GHB		*/
+#define IRQ_SOCFPGA_CPU0_PARITY_ITAG	(IRQ_SOCFPGA_GIC_START + 3)		/* CPU0 parity ITAG		*/
+#define IRQ_SOCFPGA_CPU0_PARITY_IDATA	(IRQ_SOCFPGA_GIC_START + 4)		/* CPU0 parity IDATA	*/
+#define IRQ_SOCFPGA_CPU0_PARITY_TLB		(IRQ_SOCFPGA_GIC_START + 5)		/* CPU0 parity TLB		*/
+#define IRQ_SOCFPGA_CPU0_PARITY_DOUTER	(IRQ_SOCFPGA_GIC_START + 6)		/* CPU0 parity DOUTER	*/
+#define IRQ_SOCFPGA_CPU0_PARITY_DTAG	(IRQ_SOCFPGA_GIC_START + 7)		/* CPU0 parity DTAG		*/
+#define IRQ_SOCFPGA_CPU0_PARITY_DDATA	(IRQ_SOCFPGA_GIC_START + 8)		/* CPU0 parity DDATA	*/
+#define IRQ_SOCFPGA_CPU0_DEFLAGS0	(IRQ_SOCFPGA_GIC_START + 9)			/* CPU0 deflasg 0 */
+#define IRQ_SOCFPGA_CPU0_DEFLAGS1	(IRQ_SOCFPGA_GIC_START + 10)		/* CPU0 deflags 1 */
+#define IRQ_SOCFPGA_CPU0_DEFLAGS2	(IRQ_SOCFPGA_GIC_START + 11)		/* CPU0 deflags 2 */
+#define IRQ_SOCFPGA_CPU0_DEFLAGS3	(IRQ_SOCFPGA_GIC_START + 12)		/* CPU0 deflags 3 */
+#define IRQ_SOCFPGA_CPU0_DEFLAGS4	(IRQ_SOCFPGA_GIC_START + 13)		/* CPU0 deflags 4 */
+#define IRQ_SOCFPGA_CPU0_DEFLAGS5	(IRQ_SOCFPGA_GIC_START + 14)		/* CPU0 deflags 5 */
+#define IRQ_SOCFPGA_CPU0_DEFLAGS6	(IRQ_SOCFPGA_GIC_START + 15)		/* CPU0 deflags 6 */
+#define IRQ_SOCFPGA_CPU1_PARITY		(IRQ_SOCFPGA_GIC_START + 16)		/* CPU1 parity */
+#define IRQ_SOCFPGA_CPU1_PARITY_BTAG	(IRQ_SOCFPGA_GIC_START + 17)	/* CPU1 parity BTAG		*/
+#define IRQ_SOCFPGA_CPU1_PARITY_GHB		(IRQ_SOCFPGA_GIC_START + 18)	/* CPU1 parity GHB		*/
+#define IRQ_SOCFPGA_CPU1_PARITY_ITAG	(IRQ_SOCFPGA_GIC_START + 19)	/* CPU1 parity ITAG		*/
+#define IRQ_SOCFPGA_CPU1_PARITY_IDATA	(IRQ_SOCFPGA_GIC_START + 20)	/* CPU1 parity IDATA	*/
+#define IRQ_SOCFPGA_CPU1_PARITY_TLB		(IRQ_SOCFPGA_GIC_START + 21)	/* CPU1 parity TLB		*/
+#define IRQ_SOCFPGA_CPU1_PARITY_DOUTER	(IRQ_SOCFPGA_GIC_START + 22)	/* CPU1 parity DOUTER	*/
+#define IRQ_SOCFPGA_CPU1_PARITY_DTAG	(IRQ_SOCFPGA_GIC_START + 23)	/* CPU1 parity DTAG		*/
+#define IRQ_SOCFPGA_CPU1_PARITY_DDATA	(IRQ_SOCFPGA_GIC_START + 24)	/* CPU1 parity DDATA	*/
+#define IRQ_SOCFPGA_CPU1_DEFLAGS0	(IRQ_SOCFPGA_GIC_START + 25)		/* CPU1 deflags 0 */
+#define IRQ_SOCFPGA_CPU1_DEFLAGS1	(IRQ_SOCFPGA_GIC_START + 26)	/* CPU1 deflags 1 */
+#define IRQ_SOCFPGA_CPU1_DEFLAGS2	(IRQ_SOCFPGA_GIC_START + 27)	/* CPU1 deflags 2 */
+#define IRQ_SOCFPGA_CPU1_DEFLAGS3	(IRQ_SOCFPGA_GIC_START + 28)	/* CPU1 deflags 3 */
+#define IRQ_SOCFPGA_CPU1_DEFLAGS4	(IRQ_SOCFPGA_GIC_START + 29)	/* CPU1 deflags 4 */
+#define IRQ_SOCFPGA_CPU1_DEFLAGS5	(IRQ_SOCFPGA_GIC_START + 30)	/* CPU1 deflags 5 */
+#define IRQ_SOCFPGA_CPU1_DEFLAGS6	(IRQ_SOCFPGA_GIC_START + 31)	/* CPU1 deflags 6 */
+#define IRQ_SOCFPGA_SCU0_PARITY	(IRQ_SOCFPGA_GIC_START + 32)	/* SCU0 parity */
+#define IRQ_SOCFPGA_SCU1_PARITY	(IRQ_SOCFPGA_GIC_START + 33)	/* SCU1 parity */
+#define IRQ_SOCFPGA_SCU_EV_ABORT	(IRQ_SOCFPGA_GIC_START + 34)	/* SCU EV abort */
+#define IRQ_SOCFPGA_L2_ECC_WRITE	(IRQ_SOCFPGA_GIC_START + 35)	/* L2 ECC write */
+#define IRQ_SOCFPGA_L2_ECC_CERR	(IRQ_SOCFPGA_GIC_START + 36)	/* L2 ECC error corrected */
+#define IRQ_SOCFPGA_L2_ECC_UERR	(IRQ_SOCFPGA_GIC_START + 37)	/* L2 ECC error uncorrected */
+#define IRQ_SOCFPGA_L2		(IRQ_SOCFPGA_GIC_START + 38)	/* L2 combined interrupts */
+#define IRQ_SOCFPGA_DDR_ECC_ERR	(IRQ_SOCFPGA_GIC_START + 39)	/* DDR ECC error */
+#define IRQ_SOCFPGA_F2S_FPGA0 	(IRQ_SOCFPGA_GIC_START + 40) 	/* FPGA IRQ 0 */
+#define IRQ_SOCFPGA_F2S_FPGA1 	(IRQ_SOCFPGA_GIC_START + 41) 	/* FPGA IRQ 1 */
+#define IRQ_SOCFPGA_F2S_FPGA2 	(IRQ_SOCFPGA_GIC_START + 42) 	/* FPGA IRQ 2 */
+#define IRQ_SOCFPGA_F2S_FPGA3 	(IRQ_SOCFPGA_GIC_START + 43) 	/* FPGA IRQ 3 */
+#define IRQ_SOCFPGA_F2S_FPGA4 	(IRQ_SOCFPGA_GIC_START + 44) 	/* FPGA IRQ 4 */
+#define IRQ_SOCFPGA_F2S_FPGA5 	(IRQ_SOCFPGA_GIC_START + 45) 	/* FPGA IRQ 5 */
+#define IRQ_SOCFPGA_F2S_FPGA6 	(IRQ_SOCFPGA_GIC_START + 46) 	/* FPGA IRQ 6 */
+#define IRQ_SOCFPGA_F2S_FPGA7 	(IRQ_SOCFPGA_GIC_START + 47) 	/* FPGA IRQ 7 */
+#define IRQ_SOCFPGA_F2S_FPGA8 	(IRQ_SOCFPGA_GIC_START + 48) 	/* FPGA IRQ 8 */
+#define IRQ_SOCFPGA_F2S_FPGA9 	(IRQ_SOCFPGA_GIC_START + 49) 	/* FPGA IRQ 9 */
+#define IRQ_SOCFPGA_F2S_FPGA10 	(IRQ_SOCFPGA_GIC_START + 50) 	/* FPGA IRQ 10 */
+#define IRQ_SOCFPGA_F2S_FPGA11 	(IRQ_SOCFPGA_GIC_START + 51) 	/* FPGA IRQ 11 */
+#define IRQ_SOCFPGA_F2S_FPGA12 	(IRQ_SOCFPGA_GIC_START + 52) 	/* FPGA IRQ 12 */
+#define IRQ_SOCFPGA_F2S_FPGA13 	(IRQ_SOCFPGA_GIC_START + 53) 	/* FPGA IRQ 13 */
+#define IRQ_SOCFPGA_F2S_FPGA14 	(IRQ_SOCFPGA_GIC_START + 54) 	/* FPGA IRQ 14 */
+#define IRQ_SOCFPGA_F2S_FPGA15 	(IRQ_SOCFPGA_GIC_START + 55) 	/* FPGA IRQ 15 */
+#define IRQ_SOCFPGA_F2S_FPGA16 	(IRQ_SOCFPGA_GIC_START + 56) 	/* FPGA IRQ 16 */
+#define IRQ_SOCFPGA_F2S_FPGA17 	(IRQ_SOCFPGA_GIC_START + 57) 	/* FPGA IRQ 17 */
+#define IRQ_SOCFPGA_F2S_FPGA18 	(IRQ_SOCFPGA_GIC_START + 58) 	/* FPGA IRQ 18 */
+#define IRQ_SOCFPGA_F2S_FPGA19 	(IRQ_SOCFPGA_GIC_START + 59) 	/* FPGA IRQ 19 */
+#define IRQ_SOCFPGA_F2S_FPGA20 	(IRQ_SOCFPGA_GIC_START + 60) 	/* FPGA IRQ 20 */
+#define IRQ_SOCFPGA_F2S_FPGA21 	(IRQ_SOCFPGA_GIC_START + 61) 	/* FPGA IRQ 21 */
+#define IRQ_SOCFPGA_F2S_FPGA22 	(IRQ_SOCFPGA_GIC_START + 62) 	/* FPGA IRQ 22 */
+#define IRQ_SOCFPGA_F2S_FPGA23 	(IRQ_SOCFPGA_GIC_START + 63) 	/* FPGA IRQ 23 */
+#define IRQ_SOCFPGA_F2S_FPGA24 	(IRQ_SOCFPGA_GIC_START + 64) 	/* FPGA IRQ 24 */
+#define IRQ_SOCFPGA_F2S_FPGA25 	(IRQ_SOCFPGA_GIC_START + 65) 	/* FPGA IRQ 25 */
+#define IRQ_SOCFPGA_F2S_FPGA26 	(IRQ_SOCFPGA_GIC_START + 66) 	/* FPGA IRQ 26 */
+#define IRQ_SOCFPGA_F2S_FPGA27 	(IRQ_SOCFPGA_GIC_START + 67) 	/* FPGA IRQ 27 */
+#define IRQ_SOCFPGA_F2S_FPGA28 	(IRQ_SOCFPGA_GIC_START + 68) 	/* FPGA IRQ 28 */
+#define IRQ_SOCFPGA_F2S_FPGA29 	(IRQ_SOCFPGA_GIC_START + 69) 	/* FPGA IRQ 29 */
+#define IRQ_SOCFPGA_F2S_FPGA30 	(IRQ_SOCFPGA_GIC_START + 70) 	/* FPGA IRQ 30 */
+#define IRQ_SOCFPGA_F2S_FPGA31 	(IRQ_SOCFPGA_GIC_START + 71) 	/* FPGA IRQ 31 */
+#define IRQ_SOCFPGA_F2S_FPGA32 	(IRQ_SOCFPGA_GIC_START + 72) 	/* FPGA IRQ 32 */
+#define IRQ_SOCFPGA_F2S_FPGA33 	(IRQ_SOCFPGA_GIC_START + 73) 	/* FPGA IRQ 33 */
+#define IRQ_SOCFPGA_F2S_FPGA34 	(IRQ_SOCFPGA_GIC_START + 74) 	/* FPGA IRQ 34 */
+#define IRQ_SOCFPGA_F2S_FPGA35 	(IRQ_SOCFPGA_GIC_START + 75) 	/* FPGA IRQ 35 */
+#define IRQ_SOCFPGA_F2S_FPGA36 	(IRQ_SOCFPGA_GIC_START + 76) 	/* FPGA IRQ 36 */
+#define IRQ_SOCFPGA_F2S_FPGA37 	(IRQ_SOCFPGA_GIC_START + 77) 	/* FPGA IRQ 37 */
+#define IRQ_SOCFPGA_F2S_FPGA38 	(IRQ_SOCFPGA_GIC_START + 78) 	/* FPGA IRQ 38 */
+#define IRQ_SOCFPGA_F2S_FPGA39 	(IRQ_SOCFPGA_GIC_START + 79) 	/* FPGA IRQ 39 */
+#define IRQ_SOCFPGA_F2S_FPGA40 	(IRQ_SOCFPGA_GIC_START + 80) 	/* FPGA IRQ 40 */
+#define IRQ_SOCFPGA_F2S_FPGA41 	(IRQ_SOCFPGA_GIC_START + 81) 	/* FPGA IRQ 41 */
+#define IRQ_SOCFPGA_F2S_FPGA42 	(IRQ_SOCFPGA_GIC_START + 82) 	/* FPGA IRQ 42 */
+#define IRQ_SOCFPGA_F2S_FPGA43 	(IRQ_SOCFPGA_GIC_START + 83) 	/* FPGA IRQ 43 */
+#define IRQ_SOCFPGA_F2S_FPGA44 	(IRQ_SOCFPGA_GIC_START + 84) 	/* FPGA IRQ 44 */
+#define IRQ_SOCFPGA_F2S_FPGA45 	(IRQ_SOCFPGA_GIC_START + 85) 	/* FPGA IRQ 45 */
+#define IRQ_SOCFPGA_F2S_FPGA46 	(IRQ_SOCFPGA_GIC_START + 86) 	/* FPGA IRQ 46 */
+#define IRQ_SOCFPGA_F2S_FPGA47 	(IRQ_SOCFPGA_GIC_START + 87) 	/* FPGA IRQ 47 */
+#define IRQ_SOCFPGA_F2S_FPGA48 	(IRQ_SOCFPGA_GIC_START + 88) 	/* FPGA IRQ 48 */
+#define IRQ_SOCFPGA_F2S_FPGA49 	(IRQ_SOCFPGA_GIC_START + 89) 	/* FPGA IRQ 49 */
+#define IRQ_SOCFPGA_F2S_FPGA50 	(IRQ_SOCFPGA_GIC_START + 90) 	/* FPGA IRQ 50 */
+#define IRQ_SOCFPGA_F2S_FPGA51 	(IRQ_SOCFPGA_GIC_START + 91) 	/* FPGA IRQ 51 */
+#define IRQ_SOCFPGA_F2S_FPGA52 	(IRQ_SOCFPGA_GIC_START + 92) 	/* FPGA IRQ 52 */
+#define IRQ_SOCFPGA_F2S_FPGA53 	(IRQ_SOCFPGA_GIC_START + 93) 	/* FPGA IRQ 53 */
+#define IRQ_SOCFPGA_F2S_FPGA54 	(IRQ_SOCFPGA_GIC_START + 94) 	/* FPGA IRQ 54 */
+#define IRQ_SOCFPGA_F2S_FPGA55 	(IRQ_SOCFPGA_GIC_START + 95) 	/* FPGA IRQ 55 */
+#define IRQ_SOCFPGA_F2S_FPGA56 	(IRQ_SOCFPGA_GIC_START + 96) 	/* FPGA IRQ 56 */
+#define IRQ_SOCFPGA_F2S_FPGA57 	(IRQ_SOCFPGA_GIC_START + 97) 	/* FPGA IRQ 57 */
+#define IRQ_SOCFPGA_F2S_FPGA58 	(IRQ_SOCFPGA_GIC_START + 98) 	/* FPGA IRQ 58 */
+#define IRQ_SOCFPGA_F2S_FPGA59 	(IRQ_SOCFPGA_GIC_START + 99) 	/* FPGA IRQ 59 */
+#define IRQ_SOCFPGA_F2S_FPGA60 	(IRQ_SOCFPGA_GIC_START + 100)	/* FPGA IRQ 60 */
+#define IRQ_SOCFPGA_F2S_FPGA61 	(IRQ_SOCFPGA_GIC_START + 101)	/* FPGA IRQ 61 */
+#define IRQ_SOCFPGA_F2S_FPGA62 	(IRQ_SOCFPGA_GIC_START + 102)	/* FPGA IRQ 62 */
+#define IRQ_SOCFPGA_F2S_FPGA63 	(IRQ_SOCFPGA_GIC_START + 103)	/* FPGA IRQ 63 */
+#define IRQ_SOCFPGA_DMA0		(IRQ_SOCFPGA_GIC_START + 104)	/* DMA Channel 0 */
+#define IRQ_SOCFPGA_DMA1		(IRQ_SOCFPGA_GIC_START + 105)	/* DMA Channel 1 */
+#define IRQ_SOCFPGA_DMA2		(IRQ_SOCFPGA_GIC_START + 106)	/* DMA Channel 2 */
+#define IRQ_SOCFPGA_DMA3		(IRQ_SOCFPGA_GIC_START + 107)	/* DMA Channel 3 */
+#define IRQ_SOCFPGA_DMA4		(IRQ_SOCFPGA_GIC_START + 108)	/* DMA Channel 3 */
+#define IRQ_SOCFPGA_DMA5		(IRQ_SOCFPGA_GIC_START + 109)	/* DMA Channel 5 */
+#define IRQ_SOCFPGA_DMA6		(IRQ_SOCFPGA_GIC_START + 110)	/* DMA Channel 6 */
+#define IRQ_SOCFPGA_DMA7		(IRQ_SOCFPGA_GIC_START + 111)	/* DMA Channel 7 */
+#define IRQ_SOCFPGA_DMA_ABORT	(IRQ_SOCFPGA_GIC_START + 112)	/* DMA abort */
+#define IRQ_SOCFPGA_DMA_CECC	(IRQ_SOCFPGA_GIC_START + 113)	/* DMA ECC corrected */
+#define IRQ_SOCFPGA_DMA_UECC	(IRQ_SOCFPGA_GIC_START + 114)	/* DMA ECC uncorrected */
+#define IRQ_SOCFPGA_EMAC0		(IRQ_SOCFPGA_GIC_START + 115)	/* Gb-Ethernet MAC0 */
+#define IRQ_SOCFPGA_EMAC0_TX_CECC	(IRQ_SOCFPGA_GIC_START + 116)	/* Gb-Ethernet MAC0 ECC corrected */
+#define IRQ_SOCFPGA_EMAC0_TX_UECC	(IRQ_SOCFPGA_GIC_START + 117)	/* Gb-Ethernet MAC0 ECC uncorrected */
+#define IRQ_SOCFPGA_EMAC0_RX_CECC	(IRQ_SOCFPGA_GIC_START + 118)	/* Gb-Ethernet MAC0 ECC corrected */
+#define IRQ_SOCFPGA_EMAC0_RX_UECC	(IRQ_SOCFPGA_GIC_START + 119)	/* Gb-Ethernet MAC0 ECC uncorrected */
+#define IRQ_SOCFPGA_EMAC1		(IRQ_SOCFPGA_GIC_START + 120)	/* Gb-Ethernet MAC1 */
+#define IRQ_SOCFPGA_EMAC1_TX_CECC	(IRQ_SOCFPGA_GIC_START + 121)	/* Gb-Ethernet MAC1 ECC corrected */
+#define IRQ_SOCFPGA_EMAC1_TX_UECC	(IRQ_SOCFPGA_GIC_START + 122)	/* Gb-Ethernet MAC1 ECC uncorrected */
+#define IRQ_SOCFPGA_EMAC1_RX_CECC	(IRQ_SOCFPGA_GIC_START + 123)	/* Gb-Ethernet MAC1 ECC corrected */
+#define IRQ_SOCFPGA_EMAC1_RX_UECC	(IRQ_SOCFPGA_GIC_START + 124)	/* Gb-Ethernet MAC1 ECC uncorrected */
+#define IRQ_SOCFPGA_USB0		(IRQ_SOCFPGA_GIC_START + 125)	/* USB 0 generic */
+#define IRQ_SOCFPGA_USB0_CECC	(IRQ_SOCFPGA_GIC_START + 126)	/* USB 0 ECC corrected */
+#define IRQ_SOCFPGA_USB0_UECC	(IRQ_SOCFPGA_GIC_START + 127)	/* USB 0 ECC uncorrected */
+#define IRQ_SOCFPGA_USB1		(IRQ_SOCFPGA_GIC_START + 128)	/* USB 1 generic */
+#define IRQ_SOCFPGA_USB1_CECC	(IRQ_SOCFPGA_GIC_START + 129)	/* USB 1 ECC corrected */
+#define IRQ_SOCFPGA_USB1_UECC	(IRQ_SOCFPGA_GIC_START + 130)	/* USB 1 ECC uncorrected */
+#define IRQ_SOCFPGA_CAN0_STS	(IRQ_SOCFPGA_GIC_START + 131)	/* CAN0 interrupt 0 */
+#define IRQ_SOCFPGA_CAN0_MO		(IRQ_SOCFPGA_GIC_START + 132)	/* CAN0 interrupt 1 */
+#define IRQ_SOCFPGA_CAN0_CECC	(IRQ_SOCFPGA_GIC_START + 133)	/* CAN0 ECC corrected */
+#define IRQ_SOCFPGA_CAN0_UECC	(IRQ_SOCFPGA_GIC_START + 134)	/* CAN0 ECC uncorrected */
+#define IRQ_SOCFPGA_CAN1_STS	(IRQ_SOCFPGA_GIC_START + 135)	/* CAN1 interrupt 0 */
+#define IRQ_SOCFPGA_CAN1_MO		(IRQ_SOCFPGA_GIC_START + 136)	/* CAN1 interrupt 1 */
+#define IRQ_SOCFPGA_CAN1_CECC	(IRQ_SOCFPGA_GIC_START + 137)	/* CAN1 ECC corrected */
+#define IRQ_SOCFPGA_CAN1_UECC	(IRQ_SOCFPGA_GIC_START + 138)	/* CAN1 ECC uncorrected */
+#define IRQ_SOCFPGA_SDMMC		(IRQ_SOCFPGA_GIC_START + 139)	/* SD/MMC */
+#define IRQ_SOCFPGA_SDMMC_PA_CECC	(IRQ_SOCFPGA_GIC_START + 140)	/* SD/MMC PortA ECC corrected */
+#define IRQ_SOCFPGA_SDMMC_PA_UECC	(IRQ_SOCFPGA_GIC_START + 141)	/* SD/MMC PortA ECC uncorrected */
+#define IRQ_SOCFPGA_SDMMC_PB_CECC	(IRQ_SOCFPGA_GIC_START + 142)	/* SD/MMC PortB ECC corrected */
+#define IRQ_SOCFPGA_SDMMC_PB_UECC	(IRQ_SOCFPGA_GIC_START + 143)	/* SD/MMC PortB ECC uncorrected */
+#define IRQ_SOCFPGA_NAND		(IRQ_SOCFPGA_GIC_START + 144)	/* NAND */
+#define IRQ_SOCFPGA_NAND_R_CECC	(IRQ_SOCFPGA_GIC_START + 145)	/* NAND read ECC corrected */
+#define IRQ_SOCFPGA_NAND_R_UECC	(IRQ_SOCFPGA_GIC_START + 146)	/* NAND read ECC uncorrected */
+#define IRQ_SOCFPGA_NAND_W_CECC	(IRQ_SOCFPGA_GIC_START + 147)	/* NAND write ECC corrected */
+#define IRQ_SOCFPGA_NAND_W_UECC	(IRQ_SOCFPGA_GIC_START + 148)	/* NAND write ECC uncorrected */
+#define IRQ_SOCFPGA_NAND_E_CECC	(IRQ_SOCFPGA_GIC_START + 149)	/* NAND error ECC corrected */
+#define IRQ_SOCFPGA_NAND_E_UECC	(IRQ_SOCFPGA_GIC_START + 150)	/* NAND error ECC uncorrected */
+#define IRQ_SOCFPGA_QSPI		(IRQ_SOCFPGA_GIC_START + 151)	/* Quad-SPI */
+#define IRQ_SOCFPGA_QSPI_CECC	(IRQ_SOCFPGA_GIC_START + 152)	/* Quad-SPI ECC corrected */
+#define IRQ_SOCFPGA_QSPI_UECC	(IRQ_SOCFPGA_GIC_START + 153)	/* Quad-SPI ECC uncorrected */
+#define IRQ_SOCFPGA_SPI0		(IRQ_SOCFPGA_GIC_START + 154)	/* SPI 0 */
+#define IRQ_SOCFPGA_SPI1		(IRQ_SOCFPGA_GIC_START + 155)	/* SPI 1 */
+#define IRQ_SOCFPGA_SPI2		(IRQ_SOCFPGA_GIC_START + 156)	/* SPI 2 */
+#define IRQ_SOCFPGA_SPI3		(IRQ_SOCFPGA_GIC_START + 157)	/* SPI 3 */
+#define IRQ_SOCFPGA_I2C0		(IRQ_SOCFPGA_GIC_START + 158)	/* I2C 0 */
+#define IRQ_SOCFPGA_I2C1		(IRQ_SOCFPGA_GIC_START + 159)	/* I2C 1 */
+#define IRQ_SOCFPGA_I2C2		(IRQ_SOCFPGA_GIC_START + 160)	/* I2C 2 */
+#define IRQ_SOCFPGA_I2C3		(IRQ_SOCFPGA_GIC_START + 161)	/* I2C 3 */
+#define IRQ_SOCFPGA_UART0		(IRQ_SOCFPGA_GIC_START + 162)	/* UART 0 */
+#define IRQ_SOCFPGA_UART1		(IRQ_SOCFPGA_GIC_START + 163)	/* UART 1 */
+#define IRQ_SOCFPGA_GPIO0		(IRQ_SOCFPGA_GIC_START + 164)	/* GPIO 0 */
+#define IRQ_SOCFPGA_GPIO1		(IRQ_SOCFPGA_GIC_START + 165)	/* GPIO 1 */
+#define IRQ_SOCFPGA_GPIO2		(IRQ_SOCFPGA_GIC_START + 166)	/* GPIO 2 */
+#define IRQ_SOCFPGA_L4_SP_TIMER0	(IRQ_SOCFPGA_GIC_START + 167)	/* L4 SP timer 0 */
+#define IRQ_SOCFPGA_L4_SP_TIMER1	(IRQ_SOCFPGA_GIC_START + 168)	/* L4 SP timer 1 */
+#define IRQ_SOCFPGA_L4_OSC1_TIMER0	(IRQ_SOCFPGA_GIC_START + 169)	/* L4 OSC1 timer 0 */
+#define IRQ_SOCFPGA_L4_OSC1_TIMER1	(IRQ_SOCFPGA_GIC_START + 170)	/* L4 OSC1 timer 1 */
+#define IRQ_SOCFPGA_WD0		(IRQ_SOCFPGA_GIC_START + 171)	/* Watchdog timer 0 */
+#define IRQ_SOCFPGA_WD1		(IRQ_SOCFPGA_GIC_START + 172)	/* Watchdog timer 1 */
+#define IRQ_SOCFPGA_CLK_MAN		(IRQ_SOCFPGA_GIC_START + 173)	/* Clock manager */
+#define IRQ_SOCFPGA_MPU_WAKE	(IRQ_SOCFPGA_GIC_START + 174)	/* MPU wake */
+#define IRQ_SOCFPGA_FPGA_MON	(IRQ_SOCFPGA_GIC_START + 175)	/* FPGA monitor */
+#define IRQ_SOCFPGA_CPU0_CTI	(IRQ_SOCFPGA_GIC_START + 176)	/* Coresight CPU0 CTI */
+#define IRQ_SOCFPGA_CPU1_CTI	(IRQ_SOCFPGA_GIC_START + 177)	/* Coresight CPU1 CTI */
+#define IRQ_SOCFPGA_OCRAM_CECC	(IRQ_SOCFPGA_GIC_START + 178)	/* on-chip RAM ECC corrected */
+#define IRQ_SOCFPGA_OCRAM_UECC	(IRQ_SOCFPGA_GIC_START + 179)	/* on-chip RAM ECC uncorrected */
+
+/* Soft IRQ */
+#define SOFTIRQ_SOCFPGA_DMADEV 	(IRQ_SOCFPGA_GIC_START + 180)
+#define SOFTIRQ_SOCFPGA_GPIO_0_0	(IRQ_SOCFPGA_GIC_START + 181)
+#define SOFTIRQ_SOCFPGA_GPIO_0_1	(IRQ_SOCFPGA_GIC_START + 182)
+#define SOFTIRQ_SOCFPGA_GPIO_0_2	(IRQ_SOCFPGA_GIC_START + 183)
+#define SOFTIRQ_SOCFPGA_GPIO_0_3	(IRQ_SOCFPGA_GIC_START + 184)
+#define SOFTIRQ_SOCFPGA_GPIO_0_4	(IRQ_SOCFPGA_GIC_START + 185)
+#define SOFTIRQ_SOCFPGA_GPIO_0_5	(IRQ_SOCFPGA_GIC_START + 186)
+#define SOFTIRQ_SOCFPGA_GPIO_0_6	(IRQ_SOCFPGA_GIC_START + 187)
+#define SOFTIRQ_SOCFPGA_GPIO_0_7	(IRQ_SOCFPGA_GIC_START + 188)
+#define SOFTIRQ_SOCFPGA_GPIO_0_8	(IRQ_SOCFPGA_GIC_START + 189)
+#define SOFTIRQ_SOCFPGA_GPIO_0_9	(IRQ_SOCFPGA_GIC_START + 190)
+#define SOFTIRQ_SOCFPGA_GPIO_0_10	(IRQ_SOCFPGA_GIC_START + 191)
+#define SOFTIRQ_SOCFPGA_GPIO_0_11	(IRQ_SOCFPGA_GIC_START + 192)
+#define SOFTIRQ_SOCFPGA_GPIO_0_12	(IRQ_SOCFPGA_GIC_START + 193)
+#define SOFTIRQ_SOCFPGA_GPIO_0_13	(IRQ_SOCFPGA_GIC_START + 194)
+#define SOFTIRQ_SOCFPGA_GPIO_0_14	(IRQ_SOCFPGA_GIC_START + 195)
+#define SOFTIRQ_SOCFPGA_GPIO_0_15	(IRQ_SOCFPGA_GIC_START + 196)
+#define SOFTIRQ_SOCFPGA_GPIO_0_16	(IRQ_SOCFPGA_GIC_START + 197)
+#define SOFTIRQ_SOCFPGA_GPIO_0_17	(IRQ_SOCFPGA_GIC_START + 198)
+#define SOFTIRQ_SOCFPGA_GPIO_0_18	(IRQ_SOCFPGA_GIC_START + 199)
+#define SOFTIRQ_SOCFPGA_GPIO_0_19	(IRQ_SOCFPGA_GIC_START + 200)
+#define SOFTIRQ_SOCFPGA_GPIO_0_20	(IRQ_SOCFPGA_GIC_START + 201)
+#define SOFTIRQ_SOCFPGA_GPIO_0_21	(IRQ_SOCFPGA_GIC_START + 202)
+#define SOFTIRQ_SOCFPGA_GPIO_0_22	(IRQ_SOCFPGA_GIC_START + 203)
+#define SOFTIRQ_SOCFPGA_GPIO_0_23	(IRQ_SOCFPGA_GIC_START + 204)
+#define SOFTIRQ_SOCFPGA_GPIO_0_24	(IRQ_SOCFPGA_GIC_START + 205)
+#define SOFTIRQ_SOCFPGA_GPIO_0_25	(IRQ_SOCFPGA_GIC_START + 206)
+#define SOFTIRQ_SOCFPGA_GPIO_0_26	(IRQ_SOCFPGA_GIC_START + 207)
+#define SOFTIRQ_SOCFPGA_GPIO_0_27	(IRQ_SOCFPGA_GIC_START + 208)
+#define SOFTIRQ_SOCFPGA_GPIO_0_28	(IRQ_SOCFPGA_GIC_START + 209)
+#define SOFTIRQ_SOCFPGA_GPIO_0_29	(IRQ_SOCFPGA_GIC_START + 210)
+#define SOFTIRQ_SOCFPGA_GPIO_1_0	(IRQ_SOCFPGA_GIC_START + 211)
+#define SOFTIRQ_SOCFPGA_GPIO_1_1	(IRQ_SOCFPGA_GIC_START + 212)
+#define SOFTIRQ_SOCFPGA_GPIO_1_2	(IRQ_SOCFPGA_GIC_START + 213)
+#define SOFTIRQ_SOCFPGA_GPIO_1_3	(IRQ_SOCFPGA_GIC_START + 214)
+#define SOFTIRQ_SOCFPGA_GPIO_1_4	(IRQ_SOCFPGA_GIC_START + 215)
+#define SOFTIRQ_SOCFPGA_GPIO_1_5	(IRQ_SOCFPGA_GIC_START + 216)
+#define SOFTIRQ_SOCFPGA_GPIO_1_6	(IRQ_SOCFPGA_GIC_START + 217)
+#define SOFTIRQ_SOCFPGA_GPIO_1_7	(IRQ_SOCFPGA_GIC_START + 218)
+#define SOFTIRQ_SOCFPGA_GPIO_1_8	(IRQ_SOCFPGA_GIC_START + 219)
+#define SOFTIRQ_SOCFPGA_GPIO_1_9	(IRQ_SOCFPGA_GIC_START + 220)
+#define SOFTIRQ_SOCFPGA_GPIO_1_10	(IRQ_SOCFPGA_GIC_START + 221)
+#define SOFTIRQ_SOCFPGA_GPIO_1_11	(IRQ_SOCFPGA_GIC_START + 222)
+#define SOFTIRQ_SOCFPGA_GPIO_1_12	(IRQ_SOCFPGA_GIC_START + 223)
+#define SOFTIRQ_SOCFPGA_GPIO_1_13	(IRQ_SOCFPGA_GIC_START + 224)
+#define SOFTIRQ_SOCFPGA_GPIO_1_14	(IRQ_SOCFPGA_GIC_START + 225)
+#define SOFTIRQ_SOCFPGA_GPIO_1_15	(IRQ_SOCFPGA_GIC_START + 226)
+#define SOFTIRQ_SOCFPGA_GPIO_1_16	(IRQ_SOCFPGA_GIC_START + 227)
+#define SOFTIRQ_SOCFPGA_GPIO_1_17	(IRQ_SOCFPGA_GIC_START + 228)
+#define SOFTIRQ_SOCFPGA_GPIO_1_18	(IRQ_SOCFPGA_GIC_START + 229)
+#define SOFTIRQ_SOCFPGA_GPIO_1_19	(IRQ_SOCFPGA_GIC_START + 230)
+#define SOFTIRQ_SOCFPGA_GPIO_1_20	(IRQ_SOCFPGA_GIC_START + 231)
+#define SOFTIRQ_SOCFPGA_GPIO_1_21	(IRQ_SOCFPGA_GIC_START + 232)
+#define SOFTIRQ_SOCFPGA_GPIO_1_22	(IRQ_SOCFPGA_GIC_START + 233)
+#define SOFTIRQ_SOCFPGA_GPIO_1_23	(IRQ_SOCFPGA_GIC_START + 234)
+#define SOFTIRQ_SOCFPGA_GPIO_1_24	(IRQ_SOCFPGA_GIC_START + 235)
+#define SOFTIRQ_SOCFPGA_GPIO_1_25	(IRQ_SOCFPGA_GIC_START + 236)
+#define SOFTIRQ_SOCFPGA_GPIO_1_26	(IRQ_SOCFPGA_GIC_START + 237)
+#define SOFTIRQ_SOCFPGA_GPIO_1_27	(IRQ_SOCFPGA_GIC_START + 238)
+#define SOFTIRQ_SOCFPGA_GPIO_1_28	(IRQ_SOCFPGA_GIC_START + 239)
+#define SOFTIRQ_SOCFPGA_GPIO_1_29	(IRQ_SOCFPGA_GIC_START + 240)
+#define SOFTIRQ_SOCFPGA_GPIO_2_0	(IRQ_SOCFPGA_GIC_START + 241)
+#define SOFTIRQ_SOCFPGA_GPIO_2_1	(IRQ_SOCFPGA_GIC_START + 242)
+#define SOFTIRQ_SOCFPGA_GPIO_2_2	(IRQ_SOCFPGA_GIC_START + 243)
+#define SOFTIRQ_SOCFPGA_GPIO_2_3	(IRQ_SOCFPGA_GIC_START + 244)
+#define SOFTIRQ_SOCFPGA_GPIO_2_4	(IRQ_SOCFPGA_GIC_START + 245)
+#define SOFTIRQ_SOCFPGA_GPIO_2_5	(IRQ_SOCFPGA_GIC_START + 246)
+#define SOFTIRQ_SOCFPGA_GPIO_2_6	(IRQ_SOCFPGA_GIC_START + 247)
+#define SOFTIRQ_SOCFPGA_GPIO_2_7	(IRQ_SOCFPGA_GIC_START + 248)
+#define SOFTIRQ_SOCFPGA_GPIO_2_8	(IRQ_SOCFPGA_GIC_START + 249)
+#define SOFTIRQ_SOCFPGA_GPIO_2_9	(IRQ_SOCFPGA_GIC_START + 250)
+#define SOFTIRQ_SOCFPGA_GPIO_2_10	(IRQ_SOCFPGA_GIC_START + 251)
+#define SOFTIRQ_SOCFPGA_GPIO_2_11	(IRQ_SOCFPGA_GIC_START + 252)
+#define SOFTIRQ_SOCFPGA_GPIO_2_12	(IRQ_SOCFPGA_GIC_START + 253)
+#define SOFTIRQ_SOCFPGA_GPIO_2_13	(IRQ_SOCFPGA_GIC_START + 254)
+#define SOFTIRQ_SOCFPGA_GPIO_2_14	(IRQ_SOCFPGA_GIC_START + 255)
+#define SOFTIRQ_SOCFPGA_GPIO_2_15	(IRQ_SOCFPGA_GIC_START + 256)
+#define SOFTIRQ_SOCFPGA_GPIO_2_16	(IRQ_SOCFPGA_GIC_START + 257)
+#define SOFTIRQ_SOCFPGA_GPIO_2_17	(IRQ_SOCFPGA_GIC_START + 258)
+#define SOFTIRQ_SOCFPGA_GPIO_2_18	(IRQ_SOCFPGA_GIC_START + 259)
+#define SOFTIRQ_SOCFPGA_GPIO_2_19	(IRQ_SOCFPGA_GIC_START + 260)

+#define NR_IRQS 512

+++ b/arch/arm/mach-socfpga/include/mach/system.h

arch/arm/mach-socfpga/Makefile.boot new file +21 -0

@@ -0,0 +1,31 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation
+ *
+ * Modified from arch/arm/mach-realview/include/mach/system.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+

Below a few comments from my modest experience on the mach-mvebu SoC support.

Le Wed, 27 Jun 2012 08:50:06 -0500,
<[email protected]> a ?crit :

Quoted 1 line

+config ARCH_SOCFPGA

Is SOCFPGA a good name? It seems like a very generic name. Shouldn't it be ARCH_ALTERA_SOCFPGA a better name? I suspect other vendors will provide a SoC together with a FPGA.

Quoted 9 lines

arch/arm/mach-socfpga/Kconfig new file +9 -0

+choice
+	prompt "Altera SOCFPGA Platform"
+	default MACH_SOCFPGA_CYCLONE5
+	depends on ARCH_SOCFPGA
+	help
+		Select SOCFPGA platform type
+
+config MACH_SOCFPGA_CYCLONE5
+	bool "SOCFPGA Cyclone5 platform"

arch/arm/mach-socfpga/Kconfig line 14

Quoted 5 lines

arch/arm/mach-socfpga/Kconfig new file +5 -0

+	select HAVE_SMP
+	select PLAT_SOCFPGA_ETH
+	help
+	  Include support for the Altera(R) Cyclone5 development platform.
+endchoice

Why do you need a "choice" here? The code should be able to support building multiple platforms at once.

And even more: for a given SoC
variant, we now generally only want one config options, the board-level details being abstracted out by the device tree.

arch/arm/mach-socfpga/Makefile.boot line 3

Quoted 7 lines

index 0000000..7a1f3c0

arch/arm/mach-socfpga/Makefile.boot new file +3 -0

@@ -0,0 +1,3 @@
+zreladdr-y	:= 0x00008000
+params_phys-y	:= 0x00000100
+initrd_phys-y	:= 0x00800000

With the device tree, the params_phys-y and initrd_phys-y variables are useless.

Quoted 5 lines

arch/arm/mach-socfpga/Makefile.boot new file +5 -0

+/*
+ * SOCFPGA interrupt sources
+ */
+#define IRQ_SOCFPGA_CPU0_PARITY	(IRQ_SOCFPGA_GIC_START + 0)		/* CPU0 parity */
+#define IRQ_SOCFPGA_CPU0_PARITY_BTAG	(IRQ_SOCFPGA_GIC_START + 1)		/* CPU0 parity BTAG		*/

arch/arm/mach-socfpga/Makefile.boot

Quoted 3 lines

arch/arm/mach-socfpga/Makefile.boot new file +3 -0

+#define SOFTIRQ_SOCFPGA_GPIO_2_27	(IRQ_SOCFPGA_GIC_START + 268)
+#define SOFTIRQ_SOCFPGA_GPIO_2_28	(IRQ_SOCFPGA_GIC_START + 269)
+#define SOFTIRQ_SOCFPGA_GPIO_2_29	(IRQ_SOCFPGA_GIC_START + 270)

Those huge lists of IRQs are no longer useful with the device tree, you can get rid of them.

Quoted 1 line

+#define NR_IRQS 512

You should be looking at using SPARSE_IRQ to avoid having a maximum number of irqs. See for example mach-highbank/.

Quoted 5 lines

arch/arm/mach-socfpga/Makefile.boot new file +5 -0

+static inline void arch_idle(void)
+{
+	/*
+	 * This should do all the clock switching
+	 * and wait for interrupt tricks

arch/arm/mach-socfpga/Makefile.boot

Quoted 5 lines

arch/arm/mach-socfpga/Makefile.boot new file +5 -0

+	 */
+	cpu_do_idle();
+}
+
+#endif

This isn't used anywhere, and the system.h header is being removed from sub-architectures, if I understood correctly.

Quoted 5 lines

index 101b968..2f9a81e 100644

arch/arm/mm/Kconfig +0 -0

@@ -381,7 +381,7 @@ config CPU_V6K
 

arch/arm/mm/Kconfig config CPU_V6K · line 387

Quoted 7 lines

arch/arm/mm/Kconfig +1 -1

 # ARMv7
 config CPU_V7
-	bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
+	bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_SOCFPGA
 	select CPU_32v6K
 	select CPU_32v7
 	select CPU_ABRT_EV7

Apparently, your SoC is ARMv7 only at the moment, so you don't need to do this. Just keep the "select CPU_V7" in your ARCH_SOCFPGA option.

Quoted 3 lines

Is SOCFPGA a good name? It seems like a very generic name. Shouldn't it be ARCH_ALTERA_SOCFPGA a better name? I suspect other vendors will provide a SoC together with a FPGA.

I guess for config option name, ALTERA_SOCFPGA is okay, but for directory name it would be a little bit long. Would that work?

Quoted 3 lines

And even more: for a given SoC
variant, we now generally only want one config options, the board-level details being abstracted out by the device tree.

Will look into that later.

Ok.

arch/arm/mach-socfpga/socfpga_cyclone5.c:119: error:
'IRQ_SOCFPGA_L4_OSC1_TIMER0' undeclared (first use in this function)

Looks like we'll meed a bit more of dt :-).

Quoted 4 lines

Quoted 1 line

+#define NR_IRQS 512

You should be looking at using SPARSE_IRQ to avoid having a maximum number of irqs. See for example mach-highbank/.

Is maximum number of interrupts a problem? 512 does not seem excessive.

Le Wed, 27 Jun 2012 20:05:16 +0200,
Pavel Machek <[email protected]> a ?crit :

Quoted 4 lines

Quoted 3 lines

Is SOCFPGA a good name? It seems like a very generic name. Shouldn't it be ARCH_ALTERA_SOCFPGA a better name? I suspect other vendors will provide a SoC together with a FPGA.

Quoted 2 lines

I guess for config option name, ALTERA_SOCFPGA is okay, but for directory name it would be a little bit long. Would that work?

Hum, yes, maybe. Maybe just MACH_ALTERA, and mach-altera then? Hopefully others will have better ideas.

Quoted 6 lines

Quoted 4 lines

And even more: for a given SoC
variant, we now generally only want one config options, the board-level details being abstracted out by the device tree.

Will look into that later.

Ok. If you look at other platforms, they now typically have only one DT_MACHINE_START, and one configuration option associated to it, for each SoC variant. The different boards are only described using DT.

Quoted 6 lines

Ok.

arch/arm/mach-socfpga/socfpga_cyclone5.c:119: error:
'IRQ_SOCFPGA_L4_OSC1_TIMER0' undeclared (first use in this function)

Looks like we'll meed a bit more of dt :-).

Yes, you need more DT. You need a DT node for the timer, which will contain all the details like base I/O address and IRQ.

Quoted 7 lines

Quoted 4 lines

Quoted 1 line

+#define NR_IRQS 512

You should be looking at using SPARSE_IRQ to avoid having a maximum number of irqs. See for example mach-highbank/.

Is maximum number of interrupts a problem? 512 does not seem excessive.

Regardless of the value of NR_IRQS, there is apparently a trend to use SPARSE_IRQ anyway. However, I am not at the best place to explain why SPARSE_IRQ is now considered the right thing to use.

Best regards,

Thomas

Quoted 2 lines

Hum, yes, maybe. Maybe just MACH_ALTERA, and mach-altera then? Hopefully others will have better ideas.

First off, thanks for the thoughtful review, its very much appreciated.

Unless its a really strong objection, I'd like to stick with mach-socfpga. This is a name that Altera has started to market this hwt around and I would like to stick with it.

Quoted 3 lines

Unless its a really strong objection, I'd like to stick with mach-socfpga. This is a name that Altera has started to market this hwt around and I would like to stick with it.

I am definitely amongst the person who will take that decision, so I can't say what will happen with this choice, but feel free to push it forward, and you'll how it goes.

Quoted 7 lines

Quoted 4 lines

Quoted 1 line

+#define NR_IRQS 512

You should be looking at using SPARSE_IRQ to avoid having a maximum number of irqs. See for example mach-highbank/.

Is maximum number of interrupts a problem? 512 does not seem excessive.

Regardless of the value of NR_IRQS, there is apparently a trend to use SPARSE_IRQ anyway. However, I am not at the best place to explain why SPARSE_IRQ is now considered the right thing to use.

Quoted 11 lines · Thomas Petazzoni

Quoted 7 lines

Quoted 4 lines

Quoted 1 line

+#define NR_IRQS 512

You should be looking at using SPARSE_IRQ to avoid having a maximum number of irqs. See for example mach-highbank/.

Is maximum number of interrupts a problem? 512 does not seem excessive.

Regardless of the value of NR_IRQS, there is apparently a trend to use SPARSE_IRQ anyway. However, I am not at the best place to explain why SPARSE_IRQ is now considered the right thing to use.

The main reason for me is to get rid of a hardcoded NR_IRQS constant, whihc is a blocker for multiplatform kernels. New platforms should do all they can to allow being built together with other platforms in the same kernel. While we're not there yet, doing sparse irq is an important step in the right direction and should not be hard to do for new code.

Review

Quoted 11 lines

static void __init socfpga_cyclone5_init(void)
{

(quoted diff) +5 -0

+       int i;
+       for (i = 0; i < 512; i++) {
+               dynamic_irq_init(i);
+       }
+
 #ifdef CONFIG_CACHE_L2X0
        /* 8-way, 64K/way, evmon/parity/share */
        l2x0_of_init(0x00760000, 0xfe000fff);

This looks wrong, I think what you should do instead is to call irq_domain_add_legacy() for each controller you register as the first step, and then try to convert the controllers to use irq_domain_add_linear() as the second step. See also Documentation/IRQ-domain.txt.

Hi!

This fixes early_printk() compilation for
socfpga. (senduart/busyuart/waituart were missing). It does that by making Picochip code generic.

Signed-off-by Pavel Machek <[email protected]>

Acked-by Dinh Nguyen <[email protected]>

Acked-by Jamie Iles <[email protected]

Quoted 4 lines

This fixes early_printk() compilation for
socfpga. (senduart/busyuart/waituart were missing). It does that by making Picochip code generic.

Quoted 3 lines

Signed-off-by Pavel Machek <[email protected]>

Acked-by Dinh Nguyen <[email protected]>

Acked-by Jamie Iles <[email protected]

Applied to fixes branch of arm-soc, but please be more explicit about what you want to happen with patches in the future. Ideally we would get pull requests for patches on each platform from only one person, so please coordinate with Dinh Nguyen who that should be.

Some minor things:

* If you include something in the email that should not be part of the git changelog (e.g. "Hi!"), then please put it below the "---" line under the Signed-off list.

* you are missing a '>' after Jamies email address

* When you submit a patch for inclusion, please always take both Olof and me on Cc on the email, since we are doing this work together and take turns, so you might not always know which one will take the patch. We have an alias "arm at kernel.org" that you can also use.

Quoted 4 lines

Quoted 4 lines

This fixes early_printk() compilation for
socfpga. (senduart/busyuart/waituart were missing). It does that by making Picochip code generic.

Quoted 8 lines

Quoted 3 lines

Signed-off-by Pavel Machek <[email protected]>

Acked-by Dinh Nguyen <[email protected]>

Acked-by Jamie Iles <[email protected]

Applied to fixes branch of arm-soc, but please be more explicit about what you want to happen with patches in the future. Ideally we would get pull requests for patches on each platform from only one person, so please coordinate with Dinh Nguyen who that should be.

Dinh is the maintainer, so if we can only send patches from one person, it needs to be him. If you'd be willing to take patches from second person, that would help us... if not, of course I can send all the patches through Dinh.

Quoted 5 lines

* When you submit a patch for inclusion, please always take both Olof and me on Cc on the email, since we are doing this work together and take turns, so you might not always know which one will take the patch. We have an alias "arm at kernel.org" that you can also use.

Olof Johansson <[email protected]>? Can do.

But... perhaps you should add an entry into MAINTAINERS file explaining all this? arm at kernel.org is not mentioned there, Olof is not mentioned as maintaining arm. (And yes, I did check it before original patch submission).

Quoted 13 lines

Quoted 4 lines

Quoted 4 lines

This fixes early_printk() compilation for
socfpga. (senduart/busyuart/waituart were missing). It does that by making Picochip code generic.

Quoted 8 lines

Quoted 3 lines

Signed-off-by Pavel Machek <[email protected]>

Acked-by Dinh Nguyen <[email protected]>

Acked-by Jamie Iles <[email protected]

Applied to fixes branch of arm-soc, but please be more explicit about what you want to happen with patches in the future. Ideally we would get pull requests for patches on each platform from only one person, so please coordinate with Dinh Nguyen who that should be.

Quoted 4 lines

Dinh is the maintainer, so if we can only send patches from one person, it needs to be him. If you'd be willing to take patches from second person, that would help us... if not, of course I can send all the patches through Dinh.

You can both send patches, we just need to know what to expect. For most platforms it works best if one person collects the patches from everyone.

If you are sending patches with both Dinh and us as the recipients, just make it clear who you want to pick up the patch.

Quoted 18 lines

Quoted 13 lines

Quoted 4 lines

Quoted 4 lines

This fixes early_printk() compilation for
socfpga. (senduart/busyuart/waituart were missing). It does that by making Picochip code generic.

Quoted 8 lines

Quoted 3 lines

Signed-off-by Pavel Machek <[email protected]>

Acked-by Dinh Nguyen <[email protected]>

Acked-by Jamie Iles <[email protected]

Applied to fixes branch of arm-soc, but please be more explicit about what you want to happen with patches in the future. Ideally we would get pull requests for patches on each platform from only one person, so please coordinate with Dinh Nguyen who that should be.

Quoted 4 lines

Dinh is the maintainer, so if we can only send patches from one person, it needs to be him. If you'd be willing to take patches from second person, that would help us... if not, of course I can send all the patches through Dinh.

Quoted 6 lines

You can both send patches, we just need to know what to expect. For most platforms it works best if one person collects the patches from everyone.

If you are sending patches with both Dinh and us as the recipients, just make it clear who you want to pick up the patch.

Thanks. Would "[PATCH for soc]" in subject line be suitable markup?

BTW current for-next soc tree does not compile for me, with

arch/arm/mach-vexpress/built-in.o: In function `v2m_timer_init':
hotplug.c:(.init.text+0xd0): undefined reference to `vexpress_clk_init'
arch/arm/mach-vexpress/built-in.o: In function `v2m_dt_timer_init':
hotplug.c:(.init.text+0x100): undefined reference to `vexpress_clk_of_init'
make: *** [vmlinux] Error 1

arch/arm/mach-vexpress/v2m.c: vexpress_clk_init(ioremap(V2M_SYSCTL, SZ_4K));
include/linux/vexpress.h:void vexpress_clk_init(void __iomem *sp810_base);

...seems vexpress_clk_init is not there, yet... And what is more serious:

pavel at amd:~/mainline-altera/linux$ grep mach-vexpress MAINTAINERS pavel at amd:~/mainline-altera/linux$

vexpress_clk_of_init(); has same problem.

Quoted 6 lines · Pavel Machek

arch/arm/mach-vexpress/v2m.c: vexpress_clk_init(ioremap(V2M_SYSCTL, SZ_4K));
include/linux/vexpress.h:void vexpress_clk_init(void __iomem *sp810_base);

...seems vexpress_clk_init is not there, yet... And what is more serious:

Quoted 4 lines

pavel at amd:~/mainline-altera/linux$ grep mach-vexpress MAINTAINERS pavel at amd:~/mainline-altera/linux$

vexpress_clk_of_init(); has same problem.

I've already reported both to Pawel Moll, and he already came back with a new series, but we're still trying to work out the dependencies.

Quoted 6 lines

You can both send patches, we just need to know what to expect. For most platforms it works best if one person collects the patches from everyone.

If you are sending patches with both Dinh and us as the recipients, just make it clear who you want to pick up the patch.

Thanks. Would "[PATCH for soc]" in subject line be suitable markup?

Early printk code needs UART to be mapped early during boot. early_printk() is left there during the start-up; it is useful as our emulators are fairly slow.

Signed-off-by Pavel Machek <[email protected]>

Acked-by Dinh Nguyen <[email protected]>

arch/arm/mach-socfpga/socfpga.c +11 -0

index ab81ea9..49fb62b 100644
@@ -37,6 +37,15 @@ static struct map_desc scu_io_desc __initdata = {
 	.type		= MT_DEVICE,
 };
 
+
+
+static struct map_desc uart_io_desc __initdata = {
+	.virtual	= 0xfec02000,
+	.pfn		= __phys_to_pfn(0xffc02000),
+	.length		= SZ_8K,
+	.type		= MT_DEVICE,
+};
+
 static void __init socfpga_scu_map_io(void)
 {
 	unsigned long base;

@@ -51,6 +60,8 @@ static void __init socfpga_scu_map_io(void)
 static void __init socfpga_map_io(void)
 {
 	socfpga_scu_map_io();
+	iotable_init(&uart_io_desc, 1);
+	early_printk("Early printk initialized\n");
 }
 
 const static struct of_device_id irq_match[] = {

Hi!

Quoted 4 lines

Early printk code needs UART to be mapped early during boot. early_printk() is left there during the start-up; it is useful as our emulators are fairly slow.

Quoted 2 lines

Signed-off-by Pavel Machek <[email protected]>

Acked-by Dinh Nguyen <[email protected]>

Could we get this one applied? No comments for quite a while... and it is needed for machine not to crash with early_printk used...
Pavel

Quoted 12 lines

(quoted diff) +12 -0

+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <mach/clkdev.h>
+
+int clk_enable(struct clk *clk)
+{
+	return 0;
+}
+EXPORT_SYMBOL(clk_enable);

I don't think the ARM maintainers want more implementations of the clock API. New SoCs should instead use the new clock framework in drivers/clk/. See Documentation/clk.txt for details. You can for example look at the mxs or spear implementations for examples.

Review

Quoted 5 lines

(quoted diff) +5 -0

+	{
+		.dev_id		= "dma-pl330",
+		.clk		= &l4_main_clk,
+	}
+};

These should use the clock framework.

Quoted 4 lines

I don't think the ARM maintainers want more implementations of the clock API. New SoCs should instead use the new clock framework in drivers/clk/. See Documentation/clk.txt for details. You can for example look at the mxs or spear implementations for examples.

Agreed. Looks like fixed-rates.

Quoted 7 lines

Review

Quoted 5 lines

(quoted diff) +5 -0

+	{
+		.dev_id		= "dma-pl330",
+		.clk		= &l4_main_clk,
+	}
+};

These should use the clock framework.

Yep. Something like this? (Untested)

Review

Quoted 7 lines

(quoted diff) +7 -0

+struct plat_serial8250_port uart_platform_data[] = {
+		{
+		.type		= PORT_16850,
+		.flags 		= UPF_BOOT_AUTOCONF | UPF_IOREMAP | \
+				  UPF_FIXED_TYPE,
+		},
+};

This sounds strange. Why aren't you using the ns16850 compatible string to instantiate the UART devices directly from your device tree?

Hmm, strange. I see picoxcell-pc3x2.dtsi using similar dw-apb-uart. According to 8250_dw.c, it is not completely 16550-compatible, and uses slightly modified driver.

So it can be driven from dts, but not as ns16850 compatible. This patch does so.

Hello,

Le Wed, 4 Jul 2012 12:56:53 +0200,
Pavel Machek <[email protected]> a ?crit :

Quoted 4 lines

Hmm, strange. I see picoxcell-pc3x2.dtsi using similar dw-apb-uart. According to 8250_dw.c, it is not completely 16550-compatible, and uses slightly modified driver.

Quoted 2 lines

So it can be driven from dts, but not as ns16850 compatible. This patch does so.

I guess your patch misses the .dts bits, but other than that, looks much better without this bizarre notifier thing.

Do you plan to resend a complete v2 with all your patches nicely rebased? It's not that easy to review such a set of small cleanup increments :-)

-----Original Message-----
From: Pavel Machek [mailto:pavel at denx.de]
Sent: Wednesday, July 04, 2012 6:24 AM
To: Thomas Petazzoni
Cc: Dinh Nguyen; linux at arm.linux.org.uk; Kenneth Chong Yin Tan; wd at denx.de; linux-arm-kernel at lists.infradead.org
Subject: Re: [RFC PATCHv1 1/2] ARM: socfpga: initial support for Altera's SOCFPGA platform.

Quoted 9 lines · Thomas Petazzoni

Hello,

Le Wed, 4 Jul 2012 12:56:53 +0200,
Pavel Machek <[email protected]> a ?crit :

Quoted 4 lines

Hmm, strange. I see picoxcell-pc3x2.dtsi using similar dw-apb-uart. According to 8250_dw.c, it is not completely 16550-compatible, and uses slightly modified driver.

Quoted 5 lines

Quoted 2 lines

So it can be driven from dts, but not as ns16850 compatible. This patch does so.

I guess your patch misses the .dts bits, but other than that, looks much better without this bizarre notifier thing.

It turned out that dts already does the right thing.

Quoted 3 lines

Do you plan to resend a complete v2 with all your patches nicely rebased? It's not that easy to review such a set of small cleanup increments :-)

Sorry about that. Obviously, complete v2 will follow when major problems are fixed. (We do use git tree for coordination; I guess we should make it public at this point?)

Thanks,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures)
http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Quoted 7 lines

Quoted 3 lines

Do you plan to resend a complete v2 with all your patches nicely rebased? It's not that easy to review such a set of small cleanup increments :-)

Sorry about that. Obviously, complete v2 will follow when major problems are fixed. (We do use git tree for coordination; I guess we should make it public at this point?)

I'm reworking the patch to use the exisiting
clocksource/dw_apb_timer driver.

Quoted 5 lines

arch/arm/mach-socfpga/common.c new file +5 -0

+/*
+ * Set up the clock source and clock events devices
+ */
+
+void __init socfpga_timer_init(void __iomem *src_timer_base,

arch/arm/mach-socfpga/common.c line 133

Quoted 10 lines

arch/arm/mach-socfpga/common.c new file +10 -0

+				void __iomem *event_timer_base,
+				unsigned int event_timer_irq)
+{
+	/*
+	 * Initialise to a known state (all timers off)
+	 */
+	writel(0, sp_timer0_va_base + TIMER_CTRL);
+	writel(0, sp_timer1_va_base + TIMER_CTRL);
+	writel(0, osc_timer0_va_base + TIMER_CTRL);
+	writel(0, osc_timer1_va_base + TIMER_CTRL);

Shouldn't this be done within the timer driver itself?

Quoted 1 line

+++ b/arch/arm/mach-socfpga/dw_apb_timer.c

The clocksource/clockevents driver now go into drivers/clocksource/, and the corresponding maintainers should be CC'ed (Thomas Gleixner and John Stultz.

Quoted 3 lines

The clocksource/clockevents driver now go into drivers/clocksource/, and the corresponding maintainers should be CC'ed (Thomas Gleixner and John Stultz.

Hmm, fortunately drivers/clocksource already has one such driver. Maybe arch/arm/mach-picoxcell/time.c can be used as a template?

From: Dinh Nguyen <[email protected]>

Adding core definitions for Altera's SOCFPGA ARM platform.

Signed-off-by Dinh Nguyen <[email protected]>

Reviewed-by Pavel Machek <[email protected]>

---
 MAINTAINERS                                        |    5 +
 arch/arm/Kconfig                                   |   19 ++
 arch/arm/Makefile                                  |    1 +
 arch/arm/mach-socfpga/Kconfig                      |   21 ++
 arch/arm/mach-socfpga/Makefile                     |    8 +
 arch/arm/mach-socfpga/Makefile.boot                |    3 +
 arch/arm/mach-socfpga/clock.c                      |   50 ++++
 arch/arm/mach-socfpga/common.c                     |  156 ++++++++++
 arch/arm/mach-socfpga/common.h                     |   38 +++
 arch/arm/mach-socfpga/dw_apb_timer.c               |  164 +++++++++++
 arch/arm/mach-socfpga/headsmp.S                    |   41 +++
 arch/arm/mach-socfpga/hotplug.c                    |  125 ++++++++
 arch/arm/mach-socfpga/include/mach/clock.h         |   11 +
 arch/arm/mach-socfpga/include/mach/debug-macro.S   |   29 ++
 arch/arm/mach-socfpga/include/mach/dw_apb_timer.h  |   38 +++
 arch/arm/mach-socfpga/include/mach/io.h            |   27 ++
 arch/arm/mach-socfpga/include/mach/iomap.h         |   37 +++
 arch/arm/mach-socfpga/include/mach/irqs.h          |  305 ++++++++++++++++++++
 arch/arm/mach-socfpga/include/mach/memory.h        |   32 ++
 arch/arm/mach-socfpga/include/mach/smp.h           |   15 +
 arch/arm/mach-socfpga/include/mach/socfpga-timer.h |   27 ++
 arch/arm/mach-socfpga/include/mach/system.h        |   31 ++
 arch/arm/mach-socfpga/include/mach/timex.h         |   19 ++
 arch/arm/mach-socfpga/include/mach/uncompress.h    |   44 +++
 arch/arm/mach-socfpga/localtimer.c                 |   34 +++
 arch/arm/mach-socfpga/platsmp.c                    |  154 ++++++++++
 arch/arm/mm/Kconfig                                |    2 +-
 27 files changed, 1435 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-socfpga/Kconfig
 create mode 100644 arch/arm/mach-socfpga/Makefile
 create mode 100644 arch/arm/mach-socfpga/Makefile.boot
 create mode 100644 arch/arm/mach-socfpga/clock.c
 create mode 100644 arch/arm/mach-socfpga/common.c
 create mode 100644 arch/arm/mach-socfpga/common.h
 create mode 100644 arch/arm/mach-socfpga/dw_apb_timer.c
 create mode 100644 arch/arm/mach-socfpga/headsmp.S
 create mode 100644 arch/arm/mach-socfpga/hotplug.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-socfpga/include/mach/dw_apb_timer.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/io.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/iomap.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/irqs.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/memory.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/smp.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/socfpga-timer.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/system.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/timex.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-socfpga/localtimer.c
 create mode 100644 arch/arm/mach-socfpga/platsmp.c

MAINTAINERS +5 -0

index eb22272..193b4e4 100644
@@ -1103,6 +1103,11 @@ S:	Supported
 F:	arch/arm/mach-shmobile/
 F:	drivers/sh/
 
+ARM/SOCFPGA ARCHITECTURE
+M:	Dinh Nguyen <[email protected]>
+S:	Supported
+F:	arch/arm/mach-socfpga/
+
 ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
 M:	Lennert Buytenhek <[email protected]>
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)

arch/arm/Kconfig +3 -0

index a91009c..b1578e1 100644
@@ -250,6 +250,22 @@ choice
 	prompt "ARM system type"
 	default ARCH_VERSATILE
 
+config ARCH_SOCFPGA
+	bool "Altera SOCFPGA family"
+	select CPU_V7

arch/arm/Kconfig +5 -0

+	help
+	  This enables support for Altera SOCFPGA Cyclone V platform
+
 config ARCH_INTEGRATOR
 	bool "ARM Ltd. Integrator family"
 	select ARM_AMBA

@@ -1056,6 +1072,8 @@ source "arch/arm/mach-sa1100/Kconfig"
 source "arch/arm/plat-samsung/Kconfig"
 source "arch/arm/plat-s3c24xx/Kconfig"
 
+source "arch/arm/mach-socfpga/Kconfig"
+
 source "arch/arm/plat-spear/Kconfig"
 
 source "arch/arm/mach-s3c24xx/Kconfig"

arch/arm/Kconfig +0 -0

 	default 100
 
 config THUMB2_KERNEL

arch/arm/Makefile +1 -0

index 0298b00..1fe5702 100644
@@ -193,6 +193,7 @@ machine-$(CONFIG_MACH_SPEAR310)		:= spear3xx
 machine-$(CONFIG_MACH_SPEAR320)		:= spear3xx
 machine-$(CONFIG_MACH_SPEAR600)		:= spear6xx
 machine-$(CONFIG_ARCH_ZYNQ)		:= zynq
+machine-$(CONFIG_ARCH_SOCFPGA) 	:= socfpga
 
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.

arch/arm/mach-socfpga/Kconfig new file +21 -0

new file mode 100644
index 0000000..3fbbd0a
@@ -0,0 +1,21 @@
+choice
+	prompt "Altera SOCFPGA Platform"
+	default MACH_SOCFPGA_CYCLONE5
+	depends on ARCH_SOCFPGA
+	help
+		Select SOCFPGA platform type
+
+config MACH_SOCFPGA_CYCLONE5
+	bool "SOCFPGA Cyclone5 platform"
+	select HAVE_SMP
+	select PLAT_SOCFPGA_ETH
+	help
+	  Include support for the Altera(R) Cyclone5 development platform.
+endchoice
+
+config SOCFPGA_TIMER_HZ
+	int "Kernel internal timer frequency "
+	range 20 1024
+	default "100"
+	help
+	  Kernel internal timer frequency should be a divisor of 77161.

arch/arm/mach-socfpga/Makefile new file +8 -0

new file mode 100644
index 0000000..5502add
@@ -0,0 +1,8 @@
+#
+# Makefile for the linux kernel.
+#
+
+obj-y					:= common.o clock.o dw_apb_timer.o
+obj-$(CONFIG_MACH_SOCFPGA_CYCLONE5)	+= socfpga_cyclone5.o
+obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
\ No newline at end of file

arch/arm/mach-socfpga/Makefile.boot new file +3 -0

new file mode 100644
index 0000000..7a1f3c0
@@ -0,0 +1,3 @@
+zreladdr-y	:= 0x00008000
+params_phys-y	:= 0x00000100
+initrd_phys-y	:= 0x00800000

arch/arm/mach-socfpga/clock.c new file +50 -0

new file mode 100644
index 0000000..b5a82cd
@@ -0,0 +1,50 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2004 ARM Limited.
+ *  Written by Deep Blue Solutions Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <mach/clkdev.h>
+
+int clk_enable(struct clk *clk)
+{
+	return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	long ret = -EIO;
+	if (clk->ops && clk->ops->round)
+		ret = clk->ops->round(clk, rate);
+	return ret;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	int ret = -EIO;
+	if (clk->ops && clk->ops->set)
+		ret = clk->ops->set(clk, rate);
+	return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);

arch/arm/mach-socfpga/common.c new file +156 -0

new file mode 100644
index 0000000..a2c734a
@@ -0,0 +1,156 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <linux/gfp.h>
+#include <linux/of_platform.h>
+
+#include <mach/iomap.h>
+#include <mach/socfpga_cyclone5.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <asm/hardware/arm_timer.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/map.h>
+
+#include <mach/irqs.h>
+#include <mach/socfpga-timer.h>
+
+#include <linux/mmc/dw_mmc.h>
+#include <linux/serial_8250.h>
+
+#include "common.h"
+
+extern struct dw_mci_board sdmmc_platform_data;
+extern struct dma_pl330_platdata dma_platform_data;
+
+#define DW_APB_UART_OF_COMPATIBLE			"snps,dw-apb-uart"
+
+#define SOCFPGA_MPU_PERIHCLK_FREQ_HZ			(800000000 / 4)
+#define SOCFPGA_L4_MAIN_CLK					(400000000)
+
+static struct clk dummy_apb_pclk;
+static struct clk dummy_i2c_clk = {
+	.rate   = 100000000,
+};
+static struct clk dummy_spim_clk = {
+	.rate   = 100000000,
+};
+static struct clk mpu_periphclk = {
+	.rate   = SOCFPGA_MPU_PERIHCLK_FREQ_HZ,
+};
+
+static struct clk l4_main_clk = {
+	.rate   = SOCFPGA_L4_MAIN_CLK,
+};
+
+static struct clk_lookup lookups[] = {
+	{	/* Bus clock */
+		.con_id		= "apb_pclk",
+		.clk		= &dummy_apb_pclk,
+	},
+	{
+		.dev_id		= "ffc04000.i2c",
+		.clk		= &dummy_i2c_clk,
+	},
+	{
+		.dev_id		= "ffc05000.i2c",
+		.clk		= &dummy_i2c_clk,
+	},
+	{
+		.dev_id		= "dw-spi-mmio.0",
+		.clk		= &dummy_spim_clk,
+	},
+	{
+		.dev_id		= "dw-spi-mmio.1",
+		.clk		= &dummy_spim_clk,
+	},
+	{
+		.dev_id		= "smp_twd",
+		.clk		= &mpu_periphclk,
+	},
+	{
+		.dev_id		= "dma-pl330",
+		.clk		= &l4_main_clk,
+	}
+};
+
+struct plat_serial8250_port uart_platform_data[] = {
+		{
+		.type		= PORT_16850,
+		.flags 		= UPF_BOOT_AUTOCONF | UPF_IOREMAP | \
+				  UPF_FIXED_TYPE,
+		},
+};
+
+void __init socfpga_init_early(void)
+{
+	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+}
+
+/*
+ * Where is the timer (VA)?
+ */
+void __iomem *sp_timer0_va_base;
+void __iomem *sp_timer1_va_base;
+void __iomem *osc_timer0_va_base;
+void __iomem *osc_timer1_va_base;
+
+/*
+ * Set up the clock source and clock events devices
+ */
+
+void __init socfpga_timer_init(void __iomem *src_timer_base,
+				void __iomem *event_timer_base,
+				unsigned int event_timer_irq)
+{
+	/*
+	 * Initialise to a known state (all timers off)
+	 */
+	writel(0, sp_timer0_va_base + TIMER_CTRL);
+	writel(0, sp_timer1_va_base + TIMER_CTRL);
+	writel(0, osc_timer0_va_base + TIMER_CTRL);
+	writel(0, osc_timer1_va_base + TIMER_CTRL);
+
+	dwapbt_clocksource_init(src_timer_base);
+	dwapbt_clockevents_init(event_timer_base, event_timer_irq);
+}
+
+/*
+ * Setup the memory banks.
+ */
+void socfpga_fixup(struct tag *tags, char **from, struct meminfo *meminfo)
+{
+	meminfo->bank[0].start = 0x0;
+	meminfo->bank[0].size = SZ_256M;
+	meminfo->nr_banks = 1;
+}
+
+int socfpga_notifier(struct device *device)
+{
+	struct device_node *dn = device->of_node;
+
+	if (of_device_is_compatible(dn, DW_APB_UART_OF_COMPATIBLE))
+		device->platform_data = &uart_platform_data;
+	return 0;
+}

arch/arm/mach-socfpga/common.h new file +38 -0

new file mode 100644
index 0000000..7cad4f1
@@ -0,0 +1,38 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ASM_ARCH_SOCFPGA_H
+#define __ASM_ARCH_SOCFPGA_H
+
+#include <asm/setup.h>
+
+struct machine_desc;
+
+extern void __iomem *sp_timer0_va_base;
+extern void __iomem *sp_timer1_va_base;
+extern void __iomem *osc_timer0_va_base;
+extern void __iomem *osc_timer1_va_base;
+
+extern void socfpga_init_early(void);
+extern void socfpga_fixup(struct tag *tags, char **from,
+				struct meminfo *meminfo);
+extern void socfpga_timer_init(void __iomem *src_timer_base,
+				void __iomem *event_timer_base,
+				unsigned int event_timer_irq);
+extern int socfpga_notifier(struct device *device);
+
+#endif

arch/arm/mach-socfpga/dw_apb_timer.c new file +164 -0

new file mode 100644
index 0000000..64c8d96
@@ -0,0 +1,164 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <mach/dw_apb_timer.h>
+#include <mach/socfpga-timer.h>
+#include <mach/iomap.h>
+#include <mach/clock.h>
+
+#define TIMER_SP_FREQ_KHZ	(SOCFPGA_SP_TIMER_FREQ_HZ / 1000)
+#define TIMER_OSC_FREQ_KHZ	(SOCFPGA_OSC_TIMER_FREQ_HZ / 1000)
+
+#define TIMER_RELOAD	(TIMER_OSC_FREQ_KHZ * 1000 / HZ)
+
+static void __iomem *clksrc_base;
+
+static cycle_t dwapbt_read(struct clocksource *cs)
+{
+	return ~readl(clksrc_base + TIMER_VALUE);
+}
+
+static struct clocksource clocksource_dwapbt = {
+	.name		= "SP Timer 0",
+	.rating		= 200,
+	.read		= dwapbt_read,
+	.mask		= CLOCKSOURCE_MASK(32),
+	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+void __init dwapbt_clocksource_init(void __iomem *base)
+{
+	struct clocksource *cs = &clocksource_dwapbt;
+
+	clksrc_base = base;
+
+	/* setup free-running clocksource */
+	writel(0, clksrc_base + TIMER_CTRL);
+	writel(~0, clksrc_base + TIMER_LOAD);
+	writel(TIMER_CTRL_INTMASK | TIMER_CTRL_ENABLE,
+		clksrc_base + TIMER_CTRL);
+
+	clocksource_register_khz(cs, TIMER_SP_FREQ_KHZ);
+}
+
+
+static void __iomem *clkevt_base;
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t dwapbt_timer_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = dev_id;
+
+	/* clear the interrupt */
+	readl(clkevt_base + TIMER_INT_CLEAR);
+
+	/* Ooppss... spurious interrupt */
+	if (unlikely(!evt->event_handler))
+		return IRQ_NONE;
+
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static void dwapbt_set_mode(enum clock_event_mode mode,
+	struct clock_event_device *evt)
+{
+	unsigned long ctrl = 0;
+
+	ctrl = readl(clkevt_base + TIMER_CTRL);
+
+	/* Reset control register and disable the timer */
+	writel(0, clkevt_base + TIMER_CTRL);
+
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		/* Program load register */
+		writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD);
+
+		ctrl |= TIMER_CTRL_ENABLE;
+		ctrl |= TIMER_CTRL_PERIODIC;
+		ctrl &= ~TIMER_CTRL_INTMASK;
+		writel(ctrl, clkevt_base + TIMER_CTRL);
+		break;
+
+	case CLOCK_EVT_MODE_ONESHOT:
+		/* period set, and timer enabled in 'next_event' hook */
+		ctrl &= ~TIMER_CTRL_PERIODIC;
+		ctrl &= ~TIMER_CTRL_INTMASK;
+		writel(ctrl, clkevt_base + TIMER_CTRL);
+		break;
+
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_SHUTDOWN:
+	default:
+		break;
+	}
+}
+
+static int dwapbt_set_next_event(unsigned long next,
+	struct clock_event_device *evt)
+{
+	unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
+
+	/* Disable timer */
+	writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
+
+	writel(next, clkevt_base + TIMER_LOAD);
+	writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
+
+	return 0;
+}
+
+static struct clock_event_device dwapbt_clockevent = {
+	.name		= "OSC Timer 0",
+	.shift		= 32,
+	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+	.set_mode	= dwapbt_set_mode,
+	.set_next_event	= dwapbt_set_next_event,
+	.rating		= 250,
+	.cpumask	= cpu_all_mask,
+};
+
+static struct irqaction dwapbt_timer_irq = {
+	.name		= "timer",
+	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+	.handler	= dwapbt_timer_interrupt,
+	.dev_id		= &dwapbt_clockevent,
+};
+
+void __init dwapbt_clockevents_init(void __iomem *base, unsigned int timer_irq)
+{
+	struct clock_event_device *evt = &dwapbt_clockevent;
+
+	clkevt_base = base;
+
+	evt->irq = timer_irq;
+	evt->mult = div_sc(TIMER_OSC_FREQ_KHZ, NSEC_PER_MSEC, evt->shift);
+	evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
+	evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
+
+	setup_irq(timer_irq, &dwapbt_timer_irq);
+	clockevents_register_device(evt);
+}

arch/arm/mach-socfpga/headsmp.S new file +41 -0

new file mode 100644
index 0000000..e432aec
@@ -0,0 +1,41 @@
+/*
+ *  Modified from: linux/arch/arm/plat-versatile/headsmp.S
+ *
+ *  Copyright (c) 2003 ARM Limited
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+	__INIT
+
+/*
+ * Entry point for secondary CPUs.
+ * This provides a "holding pen" into which all secondary cores are held
+ * until we're ready for them to initialise.
+ */
+ENTRY(socfpga_secondary_startup)
+	mrc	p15, 0, r0, c0, c0, 5
+	and	r0, r0, #15
+	adr	r4, 1f
+	ldmia	r4, {r5, r6}
+	sub	r4, r4, r5
+	add	r6, r6, r4
+pen:	ldr	r7, [r6]
+	cmp	r7, r0
+	bne	pen
+
+	/*
+	 * we've been released from the holding pen: secondary_stack
+	 * should now contain the SVC stack for this core
+	 */
+	b	secondary_startup
+
+	.align
+1:	.long	.
+	.long	pen_release
+ENDPROC(socfpga_secondary_startup)

arch/arm/mach-socfpga/hotplug.c new file +51 -0

new file mode 100644
index 0000000..f9fc9ff
@@ -0,0 +1,125 @@
+/*
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+#include <asm/cp15.h>
+#include <asm/smp_plat.h>
+
+extern int pen_release;
+
+static inline void cpu_enter_lowpower(void)
+{
+	unsigned int v;
+
+	flush_cache_all();
+	asm volatile(
+	"	mcr	p15, 0, %1, c7, c5, 0\n"
+	"	mcr	p15, 0, %1, c7, c10, 4\n"
+	/*
+	 * Turn off coherency
+	 */
+	"	mrc	p15, 0, %0, c1, c0, 1\n"
+	"	bic	%0, %0, #0x20\n"
+	"	mcr	p15, 0, %0, c1, c0, 1\n"
+	"	mrc	p15, 0, %0, c1, c0, 0\n"
+	"	bic	%0, %0, %2\n"
+	"	mcr	p15, 0, %0, c1, c0, 0\n"
+	  : "=&r" (v)
+	  : "r" (0), "Ir" (CR_C)
+	  : "cc");
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+	unsigned int v;
+
+	asm volatile("mrc	p15, 0, %0, c1, c0, 0\n"
+	"	orr	%0, %0, %1\n"
+	"	mcr	p15, 0, %0, c1, c0, 0\n"
+	"	mrc	p15, 0, %0, c1, c0, 1\n"
+	"	orr	%0, %0, #0x20\n"
+	"	mcr	p15, 0, %0, c1, c0, 1\n"
+	  : "=&r" (v)

arch/arm/mach-socfpga/hotplug.c new file +64 -0

+	 */
+	for (;;) {
+		/*
+		 * here's the WFI
+		 */
+		asm volatile(".word	0xe320f003\n"
+		    : : : "memory", "cc");
+
+		if (pen_release == cpu_logical_map(cpu)) {
+			/*
+			 * OK, proper wakeup, we're done
+			 */
+			break;
+		}
+
+		/*
+		 * Getting here, means that we have come out of WFI without
+		 * having been woken up - this shouldn't happen
+		 *
+		 * Just note it happening - when we're woken, we can report
+		 * its occurrence.
+		 */
+		(*spurious)++;
+	}
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+	return 1;
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+	int spurious = 0;
+
+	/*
+	 * we're ready for shutdown now, so do it
+	 */
+	cpu_enter_lowpower();
+	platform_do_lowpower(cpu, &spurious);
+
+	/*
+	 * bring this CPU back into the world of cache
+	 * coherency, and then restore interrupts
+	 */
+	cpu_leave_lowpower();
+
+	if (spurious)
+		pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+	/*
+	 * we don't allow CPU 0 to be shutdown (it is still too special
+	 * e.g. clock tick interrupts)
+	 */
+	return cpu == 0 ? -EPERM : 0;
+}

arch/arm/mach-socfpga/include/mach/clock.h new file +0 -0

new file mode 100644
index 0000000..5187064

arch/arm/mach-socfpga/include/mach/clock.h new file +2 -0

+
+#endif

arch/arm/mach-socfpga/include/mach/debug-macro.S new file +29 -0

new file mode 100644
index 0000000..d6283f5
@@ -0,0 +1,29 @@
+/*
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef DEBUG_LL_UART_OFFSET
+#define DEBUG_LL_UART_OFFSET	0x00002000
+#elif DEBUG_LL_UART_OFFSET != 0x00002000
+#warning "DEBUG_LL_UART_OFFSET already defined to a different value"
+#endif
+
+#ifndef DEBUG_LL_UART_OFFSET
+#error "Unknown SOCFPGA platform"
+#endif
+
+		.macro	addruart, rp, rv, tmp
+		mov	\rp, #DEBUG_LL_UART_OFFSET
+		orr	\rp, \rp, #0x00c00000
+		orr	\rv, \rp, #0xfe000000	@ virtual base
+		orr	\rp, \rp, #0xff000000	@ physical base
+		.endm
+
+#define UART_SHIFT	2
+
+#include <asm/hardware/debug-8250.S>

arch/arm/mach-socfpga/include/mach/dw_apb_timer.h new file +38 -0

new file mode 100644
index 0000000..3c58a56
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+#ifndef __ASM_ARM_HARDWARE_DW_APB_TIMER_H
+#define __ASM_ARM_HARDWARE_DW_APB_TIMER_H
+
+/* Individual timer register */
+#define TIMER_LOAD              0x00            /* Load value rw */
+#define TIMER_VALUE             0x04            /* Current value ro */
+#define TIMER_CTRL              0x08            /* Control register rw */
+#define TIMER_INT_CLEAR         0x0c            /* Interrupt clear ro */
+#define TIMER_INT_STAT          0x10            /* Interrupt status ro */
+
+/* Shared timer register */
+#define TIMERS_INT_STAT         0xa0            /* Masked interrupt status ro */
+#define TIMERS_INT_CLEAR        0xa4            /* Interrupt clear ro */
+#define TIMERS_INT_STAT_RAW     0xa8            /* Raw interrupt status ro */
+#define TIMERS_VERSION          0xac            /* Version */
+
+#define TIMER_CTRL_ENABLE	(1 << 0)        /* Timer Enable = 1 */
+#define TIMER_CTRL_PERIODIC	(1 << 1)        /* Periodic mode = 0 */
+#define TIMER_CTRL_INTMASK	(1 << 2)        /* Interrupt mask = 1 */
+
+#endif

arch/arm/mach-socfpga/include/mach/io.h new file +15 -0

new file mode 100644
index 0000000..ff150b0
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License

arch/arm/mach-socfpga/include/mach/io.h new file +2 -0

+
+#endif

arch/arm/mach-socfpga/include/mach/iomap.h new file +13 -0

new file mode 100644
index 0000000..656482d
@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *

arch/arm/mach-socfpga/include/mach/iomap.h new file +14 -0

+/*
+ * Statically mapped addresses:
+ *
+ * 10xx xxxx -> fbxx xxxx
+ * 1exx xxxx -> fdxx xxxx
+ * 1fxx xxxx -> fexx xxxx
+ */
+#define IO_ADDRESS(x)		(((x) & 0x03ffffff) + 0xfb000000)
+#else
+#define IO_ADDRESS(x)		(x)
+#endif
+#define __io_address(n)		IOMEM(IO_ADDRESS(n))
+
+#endif
\ No newline at end of file

arch/arm/mach-socfpga/include/mach/irqs.h new file +290 -0

new file mode 100644
index 0000000..65db73a
@@ -0,0 +1,305 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+#define IRQ_SOCFPGA_GIC_START	32
+#define IRQ_LOCALWDOG		30
+
+
+/*
+ * SOCFPGA interrupt sources
+ */
+#define IRQ_SOCFPGA_CPU0_PARITY	(IRQ_SOCFPGA_GIC_START + 0)		/* CPU0 parity */
+#define IRQ_SOCFPGA_CPU0_PARITY_BTAG	(IRQ_SOCFPGA_GIC_START + 1)		/* CPU0 parity BTAG		*/
+#define IRQ_SOCFPGA_CPU0_PARITY_GHB		(IRQ_SOCFPGA_GIC_START + 2)		/* CPU0 parity GHB		*/
+#define IRQ_SOCFPGA_CPU0_PARITY_ITAG	(IRQ_SOCFPGA_GIC_START + 3)		/* CPU0 parity ITAG		*/
+#define IRQ_SOCFPGA_CPU0_PARITY_IDATA	(IRQ_SOCFPGA_GIC_START + 4)		/* CPU0 parity IDATA	*/
+#define IRQ_SOCFPGA_CPU0_PARITY_TLB		(IRQ_SOCFPGA_GIC_START + 5)		/* CPU0 parity TLB		*/
+#define IRQ_SOCFPGA_CPU0_PARITY_DOUTER	(IRQ_SOCFPGA_GIC_START + 6)		/* CPU0 parity DOUTER	*/
+#define IRQ_SOCFPGA_CPU0_PARITY_DTAG	(IRQ_SOCFPGA_GIC_START + 7)		/* CPU0 parity DTAG		*/
+#define IRQ_SOCFPGA_CPU0_PARITY_DDATA	(IRQ_SOCFPGA_GIC_START + 8)		/* CPU0 parity DDATA	*/
+#define IRQ_SOCFPGA_CPU0_DEFLAGS0	(IRQ_SOCFPGA_GIC_START + 9)			/* CPU0 deflasg 0 */
+#define IRQ_SOCFPGA_CPU0_DEFLAGS1	(IRQ_SOCFPGA_GIC_START + 10)		/* CPU0 deflags 1 */
+#define IRQ_SOCFPGA_CPU0_DEFLAGS2	(IRQ_SOCFPGA_GIC_START + 11)		/* CPU0 deflags 2 */
+#define IRQ_SOCFPGA_CPU0_DEFLAGS3	(IRQ_SOCFPGA_GIC_START + 12)		/* CPU0 deflags 3 */
+#define IRQ_SOCFPGA_CPU0_DEFLAGS4	(IRQ_SOCFPGA_GIC_START + 13)		/* CPU0 deflags 4 */
+#define IRQ_SOCFPGA_CPU0_DEFLAGS5	(IRQ_SOCFPGA_GIC_START + 14)		/* CPU0 deflags 5 */
+#define IRQ_SOCFPGA_CPU0_DEFLAGS6	(IRQ_SOCFPGA_GIC_START + 15)		/* CPU0 deflags 6 */
+#define IRQ_SOCFPGA_CPU1_PARITY		(IRQ_SOCFPGA_GIC_START + 16)		/* CPU1 parity */
+#define IRQ_SOCFPGA_CPU1_PARITY_BTAG	(IRQ_SOCFPGA_GIC_START + 17)	/* CPU1 parity BTAG		*/
+#define IRQ_SOCFPGA_CPU1_PARITY_GHB		(IRQ_SOCFPGA_GIC_START + 18)	/* CPU1 parity GHB		*/
+#define IRQ_SOCFPGA_CPU1_PARITY_ITAG	(IRQ_SOCFPGA_GIC_START + 19)	/* CPU1 parity ITAG		*/
+#define IRQ_SOCFPGA_CPU1_PARITY_IDATA	(IRQ_SOCFPGA_GIC_START + 20)	/* CPU1 parity IDATA	*/
+#define IRQ_SOCFPGA_CPU1_PARITY_TLB		(IRQ_SOCFPGA_GIC_START + 21)	/* CPU1 parity TLB		*/
+#define IRQ_SOCFPGA_CPU1_PARITY_DOUTER	(IRQ_SOCFPGA_GIC_START + 22)	/* CPU1 parity DOUTER	*/
+#define IRQ_SOCFPGA_CPU1_PARITY_DTAG	(IRQ_SOCFPGA_GIC_START + 23)	/* CPU1 parity DTAG		*/
+#define IRQ_SOCFPGA_CPU1_PARITY_DDATA	(IRQ_SOCFPGA_GIC_START + 24)	/* CPU1 parity DDATA	*/
+#define IRQ_SOCFPGA_CPU1_DEFLAGS0	(IRQ_SOCFPGA_GIC_START + 25)		/* CPU1 deflags 0 */
+#define IRQ_SOCFPGA_CPU1_DEFLAGS1	(IRQ_SOCFPGA_GIC_START + 26)	/* CPU1 deflags 1 */
+#define IRQ_SOCFPGA_CPU1_DEFLAGS2	(IRQ_SOCFPGA_GIC_START + 27)	/* CPU1 deflags 2 */
+#define IRQ_SOCFPGA_CPU1_DEFLAGS3	(IRQ_SOCFPGA_GIC_START + 28)	/* CPU1 deflags 3 */
+#define IRQ_SOCFPGA_CPU1_DEFLAGS4	(IRQ_SOCFPGA_GIC_START + 29)	/* CPU1 deflags 4 */
+#define IRQ_SOCFPGA_CPU1_DEFLAGS5	(IRQ_SOCFPGA_GIC_START + 30)	/* CPU1 deflags 5 */
+#define IRQ_SOCFPGA_CPU1_DEFLAGS6	(IRQ_SOCFPGA_GIC_START + 31)	/* CPU1 deflags 6 */
+#define IRQ_SOCFPGA_SCU0_PARITY	(IRQ_SOCFPGA_GIC_START + 32)	/* SCU0 parity */
+#define IRQ_SOCFPGA_SCU1_PARITY	(IRQ_SOCFPGA_GIC_START + 33)	/* SCU1 parity */
+#define IRQ_SOCFPGA_SCU_EV_ABORT	(IRQ_SOCFPGA_GIC_START + 34)	/* SCU EV abort */
+#define IRQ_SOCFPGA_L2_ECC_WRITE	(IRQ_SOCFPGA_GIC_START + 35)	/* L2 ECC write */
+#define IRQ_SOCFPGA_L2_ECC_CERR	(IRQ_SOCFPGA_GIC_START + 36)	/* L2 ECC error corrected */
+#define IRQ_SOCFPGA_L2_ECC_UERR	(IRQ_SOCFPGA_GIC_START + 37)	/* L2 ECC error uncorrected */
+#define IRQ_SOCFPGA_L2		(IRQ_SOCFPGA_GIC_START + 38)	/* L2 combined interrupts */
+#define IRQ_SOCFPGA_DDR_ECC_ERR	(IRQ_SOCFPGA_GIC_START + 39)	/* DDR ECC error */
+#define IRQ_SOCFPGA_F2S_FPGA0 	(IRQ_SOCFPGA_GIC_START + 40) 	/* FPGA IRQ 0 */
+#define IRQ_SOCFPGA_F2S_FPGA1 	(IRQ_SOCFPGA_GIC_START + 41) 	/* FPGA IRQ 1 */
+#define IRQ_SOCFPGA_F2S_FPGA2 	(IRQ_SOCFPGA_GIC_START + 42) 	/* FPGA IRQ 2 */
+#define IRQ_SOCFPGA_F2S_FPGA3 	(IRQ_SOCFPGA_GIC_START + 43) 	/* FPGA IRQ 3 */
+#define IRQ_SOCFPGA_F2S_FPGA4 	(IRQ_SOCFPGA_GIC_START + 44) 	/* FPGA IRQ 4 */
+#define IRQ_SOCFPGA_F2S_FPGA5 	(IRQ_SOCFPGA_GIC_START + 45) 	/* FPGA IRQ 5 */
+#define IRQ_SOCFPGA_F2S_FPGA6 	(IRQ_SOCFPGA_GIC_START + 46) 	/* FPGA IRQ 6 */
+#define IRQ_SOCFPGA_F2S_FPGA7 	(IRQ_SOCFPGA_GIC_START + 47) 	/* FPGA IRQ 7 */
+#define IRQ_SOCFPGA_F2S_FPGA8 	(IRQ_SOCFPGA_GIC_START + 48) 	/* FPGA IRQ 8 */
+#define IRQ_SOCFPGA_F2S_FPGA9 	(IRQ_SOCFPGA_GIC_START + 49) 	/* FPGA IRQ 9 */
+#define IRQ_SOCFPGA_F2S_FPGA10 	(IRQ_SOCFPGA_GIC_START + 50) 	/* FPGA IRQ 10 */
+#define IRQ_SOCFPGA_F2S_FPGA11 	(IRQ_SOCFPGA_GIC_START + 51) 	/* FPGA IRQ 11 */
+#define IRQ_SOCFPGA_F2S_FPGA12 	(IRQ_SOCFPGA_GIC_START + 52) 	/* FPGA IRQ 12 */
+#define IRQ_SOCFPGA_F2S_FPGA13 	(IRQ_SOCFPGA_GIC_START + 53) 	/* FPGA IRQ 13 */
+#define IRQ_SOCFPGA_F2S_FPGA14 	(IRQ_SOCFPGA_GIC_START + 54) 	/* FPGA IRQ 14 */
+#define IRQ_SOCFPGA_F2S_FPGA15 	(IRQ_SOCFPGA_GIC_START + 55) 	/* FPGA IRQ 15 */
+#define IRQ_SOCFPGA_F2S_FPGA16 	(IRQ_SOCFPGA_GIC_START + 56) 	/* FPGA IRQ 16 */
+#define IRQ_SOCFPGA_F2S_FPGA17 	(IRQ_SOCFPGA_GIC_START + 57) 	/* FPGA IRQ 17 */
+#define IRQ_SOCFPGA_F2S_FPGA18 	(IRQ_SOCFPGA_GIC_START + 58) 	/* FPGA IRQ 18 */
+#define IRQ_SOCFPGA_F2S_FPGA19 	(IRQ_SOCFPGA_GIC_START + 59) 	/* FPGA IRQ 19 */
+#define IRQ_SOCFPGA_F2S_FPGA20 	(IRQ_SOCFPGA_GIC_START + 60) 	/* FPGA IRQ 20 */
+#define IRQ_SOCFPGA_F2S_FPGA21 	(IRQ_SOCFPGA_GIC_START + 61) 	/* FPGA IRQ 21 */
+#define IRQ_SOCFPGA_F2S_FPGA22 	(IRQ_SOCFPGA_GIC_START + 62) 	/* FPGA IRQ 22 */
+#define IRQ_SOCFPGA_F2S_FPGA23 	(IRQ_SOCFPGA_GIC_START + 63) 	/* FPGA IRQ 23 */
+#define IRQ_SOCFPGA_F2S_FPGA24 	(IRQ_SOCFPGA_GIC_START + 64) 	/* FPGA IRQ 24 */
+#define IRQ_SOCFPGA_F2S_FPGA25 	(IRQ_SOCFPGA_GIC_START + 65) 	/* FPGA IRQ 25 */
+#define IRQ_SOCFPGA_F2S_FPGA26 	(IRQ_SOCFPGA_GIC_START + 66) 	/* FPGA IRQ 26 */
+#define IRQ_SOCFPGA_F2S_FPGA27 	(IRQ_SOCFPGA_GIC_START + 67) 	/* FPGA IRQ 27 */
+#define IRQ_SOCFPGA_F2S_FPGA28 	(IRQ_SOCFPGA_GIC_START + 68) 	/* FPGA IRQ 28 */
+#define IRQ_SOCFPGA_F2S_FPGA29 	(IRQ_SOCFPGA_GIC_START + 69) 	/* FPGA IRQ 29 */
+#define IRQ_SOCFPGA_F2S_FPGA30 	(IRQ_SOCFPGA_GIC_START + 70) 	/* FPGA IRQ 30 */
+#define IRQ_SOCFPGA_F2S_FPGA31 	(IRQ_SOCFPGA_GIC_START + 71) 	/* FPGA IRQ 31 */
+#define IRQ_SOCFPGA_F2S_FPGA32 	(IRQ_SOCFPGA_GIC_START + 72) 	/* FPGA IRQ 32 */
+#define IRQ_SOCFPGA_F2S_FPGA33 	(IRQ_SOCFPGA_GIC_START + 73) 	/* FPGA IRQ 33 */
+#define IRQ_SOCFPGA_F2S_FPGA34 	(IRQ_SOCFPGA_GIC_START + 74) 	/* FPGA IRQ 34 */
+#define IRQ_SOCFPGA_F2S_FPGA35 	(IRQ_SOCFPGA_GIC_START + 75) 	/* FPGA IRQ 35 */
+#define IRQ_SOCFPGA_F2S_FPGA36 	(IRQ_SOCFPGA_GIC_START + 76) 	/* FPGA IRQ 36 */
+#define IRQ_SOCFPGA_F2S_FPGA37 	(IRQ_SOCFPGA_GIC_START + 77) 	/* FPGA IRQ 37 */
+#define IRQ_SOCFPGA_F2S_FPGA38 	(IRQ_SOCFPGA_GIC_START + 78) 	/* FPGA IRQ 38 */
+#define IRQ_SOCFPGA_F2S_FPGA39 	(IRQ_SOCFPGA_GIC_START + 79) 	/* FPGA IRQ 39 */
+#define IRQ_SOCFPGA_F2S_FPGA40 	(IRQ_SOCFPGA_GIC_START + 80) 	/* FPGA IRQ 40 */
+#define IRQ_SOCFPGA_F2S_FPGA41 	(IRQ_SOCFPGA_GIC_START + 81) 	/* FPGA IRQ 41 */
+#define IRQ_SOCFPGA_F2S_FPGA42 	(IRQ_SOCFPGA_GIC_START + 82) 	/* FPGA IRQ 42 */
+#define IRQ_SOCFPGA_F2S_FPGA43 	(IRQ_SOCFPGA_GIC_START + 83) 	/* FPGA IRQ 43 */
+#define IRQ_SOCFPGA_F2S_FPGA44 	(IRQ_SOCFPGA_GIC_START + 84) 	/* FPGA IRQ 44 */
+#define IRQ_SOCFPGA_F2S_FPGA45 	(IRQ_SOCFPGA_GIC_START + 85) 	/* FPGA IRQ 45 */
+#define IRQ_SOCFPGA_F2S_FPGA46 	(IRQ_SOCFPGA_GIC_START + 86) 	/* FPGA IRQ 46 */
+#define IRQ_SOCFPGA_F2S_FPGA47 	(IRQ_SOCFPGA_GIC_START + 87) 	/* FPGA IRQ 47 */
+#define IRQ_SOCFPGA_F2S_FPGA48 	(IRQ_SOCFPGA_GIC_START + 88) 	/* FPGA IRQ 48 */
+#define IRQ_SOCFPGA_F2S_FPGA49 	(IRQ_SOCFPGA_GIC_START + 89) 	/* FPGA IRQ 49 */
+#define IRQ_SOCFPGA_F2S_FPGA50 	(IRQ_SOCFPGA_GIC_START + 90) 	/* FPGA IRQ 50 */
+#define IRQ_SOCFPGA_F2S_FPGA51 	(IRQ_SOCFPGA_GIC_START + 91) 	/* FPGA IRQ 51 */
+#define IRQ_SOCFPGA_F2S_FPGA52 	(IRQ_SOCFPGA_GIC_START + 92) 	/* FPGA IRQ 52 */
+#define IRQ_SOCFPGA_F2S_FPGA53 	(IRQ_SOCFPGA_GIC_START + 93) 	/* FPGA IRQ 53 */
+#define IRQ_SOCFPGA_F2S_FPGA54 	(IRQ_SOCFPGA_GIC_START + 94) 	/* FPGA IRQ 54 */
+#define IRQ_SOCFPGA_F2S_FPGA55 	(IRQ_SOCFPGA_GIC_START + 95) 	/* FPGA IRQ 55 */
+#define IRQ_SOCFPGA_F2S_FPGA56 	(IRQ_SOCFPGA_GIC_START + 96) 	/* FPGA IRQ 56 */
+#define IRQ_SOCFPGA_F2S_FPGA57 	(IRQ_SOCFPGA_GIC_START + 97) 	/* FPGA IRQ 57 */
+#define IRQ_SOCFPGA_F2S_FPGA58 	(IRQ_SOCFPGA_GIC_START + 98) 	/* FPGA IRQ 58 */
+#define IRQ_SOCFPGA_F2S_FPGA59 	(IRQ_SOCFPGA_GIC_START + 99) 	/* FPGA IRQ 59 */
+#define IRQ_SOCFPGA_F2S_FPGA60 	(IRQ_SOCFPGA_GIC_START + 100)	/* FPGA IRQ 60 */
+#define IRQ_SOCFPGA_F2S_FPGA61 	(IRQ_SOCFPGA_GIC_START + 101)	/* FPGA IRQ 61 */
+#define IRQ_SOCFPGA_F2S_FPGA62 	(IRQ_SOCFPGA_GIC_START + 102)	/* FPGA IRQ 62 */
+#define IRQ_SOCFPGA_F2S_FPGA63 	(IRQ_SOCFPGA_GIC_START + 103)	/* FPGA IRQ 63 */
+#define IRQ_SOCFPGA_DMA0		(IRQ_SOCFPGA_GIC_START + 104)	/* DMA Channel 0 */
+#define IRQ_SOCFPGA_DMA1		(IRQ_SOCFPGA_GIC_START + 105)	/* DMA Channel 1 */
+#define IRQ_SOCFPGA_DMA2		(IRQ_SOCFPGA_GIC_START + 106)	/* DMA Channel 2 */
+#define IRQ_SOCFPGA_DMA3		(IRQ_SOCFPGA_GIC_START + 107)	/* DMA Channel 3 */
+#define IRQ_SOCFPGA_DMA4		(IRQ_SOCFPGA_GIC_START + 108)	/* DMA Channel 3 */
+#define IRQ_SOCFPGA_DMA5		(IRQ_SOCFPGA_GIC_START + 109)	/* DMA Channel 5 */
+#define IRQ_SOCFPGA_DMA6		(IRQ_SOCFPGA_GIC_START + 110)	/* DMA Channel 6 */
+#define IRQ_SOCFPGA_DMA7		(IRQ_SOCFPGA_GIC_START + 111)	/* DMA Channel 7 */
+#define IRQ_SOCFPGA_DMA_ABORT	(IRQ_SOCFPGA_GIC_START + 112)	/* DMA abort */
+#define IRQ_SOCFPGA_DMA_CECC	(IRQ_SOCFPGA_GIC_START + 113)	/* DMA ECC corrected */
+#define IRQ_SOCFPGA_DMA_UECC	(IRQ_SOCFPGA_GIC_START + 114)	/* DMA ECC uncorrected */
+#define IRQ_SOCFPGA_EMAC0		(IRQ_SOCFPGA_GIC_START + 115)	/* Gb-Ethernet MAC0 */
+#define IRQ_SOCFPGA_EMAC0_TX_CECC	(IRQ_SOCFPGA_GIC_START + 116)	/* Gb-Ethernet MAC0 ECC corrected */
+#define IRQ_SOCFPGA_EMAC0_TX_UECC	(IRQ_SOCFPGA_GIC_START + 117)	/* Gb-Ethernet MAC0 ECC uncorrected */
+#define IRQ_SOCFPGA_EMAC0_RX_CECC	(IRQ_SOCFPGA_GIC_START + 118)	/* Gb-Ethernet MAC0 ECC corrected */
+#define IRQ_SOCFPGA_EMAC0_RX_UECC	(IRQ_SOCFPGA_GIC_START + 119)	/* Gb-Ethernet MAC0 ECC uncorrected */
+#define IRQ_SOCFPGA_EMAC1		(IRQ_SOCFPGA_GIC_START + 120)	/* Gb-Ethernet MAC1 */
+#define IRQ_SOCFPGA_EMAC1_TX_CECC	(IRQ_SOCFPGA_GIC_START + 121)	/* Gb-Ethernet MAC1 ECC corrected */
+#define IRQ_SOCFPGA_EMAC1_TX_UECC	(IRQ_SOCFPGA_GIC_START + 122)	/* Gb-Ethernet MAC1 ECC uncorrected */
+#define IRQ_SOCFPGA_EMAC1_RX_CECC	(IRQ_SOCFPGA_GIC_START + 123)	/* Gb-Ethernet MAC1 ECC corrected */
+#define IRQ_SOCFPGA_EMAC1_RX_UECC	(IRQ_SOCFPGA_GIC_START + 124)	/* Gb-Ethernet MAC1 ECC uncorrected */
+#define IRQ_SOCFPGA_USB0		(IRQ_SOCFPGA_GIC_START + 125)	/* USB 0 generic */
+#define IRQ_SOCFPGA_USB0_CECC	(IRQ_SOCFPGA_GIC_START + 126)	/* USB 0 ECC corrected */
+#define IRQ_SOCFPGA_USB0_UECC	(IRQ_SOCFPGA_GIC_START + 127)	/* USB 0 ECC uncorrected */
+#define IRQ_SOCFPGA_USB1		(IRQ_SOCFPGA_GIC_START + 128)	/* USB 1 generic */
+#define IRQ_SOCFPGA_USB1_CECC	(IRQ_SOCFPGA_GIC_START + 129)	/* USB 1 ECC corrected */
+#define IRQ_SOCFPGA_USB1_UECC	(IRQ_SOCFPGA_GIC_START + 130)	/* USB 1 ECC uncorrected */
+#define IRQ_SOCFPGA_CAN0_STS	(IRQ_SOCFPGA_GIC_START + 131)	/* CAN0 interrupt 0 */
+#define IRQ_SOCFPGA_CAN0_MO		(IRQ_SOCFPGA_GIC_START + 132)	/* CAN0 interrupt 1 */
+#define IRQ_SOCFPGA_CAN0_CECC	(IRQ_SOCFPGA_GIC_START + 133)	/* CAN0 ECC corrected */
+#define IRQ_SOCFPGA_CAN0_UECC	(IRQ_SOCFPGA_GIC_START + 134)	/* CAN0 ECC uncorrected */
+#define IRQ_SOCFPGA_CAN1_STS	(IRQ_SOCFPGA_GIC_START + 135)	/* CAN1 interrupt 0 */
+#define IRQ_SOCFPGA_CAN1_MO		(IRQ_SOCFPGA_GIC_START + 136)	/* CAN1 interrupt 1 */
+#define IRQ_SOCFPGA_CAN1_CECC	(IRQ_SOCFPGA_GIC_START + 137)	/* CAN1 ECC corrected */
+#define IRQ_SOCFPGA_CAN1_UECC	(IRQ_SOCFPGA_GIC_START + 138)	/* CAN1 ECC uncorrected */
+#define IRQ_SOCFPGA_SDMMC		(IRQ_SOCFPGA_GIC_START + 139)	/* SD/MMC */
+#define IRQ_SOCFPGA_SDMMC_PA_CECC	(IRQ_SOCFPGA_GIC_START + 140)	/* SD/MMC PortA ECC corrected */
+#define IRQ_SOCFPGA_SDMMC_PA_UECC	(IRQ_SOCFPGA_GIC_START + 141)	/* SD/MMC PortA ECC uncorrected */
+#define IRQ_SOCFPGA_SDMMC_PB_CECC	(IRQ_SOCFPGA_GIC_START + 142)	/* SD/MMC PortB ECC corrected */
+#define IRQ_SOCFPGA_SDMMC_PB_UECC	(IRQ_SOCFPGA_GIC_START + 143)	/* SD/MMC PortB ECC uncorrected */
+#define IRQ_SOCFPGA_NAND		(IRQ_SOCFPGA_GIC_START + 144)	/* NAND */
+#define IRQ_SOCFPGA_NAND_R_CECC	(IRQ_SOCFPGA_GIC_START + 145)	/* NAND read ECC corrected */
+#define IRQ_SOCFPGA_NAND_R_UECC	(IRQ_SOCFPGA_GIC_START + 146)	/* NAND read ECC uncorrected */
+#define IRQ_SOCFPGA_NAND_W_CECC	(IRQ_SOCFPGA_GIC_START + 147)	/* NAND write ECC corrected */
+#define IRQ_SOCFPGA_NAND_W_UECC	(IRQ_SOCFPGA_GIC_START + 148)	/* NAND write ECC uncorrected */
+#define IRQ_SOCFPGA_NAND_E_CECC	(IRQ_SOCFPGA_GIC_START + 149)	/* NAND error ECC corrected */
+#define IRQ_SOCFPGA_NAND_E_UECC	(IRQ_SOCFPGA_GIC_START + 150)	/* NAND error ECC uncorrected */
+#define IRQ_SOCFPGA_QSPI		(IRQ_SOCFPGA_GIC_START + 151)	/* Quad-SPI */
+#define IRQ_SOCFPGA_QSPI_CECC	(IRQ_SOCFPGA_GIC_START + 152)	/* Quad-SPI ECC corrected */
+#define IRQ_SOCFPGA_QSPI_UECC	(IRQ_SOCFPGA_GIC_START + 153)	/* Quad-SPI ECC uncorrected */
+#define IRQ_SOCFPGA_SPI0		(IRQ_SOCFPGA_GIC_START + 154)	/* SPI 0 */
+#define IRQ_SOCFPGA_SPI1		(IRQ_SOCFPGA_GIC_START + 155)	/* SPI 1 */
+#define IRQ_SOCFPGA_SPI2		(IRQ_SOCFPGA_GIC_START + 156)	/* SPI 2 */
+#define IRQ_SOCFPGA_SPI3		(IRQ_SOCFPGA_GIC_START + 157)	/* SPI 3 */
+#define IRQ_SOCFPGA_I2C0		(IRQ_SOCFPGA_GIC_START + 158)	/* I2C 0 */
+#define IRQ_SOCFPGA_I2C1		(IRQ_SOCFPGA_GIC_START + 159)	/* I2C 1 */
+#define IRQ_SOCFPGA_I2C2		(IRQ_SOCFPGA_GIC_START + 160)	/* I2C 2 */
+#define IRQ_SOCFPGA_I2C3		(IRQ_SOCFPGA_GIC_START + 161)	/* I2C 3 */
+#define IRQ_SOCFPGA_UART0		(IRQ_SOCFPGA_GIC_START + 162)	/* UART 0 */
+#define IRQ_SOCFPGA_UART1		(IRQ_SOCFPGA_GIC_START + 163)	/* UART 1 */
+#define IRQ_SOCFPGA_GPIO0		(IRQ_SOCFPGA_GIC_START + 164)	/* GPIO 0 */
+#define IRQ_SOCFPGA_GPIO1		(IRQ_SOCFPGA_GIC_START + 165)	/* GPIO 1 */
+#define IRQ_SOCFPGA_GPIO2		(IRQ_SOCFPGA_GIC_START + 166)	/* GPIO 2 */
+#define IRQ_SOCFPGA_L4_SP_TIMER0	(IRQ_SOCFPGA_GIC_START + 167)	/* L4 SP timer 0 */
+#define IRQ_SOCFPGA_L4_SP_TIMER1	(IRQ_SOCFPGA_GIC_START + 168)	/* L4 SP timer 1 */
+#define IRQ_SOCFPGA_L4_OSC1_TIMER0	(IRQ_SOCFPGA_GIC_START + 169)	/* L4 OSC1 timer 0 */
+#define IRQ_SOCFPGA_L4_OSC1_TIMER1	(IRQ_SOCFPGA_GIC_START + 170)	/* L4 OSC1 timer 1 */
+#define IRQ_SOCFPGA_WD0		(IRQ_SOCFPGA_GIC_START + 171)	/* Watchdog timer 0 */
+#define IRQ_SOCFPGA_WD1		(IRQ_SOCFPGA_GIC_START + 172)	/* Watchdog timer 1 */
+#define IRQ_SOCFPGA_CLK_MAN		(IRQ_SOCFPGA_GIC_START + 173)	/* Clock manager */
+#define IRQ_SOCFPGA_MPU_WAKE	(IRQ_SOCFPGA_GIC_START + 174)	/* MPU wake */
+#define IRQ_SOCFPGA_FPGA_MON	(IRQ_SOCFPGA_GIC_START + 175)	/* FPGA monitor */
+#define IRQ_SOCFPGA_CPU0_CTI	(IRQ_SOCFPGA_GIC_START + 176)	/* Coresight CPU0 CTI */
+#define IRQ_SOCFPGA_CPU1_CTI	(IRQ_SOCFPGA_GIC_START + 177)	/* Coresight CPU1 CTI */
+#define IRQ_SOCFPGA_OCRAM_CECC	(IRQ_SOCFPGA_GIC_START + 178)	/* on-chip RAM ECC corrected */
+#define IRQ_SOCFPGA_OCRAM_UECC	(IRQ_SOCFPGA_GIC_START + 179)	/* on-chip RAM ECC uncorrected */
+
+/* Soft IRQ */
+#define SOFTIRQ_SOCFPGA_DMADEV 	(IRQ_SOCFPGA_GIC_START + 180)
+#define SOFTIRQ_SOCFPGA_GPIO_0_0	(IRQ_SOCFPGA_GIC_START + 181)
+#define SOFTIRQ_SOCFPGA_GPIO_0_1	(IRQ_SOCFPGA_GIC_START + 182)
+#define SOFTIRQ_SOCFPGA_GPIO_0_2	(IRQ_SOCFPGA_GIC_START + 183)
+#define SOFTIRQ_SOCFPGA_GPIO_0_3	(IRQ_SOCFPGA_GIC_START + 184)
+#define SOFTIRQ_SOCFPGA_GPIO_0_4	(IRQ_SOCFPGA_GIC_START + 185)
+#define SOFTIRQ_SOCFPGA_GPIO_0_5	(IRQ_SOCFPGA_GIC_START + 186)
+#define SOFTIRQ_SOCFPGA_GPIO_0_6	(IRQ_SOCFPGA_GIC_START + 187)
+#define SOFTIRQ_SOCFPGA_GPIO_0_7	(IRQ_SOCFPGA_GIC_START + 188)
+#define SOFTIRQ_SOCFPGA_GPIO_0_8	(IRQ_SOCFPGA_GIC_START + 189)
+#define SOFTIRQ_SOCFPGA_GPIO_0_9	(IRQ_SOCFPGA_GIC_START + 190)
+#define SOFTIRQ_SOCFPGA_GPIO_0_10	(IRQ_SOCFPGA_GIC_START + 191)
+#define SOFTIRQ_SOCFPGA_GPIO_0_11	(IRQ_SOCFPGA_GIC_START + 192)
+#define SOFTIRQ_SOCFPGA_GPIO_0_12	(IRQ_SOCFPGA_GIC_START + 193)
+#define SOFTIRQ_SOCFPGA_GPIO_0_13	(IRQ_SOCFPGA_GIC_START + 194)
+#define SOFTIRQ_SOCFPGA_GPIO_0_14	(IRQ_SOCFPGA_GIC_START + 195)
+#define SOFTIRQ_SOCFPGA_GPIO_0_15	(IRQ_SOCFPGA_GIC_START + 196)
+#define SOFTIRQ_SOCFPGA_GPIO_0_16	(IRQ_SOCFPGA_GIC_START + 197)
+#define SOFTIRQ_SOCFPGA_GPIO_0_17	(IRQ_SOCFPGA_GIC_START + 198)
+#define SOFTIRQ_SOCFPGA_GPIO_0_18	(IRQ_SOCFPGA_GIC_START + 199)
+#define SOFTIRQ_SOCFPGA_GPIO_0_19	(IRQ_SOCFPGA_GIC_START + 200)
+#define SOFTIRQ_SOCFPGA_GPIO_0_20	(IRQ_SOCFPGA_GIC_START + 201)
+#define SOFTIRQ_SOCFPGA_GPIO_0_21	(IRQ_SOCFPGA_GIC_START + 202)
+#define SOFTIRQ_SOCFPGA_GPIO_0_22	(IRQ_SOCFPGA_GIC_START + 203)
+#define SOFTIRQ_SOCFPGA_GPIO_0_23	(IRQ_SOCFPGA_GIC_START + 204)
+#define SOFTIRQ_SOCFPGA_GPIO_0_24	(IRQ_SOCFPGA_GIC_START + 205)
+#define SOFTIRQ_SOCFPGA_GPIO_0_25	(IRQ_SOCFPGA_GIC_START + 206)
+#define SOFTIRQ_SOCFPGA_GPIO_0_26	(IRQ_SOCFPGA_GIC_START + 207)
+#define SOFTIRQ_SOCFPGA_GPIO_0_27	(IRQ_SOCFPGA_GIC_START + 208)
+#define SOFTIRQ_SOCFPGA_GPIO_0_28	(IRQ_SOCFPGA_GIC_START + 209)
+#define SOFTIRQ_SOCFPGA_GPIO_0_29	(IRQ_SOCFPGA_GIC_START + 210)
+#define SOFTIRQ_SOCFPGA_GPIO_1_0	(IRQ_SOCFPGA_GIC_START + 211)
+#define SOFTIRQ_SOCFPGA_GPIO_1_1	(IRQ_SOCFPGA_GIC_START + 212)
+#define SOFTIRQ_SOCFPGA_GPIO_1_2	(IRQ_SOCFPGA_GIC_START + 213)
+#define SOFTIRQ_SOCFPGA_GPIO_1_3	(IRQ_SOCFPGA_GIC_START + 214)
+#define SOFTIRQ_SOCFPGA_GPIO_1_4	(IRQ_SOCFPGA_GIC_START + 215)
+#define SOFTIRQ_SOCFPGA_GPIO_1_5	(IRQ_SOCFPGA_GIC_START + 216)
+#define SOFTIRQ_SOCFPGA_GPIO_1_6	(IRQ_SOCFPGA_GIC_START + 217)
+#define SOFTIRQ_SOCFPGA_GPIO_1_7	(IRQ_SOCFPGA_GIC_START + 218)
+#define SOFTIRQ_SOCFPGA_GPIO_1_8	(IRQ_SOCFPGA_GIC_START + 219)
+#define SOFTIRQ_SOCFPGA_GPIO_1_9	(IRQ_SOCFPGA_GIC_START + 220)
+#define SOFTIRQ_SOCFPGA_GPIO_1_10	(IRQ_SOCFPGA_GIC_START + 221)
+#define SOFTIRQ_SOCFPGA_GPIO_1_11	(IRQ_SOCFPGA_GIC_START + 222)
+#define SOFTIRQ_SOCFPGA_GPIO_1_12	(IRQ_SOCFPGA_GIC_START + 223)
+#define SOFTIRQ_SOCFPGA_GPIO_1_13	(IRQ_SOCFPGA_GIC_START + 224)
+#define SOFTIRQ_SOCFPGA_GPIO_1_14	(IRQ_SOCFPGA_GIC_START + 225)
+#define SOFTIRQ_SOCFPGA_GPIO_1_15	(IRQ_SOCFPGA_GIC_START + 226)
+#define SOFTIRQ_SOCFPGA_GPIO_1_16	(IRQ_SOCFPGA_GIC_START + 227)
+#define SOFTIRQ_SOCFPGA_GPIO_1_17	(IRQ_SOCFPGA_GIC_START + 228)
+#define SOFTIRQ_SOCFPGA_GPIO_1_18	(IRQ_SOCFPGA_GIC_START + 229)
+#define SOFTIRQ_SOCFPGA_GPIO_1_19	(IRQ_SOCFPGA_GIC_START + 230)
+#define SOFTIRQ_SOCFPGA_GPIO_1_20	(IRQ_SOCFPGA_GIC_START + 231)
+#define SOFTIRQ_SOCFPGA_GPIO_1_21	(IRQ_SOCFPGA_GIC_START + 232)
+#define SOFTIRQ_SOCFPGA_GPIO_1_22	(IRQ_SOCFPGA_GIC_START + 233)
+#define SOFTIRQ_SOCFPGA_GPIO_1_23	(IRQ_SOCFPGA_GIC_START + 234)
+#define SOFTIRQ_SOCFPGA_GPIO_1_24	(IRQ_SOCFPGA_GIC_START + 235)
+#define SOFTIRQ_SOCFPGA_GPIO_1_25	(IRQ_SOCFPGA_GIC_START + 236)
+#define SOFTIRQ_SOCFPGA_GPIO_1_26	(IRQ_SOCFPGA_GIC_START + 237)
+#define SOFTIRQ_SOCFPGA_GPIO_1_27	(IRQ_SOCFPGA_GIC_START + 238)
+#define SOFTIRQ_SOCFPGA_GPIO_1_28	(IRQ_SOCFPGA_GIC_START + 239)
+#define SOFTIRQ_SOCFPGA_GPIO_1_29	(IRQ_SOCFPGA_GIC_START + 240)
+#define SOFTIRQ_SOCFPGA_GPIO_2_0	(IRQ_SOCFPGA_GIC_START + 241)
+#define SOFTIRQ_SOCFPGA_GPIO_2_1	(IRQ_SOCFPGA_GIC_START + 242)
+#define SOFTIRQ_SOCFPGA_GPIO_2_2	(IRQ_SOCFPGA_GIC_START + 243)
+#define SOFTIRQ_SOCFPGA_GPIO_2_3	(IRQ_SOCFPGA_GIC_START + 244)
+#define SOFTIRQ_SOCFPGA_GPIO_2_4	(IRQ_SOCFPGA_GIC_START + 245)
+#define SOFTIRQ_SOCFPGA_GPIO_2_5	(IRQ_SOCFPGA_GIC_START + 246)
+#define SOFTIRQ_SOCFPGA_GPIO_2_6	(IRQ_SOCFPGA_GIC_START + 247)
+#define SOFTIRQ_SOCFPGA_GPIO_2_7	(IRQ_SOCFPGA_GIC_START + 248)
+#define SOFTIRQ_SOCFPGA_GPIO_2_8	(IRQ_SOCFPGA_GIC_START + 249)
+#define SOFTIRQ_SOCFPGA_GPIO_2_9	(IRQ_SOCFPGA_GIC_START + 250)
+#define SOFTIRQ_SOCFPGA_GPIO_2_10	(IRQ_SOCFPGA_GIC_START + 251)
+#define SOFTIRQ_SOCFPGA_GPIO_2_11	(IRQ_SOCFPGA_GIC_START + 252)
+#define SOFTIRQ_SOCFPGA_GPIO_2_12	(IRQ_SOCFPGA_GIC_START + 253)
+#define SOFTIRQ_SOCFPGA_GPIO_2_13	(IRQ_SOCFPGA_GIC_START + 254)
+#define SOFTIRQ_SOCFPGA_GPIO_2_14	(IRQ_SOCFPGA_GIC_START + 255)
+#define SOFTIRQ_SOCFPGA_GPIO_2_15	(IRQ_SOCFPGA_GIC_START + 256)
+#define SOFTIRQ_SOCFPGA_GPIO_2_16	(IRQ_SOCFPGA_GIC_START + 257)
+#define SOFTIRQ_SOCFPGA_GPIO_2_17	(IRQ_SOCFPGA_GIC_START + 258)
+#define SOFTIRQ_SOCFPGA_GPIO_2_18	(IRQ_SOCFPGA_GIC_START + 259)
+#define SOFTIRQ_SOCFPGA_GPIO_2_19	(IRQ_SOCFPGA_GIC_START + 260)
+#define SOFTIRQ_SOCFPGA_GPIO_2_20	(IRQ_SOCFPGA_GIC_START + 261)

arch/arm/mach-socfpga/include/mach/irqs.h new file +4 -0

+
+#define MAX_GIC_NR		1
+
+#endif	/* __MACH_IRQS_H */

arch/arm/mach-socfpga/include/mach/memory.h new file +20 -0

new file mode 100644
index 0000000..88e0ae9
@@ -0,0 +1,32 @@
+/*
+ *
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+