arm: Add basic support for new Marvell Armada 370 and Armada XP SoC

From: Gregory Clement <[email protected]>

Timer 0 is used as free-running clocksource, while timer 1 is used as clock_event_device.

Signed-off-by Gregory CLEMENT <[email protected]>

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Lior Amsalem <[email protected]>

+++ b/arch/arm/mach-mvebu/include/mach/uncompress.h

arch/arm/mach-mvebu/include/mach/uncompress.h new file +9 -0

@@ -0,0 +1,43 @@
+/*
+ * Marvell Armada SoC kernel uncompression UART routines
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any

What physical address does this come out to? All Orion platforms have the serial port at the same place, 0xf1012000. If 370/XP is the same, i suggest dropping this #include, hard code the address, and we share the implementation for all SoCs.

If however, the ASIC engineers have decided to move it, we need some extra logic to handle different base addresses for Dove and 370/XP which should be supportable in one kernel binary.

OMAP has some logic to handle this kind of problems, see plat-omap/include/plat/uncompress.h. We can quite certainly overcome this problem somehow.

Quoted 3 lines

OMAP has some logic to handle this kind of problems, see plat-omap/include/plat/uncompress.h. We can quite certainly overcome this problem somehow.

That file says:

* Initialize the port based on the machine ID from the bootloader.

Which when using DT we don't have.

As you said, we can overcome this somehow. We just need to be aware there will be changes here.

It would also be nice if Marvell ASIC engineers didn't randomly move things around in the address space....

It would also be nice if Marvell ASIC engineers didn't randomly move things around in the address space....

Quoted 2 lines · Andrew Lunn

It would also be nice if Marvell ASIC engineers didn't randomly move things around in the address space....

They didn't. The _software_ engineers did.

Now it seems that all the u-Boot implementations for Orion/Kirkwood out there have always moved the window containing the serial ports from its default 0xd0000000 address to 0xf1000000. Why they did that I have no idea. And Linux simply took those remapped physical addresses as authoritative.

And whether or not Armada 370/XP still have this physical remap ability I don't know. And if it does, then why didn't it follow the same 0xf1000000 tradition as all the other mvebu targets before them I don't know either. Maybe this could be considered?

Quoted 6 lines

Now it seems that all the u-Boot implementations for Orion/Kirkwood out there have always moved the window containing the serial ports from its default 0xd0000000 address to 0xf1000000. Why they did that I have no idea. And Linux simply took those remapped physical addresses as authoritative.

Quoted 4 lines

And whether or not Armada 370/XP still have this physical remap ability I don't know. And if it does, then why didn't it follow the same 0xf1000000 tradition as all the other mvebu targets before them I don't know either. Maybe this could be considered?

Thomas, Gregory, could you look at this?

Are the uboot source open, or are you using a proprietary Marvell version?

When Arnd first proposed moving everything into one directory, i had a quick look at the memory map. The Orions have more than just the serial ports at the same address. If i remember correctly, I2C, SPI, PCIE0, USB0, XOR, and ETH0 are all at the same physical address. Unfortunately, they have different virtual addresses. So I played around unifying the virtual address map.

Doing this will allow some code simplification, header file simplification, and sharing of some .dtsi and DT across all Orion systems.

Its not something i want to do right now, but having 370/XP the same as Orion would be a step towards this.

Signed-off-by Gregory CLEMENT <[email protected]>

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Lior Amsalem <[email protected]>

---
 arch/arm/mach-mvebu/include/mach/debug-macro.S |   24 +++++++++++++
 arch/arm/mach-mvebu/include/mach/timex.h       |   13 +++++++
 arch/arm/mach-mvebu/include/mach/uncompress.h  |   43 ++++++++++++++++++++++++
 3 files changed, 80 insertions(+)
 create mode 100644 arch/arm/mach-mvebu/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-mvebu/include/mach/timex.h
 create mode 100644 arch/arm/mach-mvebu/include/mach/uncompress.h

arch/arm/mach-mvebu/include/mach/debug-macro.S new file +24 -0

new file mode 100644
index 0000000..2282576
@@ -0,0 +1,24 @@
+/*
+ * Early serial output macro for Marvell  SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory Clement <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <mach/armada-370-xp.h>
+
+	.macro	addruart, rp, rv, tmp
+	ldr	\rp, =ARMADA_370_XP_REGS_PHYS_BASE
+	ldr	\rv, =ARMADA_370_XP_REGS_VIRT_BASE
+	orr	\rp, \rp, #0x00012000
+	orr	\rv, \rv, #0x00012000
+	.endm
+
+#define UART_SHIFT	2
+#include <asm/hardware/debug-8250.S>

arch/arm/mach-mvebu/include/mach/timex.h new file +13 -0

new file mode 100644
index 0000000..ab324a3
@@ -0,0 +1,13 @@
+/*
+ * Marvell Armada SoC time definitions
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE		(100 * HZ)

arch/arm/mach-mvebu/include/mach/uncompress.h new file +43 -0

new file mode 100644
index 0000000..d6a100c
@@ -0,0 +1,43 @@
+/*
+ * Marvell Armada SoC kernel uncompression UART routines
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/armada-370-xp.h>
+
+#define UART_THR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\
+								+ 0x12000))
+#define UART_LSR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\
+								+ 0x12014))
+
+#define LSR_THRE	0x20
+
+static void putc(const char c)
+{
+	int i;
+
+	for (i = 0; i < 0x1000; i++) {
+		/* Transmit fifo not full? */
+		if (*UART_LSR & LSR_THRE)
+			break;
+	}
+
+	*UART_THR = c;
+}
+
+static void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()

Signature · 1 line

1.7.9.5

From: Gregory CLEMENT <[email protected]>

[ben.dooks at codethink.co.uk: fixup style error in system-controller] [ben.dooks at codethink.co.uk: check result of of_match_node()]

Signed-off-by Gregory CLEMENT <[email protected]>

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Lior Amsalem <[email protected]>

---
 arch/arm/mach-mvebu/Kconfig             |    7 +++
 arch/arm/mach-mvebu/Makefile            |    1 +
 arch/arm/mach-mvebu/Makefile.boot       |    1 +
 arch/arm/mach-mvebu/common.h            |   20 ++++++
 arch/arm/mach-mvebu/system-controller.c |  105 +++++++++++++++++++++++++++++++
 5 files changed, 134 insertions(+)
 create mode 100644 arch/arm/mach-mvebu/Kconfig
 create mode 100644 arch/arm/mach-mvebu/Makefile
 create mode 100644 arch/arm/mach-mvebu/Makefile.boot
 create mode 100644 arch/arm/mach-mvebu/common.h
 create mode 100644 arch/arm/mach-mvebu/system-controller.c

arch/arm/mach-mvebu/Kconfig new file +7 -0

new file mode 100644
index 0000000..72d39e5
@@ -0,0 +1,7 @@
+if ARCH_MVEBU
+
+menu "Marvell SOC with device tree"
+
+endmenu
+
+endif

arch/arm/mach-mvebu/Makefile new file +1 -0

new file mode 100644
index 0000000..7366ae7
@@ -0,0 +1 @@
+obj-y += system-controller.o

arch/arm/mach-mvebu/Makefile.boot new file +1 -0

new file mode 100644
index 0000000..b327175
@@ -0,0 +1 @@
+zreladdr-y := 0x00008000

arch/arm/mach-mvebu/common.h new file +20 -0

new file mode 100644
index 0000000..f0eaa21
@@ -0,0 +1,20 @@
+/*
+ * Core functions for Marvell System On Chip
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARCH_MVEBU_COMMON_H
+#define __ARCH_MVEBU_COMMON_H
+
+void mvebu_restart(char mode, const char *cmd);
+
+#endif

arch/arm/mach-mvebu/system-controller.c new file +105 -0

new file mode 100644
index 0000000..b8079df
@@ -0,0 +1,105 @@
+/*
+ * System controller support for Armada 370 and XP platforms.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * The Armada 370 and Armada XP SoCs both have a range of
+ * miscellaneous registers, that do not belong to a particular device,
+ * but rather provide system-level features. This basic
+ * system-controller driver provides a device tree binding for those
+ * registers, and implements utility functions offering various
+ * features related to those registers.
+ *
+ * For now, the feature set is limited to restarting the platform by a
+ * soft-reset, but it might be extended in the future.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+static void __iomem *system_controller_base;
+
+struct mvebu_system_controller {
+	u32 rstoutn_mask_offset;
+	u32 system_soft_reset_offset;
+
+	u32 rstoutn_mask_reset_out_en;
+	u32 system_soft_reset;
+};
+static struct mvebu_system_controller *mvebu_sc;
+
+const struct mvebu_system_controller armada_370_xp_system_controller = {
+	.rstoutn_mask_offset = 0x60,
+	.system_soft_reset_offset = 0x64,
+	.rstoutn_mask_reset_out_en = 0x1,
+	.system_soft_reset = 0x1,
+};
+
+const struct mvebu_system_controller orion_system_controller = {
+	.rstoutn_mask_offset = 0x108,
+	.system_soft_reset_offset = 0x10c,
+	.rstoutn_mask_reset_out_en = 0x4,
+	.system_soft_reset = 0x1,
+};
+
+static struct of_device_id of_system_controller_table[] = {
+	{
+		.compatible = "marvell,orion-system-controller",
+		.data = (void *) &orion_system_controller,
+	}, {
+		.compatible = "marvell,armada-370-xp-system-controller",
+		.data = (void *) &armada_370_xp_system_controller,
+	},
+	{ /* end of list */ },
+};
+
+void mvebu_restart(char mode, const char *cmd)
+{
+	if (!system_controller_base) {
+		pr_err("Cannot restart, system-controller not available: check the device tree\n");
+	} else {
+		/*
+		 * Enable soft reset to assert RSTOUTn.
+		 */
+		writel(mvebu_sc->rstoutn_mask_reset_out_en,
+			system_controller_base +
+			mvebu_sc->rstoutn_mask_offset);
+		/*
+		 * Assert soft reset.
+		 */
+		writel(mvebu_sc->system_soft_reset,
+			system_controller_base +
+			mvebu_sc->system_soft_reset_offset);
+	}
+
+	while (1)
+		;
+}
+
+static int __init mvebu_system_controller_init(void)
+{
+	struct device_node *np;
+
+	np = of_find_matching_node(NULL, of_system_controller_table);
+	if (np) {
+		const struct of_device_id *match =
+		    of_match_node(of_system_controller_table, np);
+		BUG_ON(!match);
+		system_controller_base = of_iomap(np, 0);
+		mvebu_sc = (struct mvebu_system_controller *)match->data;
+	}
+
+	return 0;
+}
+
+arch_initcall(mvebu_system_controller_init);

Signature · 1 line

1.7.9.5

[ben.dooks at codethink.co.uk: ensure error check on of_property_read_u32] [ben.dooks at codethink.co.uk: use mpic address instead of bus-unit's ] [ben.dooks at codethink.co.uk: BUG_ON() if the of_iomap() fails for mpic] [ben.dooks at codethink.co.uk: move mpic per-cpu register base ] [ben.dooks at codethink.co.uk: number fetch should use irqd_to_hwirq()]

Signed-off-by Gregory CLEMENT <[email protected]>

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Lior Amsalem <[email protected]>

Signed-off-by Ben Dooks <[email protected]>

---
 arch/arm/boot/dts/armada-370-db.dts              |   42 +++++++
 arch/arm/boot/dts/armada-370-xp.dtsi             |   68 +++++++++++
 arch/arm/boot/dts/armada-370.dtsi                |   35 ++++++
 arch/arm/boot/dts/armada-xp-db.dts               |   50 +++++++++
 arch/arm/boot/dts/armada-xp.dtsi                 |   55 +++++++++
 arch/arm/mach-mvebu/Kconfig                      |    9 ++
 arch/arm/mach-mvebu/Makefile                     |    1 +
 arch/arm/mach-mvebu/armada-370-xp.c              |   63 +++++++++++
 arch/arm/mach-mvebu/common.h                     |    3 +
 arch/arm/mach-mvebu/include/mach/armada-370-xp.h |   22 ++++
 arch/arm/mach-mvebu/irq-armada-370-xp.c          |  130 ++++++++++++++++++++++
 11 files changed, 478 insertions(+)

 create mode 100644 arch/arm/boot/dts/armada-370-db.dts
 create mode 100644 arch/arm/boot/dts/armada-370-xp.dtsi
 create mode 100644 arch/arm/boot/dts/armada-370.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-db.dts
 create mode 100644 arch/arm/boot/dts/armada-xp.dtsi
 create mode 100644 arch/arm/mach-mvebu/armada-370-xp.c
 create mode 100644 arch/arm/mach-mvebu/include/mach/armada-370-xp.h
 create mode 100644 arch/arm/mach-mvebu/irq-armada-370-xp.c

arch/arm/boot/dts/armada-370-db.dts new file +42 -0

new file mode 100644
index 0000000..fffd5c2
@@ -0,0 +1,42 @@
+/*
+ * Device Tree file for Marvell Armada 370 evaluation board
+ * (DB-88F6710-BP-DDR3)
+ *
+ *  Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "armada-370.dtsi"
+
+/ {
+	model = "Marvell Armada 370 Evaluation Board";
+	compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>; /* 512 MB */
+	};
+
+	soc {
+		serial at d0012000 {
+			clock-frequency = <200000000>;
+			status = "okay";
+		};
+		timer at d0020300 {
+			clock-frequency = <600000000>;
+			status = "okay";
+		};
+	};
+};

arch/arm/boot/dts/armada-370-xp.dtsi new file +68 -0

new file mode 100644
index 0000000..9b55f01
@@ -0,0 +1,68 @@
+/*
+ * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ * Ben Dooks <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file contains the definitions that are common to the Armada
+ * 370 and Armada XP SoC.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "Marvell Armada 370 and XP SoC";
+	compatible = "marvell,armada_370_xp";
+
+	cpus {
+		cpu at 0 {
+			compatible = "marvell,sheeva-v7";
+		};
+	};
+
+	mpic: interrupt-controller at d0020000 {
+	      compatible = "marvell,mpic";
+	      #interrupt-cells = <1>;
+	      #address-cells = <1>;
+	      #size-cells = <1>;
+	      interrupt-controller;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&mpic>;
+		ranges;
+
+		serial at d0012000 {
+				compatible = "ns16550";
+				reg = <0xd0012000 0x100>;
+				reg-shift = <2>;
+				interrupts = <41>;
+				status = "disabled";
+		};
+		serial at d0012100 {
+				compatible = "ns16550";
+				reg = <0xd0012100 0x100>;
+				reg-shift = <2>;
+				interrupts = <42>;
+				status = "disabled";
+		};
+
+		timer at d0020300 {
+			       compatible = "marvell,timer";
+			       reg = <0xd0020300 0x30>;
+			       interrupts = <37>, <38>, <39>, <40>;
+		};
+	};
+};
+

arch/arm/boot/dts/armada-370.dtsi new file +35 -0

new file mode 100644
index 0000000..3228ccc
@@ -0,0 +1,35 @@
+/*
+ * Device Tree Include file for Marvell Armada 370 family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada 370 SoC that are not
+ * common to all Armada SoCs.
+ */
+
+/include/ "armada-370-xp.dtsi"
+
+/ {
+	model = "Marvell Armada 370 family SoC";
+	compatible = "marvell,armada370", "marvell,armada-370-xp";
+
+	mpic: interrupt-controller at d0020000 {
+	      reg = <0xd0020a00 0x1d0>,
+		    <0xd0021870 0x58>;
+	};
+
+	soc {
+		system-controller at d0018200 {
+				compatible = "marvell,armada-370-xp-system-controller";
+				reg = <0xd0018200 0x100>;
+		};
+	};
+};

arch/arm/boot/dts/armada-xp-db.dts new file +50 -0

new file mode 100644
index 0000000..f97040d
@@ -0,0 +1,50 @@
+/*
+ * Device Tree file for Marvell Armada XP evaluation board
+ * (DB-78460-BP)
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP Evaluation Board";
+	compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000>; /* 2 GB */
+	};
+
+	soc {
+		serial at d0012000 {
+			clock-frequency = <250000000>;
+			status = "okay";
+		};
+		serial at d0012100 {
+			clock-frequency = <250000000>;
+			status = "okay";
+		};
+		serial at d0012200 {
+			clock-frequency = <250000000>;
+			status = "okay";
+		};
+		serial at d0012300 {
+			clock-frequency = <250000000>;
+			status = "okay";
+		};
+	};
+};

arch/arm/boot/dts/armada-xp.dtsi new file +55 -0

new file mode 100644
index 0000000..e1fa7e6
@@ -0,0 +1,55 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ * Ben Dooks <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada 370 SoC that are not
+ * common to all Armada SoCs.
+ */
+
+/include/ "armada-370-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP family SoC";
+	compatible = "marvell,armadaxp", "marvell,armada-370-xp";
+
+	mpic: interrupt-controller at d0020000 {
+	      reg = <0xd0020a00 0x1d0>,
+		    <0xd0021870 0x58>;
+	};
+
+	soc {
+		serial at d0012200 {
+				compatible = "ns16550";
+				reg = <0xd0012200 0x100>;
+				reg-shift = <2>;
+				interrupts = <43>;
+				status = "disabled";
+		};
+		serial at d0012300 {
+				compatible = "ns16550";
+				reg = <0xd0012300 0x100>;
+				reg-shift = <2>;
+				interrupts = <44>;
+				status = "disabled";
+		};
+
+		timer at d0020300 {
+				marvell,timer-25Mhz;
+		};
+
+		system-controller at d0018200 {
+				compatible = "marvell,armada-370-xp-system-controller";
+				reg = <0xd0018200 0x500>;
+		};
+	};
+};

arch/arm/mach-mvebu/Kconfig +9 -0

index 72d39e5..caa2c5e 100644
@@ -2,6 +2,15 @@ if ARCH_MVEBU
 
 menu "Marvell SOC with device tree"
 
+config MACH_ARMADA_370_XP
+	bool "Marvell Armada 370 and Aramada XP boards"
+	select ARMADA_370_XP_TIMER
+	select CPU_V7
+	help
+
+	  Say 'Y' here if you want your kernel to support boards based on
+	  Marvell Armada 370 or Armada XP with device tree.
+
 endmenu
 
 endif

arch/arm/mach-mvebu/Makefile +1 -0

index 7366ae7..e61d2b8 100644
@@ -1 +1,2 @@
 obj-y += system-controller.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o

arch/arm/mach-mvebu/armada-370-xp.c new file +63 -0

new file mode 100644
index 0000000..4ef923b
@@ -0,0 +1,63 @@
+/*
+ * Device Tree support for Armada 370 and XP platforms.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_platform.h>
+#include <linux/io.h>
+#include <linux/time-armada-370-xp.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <mach/armada-370-xp.h>
+#include "common.h"
+
+static struct map_desc armada_370_xp_io_desc[] __initdata = {
+	{
+		.virtual	= ARMADA_370_XP_REGS_VIRT_BASE,
+		.pfn		= __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
+		.length		= ARMADA_370_XP_REGS_SIZE,
+		.type		= MT_DEVICE,
+	},
+};
+
+void __init armada_370_xp_map_io(void)
+{
+	iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
+}
+
+struct sys_timer armada_370_xp_timer = {
+	.init		= armada_370_xp_timer_init,
+};
+
+static void __init armada_370_xp_dt_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char * const armada_370_xp_dt_board_dt_compat[] = {
+	"marvell,a370-db",
+	"marvell,axp-db",
+	NULL,
+};
+
+DT_MACHINE_START(ARMADA_XP_DT, "Marvell Aramada 370/XP (Device Tree)")
+	.init_machine	= armada_370_xp_dt_init,
+	.map_io		= armada_370_xp_map_io,
+	.init_irq	= armada_370_xp_init_irq,
+	.handle_irq     = armada_370_xp_handle_irq,
+	.timer		= &armada_370_xp_timer,
+	.restart	= mvebu_restart,
+	.dt_compat	= armada_370_xp_dt_board_dt_compat,
+MACHINE_END

arch/arm/mach-mvebu/common.h +3 -0

index f0eaa21..02f89ea 100644
@@ -17,4 +17,7 @@
 
 void mvebu_restart(char mode, const char *cmd);
 
+void armada_370_xp_init_irq(void);
+void armada_370_xp_handle_irq(struct pt_regs *regs);
+
 #endif

arch/arm/mach-mvebu/include/mach/armada-370-xp.h new file +22 -0

new file mode 100644
index 0000000..25f0ca8
@@ -0,0 +1,22 @@
+/*
+ * Generic definitions for Marvell Armada_370_XP SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_ARMADA_370_XP_H
+#define __MACH_ARMADA_370_XP_H
+
+#define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000
+#define ARMADA_370_XP_REGS_VIRT_BASE	0xfeb00000
+#define ARMADA_370_XP_REGS_SIZE		SZ_1M
+
+#endif /* __MACH_ARMADA_370_XP_H */

arch/arm/mach-mvebu/irq-armada-370-xp.c new file +130 -0

new file mode 100644
index 0000000..645a8d3
@@ -0,0 +1,130 @@
+/*
+ * Marvell Armada 370 and Armada XP SoC IRQ handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <[email protected]>
+ * Gregory CLEMENT <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ * Ben Dooks <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <asm/mach/arch.h>
+#include <asm/exception.h>
+
+/* Interrupt Controller Registers Map */
+#define ARMADA_370_XP_INT_SET_MASK_OFFS		(0x48)
+#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS	(0x4C)
+
+#define ARMADA_370_XP_INT_SET_ENABLE_OFFS	(0x30)
+#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS	(0x34)
+
+#define ARMADA_370_XP_CPU_INTACK_OFFS		(0x44)
+
+#define ARMADA_370_XP_NR_IRQS			(115)
+
+static void __iomem *per_cpu_int_base;
+static void __iomem *main_int_base;
+static struct irq_domain *armada_370_xp_mpic_domain;
+
+static void armada_370_xp_irq_mask(struct irq_data *d)
+{
+	writel(irqd_to_hwirq(d),
+	       per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
+}
+
+static void armada_370_xp_irq_unmask(struct irq_data *d)
+{
+	writel(irqd_to_hwirq(d),
+	       per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+}
+
+static struct irq_chip armada_370_xp_irq_chip = {
+	.name		= "armada_370_xp_irq",
+	.irq_mask       = armada_370_xp_irq_mask,
+	.irq_mask_ack   = armada_370_xp_irq_mask,
+	.irq_unmask     = armada_370_xp_irq_unmask,
+};
+
+static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
+				      unsigned int virq, irq_hw_number_t hw)
+{
+	armada_370_xp_irq_mask(irq_get_irq_data(virq));
+	writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
+
+	irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
+				 handle_level_irq);
+	irq_set_status_flags(virq, IRQ_LEVEL);
+	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+	return 0;
+}
+
+static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
+	.map = armada_370_xp_mpic_irq_map,
+	.xlate = irq_domain_xlate_onecell,
+};
+
+static int __init armada_370_xp_mpic_of_init(struct device_node *node,
+					     struct device_node *parent)
+{
+	main_int_base = of_iomap(node, 0);
+	per_cpu_int_base = of_iomap(node, 1);
+
+	BUG_ON(!main_int_base);
+	BUG_ON(!per_cpu_int_base);
+
+	armada_370_xp_mpic_domain =
+	    irq_domain_add_linear(node, ARMADA_370_XP_NR_IRQS,
+				  &armada_370_xp_mpic_irq_ops, NULL);
+
+	if (!armada_370_xp_mpic_domain)
+		panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
+
+	irq_set_default_host(armada_370_xp_mpic_domain);
+	return 0;
+}
+
+asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
+							       *regs)
+{
+	u32 irqstat, irqnr;
+
+	do {
+		irqstat = readl_relaxed(per_cpu_int_base +
+					ARMADA_370_XP_CPU_INTACK_OFFS);
+		irqnr = irqstat & 0x3FF;
+
+		if (irqnr < 1023) {
+			irqnr =
+			    irq_find_mapping(armada_370_xp_mpic_domain, irqnr);
+			handle_IRQ(irqnr, regs);
+			continue;
+		}
+
+		break;
+	} while (1);
+}
+
+static const struct of_device_id mpic_of_match[] __initconst = {
+	{.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init},
+	{},
+};
+
+void __init armada_370_xp_init_irq(void)
+{
+	of_irq_init(mpic_of_match);
+}

Signature · 1 line

1.7.9.5

From: Gregory CLEMENT <[email protected]>

Signed-off-by Gregory CLEMENT <[email protected]>

Signed-off-by Thomas Petazzoni <[email protected]>

Signed-off-by Lior Amsalem <[email protected]>

---
 arch/arm/Kconfig  |   14 ++++++++++++++
 arch/arm/Makefile |    1 +
 2 files changed, 15 insertions(+)

arch/arm/Kconfig +14 -0

index 8e02882..519b5e0 100644
@@ -533,6 +533,18 @@ config ARCH_IXP4XX
 	help
 	  Support for Intel's IXP4XX (XScale) family of processors.
 
+config ARCH_MVEBU
+	bool "Marvell SOCs with Device Tree support"
+	select GENERIC_CLOCKEVENTS
+	select MULTI_IRQ_HANDLER
+	select SPARSE_IRQ
+	select CLKSRC_MMIO
+	select GENERIC_IRQ_CHIP
+	select IRQ_DOMAIN
+	select COMMON_CLK
+	help
+	  Support for the Marvell SoC Family with device tree support
+
 config ARCH_DOVE
 	bool "Marvell Dove"
 	select CPU_V7

@@ -987,6 +999,8 @@ endchoice
 # Kconfigs may be included either alphabetically (according to the
 # plat- suffix) or along side the corresponding mach-* source.
 #
+source "arch/arm/mach-mvebu/Kconfig"
+
 source "arch/arm/mach-at91/Kconfig"
 
 source "arch/arm/mach-bcmring/Kconfig"

arch/arm/Makefile +1 -0

index 0298b00..f1a1a71 100644
@@ -157,6 +157,7 @@ machine-$(CONFIG_ARCH_MV78XX0)		:= mv78xx0
 machine-$(CONFIG_ARCH_IMX_V4_V5)	:= imx
 machine-$(CONFIG_ARCH_IMX_V6_V7)	:= imx
 machine-$(CONFIG_ARCH_MXS)		:= mxs
+machine-$(CONFIG_ARCH_MVEBU)		:= mvebu
 machine-$(CONFIG_ARCH_NETX)		:= netx
 machine-$(CONFIG_ARCH_NOMADIK)		:= nomadik
 machine-$(CONFIG_ARCH_OMAP1)		:= omap1

Signature · 1 line

1.7.9.5

Arnd, Olof,

You'll find in this patch set the seventh version of the initial support for a new family of ARMv7-compatible Marvell SoCs.

As for the previous releases, both the Armada 370 and the Armada XP SoCs are supported in this directory, and we are able to build a single kernel image that boots on both SoCs. Both SoCs use the PJ4B processor, a Marvell-developed ARM core that implements the ARMv7 instruction set. We are currently using Marvell evaluation boards for both of those SoCs, and the support for those boards is added in this patch set.

We remained focused on a limited preliminary support which only includes the necessary code for timer and IRQ support, the serial controller is a standard 16550-compatible one. The diffstat looks like:

-----Original Message-----
From: Thomas Petazzoni [mailto:thomas.petazzoni at free-electrons.com]
Sent: Monday, July 02, 2012 6:39 PM
To: Arnd Bergmann; Olof Johansson
Cc: Ben Dooks; Jason Cooper; Andrew Lunn; Nicolas Pitre; Lior Amsalem; Maen Suleiman; linux-arm-kernel at lists.infradead.org; Thomas Petazzoni; Gregory Clement; Jon Masters; David Marlin; Tawfik Bayouk; Shadi Ammouri; Eran Ben-Avi; Yehuda Yitschak; Nadav Haklai; Eric Miao
Subject: [PATCH v7] arm: Add basic support for new Marvell Armada 370 and Armada XP SoC

Arnd, Olof,

You'll find in this patch set the seventh version of the initial support for a new family of ARMv7-compatible Marvell SoCs.

As for the previous releases, both the Armada 370 and the Armada XP SoCs are supported in this directory, and we are able to build a single kernel image that boots on both SoCs. Both SoCs use the PJ4B processor, a Marvell- developed ARM core that implements the ARMv7 instruction set. We are currently using Marvell evaluation boards for both of those SoCs, and the support for those boards is added in this patch set.

Best regards,

Thomas Petazzoni

-----Original Message-----
From: Yehuda Yitschak
Sent: Wednesday, July 04, 2012 3:11 PM
To: Thomas Petazzoni; Arnd Bergmann; Olof Johansson
Cc: Ben Dooks; Jason Cooper; Andrew Lunn; Nicolas Pitre; Lior Amsalem; Maen Suleiman; linux-arm-kernel at lists.infradead.org; Gregory Clement; Jon Masters; David Marlin; Tawfik Bayouk; Shadi Ammouri; Eran Ben-Avi; Nadav Haklai; Eric Miao
Subject: RE: [PATCH v7] arm: Add basic support for new Marvell Armada 370 and Armada XP SoC

Quoted 9 lines

-----Original Message-----
From: Thomas Petazzoni [mailto:thomas.petazzoni at free-electrons.com]
Sent: Monday, July 02, 2012 6:39 PM
To: Arnd Bergmann; Olof Johansson
Cc: Ben Dooks; Jason Cooper; Andrew Lunn; Nicolas Pitre; Lior Amsalem; Maen Suleiman; linux-arm-kernel at lists.infradead.org; Thomas Petazzoni; Gregory Clement; Jon Masters; David Marlin; Tawfik Bayouk; Shadi Ammouri; Eran Ben-Avi; Yehuda Yitschak; Nadav Haklai; Eric Miao
Subject: [PATCH v7] arm: Add basic support for new Marvell Armada 370

and

Quoted 10 lines

Armada XP SoC

Arnd, Olof,

You'll find in this patch set the seventh version of the initial support for a new family of ARMv7-compatible Marvell SoCs.

As for the previous releases, both the Armada 370 and the Armada XP SoCs are supported in this directory, and we are able to build a single kernel image that boots on both SoCs. Both SoCs use the PJ4B processor, a

Marvell-

Quoted 4 lines

developed ARM core that implements the ARMv7 instruction set. We are currently using Marvell evaluation boards for both of those SoCs, and the support for those boards is added in this patch set.

Hi, tested by me on Armada XP board. So,

Tested-by Yehuda Yitschak <[email protected]>

[snip]

Quoted 4 lines

Best regards,

Thomas Petazzoni

Regards,
Yehuda Yitschak