spi: s3c64xx: add support for device tree

PATCH Superseded Thomas Abraham 3 participants 22 messages Jul 11, 2012 – Jul 15, 2012

Subsystems (6)

Device tree bindings Arm (32-bit) Arm sub-architectures SPI +2 more subsystems

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Thomas Abraham

author

2012-07-11 15:27 UTC #0 lore raw

v5 cover spi: s3c64xx: add support for device tree

Changes since v4:
- Includes the missing gpio request for slave select line gpio as suggested by Mark Brown.

Changes since v3:
- Fixed the build breakage after applying 3rd patch in this series (which had dependency on the 6th patch). This was reported by Doug Anderson.

Changes since v2:
- Removed renaming of platform device name at runtime
- Includes other minor fixes suggested by Olof, Grant, Kukjin and Abhilash.
- Rebased to Linux 3.5-rc1

Changes since v1:
- Incorporated changes suggested by Mark Brown
- Merged 2nd, 3rd and 5th patch into one single patch.
- Listed the order of gpios in the device tree support documentation.
- Switched to generic property names for chip select gpio line and number of slave select lines.
- Moved the platform enablement patches for Exynos4 and Exynos5 into a different patch series.
- Included Ack from Jaswinder Singh <[email protected]>.

This patch series adds device tree based discovery support for Samsung's s3c64xx compatible spi controller. This is mainly tested for Exynos4210 and Exynos5250 with onboard spi nor flash device.

The patch series (6 patches) that add board/platform specific support has no changes since the v2 version. This series is available at:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-May/100812.html

Thomas Abraham

author

2012-07-11 15:27 UTC #1 lore raw

PATCH v5 1/6 spi: s3c64xx: remove unused S3C64XX_SPI_ST_TRLCNTZ macro

The macro S3C64XX_SPI_ST_TRLCNTZ is not used and hence it is removed.

Signed-off-by Thomas Abraham <[email protected]>

Acked-by Jaswinder Singh <[email protected]>

Acked-by Grant Likely <[email protected]>

---
 drivers/spi/spi-s3c64xx.c |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

drivers/spi/spi-s3c64xx.c +0 -4

index 3c36cfa..6e60eec 100644
@@ -113,10 +113,6 @@
 
 #define S3C64XX_SPI_FBCLK_MSK		(3<<0)
 
-#define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \
-					(((i)->fifo_lvl_mask + 1))) \
-					? 1 : 0)
-
 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0)
 #define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
 #define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)

Signature · 1 line

1.6.6.rc2

Thomas Abraham

author

2012-07-11 15:27 UTC #2 lore raw

PATCH v5 2/6 spi: s3c64xx: move controller information into driver data

In reply to Thomas Abraham

Platform data is used to specify controller hardware specific information such as the tx/rx fifo level mask and bit offset of rx fifo level. Such information is not suitable to be supplied from device tree. Instead, it can be moved into the driver data and removed from platform data.

Signed-off-by Thomas Abraham <[email protected]>

Acked-by Jaswinder Singh <[email protected]>

Acked-by Grant Likely <[email protected]>

---
 arch/arm/mach-exynos/clock-exynos4.c             |   18 ++--
 arch/arm/mach-exynos/setup-spi.c                 |   25 ----
 arch/arm/mach-s3c24xx/clock-s3c2416.c            |    3 +-
 arch/arm/mach-s3c24xx/clock-s3c2443.c            |    2 +-
 arch/arm/mach-s3c24xx/common-s3c2443.c           |    4 +-
 arch/arm/mach-s3c24xx/setup-spi.c                |    8 -
 arch/arm/mach-s3c64xx/clock.c                    |   20 ++--
 arch/arm/mach-s3c64xx/setup-spi.c                |   13 --
 arch/arm/mach-s5p64x0/clock-s5p6440.c            |   12 +-
 arch/arm/mach-s5p64x0/clock-s5p6450.c            |   12 +-
 arch/arm/mach-s5p64x0/setup-spi.c                |   16 ---
 arch/arm/mach-s5pc100/clock.c                    |   30 ++--
 arch/arm/mach-s5pc100/setup-spi.c                |   22 ---
 arch/arm/mach-s5pv210/clock.c                    |   14 +-
 arch/arm/mach-s5pv210/setup-spi.c                |   15 --
 arch/arm/plat-samsung/include/plat/s3c64xx-spi.h |   15 --
 drivers/spi/spi-s3c64xx.c                        |  150 ++++++++++++++++++----
 17 files changed, 181 insertions(+), 198 deletions(-)

arch/arm/mach-exynos/clock-exynos4.c +9 -9

index bcb7db4..10a46a9 100644
@@ -586,17 +586,17 @@ static struct clk exynos4_init_clocks_off[] = {
 		.ctrlbit	= (1 << 13),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "exynos4210-spi.0",
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 16),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "exynos4210-spi.1",
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 17),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.2",
+		.devname	= "exynos4210-spi.2",
 		.enable		= exynos4_clk_ip_peril_ctrl,
 		.ctrlbit	= (1 << 18),
 	}, {

@@ -1245,7 +1245,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
 static struct clksrc_clk exynos4_clk_sclk_spi0 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "exynos4210-spi.0",
 		.enable		= exynos4_clksrc_mask_peril1_ctrl,
 		.ctrlbit	= (1 << 16),
 	},

@@ -1257,7 +1257,7 @@ static struct clksrc_clk exynos4_clk_sclk_spi0 = {
 static struct clksrc_clk exynos4_clk_sclk_spi1 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "exynos4210-spi.1",
 		.enable		= exynos4_clksrc_mask_peril1_ctrl,
 		.ctrlbit	= (1 << 20),
 	},

@@ -1269,7 +1269,7 @@ static struct clksrc_clk exynos4_clk_sclk_spi1 = {
 static struct clksrc_clk exynos4_clk_sclk_spi2 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.2",
+		.devname	= "exynos4210-spi.2",
 		.enable		= exynos4_clksrc_mask_peril1_ctrl,
 		.ctrlbit	= (1 << 24),
 	},

@@ -1347,9 +1347,9 @@ static struct clk_lookup exynos4_clk_lookup[] = {
 	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
 	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
 	CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
-	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
-	CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
+	CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
+	CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
+	CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
 };
 
 static int xtal_rate;

arch/arm/mach-exynos/setup-spi.c +0 ~~-25~~

index 833ff40..a71ec4d 100644
@@ -12,17 +12,8 @@
 #include <linux/platform_device.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-	.fifo_lvl_mask	= 0x1ff,
-	.rx_lvl_offset	= 15,
-	.high_speed	= 1,
-	.clk_from_cmu	= true,
-	.tx_st_done	= 25,
-};
-
 int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));

@@ -34,14 +25,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 15,
-	.high_speed	= 1,
-	.clk_from_cmu	= true,
-	.tx_st_done	= 25,
-};
-
 int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));

@@ -53,14 +36,6 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI2
-struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 15,
-	.high_speed	= 1,
-	.clk_from_cmu	= true,
-	.tx_st_done	= 25,
-};
-
 int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));

arch/arm/mach-s3c24xx/clock-s3c2416.c +2 -1

index 8702ecf..14a81c2 100644
@@ -144,7 +144,8 @@ static struct clk_lookup s3c2416_clk_lookup[] = {
 	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
 	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk),
+	/* s3c2443-spi.0 is used on s3c2416 and s3c2450 as well */
+	CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk),
 };
 
 void __init s3c2416_init_clocks(int xtal)

arch/arm/mach-s3c24xx/clock-s3c2443.c +1 -1

index a4c5a52..7f689ce 100644
@@ -181,7 +181,7 @@ static struct clk *clks[] __initdata = {
 
 static struct clk_lookup s3c2443_clk_lookup[] = {
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk),
+	CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &clk_hsspi.clk),
 };
 
 void __init s3c2443_init_clocks(int xtal)

arch/arm/mach-s3c24xx/common-s3c2443.c +2 -2

index aeeb2be..aeb4a24 100644
@@ -559,7 +559,7 @@ static struct clk hsmmc1_clk = {
 
 static struct clk hsspi_clk = {
 	.name		= "spi",
-	.devname	= "s3c64xx-spi.0",
+	.devname	= "s3c2443-spi.0",
 	.parent		= &clk_p,
 	.enable		= s3c2443_clkcon_enable_p,
 	.ctrlbit	= S3C2443_PCLKCON_HSSPI,

@@ -633,7 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
 	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
 	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk),
+	CLKDEV_INIT("s3c2443-spi.0", "spi_busclk0", &hsspi_clk),
 };
 
 void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,

arch/arm/mach-s3c24xx/setup-spi.c +0 -8

index 5712c85..42abe15 100644
@@ -13,19 +13,11 @@
 #include <linux/platform_device.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 13,
-	.tx_st_done	= 21,
-	.high_speed	= 1,
-};
-
 int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev)
 {
 	/* enable hsspi bit in misccr */

arch/arm/mach-s3c64xx/clock.c +10 ~~-10~~

index 52f079a..28041e8 100644
@@ -178,13 +178,13 @@ static struct clk init_clocks_off[] = {
 		.ctrlbit	= S3C_CLKCON_PCLK_KEYPAD,
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s3c6410-spi.0",
 		.parent		= &clk_p,
 		.enable		= s3c64xx_pclk_ctrl,
 		.ctrlbit	= S3C_CLKCON_PCLK_SPI0,
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s3c6410-spi.1",
 		.parent		= &clk_p,
 		.enable		= s3c64xx_pclk_ctrl,
 		.ctrlbit	= S3C_CLKCON_PCLK_SPI1,

@@ -331,7 +331,7 @@ static struct clk init_clocks_off[] = {
 
 static struct clk clk_48m_spi0 = {
 	.name		= "spi_48m",
-	.devname	= "s3c64xx-spi.0",
+	.devname	= "s3c6410-spi.0",
 	.parent		= &clk_48m,
 	.enable		= s3c64xx_sclk_ctrl,
 	.ctrlbit	= S3C_CLKCON_SCLK_SPI0_48,

@@ -339,7 +339,7 @@ static struct clk clk_48m_spi0 = {
 
 static struct clk clk_48m_spi1 = {
 	.name		= "spi_48m",
-	.devname	= "s3c64xx-spi.1",
+	.devname	= "s3c6410-spi.1",
 	.parent		= &clk_48m,
 	.enable		= s3c64xx_sclk_ctrl,
 	.ctrlbit	= S3C_CLKCON_SCLK_SPI1_48,

@@ -802,7 +802,7 @@ static struct clksrc_clk clk_sclk_mmc2 = {
 static struct clksrc_clk clk_sclk_spi0 = {
 	.clk	= {
 		.name		= "spi-bus",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s3c6410-spi.0",
 		.ctrlbit	= S3C_CLKCON_SCLK_SPI0,
 		.enable		= s3c64xx_sclk_ctrl,
 	},

@@ -814,7 +814,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
 	.clk	= {
 		.name		= "spi-bus",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s3c6410-spi.1",
 		.ctrlbit	= S3C_CLKCON_SCLK_SPI1,
 		.enable		= s3c64xx_sclk_ctrl,
 	},

@@ -858,10 +858,10 @@ static struct clk_lookup s3c64xx_clk_lookup[] = {
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
 	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
 	CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
-	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
-	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
+	CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+	CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0),
+	CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+	CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1),
 };
 
 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)

arch/arm/mach-s3c64xx/setup-spi.c +0 ~~-13~~

index d9592ad..ff999d9 100644
@@ -12,15 +12,8 @@
 #include <linux/platform_device.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 13,
-	.tx_st_done	= 21,
-};
-
 int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,

@@ -30,12 +23,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 13,
-	.tx_st_done	= 21,
-};
-
 int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,

arch/arm/mach-s5p64x0/clock-s5p6440.c +6 -6

index ee1e8e7..0004455 100644
@@ -227,13 +227,13 @@ static struct clk init_clocks_off[] = {
 		.ctrlbit	= (1 << 17),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s5p64x0-spi.0",
 		.parent		= &clk_pclk_low.clk,
 		.enable		= s5p64x0_pclk_ctrl,
 		.ctrlbit	= (1 << 21),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s5p64x0-spi.1",
 		.parent		= &clk_pclk_low.clk,
 		.enable		= s5p64x0_pclk_ctrl,
 		.ctrlbit	= (1 << 22),

@@ -467,7 +467,7 @@ static struct clksrc_clk clk_sclk_uclk = {
 static struct clksrc_clk clk_sclk_spi0 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s5p64x0-spi.0",
 		.ctrlbit	= (1 << 20),
 		.enable		= s5p64x0_sclk_ctrl,
 	},

@@ -479,7 +479,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s5p64x0-spi.1",
 		.ctrlbit	= (1 << 21),
 		.enable		= s5p64x0_sclk_ctrl,
 	},

@@ -519,8 +519,8 @@ static struct clk_lookup s5p6440_clk_lookup[] = {
 	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
 	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
 	CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+	CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+	CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
 	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
 	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),

arch/arm/mach-s5p64x0/clock-s5p6450.c +6 -6

index dae6a13..f3e0ef3 100644
@@ -236,13 +236,13 @@ static struct clk init_clocks_off[] = {
 		.ctrlbit	= (1 << 17),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s5p64x0-spi.0",
 		.parent		= &clk_pclk_low.clk,
 		.enable		= s5p64x0_pclk_ctrl,
 		.ctrlbit	= (1 << 21),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s5p64x0-spi.1",
 		.parent		= &clk_pclk_low.clk,
 		.enable		= s5p64x0_pclk_ctrl,
 		.ctrlbit	= (1 << 22),

@@ -528,7 +528,7 @@ static struct clksrc_clk clk_sclk_uclk = {
 static struct clksrc_clk clk_sclk_spi0 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s5p64x0-spi.0",
 		.ctrlbit	= (1 << 20),
 		.enable		= s5p64x0_sclk_ctrl,
 	},

@@ -540,7 +540,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s5p64x0-spi.1",
 		.ctrlbit	= (1 << 21),
 		.enable		= s5p64x0_sclk_ctrl,
 	},

@@ -562,8 +562,8 @@ static struct clk_lookup s5p6450_clk_lookup[] = {
 	CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
 	CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
 	CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+	CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+	CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
 	CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
 	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),

arch/arm/mach-s5p64x0/setup-spi.c +0 ~~-16~~

index e9b8412..1cf84b5 100644
@@ -10,19 +10,9 @@
 
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
-#include <linux/io.h>
-
 #include <plat/gpio-cfg.h>
-#include <plat/cpu.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-	.fifo_lvl_mask	= 0x1ff,
-	.rx_lvl_offset	= 15,
-	.tx_st_done	= 25,
-};
-
 int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 {
 	if (soc_is_s5p6450())

@@ -36,12 +26,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 15,
-	.tx_st_done	= 25,
-};
-
 int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 {
 	if (soc_is_s5p6450())

arch/arm/mach-s5pc100/clock.c +15 ~~-15~~

index 16eca4e..9262197 100644
@@ -564,19 +564,19 @@ static struct clk init_clocks_off[] = {
 		.ctrlbit	= (1 << 5),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s5pc100-spi.0",
 		.parent		= &clk_div_d1_bus.clk,
 		.enable		= s5pc100_d1_4_ctrl,
 		.ctrlbit	= (1 << 6),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s5pc100-spi.1",
 		.parent		= &clk_div_d1_bus.clk,
 		.enable		= s5pc100_d1_4_ctrl,
 		.ctrlbit	= (1 << 7),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.2",
+		.devname	= "s5pc100-spi.2",
 		.parent		= &clk_div_d1_bus.clk,
 		.enable		= s5pc100_d1_4_ctrl,
 		.ctrlbit	= (1 << 8),

@@ -702,7 +702,7 @@ static struct clk clk_hsmmc0 = {
 
 static struct clk clk_48m_spi0 = {
 	.name		= "spi_48m",
-	.devname	= "s3c64xx-spi.0",
+	.devname	= "s5pc100-spi.0",
 	.parent		= &clk_mout_48m.clk,
 	.enable		= s5pc100_sclk0_ctrl,
 	.ctrlbit	= (1 << 7),

@@ -710,7 +710,7 @@ static struct clk clk_48m_spi0 = {
 
 static struct clk clk_48m_spi1 = {
 	.name		= "spi_48m",
-	.devname	= "s3c64xx-spi.1",
+	.devname	= "s5pc100-spi.1",
 	.parent		= &clk_mout_48m.clk,
 	.enable		= s5pc100_sclk0_ctrl,
 	.ctrlbit	= (1 << 8),

@@ -718,7 +718,7 @@ static struct clk clk_48m_spi1 = {
 
 static struct clk clk_48m_spi2 = {
 	.name		= "spi_48m",
-	.devname	= "s3c64xx-spi.2",
+	.devname	= "s5pc100-spi.2",
 	.parent		= &clk_mout_48m.clk,
 	.enable		= s5pc100_sclk0_ctrl,
 	.ctrlbit	= (1 << 9),

@@ -1085,7 +1085,7 @@ static struct clksrc_clk clk_sclk_mmc2 = {
 static struct clksrc_clk clk_sclk_spi0 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s5pc100-spi.0",
 		.ctrlbit	= (1 << 4),
 		.enable		= s5pc100_sclk0_ctrl,
 	},

@@ -1097,7 +1097,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s5pc100-spi.1",
 		.ctrlbit	= (1 << 5),
 		.enable		= s5pc100_sclk0_ctrl,
 	},

@@ -1109,7 +1109,7 @@ static struct clksrc_clk clk_sclk_spi1 = {
 static struct clksrc_clk clk_sclk_spi2 = {
 	.clk	= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.2",
+		.devname	= "s5pc100-spi.2",
 		.ctrlbit	= (1 << 6),
 		.enable		= s5pc100_sclk0_ctrl,
 	},

@@ -1315,12 +1315,12 @@ static struct clk_lookup s5pc100_clk_lookup[] = {
 	CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
 	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
 	CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
-	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
-	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
-	CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2),
-	CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
+	CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0),
+	CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
+	CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1),
+	CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
+	CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2),
+	CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
 };
 
 void __init s5pc100_register_clocks(void)

arch/arm/mach-s5pc100/setup-spi.c +0 ~~-22~~

index 431a6f7..4b42718 100644
@@ -12,16 +12,8 @@
 #include <linux/platform_device.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 13,
-	.high_speed	= 1,
-	.tx_st_done	= 21,
-};
-
 int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,

@@ -31,13 +23,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 13,
-	.high_speed	= 1,
-	.tx_st_done	= 21,
-};
-
 int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,

@@ -47,13 +32,6 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI2
-struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 13,
-	.high_speed	= 1,
-	.tx_st_done	= 21,
-};
-
 int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));

arch/arm/mach-s5pv210/clock.c +7 -7

index 09609d5..fcdf52d 100644
@@ -445,19 +445,19 @@ static struct clk init_clocks_off[] = {
 		.ctrlbit	= (1 << 11),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s5pv210-spi.0",
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
 		.ctrlbit	= (1<<12),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s5pv210-spi.1",
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
 		.ctrlbit	= (1<<13),
 	}, {
 		.name		= "spi",
-		.devname	= "s3c64xx-spi.2",
+		.devname	= "s5pv210-spi.2",
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
 		.ctrlbit	= (1<<14),

@@ -1035,7 +1035,7 @@ static struct clksrc_clk clk_sclk_mmc3 = {
 static struct clksrc_clk clk_sclk_spi0 = {
 	.clk		= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.0",
+		.devname	= "s5pv210-spi.0",
 		.enable		= s5pv210_clk_mask0_ctrl,
 		.ctrlbit	= (1 << 16),
 	},

@@ -1047,7 +1047,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
 	.clk		= {
 		.name		= "sclk_spi",
-		.devname	= "s3c64xx-spi.1",
+		.devname	= "s5pv210-spi.1",
 		.enable		= s5pv210_clk_mask0_ctrl,
 		.ctrlbit	= (1 << 17),
 	},

@@ -1331,8 +1331,8 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
 	CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
 	CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
 	CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+	CLKDEV_INIT("s5pv210-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+	CLKDEV_INIT("s5pv210-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
 };
 
 void __init s5pv210_register_clocks(void)

arch/arm/mach-s5pv210/setup-spi.c +0 ~~-15~~

index f43c504..2cd66a6 100644
@@ -12,16 +12,8 @@
 #include <linux/platform_device.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
-	.fifo_lvl_mask	= 0x1ff,
-	.rx_lvl_offset	= 15,
-	.high_speed	= 1,
-	.tx_st_done	= 25,
-};
-
 int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));

@@ -33,13 +25,6 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
-	.fifo_lvl_mask	= 0x7f,
-	.rx_lvl_offset	= 15,
-	.high_speed	= 1,
-	.tx_st_done	= 25,
-};
-
 int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 {
 	s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));

arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +0 ~~-15~~

index fa95e9a..4e9b9c3 100644
@@ -33,28 +33,13 @@ struct s3c64xx_spi_csinfo {
 /**
  * struct s3c64xx_spi_info - SPI Controller defining structure
  * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
- * @clk_from_cmu: If the SPI clock/prescalar control block is present
- *     by the platform's clock-management-unit and not in SPI controller.
  * @num_cs: Number of CS this controller emulates.
  * @cfg_gpio: Configure pins for this SPI controller.
- * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
- * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
- * @high_speed: If the controller supports HIGH_SPEED_EN bit
- * @tx_st_done: Depends on tx fifo_lvl field
  */
 struct s3c64xx_spi_info {
 	int src_clk_nr;
-	bool clk_from_cmu;
-
 	int num_cs;
-
 	int (*cfg_gpio)(struct platform_device *pdev);
-
-	/* Following two fields are for future compatibility */
-	int fifo_lvl_mask;
-	int rx_lvl_offset;
-	int high_speed;
-	int tx_st_done;
 };
 
 /**

drivers/spi/spi-s3c64xx.c +123 ~~-27~~

337 lines not on this page · raw message

Signature · 1 line

1.6.6.rc2

Thomas Abraham

author

2012-07-11 15:27 UTC #3 lore raw

PATCH v5 3/6 ARM: Samsung: Remove pdev pointer parameter from spi gpio setup functions

In reply to Thomas Abraham

The platform data pointer that is passed to the spi gpio setup functions is not used. Hence, this parameter is removed from all the spi gpio setup functions.

Signed-off-by Thomas Abraham <[email protected]>

Acked-by Jaswinder Singh <[email protected]>

---
 arch/arm/mach-exynos/setup-spi.c                 |    8 +++-----
 arch/arm/mach-s3c24xx/setup-spi.c                |    2 +-
 arch/arm/mach-s3c64xx/setup-spi.c                |    6 ++----
 arch/arm/mach-s5p64x0/setup-spi.c                |    5 ++---
 arch/arm/mach-s5pc100/setup-spi.c                |    8 +++-----
 arch/arm/mach-s5pv210/setup-spi.c                |    6 ++----
 arch/arm/plat-samsung/include/plat/s3c64xx-spi.h |    8 ++++----
 drivers/spi/spi-s3c64xx.c                        |    5 ++---
 8 files changed, 19 insertions(+), 29 deletions(-)

arch/arm/mach-exynos/setup-spi.c +3 -5

index a71ec4d..4999829 100644
@@ -9,12 +9,10 @@
  */
 
 #include <linux/gpio.h>
-#include <linux/platform_device.h>
-
 #include <plat/gpio-cfg.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
 {
 	s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
 	s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP);

@@ -25,7 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
 {
 	s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
 	s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP);

@@ -36,7 +34,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI2
-int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi2_cfg_gpio(void)
 {
 	s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
 	s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP);

arch/arm/mach-s3c24xx/setup-spi.c +1 -1

index 42abe15..3d47e02 100644
@@ -18,7 +18,7 @@
 #include <mach/regs-gpio.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev)
+int s3c64xx_spi0_cfg_gpio(void)
 {
 	/* enable hsspi bit in misccr */
 	s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1);

arch/arm/mach-s3c64xx/setup-spi.c +2 -4

index ff999d9..4dc5345 100644
@@ -9,12 +9,10 @@
  */
 
 #include <linux/gpio.h>
-#include <linux/platform_device.h>
-
 #include <plat/gpio-cfg.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
 {
 	s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
 				S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);

@@ -23,7 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
 {
 	s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,
 				S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);

arch/arm/mach-s5p64x0/setup-spi.c +2 -3

index 1cf84b5..7664356 100644
@@ -9,11 +9,10 @@
  */
 
 #include <linux/gpio.h>
-#include <linux/platform_device.h>
 #include <plat/gpio-cfg.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
 {
 	if (soc_is_s5p6450())
 		s3c_gpio_cfgall_range(S5P6450_GPC(0), 3,

@@ -26,7 +25,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
 {
 	if (soc_is_s5p6450())
 		s3c_gpio_cfgall_range(S5P6450_GPC(4), 3,

arch/arm/mach-s5pc100/setup-spi.c +3 -5

index 4b42718..1835679 100644
@@ -9,12 +9,10 @@
  */
 
 #include <linux/gpio.h>
-#include <linux/platform_device.h>
-
 #include <plat/gpio-cfg.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
 {
 	s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
 				S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);

@@ -23,7 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
 {
 	s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
 				S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);

@@ -32,7 +30,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI2
-int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi2_cfg_gpio(void)
 {
 	s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
 	s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);

arch/arm/mach-s5pv210/setup-spi.c +2 -4

index 2cd66a6..81aecc1 100644
@@ -9,12 +9,10 @@
  */
 
 #include <linux/gpio.h>
-#include <linux/platform_device.h>
-
 #include <plat/gpio-cfg.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
 {
 	s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
 	s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);

@@ -25,7 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
 {
 	s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
 	s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);

arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +4 -4

index 4e9b9c3..89dbaee 100644
@@ -39,7 +39,7 @@ struct s3c64xx_spi_csinfo {
 struct s3c64xx_spi_info {
 	int src_clk_nr;
 	int num_cs;
-	int (*cfg_gpio)(struct platform_device *pdev);
+	int (*cfg_gpio)(void);
 };
 
 /**

@@ -60,9 +60,9 @@ extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
 				      int src_clk_nr, int num_cs);
 
 /* defined by architecture to configure gpio */
-extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev);
-extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev);
-extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev);
+extern int s3c64xx_spi0_cfg_gpio(void);
+extern int s3c64xx_spi1_cfg_gpio(void);
+extern int s3c64xx_spi2_cfg_gpio(void);
 
 extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
 extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;

drivers/spi/spi-s3c64xx.c +2 -3

index 8698618..0a9e43e 100644
@@ -1071,7 +1071,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
 		goto err1;
 	}
 
-	if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) {
+	if (sci->cfg_gpio == NULL || sci->cfg_gpio()) {
 		dev_err(&pdev->dev, "Unable to config gpio\n");
 		ret = -EBUSY;
 		goto err2;

@@ -1214,12 +1214,11 @@ static int s3c64xx_spi_suspend(struct device *dev)
 
 static int s3c64xx_spi_resume(struct device *dev)
 {
-	struct platform_device *pdev = to_platform_device(dev);
 	struct spi_master *master = spi_master_get(dev_get_drvdata(dev));
 	struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 	struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 
-	sci->cfg_gpio(pdev);
+	sci->cfg_gpio();
 
 	/* Enable the clock */
 	clk_enable(sdd->src_clk);

Signature · 1 line

1.6.6.rc2

Thomas Abraham

author

2012-07-11 15:27 UTC #4 lore raw

PATCH v5 4/6 ARM: Samsung: Modify s3c64xx_spi{0|1|2}_set_platdata function

In reply to Thomas Abraham

With the spi controller hardware configuration moved into the driver data, there are no more default hardware configuration data that is passed through platform data. Accordingly, the s3c64xx_spi{0|1|2}_set_platdata functions are adapted to these changes.

Signed-off-by Thomas Abraham <[email protected]>

Acked-by Jaswinder Singh <[email protected]>

---
 arch/arm/mach-s3c64xx/mach-crag6410.c            |    2 +-
 arch/arm/plat-samsung/devs.c                     |   60 ++++++++-------------
 arch/arm/plat-samsung/include/plat/s3c64xx-spi.h |   14 +++---
 3 files changed, 31 insertions(+), 45 deletions(-)

arch/arm/mach-s3c64xx/mach-crag6410.c +1 -1

index 161c3b6..3627444 100644
@@ -798,7 +798,7 @@ static void __init crag6410_machine_init(void)
 	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
 
 	samsung_keypad_set_platdata(&crag6410_keypad_data);
-	s3c64xx_spi0_set_platdata(&s3c64xx_spi0_pdata, 0, 1);
+	s3c64xx_spi0_set_platdata(NULL, 0, 1);
 
 	platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));

arch/arm/plat-samsung/devs.c +23 ~~-37~~

119 lines not on this page · raw message

arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +7 -7

index 89dbaee..c818a7c 100644
@@ -45,19 +45,19 @@ struct s3c64xx_spi_info {
 /**
  * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
  *				initialization code.
- * @pd: SPI platform data to set.
+ * @cfg_gpio: Pointer to gpio setup function.
  * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
  * @num_cs: Number of elements in the 'cs' array.
  *
  * Call this from machine init code for each SPI Controller that
  * has some chips attached to it.
  */
-extern void s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
-				      int src_clk_nr, int num_cs);
-extern void s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
-				      int src_clk_nr, int num_cs);
-extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
-				      int src_clk_nr, int num_cs);
+extern void s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
+						int num_cs);
+extern void s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
+						int num_cs);
+extern void s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
+						int num_cs);
 
 /* defined by architecture to configure gpio */
 extern int s3c64xx_spi0_cfg_gpio(void);

Signature · 1 line

1.6.6.rc2

Thomas Abraham

author

2012-07-11 15:27 UTC #5 lore raw

PATCH v5 5/6 spi: s3c64xx: Remove the 'set_level' callback from controller data

In reply to Thomas Abraham

The set_level callback in the controller data, which is used to configure the slave select line, cannot be supported when migrating the driver to device tree based discovery. Since all the platforms currently use gpio as the slave select line, this callback can be removed from the controller data and replaced with call to gpio_set_value in the driver.

Signed-off-by Thomas Abraham <[email protected]>

Acked-by Jaswinder Singh <[email protected]>

Acked-by Grant Likely <[email protected]>

---
 arch/arm/plat-samsung/include/plat/s3c64xx-spi.h |    2 -
 drivers/spi/spi-s3c64xx.c                        |   31 ++++++++++++++++++---
 2 files changed, 26 insertions(+), 7 deletions(-)

arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +0 -2

index c818a7c..ceba18d 100644
@@ -18,7 +18,6 @@ struct platform_device;
  * @fb_delay: Slave specific feedback delay.
  *            Refer to FB_CLK_SEL register definition in SPI chapter.
  * @line: Custom 'identity' of the CS line.
- * @set_level: CS line control.
  *
  * This is per SPI-Slave Chipselect information.
  * Allocate and initialize one in machine init code and make the

@@ -27,7 +26,6 @@ struct platform_device;
 struct s3c64xx_spi_csinfo {
 	u8 fb_delay;
 	unsigned line;
-	void (*set_level)(unsigned line_id, int lvl);
 };
 
 /**

drivers/spi/spi-s3c64xx.c +26 -5

index 0a9e43e..e4182ea 100644
@@ -27,6 +27,7 @@
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/spi/spi.h>
+#include <linux/gpio.h>
 
 #include <mach/dma.h>
 #include <plat/s3c64xx-spi.h>

@@ -411,14 +412,14 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
 		if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
 			/* Deselect the last toggled device */
 			cs = sdd->tgl_spi->controller_data;
-			cs->set_level(cs->line,
-					spi->mode & SPI_CS_HIGH ? 0 : 1);
+			gpio_set_value(cs->line,
+				spi->mode & SPI_CS_HIGH ? 0 : 1);
 		}
 		sdd->tgl_spi = NULL;
 	}
 
 	cs = spi->controller_data;
-	cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
+	gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
 }
 
 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,

@@ -504,7 +505,7 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
 	if (sdd->tgl_spi == spi)
 		sdd->tgl_spi = NULL;
 
-	cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
+	gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
 }
 
 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)

@@ -833,11 +834,21 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
 	unsigned long flags;
 	int err = 0;
 
-	if (cs == NULL || cs->set_level == NULL) {
+	if (cs == NULL) {
 		dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
 		return -ENODEV;
 	}
 
+	if (!spi_get_ctldata(spi)) {
+		err = gpio_request(cs->line, dev_name(&spi->dev));
+		if (err) {
+			dev_err(&spi->dev, "request for slave select gpio "
+					"line [%d] failed\n", cs->line);
+			return -EBUSY;
+		}
+		spi_set_ctldata(spi, cs);
+	}
+
 	sdd = spi_master_get_devdata(spi->master);
 	sci = sdd->cntrlr_info;

@@ -908,6 +919,15 @@ setup_exit:
 	return err;
 }
 
+static void s3c64xx_spi_cleanup(struct spi_device *spi)
+{
+	struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
+
+	if (cs)
+		gpio_free(cs->line);
+	spi_set_ctldata(spi, NULL);
+}
+
 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
 {
 	struct s3c64xx_spi_driver_data *sdd = data;

@@ -1049,6 +1069,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
 
 	master->bus_num = sdd->port_id;
 	master->setup = s3c64xx_spi_setup;
+	master->cleanup = s3c64xx_spi_cleanup;
 	master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
 	master->transfer_one_message = s3c64xx_spi_transfer_one_message;
 	master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;

Signature · 1 line

1.6.6.rc2

Thomas Abraham

author

2012-07-11 15:27 UTC #6 lore raw

PATCH v5 6/6 spi: s3c64xx: add device tree support

In reply to Thomas Abraham

Add support for device based discovery.

Signed-off-by Thomas Abraham <[email protected]>

Acked-by Jaswinder Singh <[email protected]>

Acked-by Grant Likely <[email protected]>

---
 .../devicetree/bindings/spi/spi-samsung.txt        |  113 ++++++++
 drivers/spi/spi-s3c64xx.c                          |  305 +++++++++++++++++---
 2 files changed, 378 insertions(+), 40 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/spi/spi-samsung.txt

Documentation/devicetree/bindings/spi/spi-samsung.txt new file +113 -0

new file mode 100644
index 0000000..59bfc4f
@@ -0,0 +1,113 @@
+* Samsung SPI Controller
+
+The Samsung SPI controller is used to interface with various devices such as flash
+and display controllers using the SPI communication interface.
+
+Required SoC Specific Properties:
+
+- compatible: should be one of the following.
+    - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
+    - samsung,s3c6410-spi: for s3c6410 platforms
+    - samsung,s5p6440-spi: for s5p6440 and s5p6450 platforms
+    - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
+    - samsung,exynos4210-spi: for exynos4 and exynos5 platforms
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- interrupts: The interrupt number to the cpu. The interrupt specifier format
+  depends on the interrupt controller.
+
+- tx-dma-channel: The dma channel specifier for tx operations. The format of
+  the dma specifier depends on the dma controller.
+
+- rx-dma-channel: The dma channel specifier for rx operations. The format of
+  the dma specifier depends on the dma controller.
+
+Required Board Specific Properties:
+
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+- gpios: The gpio specifier for clock, mosi and miso interface lines (in the
+  order specified). The format of the gpio specifier depends on the gpio
+  controller.
+
+Optional Board Specific Properties:
+
+- samsung,spi-src-clk: If the spi controller includes a internal clock mux to
+  select the clock source for the spi bus clock, this property can be used to
+  indicate the clock to be used for driving the spi bus clock. If not specified,
+  the clock number 0 is used as default.
+
+- num-cs: Specifies the number of chip select lines supported. If
+  not specified, the default number of chip select lines is set to 1.
+
+SPI Controller specific data in SPI slave nodes:
+
+- The spi slave nodes should provide the following information which is required
+  by the spi controller.
+
+  - cs-gpio: A gpio specifier that specifies the gpio line used as
+    the slave select line by the spi controller. The format of the gpio
+    specifier depends on the gpio controller.
+
+  - samsung,spi-feedback-delay: The sampling phase shift to be applied on the
+    miso line (to account for any lag in the miso line). The following are the
+    valid values.
+
+      - 0: No phase shift.
+      - 1: 90 degree phase shift sampling.
+      - 2: 180 degree phase shift sampling.
+      - 3: 270 degree phase shift sampling.
+
+Aliases:
+
+- All the SPI controller nodes should be represented in the aliases node using
+  the following format 'spi{n}' where n is a unique number for the alias.
+
+
+Example:
+
+- SoC Specific Portion:
+
+	spi_0: spi@12d20000 {
+		compatible = "samsung,exynos4210-spi";
+		reg = <0x12d20000 0x100>;
+		interrupts = <0 66 0>;
+		tx-dma-channel = <&pdma0 5>;
+		rx-dma-channel = <&pdma0 4>;
+	};
+
+- Board Specific Portion:
+
+	spi_0: spi@12d20000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpios = <&gpa2 4 2 3 0>,
+			<&gpa2 6 2 3 0>,
+			<&gpa2 7 2 3 0>;
+
+		w25q80bw@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "w25x80";
+			reg = <0>;
+			spi-max-frequency = <10000>;
+
+			controller-data {
+				cs-gpio = <&gpa2 5 1 0 3>;
+				samsung,spi-feedback-delay = <0>;
+			};
+
+			partition@0 {
+				label = "U-Boot";
+				reg = <0x0 0x40000>;
+				read-only;
+			};
+
+			partition@40000 {
+				label = "Kernel";
+				reg = <0x40000 0xc0000>;
+			};
+		};
+	};

drivers/spi/spi-s3c64xx.c +265 ~~-40~~

457 lines not on this page · raw message

Signature · 1 line

1.6.6.rc2

Kukjin Kim

2012-07-12 22:38 UTC #7 lore raw

PATCH v5 6/6 spi: s3c64xx: add device tree support

Quoted 11 lines · Thomas Abraham

Add support for device based discovery.
Signed-off-by Thomas Abraham<[email protected]>
Acked-by Jaswinder Singh<[email protected]>
Acked-by Grant Likely<[email protected]>
---
  .../devicetree/bindings/spi/spi-samsung.txt        |  113 ++++++++
  drivers/spi/spi-s3c64xx.c                          |  305 +++++++++++++++++---
  2 files changed, 378 insertions(+), 40 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/spi-samsung.txt

[snip]

Quoted 33 lines

drivers/spi/spi-s3c64xx.c +29 -0

@@ -989,49 +1057,166 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
  	flush_fifo(sdd);
  }
 
+static int __devinit s3c64xx_spi_get_dmares(
+			struct s3c64xx_spi_driver_data *sdd, bool tx)
+{
+	struct platform_device *pdev = sdd->pdev;
+	struct s3c64xx_spi_dma_data *dma_data;
+	struct property *prop;
+	struct resource *res;
+	char prop_name[15], *chan_str;
+
+	if (tx) {
+		dma_data =&sdd->tx_dma;
+		dma_data->direction = DMA_TO_DEVICE;
+		chan_str = "tx";
+	} else {
+		dma_data =&sdd->rx_dma;
+		dma_data->direction = DMA_FROM_DEVICE;
+		chan_str = "rx";
+	}
+
+	if (!sdd->pdev->dev.of_node) {
+		res = platform_get_resource(pdev, IORESOURCE_DMA, tx ? 0 : 1);
+		if (!res) {
+			dev_err(&pdev->dev, "Unable to get SPI-%s dma "
+					"resource\n", chan_str);
+			return -ENXIO;
+		}
+		dma_data->dmach = res->start;
+		return 0;
+	}

drivers/spi/spi-s3c64xx.c static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) · line 1098

Quoted 10 lines

drivers/spi/spi-s3c64xx.c +10 -0

+
+	sprintf(prop_name, "%s-dma-channel", chan_str);
+	prop = of_find_property(pdev->dev.of_node, prop_name, NULL);
+	if (!prop) {
+		dev_err(&pdev->dev, "%s dma channel property not specified\n",
+					chan_str);
+		return -ENXIO;
+	}
+
+	dma_data->dmach = DMACH_DT_PROP;

Thomas, the DMACH_DT_PROP is available only on pl330 now. So seems occur following build error with s3c6400_defconfig.

drivers/spi/spi-s3c64xx.c: In function 's3c64xx_spi_get_dmares':
drivers/spi/spi-s3c64xx.c:1098: error: 'DMACH_DT_PROP' undeclared (first use in this function)
drivers/spi/spi-s3c64xx.c:1098: error: (Each undeclared identifier is reported only once
drivers/spi/spi-s3c64xx.c:1098: error: for each function it appears in.) make[3]: *** [drivers/spi/spi-s3c64xx.o] Error 1
make[2]: *** [drivers/spi] Error 2

drivers/spi/spi-s3c64xx.c static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) · line 1101

Quoted 3 lines

drivers/spi/spi-s3c64xx.c +3 -0
+	dma_data->dma_prop = prop;
+	return 0;
+}

[snip]

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Thomas Abraham

author

2012-07-13 03:55 UTC #8 lore raw

PATCH v5 6/6 spi: s3c64xx: add device tree support

Quoted 12 lines · Kukjin Kim

Thomas, the DMACH_DT_PROP is available only on pl330 now. So seems occur following build error with s3c6400_defconfig.
drivers/spi/spi-s3c64xx.c: In function 's3c64xx_spi_get_dmares':
drivers/spi/spi-s3c64xx.c:1098: error: 'DMACH_DT_PROP' undeclared (first use in this function)
drivers/spi/spi-s3c64xx.c:1098: error: (Each undeclared identifier is reported only once
drivers/spi/spi-s3c64xx.c:1098: error: for each function it appears in.) make[3]: *** [drivers/spi/spi-s3c64xx.o] Error 1
make[2]: *** [drivers/spi] Error 2

Dear Mr. Kim,

Thanks for considering these patches to be merged via your tree. For the build break you mentioned above, there was a patch submitted some time back to handle this. The link to that patch is:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-June/102627.html.
Could you please apply this patch also to your tree.

Thanks,
Thomas.

Kukjin Kim

2012-07-13 11:28 UTC #9 lore raw

PATCH v5 6/6 spi: s3c64xx: add device tree support

Quoted 16 lines · Thomas Abraham

Quoted 5 lines · Kukjin Kim
Thomas, the DMACH_DT_PROP is available only on pl330 now. So seems occur following build error with s3c6400_defconfig.
drivers/spi/spi-s3c64xx.c: In function 's3c64xx_spi_get_dmares':
drivers/spi/spi-s3c64xx.c:1098: error: 'DMACH_DT_PROP' undeclared (first
use
Quoted 7 lines
in this function)
drivers/spi/spi-s3c64xx.c:1098: error: (Each undeclared identifier is reported only once
drivers/spi/spi-s3c64xx.c:1098: error: for each function it appears in.) make[3]: *** [drivers/spi/spi-s3c64xx.o] Error 1
make[2]: *** [drivers/spi] Error 2

Quoted 9 lines

Dear Mr. Kim,
Thanks for considering these patches to be merged via your tree. For the build break you mentioned above, there was a patch submitted some time back to handle this. The link to that patch is:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-
June/102627.html.
Could you please apply this patch also to your tree.

Sure, it looks good to me, will apply that then this series will be rebased on top of that.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Thomas Abraham

author

2012-07-13 11:38 UTC #10 lore raw

PATCH v5 6/6 spi: s3c64xx: add device tree support

Quoted 26 lines · Kukjin Kim

Quoted 16 lines · Thomas Abraham
Quoted 5 lines · Kukjin Kim
Thomas, the DMACH_DT_PROP is available only on pl330 now. So seems occur following build error with s3c6400_defconfig.
drivers/spi/spi-s3c64xx.c: In function 's3c64xx_spi_get_dmares':
drivers/spi/spi-s3c64xx.c:1098: error: 'DMACH_DT_PROP' undeclared (first
use
Quoted 7 lines
in this function)
drivers/spi/spi-s3c64xx.c:1098: error: (Each undeclared identifier is reported only once
drivers/spi/spi-s3c64xx.c:1098: error: for each function it appears in.) make[3]: *** [drivers/spi/spi-s3c64xx.o] Error 1
make[2]: *** [drivers/spi] Error 2
Quoted 9 lines
Dear Mr. Kim,
Thanks for considering these patches to be merged via your tree. For the build break you mentioned above, there was a patch submitted some time back to handle this. The link to that patch is:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-
June/102627.html.
Could you please apply this patch also to your tree.

Quoted 2 lines

Sure, it looks good to me, will apply that then this series will be rebased on top of that.

There are six more patches that enable spi device tree support for Exynos4 and Exynos5 platforms. Could you consider to apply those patches as well. The link to those patches is:
http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg10851.html.

Thanks,
Thomas.

Kukjin Kim

2012-07-13 13:42 UTC #11 lore raw

PATCH v5 6/6 spi: s3c64xx: add device tree support

Quoted 32 lines · Thomas Abraham

Quoted 4 lines · Kukjin Kim
Quoted 3 lines · Thomas Abraham
Quoted 1 line · Kukjin Kim
Thomas, the DMACH_DT_PROP is available only on pl330 now. So seems
occur
Quoted 4 lines
Quoted 4 lines
Quoted 4 lines
following build error with s3c6400_defconfig.
drivers/spi/spi-s3c64xx.c: In function 's3c64xx_spi_get_dmares':
drivers/spi/spi-s3c64xx.c:1098: error: 'DMACH_DT_PROP' undeclared
(first
Quoted 5 lines
Quoted 5 lines
use
Quoted 4 lines
in this function)
drivers/spi/spi-s3c64xx.c:1098: error: (Each undeclared identifier is reported only once
drivers/spi/spi-s3c64xx.c:1098: error: for each function it appears
in.)
Quoted 6 lines
Quoted 6 lines
Quoted 3 lines
make[3]: *** [drivers/spi/spi-s3c64xx.o] Error 1
make[2]: *** [drivers/spi] Error 2
Dear Mr. Kim,
Quoted 8 lines
Quoted 7 lines
Thanks for considering these patches to be merged via your tree. For the build break you mentioned above, there was a patch submitted some time back to handle this. The link to that patch is:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-
June/102627.html.
Could you please apply this patch also to your tree.
Sure, it looks good to me, will apply that then this series will be

Quoted 9 lines

rebased
Quoted 1 line
on top of that.
There are six more patches that enable spi device tree support for Exynos4 and Exynos5 platforms. Could you consider to apply those patches as well. The link to those patches is:
http://www.mail-archive.com/linux-samsung-
soc at vger.kernel.org/msg10851.html.

Yeah, I remember, but I think some patches is needed to re-work as per comments...?

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Thomas Abraham

author

2012-07-13 14:51 UTC #12 lore raw

PATCH v5 6/6 spi: s3c64xx: add device tree support

Quoted 36 lines · Kukjin Kim

Quoted 35 lines · Thomas Abraham
Quoted 4 lines · Kukjin Kim
Quoted 3 lines · Thomas Abraham
Quoted 1 line · Kukjin Kim
Thomas, the DMACH_DT_PROP is available only on pl330 now. So seems
occur
Quoted 4 lines
Quoted 4 lines
Quoted 4 lines
following build error with s3c6400_defconfig.
drivers/spi/spi-s3c64xx.c: In function 's3c64xx_spi_get_dmares':
drivers/spi/spi-s3c64xx.c:1098: error: 'DMACH_DT_PROP' undeclared
(first
Quoted 5 lines
Quoted 5 lines
use
Quoted 4 lines
in this function)
drivers/spi/spi-s3c64xx.c:1098: error: (Each undeclared identifier is reported only once
drivers/spi/spi-s3c64xx.c:1098: error: for each function it appears
in.)
Quoted 6 lines
Quoted 6 lines
Quoted 3 lines
make[3]: *** [drivers/spi/spi-s3c64xx.o] Error 1
make[2]: *** [drivers/spi] Error 2
Dear Mr. Kim,
Quoted 8 lines
Quoted 7 lines
Thanks for considering these patches to be merged via your tree. For the build break you mentioned above, there was a patch submitted some time back to handle this. The link to that patch is:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-
June/102627.html.
Could you please apply this patch also to your tree.
Sure, it looks good to me, will apply that then this series will be
rebased
Quoted 1 line
on top of that.

Quoted 8 lines

Quoted 6 lines
There are six more patches that enable spi device tree support for Exynos4 and Exynos5 platforms. Could you consider to apply those patches as well. The link to those patches is:
http://www.mail-archive.com/linux-samsung-
soc at vger.kernel.org/msg10851.html.
Yeah, I remember, but I think some patches is needed to re-work as per comments...?

I checked again for any pending comments on v2 version. There are no pending comments for the v2 version of this patch series. Thanks.

Kukjin Kim

2012-07-15 10:39 UTC #13 lore raw

PATCH v5 6/6 spi: s3c64xx: add device tree support

Quoted 47 lines · Thomas Abraham

Quoted 8 lines · Kukjin Kim
Quoted 7 lines · Thomas Abraham
Quoted 4 lines · Kukjin Kim
Quoted 3 lines · Thomas Abraham
Quoted 1 line · Kukjin Kim
Thomas, the DMACH_DT_PROP is available only on pl330 now. So seems
occur
Quoted 8 lines
Quoted 8 lines
Quoted 4 lines
Quoted 4 lines
Quoted 4 lines
following build error with s3c6400_defconfig.
drivers/spi/spi-s3c64xx.c: In function 's3c64xx_spi_get_dmares':
drivers/spi/spi-s3c64xx.c:1098: error: 'DMACH_DT_PROP' undeclared
(first
Quoted 3 lines
Quoted 3 lines
use
Quoted 2 lines
in this function)
drivers/spi/spi-s3c64xx.c:1098: error: (Each undeclared identifier
is
Quoted 2 lines
Quoted 2 lines
Quoted 2 lines
Quoted 2 lines
Quoted 2 lines
reported only once
drivers/spi/spi-s3c64xx.c:1098: error: for each function it
appears
Quoted 9 lines
Quoted 9 lines
in.)
Quoted 8 lines
Quoted 8 lines
Quoted 3 lines
make[3]: *** [drivers/spi/spi-s3c64xx.o] Error 1
make[2]: *** [drivers/spi] Error 2
Dear Mr. Kim,
Thanks for considering these patches to be merged via your tree. For the build break you mentioned above, there was a patch submitted
some
Quoted 15 lines
Quoted 15 lines
Quoted 6 lines
Quoted 5 lines
time back to handle this. The link to that patch is:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-
June/102627.html.
Could you please apply this patch also to your tree.
Sure, it looks good to me, will apply that then this series will be
rebased
Quoted 1 line
on top of that.
There are six more patches that enable spi device tree support for Exynos4 and Exynos5 platforms. Could you consider to apply those patches as well. The link to those patches is:
http://www.mail-archive.com/linux-samsung-
soc at vger.kernel.org/msg10851.html.

Quoted 5 lines

Quoted 2 lines
Yeah, I remember, but I think some patches is needed to re-work as per comments...?
I checked again for any pending comments on v2 version. There are no pending comments for the v2 version of this patch series. Thanks.

OK, I checked v2 series you mentioned. Looks OK to me and applied into next/dt-samsung because it is related in supporting dt.

Note, I applied all of them into same dt branch, the fist one 'fix the incorrect hierarchy of spi controller bus clock for exynos4' can be sent to upstream via fixes now though. And I changed the clock name for exynos4_clk_mdout_spix to 'mdout_spi' for consensus when I applied.

If any problems, please let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Mark Brown

2012-07-11 17:49 UTC #14 lore raw

v5 cover spi: s3c64xx: add support for device tree

In reply to Thomas Abraham

Quoted 3 lines · Thomas Abraham

Changes since v4:
- Includes the missing gpio request for slave select line gpio as suggested by Mark Brown.

These looked OK (and have had quite a bit of review already so we're probably at the stage where incremental fixes are better anyway) so I tried to apply them but git am was really unhappy. I tried applying on

git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc.git spi-next

and -next. Can you check what's going on here please?
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Thomas Abraham

author

2012-07-11 18:00 UTC #15 lore raw

v5 cover spi: s3c64xx: add support for device tree

Quoted 5 lines · Mark Brown

Quoted 3 lines · Thomas Abraham
Changes since v4:
- Includes the missing gpio request for slave select line gpio as suggested by Mark Brown.

Quoted 7 lines

These looked OK (and have had quite a bit of review already so we're probably at the stage where incremental fixes are better anyway) so I tried to apply them but git am was really unhappy. I tried applying on
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc.git spi-next
and -next. Can you check what's going on here please?

These patches were based on Samsung maintainer's for-next branch with Grant's spi/next branch merged. I will check with your spi-next branch. Thanks.

Thomas Abraham

author

2012-07-12 08:47 UTC #16 lore raw

v5 cover spi: s3c64xx: add support for device tree

Quoted 10 lines · Thomas Abraham

Quoted 9 lines · Mark Brown
Quoted 3 lines · Thomas Abraham
Changes since v4:
- Includes the missing gpio request for slave select line gpio as suggested by Mark Brown.
These looked OK (and have had quite a bit of review already so we're probably at the stage where incremental fixes are better anyway) so I tried to apply them but git am was really unhappy. I tried applying on

Quoted 7 lines

Quoted 3 lines
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc.git spi-next
and -next. Can you check what's going on here please?
These patches were based on Samsung maintainer's for-next branch with Grant's spi/next branch merged. I will check with your spi-next branch. Thanks.

The 6th patch in this series has a dependency on Samsung maintainers

Kukjin Kim

2012-07-12 09:11 UTC #17 lore raw

v5 cover spi: s3c64xx: add support for device tree

In reply to Thomas Abraham

Quoted 7 lines · Thomas Abraham

Quoted 3 lines · Mark Brown
Quoted 2 lines · Thomas Abraham
Changes since v4:
- Includes the missing gpio request for slave select line gpio as
suggested

Quoted 11 lines

Quoted 7 lines
Quoted 1 line
by Mark Brown.
These looked OK (and have had quite a bit of review already so we're probably at the stage where incremental fixes are better anyway) so I tried to apply them but git am was really unhappy. I tried applying on
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc.git spi-
next
Quoted 2 lines
and -next. Can you check what's going on here please?

Firstly, this patches look ok to me.

And Mark, this touches various samsung stuff in arch/arm/ so if you're ok, I'd like to pick this up in samsung tree. We don't want to see conflicts...

Quoted 3 lines

These patches were based on Samsung maintainer's for-next branch with Grant's spi/next branch merged. I will check with your spi-next branch. Thanks.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Mark Brown

2012-07-12 13:02 UTC #18 lore raw

v5 cover spi: s3c64xx: add support for device tree

Quoted 2 lines · Kukjin Kim

And Mark, this touches various samsung stuff in arch/arm/ so if you're ok, I'd like to pick this up in samsung tree. We don't want to see conflicts...

Well, simple conflicts aren't that big a deal... However, Thomas
mentioned that in order to test this he merged the SPI tree into your
tree so perhaps there is also a dependency on the SPI tree? If that was
just for good practice testing then I agree that the best thing is to
merge via your tree, otherwise we might need to think harder.
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Thomas Abraham

author

2012-07-12 13:43 UTC #19 lore raw

v5 cover spi: s3c64xx: add support for device tree

Quoted 10 lines · Mark Brown

Quoted 2 lines · Kukjin Kim
And Mark, this touches various samsung stuff in arch/arm/ so if you're ok, I'd like to pick this up in samsung tree. We don't want to see conflicts...
Well, simple conflicts aren't that big a deal... However, Thomas mentioned that in order to test this he merged the SPI tree into your tree so perhaps there is also a dependency on the SPI tree? If that was just for good practice testing then I agree that the best thing is to merge via your tree, otherwise we might need to think harder.

There were no dependency on Grant's spi/next branch. It was merged just to ensure that nothing is broken.

Mark Brown

2012-07-12 16:16 UTC #20 lore raw

v5 cover spi: s3c64xx: add support for device tree

Quoted 10 lines · Thomas Abraham

Quoted 5 lines · Mark Brown
Well, simple conflicts aren't that big a deal... However, Thomas mentioned that in order to test this he merged the SPI tree into your tree so perhaps there is also a dependency on the SPI tree? If that was just for good practice testing then I agree that the best thing is to merge via your tree, otherwise we might need to think harder.
There were no dependency on Grant's spi/next branch. It was merged just to ensure that nothing is broken.

OK, great - then the Samsung tree it is.
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Kukjin Kim

2012-07-12 22:35 UTC #21 lore raw

v5 cover spi: s3c64xx: add support for device tree

Quoted 9 lines · Mark Brown

Quoted 7 lines · Thomas Abraham
Quoted 5 lines · Mark Brown
Well, simple conflicts aren't that big a deal... However, Thomas mentioned that in order to test this he merged the SPI tree into your tree so perhaps there is also a dependency on the SPI tree? If that was just for good practice testing then I agree that the best thing is to merge via your tree, otherwise we might need to think harder.

Quoted 4 lines

Quoted 2 lines
There were no dependency on Grant's spi/next branch. It was merged just to ensure that nothing is broken.
OK, great - then the Samsung tree it is.

Thanks, will apply.

Mark, if you want to add your ack or review on them, let me know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.