perf/x86: disable PEBS on a guest entry.
Subsystems (3)
PATCH 1/1 perf/x86: disable PEBS on a guest entry.
If PMU counter has PEBS enabled it is not enough to disable counter on a guest entry since PEBS memory write can overshoot guest entry and corrupt guest memory. Disabling PEBS during guest entry solves the problem.
Tested-by David Ahern <[email protected]>
Signed-off-by Gleb Natapov <[email protected]>
arch/x86/kernel/cpu/perf_event_intel.c +9 -1
@@ -1444,8 +1444,16 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) arr[0 ].msr =MSR_CORE_PERF_GLOBAL_CTRL ; arr[0 ].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask; arr[0 ].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask; +/* +* If PMU counter has PEBS enabled it is not enough to disable counter +* on a guest entry since PEBS memory write can overshoot guest entry +* and corrupt guest memory. Disabling PEBS solves the problem. +*/ + arr[1 ].msr =MSR_IA32_PEBS_ENABLE ; + arr[1 ].host = cpuc->pebs_enabled; + arr[1 ].guest =0 ; - *nr =1 ; + *nr =2 ;return arr; }
--
Gleb.
Commit-ID: 26a4f3c08de49c1437a7b7f97693cf22d8c31656 Gitweb: http://git.kernel.org/tip/26a4f3c08de49c1437a7b7f97693cf22d8c31656 Author: Gleb Natapov <[email protected]> AuthorDate: Thu, 9 Aug 2012 11:52:34 +0300 Committer: Thomas Gleixner <[email protected]> CommitDate: Mon, 13 Aug 2012 19:01:04 +0200
perf/x86: disable PEBS on a guest entry.
If PMU counter has PEBS enabled it is not enough to disable counter on a guest entry since PEBS memory write can overshoot guest entry and corrupt guest memory. Disabling PEBS during guest entry solves the problem.
Tested-by David Ahern <[email protected]>
Signed-off-by Gleb Natapov <[email protected]>
Signed-off-by Peter Zijlstra <[email protected]>
Signed-off-by Thomas Gleixner <[email protected]>
--- arch/x86/kernel/cpu/perf_event_intel.c | 10 +++++++++- 1 files changed, 9 insertions(+), 1 deletions(-)
arch/x86/kernel/cpu/perf_event_intel.c +9 -1
@@ -1522,8 +1522,16 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) arr[0 ].msr =MSR_CORE_PERF_GLOBAL_CTRL ; arr[0 ].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask; arr[0 ].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask; +/* +* If PMU counter has PEBS enabled it is not enough to disable counter +* on a guest entry since PEBS memory write can overshoot guest entry +* and corrupt guest memory. Disabling PEBS solves the problem. +*/ + arr[1 ].msr =MSR_IA32_PEBS_ENABLE ; + arr[1 ].host = cpuc->pebs_enabled; + arr[1 ].guest =0 ; - *nr =1 ; + *nr =2 ;return arr; }