ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register

PATCH New Kukjin Kim 3 participants 4 messages Nov 17, 2010 – Aug 13, 2012

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Arm (32-bit) Arm sub-architectures Arm Samsung Exynos

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Kukjin Kim

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2010-11-17 06:55 UTC #0 lore raw

PATCH 1/1 ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register

From: Changhwan Youn <[email protected]>

This patch is applied according to the commit 1a8e41cd672f894bbd74874eac601e6cedf838fb (ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register).

Actually, S5PV310 has same cache controller(PL310).

Following is from Catalin Marinas' commit.

Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption.

Signed-off-by Changhwan Youn <[email protected]>

Cc <[email protected]>

Cc Catalin Marinas <[email protected]>

Cc Russell King <[email protected]>

Signed-off-by Kukjin Kim <[email protected]>

---
 arch/arm/mach-s5pv310/cpu.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

arch/arm/mach-s5pv310/cpu.c +1 -1

index 82ce4aa..b2a37d0 100644
@@ -168,7 +168,7 @@ static int __init s5pv310_l2x0_cache_init(void)
 	__raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
 		     S5P_VA_L2CC + L2X0_POWER_CTRL);
 
-	l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff);
+	l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
 
 	return 0;
 }

Signature · 1 line

1.6.2.5

Catalin Marinas

2010-11-17 09:07 UTC #1 lore raw

PATCH 1/1 ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register

arch/arm/mach-s5pv310/cpu.c static int __init s5pv310_l2x0_cache_init(void) · line 171

Quoted 8 lines · Kukjin Kim

arch/arm/mach-s5pv310/cpu.c +1 -1

@@ -168,7 +168,7 @@ static int __init s5pv310_l2x0_cache_init(void)
        __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
                     S5P_VA_L2CC + L2X0_POWER_CTRL);
 
-       l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff);
+       l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);

The patch is fine.

But I think we should also set this bit in the cache-l2x0.c file if PL310. That's such a fundamental issue and it's easy to miss in the platform code.

Signature · 1 line

Catalin

shiraz hashim

2012-08-13 07:21 UTC #2 lore raw

PATCH 1/1 ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register

Hi Catalin,

Quoted 8 lines · Catalin Marinas

Quoted 6 lines · Kukjin Kim

arch/arm/mach-s5pv310/cpu.c +0 -0

@@ -168,7 +168,7 @@ static int __init s5pv310_l2x0_cache_init(void)
        __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
                     S5P_VA_L2CC + L2X0_POWER_CTRL);

Quoted 8 lines

arch/arm/mach-s5pv310/cpu.c static int __init s5pv310_l2x0_cache_init(void) · line 171
Quoted 2 lines
arch/arm/mach-s5pv310/cpu.c +1 -1
-       l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff);
+       l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
The patch is fine.
But I think we should also set this bit in the cache-l2x0.c file if PL310. That's such a fundamental issue and it's easy to miss in the platform code.

Sorry for reviving this old patch but any reasons why it didn't go to the cache-l2x0.c directly (for PL310).

--
regards
Shiraz Hashim

Catalin Marinas

2012-08-13 07:39 UTC #3 lore raw

PATCH 1/1 ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register

Quoted 15 lines · shiraz hashim

Quoted 13 lines · Catalin Marinas
arch/arm/mach-s5pv310/cpu.c static int __init s5pv310_l2x0_cache_init(void) · line 171
Quoted 8 lines · Kukjin Kim
arch/arm/mach-s5pv310/cpu.c +1 -1
@@ -168,7 +168,7 @@ static int __init s5pv310_l2x0_cache_init(void)
        __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
                     S5P_VA_L2CC + L2X0_POWER_CTRL);
 
-       l2x0_init(S5P_VA_L2CC, 0x7C070001, 0xC200ffff);
+       l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
The patch is fine.

Quoted 6 lines

Quoted 3 lines
But I think we should also set this bit in the cache-l2x0.c file if PL310. That's such a fundamental issue and it's easy to miss in the platform code.
Sorry for reviving this old patch but any reasons why it didn't go to the cache-l2x0.c directly (for PL310).

The cache-l2x0.c patch has been around for a while:

http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=6529/1

It may no longer apply cleanly but I haven't revived it since it wasn't accepted at the time.

Signature · 1 line

Catalin