mx5: Fix clocks

The imx_decode_pll() function does not exist for mx5, so remove its declaration.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---

Use clock gate definitions having names showing clearly the gated clock instead of names giving only a register field index.

This change reveals that the USB PHY clock functions were broken on i.MX51, so this patch fixes those too.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Marek Vasut <[email protected]>

---
 .../arch/arm/cpu/armv7/mx5/clock.c                 |   39 ++++-
 .../arch/arm/include/asm/arch-mx5/clock.h          |    7 +
 .../arch/arm/include/asm/arch-mx5/crm_regs.h       |  158
+++++++++++++++++++- .../drivers/usb/host/ehci-mx5.c                    | 
  5 +
 .../drivers/video/ipu_common.c                     |    2 +-
 5 files changed, 200 insertions(+), 11 deletions(-)

(quoted diff) +0 -0

u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c index c67c3cf..9b083c0 100644

arch/arm/cpu/armv7/mx5/clock.c +1 -1

 	else
-		reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
+		reg |= MXC_CCM_CCGR_CG_OFF << MXC_CCM_CCGR2_USBOH3_60M_OFFSET;
 	writel(reg, &mxc_ccm->CCGR2);
 }
 

@@ -137,6 +138,29 @@ int enable_i2c_clk(unsigned char enable, unsigned
 i2c_num) }

Dear Beno?t Th?baudeau,

Quoted 7 lines

Use clock gate definitions having names showing clearly the gated clock
instead of names giving only a register field index.

This change reveals that the USB PHY clock functions were broken on i.MX51,
so this patch fixes those too.

Expanding CC /wrt this mx51 usb biz.

Quoted 22 lines

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Marek Vasut <[email protected]>

---
 .../arch/arm/cpu/armv7/mx5/clock.c                 |   39 ++++-
 .../arch/arm/include/asm/arch-mx5/clock.h          |    7 +
 .../arch/arm/include/asm/arch-mx5/crm_regs.h       |  158
+++++++++++++++++++- .../drivers/usb/host/ehci-mx5.c
                   |
  5 +
 .../drivers/video/ipu_common.c                     |    2 +-
 5 files changed, 200 insertions(+), 11 deletions(-)

(quoted diff) +0 -0

u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/clock.c index c67c3cf..9b083c0
100644

arch/arm/cpu/armv7/mx5/clock.c +0 -0

@@ -110,10 +110,11 @@ void enable_usboh3_clk(unsigned char enable)
 	unsigned int reg;
 

arch/arm/cpu/armv7/mx5/clock.c void enable_usboh3_clk(unsigned char enable) · line 114

Quoted 3 lines

arch/arm/cpu/armv7/mx5/clock.c +1 -0

 	reg = readl(&mxc_ccm->CCGR2);
+	reg &= ~(MXC_CCM_CCGR_CG_MASK <<
 MXC_CCM_CCGR2_USBOH3_60M_OFFSET);

What's this addition?

arch/arm/cpu/armv7/mx5/clock.c void enable_usboh3_clk(unsigned char enable) · line 115

Quoted 3 lines

arch/arm/cpu/armv7/mx5/clock.c +1 -1

 	if (enable)
-		reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET;
+		reg |= MXC_CCM_CCGR_CG_ON << MXC_CCM_CCGR2_USBOH3_60M_OFFSET;

Can't you make it like ... MXC_CCM_CCGR2_USBOH3_60M(<on/off>) ... which would
emit the correct bit? So you'd wrap the bitshift into it as well ... also, using
clrsetbits_le32() won't hurt here.

Quoted 11 lines

arch/arm/cpu/armv7/mx5/clock.c +1 -1

 	else
-		reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
+		reg |= MXC_CCM_CCGR_CG_OFF << MXC_CCM_CCGR2_USBOH3_60M_OFFSET;
 	writel(reg, &mxc_ccm->CCGR2);
 }

@@ -137,6 +138,29 @@ int enable_i2c_clk(unsigned char enable,

unsigned
i2c_num) }
#endif

arch/arm/cpu/armv7/mx5/clock.c int enable_i2c_clk(unsigned char enable, unsigned i2c_num) · line 148

Quoted 8 lines

arch/arm/cpu/armv7/mx5/clock.c +8 -0

+#if defined(CONFIG_MX51)
+void set_usb_phy_clk(void)
+{
+	unsigned int reg;
+
+	reg = readl(&mxc_ccm->cscmr1);
+	reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
+	writel(reg, &mxc_ccm->cscmr1);

clrbits_le32() etc., please fix globally.

This doesn't even fit into this patch, so please split away. [...]

Clean up the i.MX5 clock driver:
- Use readl() and writel() instead of their __raw_ counterparts.
- Use the clr/setbits_le32() family of macros rather than expanding code.
- Use accessor macros for bit-fields instead of _MASK and _OFFSET.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2:
- New patch.

 .../arch/arm/cpu/armv7/mx5/clock.c                 |  237 ++++++++------------
 .../arch/arm/include/asm/arch-mx5/crm_regs.h       |   99 +++++++-
 2 files changed, 184 insertions(+), 152 deletions(-)

arch/arm/cpu/armv7/mx5/clock.c +91 -146

index 1f95536..5fca775 100644
@@ -89,94 +89,65 @@ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 
 void set_usboh3_clk(void)
 {
-	unsigned int reg;
-
-	reg = readl(&mxc_ccm->cscmr1) &
-		 ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
-	reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
-	writel(reg, &mxc_ccm->cscmr1);
-
-	reg = readl(&mxc_ccm->cscdr1);
-	reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
-	reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
-	reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
-	reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
-
-	writel(reg, &mxc_ccm->cscdr1);
+	clrsetbits_le32(&mxc_ccm->cscmr1,
+			MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
+			MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
+	clrsetbits_le32(&mxc_ccm->cscdr1,
+			MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
+			MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
+			MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
+			MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
 }
 
 void enable_usboh3_clk(unsigned char enable)
 {
-	unsigned int reg;
-
-	reg = readl(&mxc_ccm->CCGR2);
 	if (enable)
-		reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET;
+		setbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
 	else
-		reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
-	writel(reg, &mxc_ccm->CCGR2);
+		clrbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
 }
 
 #ifdef CONFIG_I2C_MXC
 /* i2c_num can be from 0 - 2 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
-	u32 reg;
 	u32 mask;
 
 	if (i2c_num > 2)
 		return -EINVAL;
 	mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 9) << 1);
-	reg = __raw_readl(&mxc_ccm->CCGR1);
 	if (enable)
-		reg |= mask;
+		setbits_le32(&mxc_ccm->CCGR1, mask);
 	else
-		reg &= ~mask;
-	__raw_writel(reg, &mxc_ccm->CCGR1);
+		clrbits_le32(&mxc_ccm->CCGR1, mask);
 	return 0;
 }
 #endif
 
 void set_usb_phy1_clk(void)
 {
-	unsigned int reg;
-
-	reg = readl(&mxc_ccm->cscmr1);
-	reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
-	writel(reg, &mxc_ccm->cscmr1);
+	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
 }
 
 void enable_usb_phy1_clk(unsigned char enable)
 {
-	unsigned int reg;
-
-	reg = readl(&mxc_ccm->CCGR4);
 	if (enable)
-		reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET;
+		setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
 	else
-		reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET);
-	writel(reg, &mxc_ccm->CCGR4);
+		clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
 }
 
 void set_usb_phy2_clk(void)
 {
-	unsigned int reg;
-
-	reg = readl(&mxc_ccm->cscmr1);
-	reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
-	writel(reg, &mxc_ccm->cscmr1);
+	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
 }
 
 void enable_usb_phy2_clk(unsigned char enable)
 {
-	unsigned int reg;
-
-	reg = readl(&mxc_ccm->CCGR4);
 	if (enable)
-		reg |= 1 << MXC_CCM_CCGR4_CG6_OFFSET;
+		setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
 	else
-		reg &= ~(1 << MXC_CCM_CCGR4_CG6_OFFSET);
-	writel(reg, &mxc_ccm->CCGR4);
+		clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
 }
 
 /*

@@ -191,19 +162,19 @@ static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
 	ctrl = readl(&pll->ctrl);
 
 	if (ctrl & MXC_DPLLC_CTL_HFSM) {
-		mfn = __raw_readl(&pll->hfs_mfn);
-		mfd = __raw_readl(&pll->hfs_mfd);
-		op = __raw_readl(&pll->hfs_op);
+		mfn = readl(&pll->hfs_mfn);
+		mfd = readl(&pll->hfs_mfd);
+		op = readl(&pll->hfs_op);
 	} else {
-		mfn = __raw_readl(&pll->mfn);
-		mfd = __raw_readl(&pll->mfd);
-		op = __raw_readl(&pll->op);
+		mfn = readl(&pll->mfn);
+		mfd = readl(&pll->mfd);
+		op = readl(&pll->op);
 	}
 
 	mfd &= MXC_DPLLC_MFD_MFD_MASK;
 	mfn &= MXC_DPLLC_MFN_MFN_MASK;
 	pdf = op & MXC_DPLLC_OP_PDF_MASK;
-	mfi = (op & MXC_DPLLC_OP_MFI_MASK) >> MXC_DPLLC_OP_MFI_OFFSET;
+	mfi = MXC_DPLLC_OP_MFI_RD(op);
 
 	/* 21.2.3 */
 	if (mfi < 5)

@@ -240,8 +211,7 @@ u32 get_mcu_main_clk(void)
 {
 	u32 reg, freq;
 
-	reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
-		MXC_CCM_CACRR_ARM_PODF_OFFSET;
+	reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
 	freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 	return freq / (reg + 1);
 }

@@ -253,12 +223,11 @@ u32 get_periph_clk(void)
 {
 	u32 reg;
 
-	reg = __raw_readl(&mxc_ccm->cbcdr);
+	reg = readl(&mxc_ccm->cbcdr);
 	if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
 		return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
-	reg = __raw_readl(&mxc_ccm->cbcmr);
-	switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
-		MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
+	reg = readl(&mxc_ccm->cbcmr);
+	switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
 	case 0:
 		return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 	case 1:

@@ -278,9 +247,8 @@ static u32 get_ipg_clk(void)
 
 	freq = get_ahb_clk();
 
-	reg = __raw_readl(&mxc_ccm->cbcdr);
-	div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
-			MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
+	reg = readl(&mxc_ccm->cbcdr);
+	div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
 
 	return freq / div;
 }

@@ -292,17 +260,13 @@ static u32 get_ipg_per_clk(void)
 {
 	u32 pred1, pred2, podf;
 
-	if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
+	if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
 		return get_ipg_clk();
 	/* Fixme: not handle what about lpm*/
-	podf = __raw_readl(&mxc_ccm->cbcdr);
-	pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
-		MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
-	pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
-		MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
-	podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
-		MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
-
+	podf = readl(&mxc_ccm->cbcdr);
+	pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
+	pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
+	podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
 	return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
 }
 

@@ -313,9 +277,8 @@ static u32 get_uart_clk(void)
 {
 	unsigned int freq, reg, pred, podf;
 
-	reg = __raw_readl(&mxc_ccm->cscmr1);
-	switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
-		MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
+	reg = readl(&mxc_ccm->cscmr1);
+	switch (MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg)) {
 	case 0x0:
 		freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 		break;

@@ -329,13 +292,9 @@ static u32 get_uart_clk(void)
 		return 66500000;
 	}
 
-	reg = __raw_readl(&mxc_ccm->cscdr1);
-
-	pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
-		MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
-
-	podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
-		MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
+	reg = readl(&mxc_ccm->cscdr1);
+	pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
+	podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
 	freq /= (pred + 1) * (podf + 1);
 
 	return freq;

@@ -347,7 +306,7 @@ static u32 get_uart_clk(void)
 static u32 get_lp_apm(void)
 {
 	u32 ret_val = 0;
-	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
+	u32 ccsr = readl(&mxc_ccm->ccsr);
 
 	if (((ccsr >> 9) & 1) == 0)
 		ret_val = MXC_HCLK;

@@ -363,15 +322,12 @@ static u32 get_lp_apm(void)
 static u32 imx_get_cspiclk(void)
 {
 	u32 ret_val = 0, pdf, pre_pdf, clk_sel;
-	u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
-	u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
+	u32 cscmr1 = readl(&mxc_ccm->cscmr1);
+	u32 cscdr2 = readl(&mxc_ccm->cscdr2);
 
-	pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
-			>> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
-	pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
-			>> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
-	clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
-			>> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
+	pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
+	pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
+	clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
 
 	switch (clk_sel) {
 	case 0:

@@ -396,28 +352,25 @@ static u32 imx_get_cspiclk(void)
 
 static u32 get_axi_a_clk(void)
 {
-	u32 cbcdr =  __raw_readl(&mxc_ccm->cbcdr);
-	u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \
-			>> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
+	u32 cbcdr = readl(&mxc_ccm->cbcdr);
+	u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
 
 	return  get_periph_clk() / (pdf + 1);
 }
 
 static u32 get_axi_b_clk(void)
 {
-	u32 cbcdr =  __raw_readl(&mxc_ccm->cbcdr);
-	u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \
-			>> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
+	u32 cbcdr = readl(&mxc_ccm->cbcdr);
+	u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
 
 	return  get_periph_clk() / (pdf + 1);
 }
 
 static u32 get_emi_slow_clk(void)
 {
-	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+	u32 cbcdr = readl(&mxc_ccm->cbcdr);
 	u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
-	u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \
-			>> MXC_CCM_CBCDR_EMI_PODF_OFFSET;
+	u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
 
 	if (emi_clk_sel)
 		return  get_ahb_clk() / (pdf + 1);

@@ -428,14 +381,12 @@ static u32 get_emi_slow_clk(void)
 static u32 get_ddr_clk(void)
 {
 	u32 ret_val = 0;
-	u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
-	u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \
-				>> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
+	u32 cbcmr = readl(&mxc_ccm->cbcmr);
+	u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
 #ifdef CONFIG_MX51
-	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+	u32 cbcdr = readl(&mxc_ccm->cbcdr);
 	if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
-		u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \
-					MXC_CCM_CBCDR_DDR_PODF_OFFSET;
+		u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
 
 		ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
 		ret_val /= ddr_clk_podf + 1;

@@ -603,62 +554,62 @@ static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
 
 #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
 	{	\
-		__raw_writel(0x1232, &pll->ctrl);		\
-		__raw_writel(0x2, &pll->config);		\
-		__raw_writel((((pd) - 1) << 0) | ((fi) << 4),	\
-			&pll->op);				\
-		__raw_writel(fn, &(pll->mfn));			\
-		__raw_writel((fd) - 1, &pll->mfd);		\
-		__raw_writel((((pd) - 1) << 0) | ((fi) << 4),	\
-			&pll->hfs_op);				\
-		__raw_writel(fn, &pll->hfs_mfn);		\
-		__raw_writel((fd) - 1, &pll->hfs_mfd);		\
-		__raw_writel(0x1232, &pll->ctrl);		\
-		while (!__raw_readl(&pll->ctrl) & 0x1)		\
+		writel(0x1232, &pll->ctrl);		\
+		writel(0x2, &pll->config);		\
+		writel((((pd) - 1) << 0) | ((fi) << 4),	\
+			&pll->op);			\
+		writel(fn, &(pll->mfn));		\
+		writel((fd) - 1, &pll->mfd);		\
+		writel((((pd) - 1) << 0) | ((fi) << 4),	\
+			&pll->hfs_op);			\
+		writel(fn, &pll->hfs_mfn);		\
+		writel((fd) - 1, &pll->hfs_mfd);	\
+		writel(0x1232, &pll->ctrl);		\
+		while (!readl(&pll->ctrl) & 0x1)	\
 			;\
 	}
 
 static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
 {
-	u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
+	u32 ccsr = readl(&mxc_ccm->ccsr);
 	struct mxc_pll_reg *pll = mxc_plls[index];
 
 	switch (index) {
 	case PLL1_CLOCK:
 		/* Switch ARM to PLL2 clock */
-		__raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
+		writel(ccsr | 0x4, &mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		__raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
+		writel(ccsr & ~0x4, &mxc_ccm->ccsr);
 		break;
 	case PLL2_CLOCK:
 		/* Switch to pll2 bypass clock */
-		__raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
+		writel(ccsr | 0x2, &mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		__raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
+		writel(ccsr & ~0x2, &mxc_ccm->ccsr);
 		break;
 	case PLL3_CLOCK:
 		/* Switch to pll3 bypass clock */
-		__raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
+		writel(ccsr | 0x1, &mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		__raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
+		writel(ccsr & ~0x1, &mxc_ccm->ccsr);
 		break;
 	case PLL4_CLOCK:
 		/* Switch to pll4 bypass clock */
-		__raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
+		writel(ccsr | 0x20, &mxc_ccm->ccsr);
 		CHANGE_PLL_SETTINGS(pll, pll_param->pd,
 					pll_param->mfi, pll_param->mfn,
 					pll_param->mfd);
 		/* Switch back */
-		__raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
+		writel(ccsr & ~0x20, &mxc_ccm->ccsr);
 		break;
 	default:
 		return -EINVAL;

@@ -687,7 +638,6 @@ static int config_core_clk(u32 ref, u32 freq)
 
 static int config_nfc_clk(u32 nfc_clk)
 {
-	u32 reg;
 	u32 parent_rate = get_emi_slow_clk();
 	u32 div = parent_rate / nfc_clk;
 

@@ -697,11 +647,10 @@ static int config_nfc_clk(u32 nfc_clk)
 		div++;
 	if (parent_rate / div > NFC_CLK_MAX)
 		div++;
-	reg = __raw_readl(&mxc_ccm->cbcdr);
-	reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
-	reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
-	__raw_writel(reg, &mxc_ccm->cbcdr);
-	while (__raw_readl(&mxc_ccm->cdhipr) != 0)
+	clrsetbits_le32(&mxc_ccm->cbcdr,
+			MXC_CCM_CBCDR_NFC_PODF_MASK,
+			MXC_CCM_CBCDR_NFC_PODF(div - 1));
+	while (readl(&mxc_ccm->cdhipr) != 0)
 		;
 	return 0;
 }

@@ -714,16 +663,15 @@ static int config_periph_clk(u32 ref, u32 freq)
 
 	memset(&pll_param, 0, sizeof(struct pll_param));
 
-	if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+	if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
 		ret = calc_pll_params(ref, freq, &pll_param);
 		if (ret != 0) {
 			printf("Error:Can't find pll parameters: %d\n",
 				ret);
 			return ret;
 		}
-		switch ((__raw_readl(&mxc_ccm->cbcmr) & \
-			MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \
-			MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
+		switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
+				readl(&mxc_ccm->cbcmr))) {
 		case 0:
 			return config_pll_clk(PLL1_CLOCK, &pll_param);
 			break;

@@ -742,8 +690,7 @@ static int config_ddr_clk(u32 emi_clk)
 {
 	u32 clk_src;
 	s32 shift = 0, clk_sel, div = 1;
-	u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
-	u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+	u32 cbcmr = readl(&mxc_ccm->cbcmr);
 
 	if (emi_clk > MAX_DDR_CLK) {
 		printf("Warning:DDR clock should not exceed %d MHz\n",

@@ -753,7 +700,7 @@ static int config_ddr_clk(u32 emi_clk)
 
 	clk_src = get_periph_clk();
 	/* Find DDR clock input */
-	clk_sel = (cbcmr >> 10) & 0x3;
+	clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
 	switch (clk_sel) {
 	case 0:
 		shift = 16;

@@ -778,12 +725,10 @@ static int config_ddr_clk(u32 emi_clk)
 	if (div > 8)
 		div = 8;
 
-	cbcdr = cbcdr & ~(0x7 << shift);
-	cbcdr |= ((div - 1) << shift);
-	__raw_writel(cbcdr, &mxc_ccm->cbcdr);
-	while (__raw_readl(&mxc_ccm->cdhipr) != 0)
+	clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
+	while (readl(&mxc_ccm->cdhipr) != 0)
 		;
-	__raw_writel(0x0, &mxc_ccm->ccdr);
+	writel(0x0, &mxc_ccm->ccdr);
 
 	return 0;
 }

@@ -856,7 +801,7 @@ void mxc_set_sata_internal_clock(void)
 
 	set_usb_phy1_clk();
 
-	writel((readl(tmp_base) & (~0x6)) | 0x4, tmp_base);
+	clrsetbits_le32(tmp_base, 0x6, 0x4);
 }
 #endif
 

arch/arm/include/asm/arch-mx5/crm_regs.h +90 -5

index 4e0fc1b..ab0e818 100644
@@ -85,115 +85,200 @@ struct mxc_ccm_reg {
 /* Define the bits in register CACRR */
 #define MXC_CCM_CACRR_ARM_PODF_OFFSET		0
 #define MXC_CCM_CACRR_ARM_PODF_MASK		0x7
+#define MXC_CCM_CACRR_ARM_PODF(v)		((v) & 0x7)
+#define MXC_CCM_CACRR_ARM_PODF_RD(r)		((r) & 0x7)
 
 /* Define the bits in register CBCDR */
 #define MXC_CCM_CBCDR_DDR_HIFREQ_SEL		(0x1 << 30)
-#define MXC_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
 #define MXC_CCM_CBCDR_DDR_PODF_OFFSET		27
+#define MXC_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
+#define MXC_CCM_CBCDR_DDR_PODF(v)		(((v) & 0x7) << 27)
+#define MXC_CCM_CBCDR_DDR_PODF_RD(r)		(((r) >> 27) & 0x7)
 #define MXC_CCM_CBCDR_EMI_CLK_SEL		(0x1 << 26)
 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET		22
 #define MXC_CCM_CBCDR_EMI_PODF_MASK		(0x7 << 22)
+#define MXC_CCM_CBCDR_EMI_PODF(v)		(((v) & 0x7) << 22)
+#define MXC_CCM_CBCDR_EMI_PODF_RD(r)		(((r) >> 22) & 0x7)
 #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET		19
 #define MXC_CCM_CBCDR_AXI_B_PODF_MASK		(0x7 << 19)
+#define MXC_CCM_CBCDR_AXI_B_PODF(v)		(((v) & 0x7) << 19)
+#define MXC_CCM_CBCDR_AXI_B_PODF_RD(r)		(((r) >> 19) & 0x7)
 #define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET		16
 #define MXC_CCM_CBCDR_AXI_A_PODF_MASK		(0x7 << 16)
+#define MXC_CCM_CBCDR_AXI_A_PODF(v)		(((v) & 0x7) << 16)
+#define MXC_CCM_CBCDR_AXI_A_PODF_RD(r)		(((r) >> 16) & 0x7)
 #define MXC_CCM_CBCDR_NFC_PODF_OFFSET		13
 #define MXC_CCM_CBCDR_NFC_PODF_MASK		(0x7 << 13)
+#define MXC_CCM_CBCDR_NFC_PODF(v)		(((v) & 0x7) << 13)
+#define MXC_CCM_CBCDR_NFC_PODF_RD(r)		(((r) >> 13) & 0x7)
 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET		10
 #define MXC_CCM_CBCDR_AHB_PODF_MASK		(0x7 << 10)
+#define MXC_CCM_CBCDR_AHB_PODF(v)		(((v) & 0x7) << 10)
+#define MXC_CCM_CBCDR_AHB_PODF_RD(r)		(((r) >> 10) & 0x7)
 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET		8
 #define MXC_CCM_CBCDR_IPG_PODF_MASK		(0x3 << 8)
+#define MXC_CCM_CBCDR_IPG_PODF(v)		(((v) & 0x3) << 8)
+#define MXC_CCM_CBCDR_IPG_PODF_RD(r)		(((r) >> 8) & 0x3)
 #define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET	6
 #define MXC_CCM_CBCDR_PERCLK_PRED1_MASK		(0x3 << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1(v)		(((v) & 0x3) << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r)	(((r) >> 6) & 0x3)
 #define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET	3
 #define MXC_CCM_CBCDR_PERCLK_PRED2_MASK		(0x7 << 3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2(v)		(((v) & 0x7) << 3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r)	(((r) >> 3) & 0x7)
 #define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET	0
 #define MXC_CCM_CBCDR_PERCLK_PODF_MASK		0x7
+#define MXC_CCM_CBCDR_PERCLK_PODF(v)		((v) & 0x7)
+#define MXC_CCM_CBCDR_PERCLK_PODF_RD(r)		((r) & 0x7)
 
 /* Define the bits in register CSCMR1 */
 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET		30
 #define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK		(0x3 << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v)		(((v) & 0x3) << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r)		(((r) >> 30) & 0x3)
 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET		28
 #define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK		(0x3 << 28)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET		26
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v)		(((v) & 0x3) << 28)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r)		(((r) >> 28) & 0x3)
 #define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL			(0x1 << 26)
 #define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET		24
 #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK		(0x3 << 24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r)		(((r) >> 24) & 0x3)
 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET		22
 #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK		(0x3 << 22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v)		(((v) & 0x3) << 22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r)		(((r) >> 22) & 0x3)
 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET	20
 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK	(0x3 << 20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v)		(((v) & 0x3) << 20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r)	(((r) >> 20) & 0x3)
 #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL			(0x1 << 19)
 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 18)
 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET	16
 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK	(0x3 << 16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v)		(((v) & 0x3) << 16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r)	(((r) >> 16) & 0x3)
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		14
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r)		(((r) >> 14) & 0x3)
 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		12
 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r)		(((r) >> 12) & 0x3)
 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL			(0x1 << 11)
 #define MXC_CCM_CSCMR1_VPU_RCLK_SEL			(0x1 << 10)
 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET		8
 #define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v)		(((v) & 0x3) << 8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r)		(((r) >> 8) & 0x3)
 #define MXC_CCM_CSCMR1_TVE_CLK_SEL			(0x1 << 7)
 #define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL			(0x1 << 6)
 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET		4
 #define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK		(0x3 << 4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r)		(((r) >> 4) & 0x3)
 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET		2
 #define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK		(0x3 << 2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r)		(((r) >> 2) & 0x3)
 #define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL		(0x1 << 1)
 #define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL		0x1
 
 /* Define the bits in register CSCDR2 */
 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET		25
 #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK		(0x7 << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v)			(((v) & 0x7) << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r)		(((r) >> 25) & 0x7)
 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET		19
 #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK		(0x3F << 19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v)			(((v) & 0x3F) << 19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r)		(((r) >> 19) & 0x3F)
 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET		16
 #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK		(0x7 << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED(v)			(((v) & 0x7) << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r)		(((r) >> 16) & 0x7)
 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET		9
 #define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK		(0x3F << 9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF(v)			(((v) & 0x3F) << 9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r)		(((r) >> 9) & 0x3F)
 #define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET		6
-#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK		(0x7 << 6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET		0
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK		0x3F
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK		(0x7 << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v)		(((v) & 0x7) << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r)		(((r) >> 6) & 0x7)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET		0
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK		0x3F
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v)		((v) & 0x3F)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r)		((r) & 0x3F)
 
 /* Define the bits in register CBCMR */
 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET		14
 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v)		(((v) & 0x3) << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r)		(((r) >> 14) & 0x3)
 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET		12
 #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK		(0x3 << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r)		(((r) >> 12) & 0x3)
 #define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET		10
 #define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK			(0x3 << 10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r)			(((r) >> 10) & 0x3)
 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET		8
 #define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v)		(((v) & 0x3) << 8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r)		(((r) >> 8) & 0x3)
 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET		6
 #define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK		(0x3 << 6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v)		(((v) & 0x3) << 6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r)		(((r) >> 6) & 0x3)
 #define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET		4
 #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK			(0x3 << 4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r)			(((r) >> 4) & 0x3)
 #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL		(0x1 << 1)
 #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL		(0x1 << 0)
 
 /* Define the bits in register CSCDR1 */
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET	22
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK	(0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v)		(((v) & 0x7) << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r)	(((r) >> 22) & 0x7)
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET	19
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK	(0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v)		(((v) & 0x7) << 19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r)	(((r) >> 19) & 0x7)
 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET	16
 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK	(0x7 << 16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v)		(((v) & 0x7) << 16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r)	(((r) >> 16) & 0x7)
 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET		14
 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK		(0x3 << 14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r)		(((r) >> 14) & 0x3)
 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET	11
 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK	(0x7 << 11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v)		(((v) & 0x7) << 11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r)	(((r) >> 11) & 0x7)
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		8
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v)		(((v) & 0x7) << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r)		(((r) >> 8) & 0x7)
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v)		(((v) & 0x3) << 6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r)		(((r) >> 6) & 0x3)
 #define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET		3
 #define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK		(0x7 << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED(v)			(((v) & 0x7) << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r)		(((r) >> 3) & 0x7)
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		0
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		0x7
+#define MXC_CCM_CSCDR1_UART_CLK_PODF(v)			((v) & 0x7)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r)		((r) & 0x7)
 
 /* Define the bits in register CCDR */
 #define MXC_CCM_CCDR_IPU_HS_MASK			(0x1 << 17)

@@ -213,8 +298,10 @@ struct mxc_ccm_reg {
 #define	MXC_DPLLC_CTL_DPDCK0_2_EN			(1 << 12)

Use clock gate definitions having names showing clearly the gated clock instead of names giving only a register field index.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---
This change reveals (clock.c won't build) that the USB PHY clock functions were broken on i.MX51, which is fixed by the following 2 patches.

This patch supersedes http://patchwork.ozlabs.org/patch/177403/ . Changes for v2:
- Split patch into 3 parts (the 3, 4 and 5 from this v2 series).
- Use the created definitions for enable_i2c_clk().

 .../arch/arm/cpu/armv7/mx5/clock.c                 |   15 +-
 .../arch/arm/include/asm/arch-mx5/crm_regs.h       |  279 +++++++++++++++++++-
 .../drivers/video/ipu_common.c                     |    2 +-
 3 files changed, 284 insertions(+), 12 deletions(-)

arch/arm/cpu/armv7/mx5/clock.c +2 -2

index 5fca775..32a69d4 100644
@@ -102,9 +102,9 @@ void set_usboh3_clk(void)
 void enable_usboh3_clk(unsigned char enable)
 {
 	if (enable)
-		setbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
+		setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_USBOH3_60M(1));
 	else
-		clrbits_le32(&mxc_ccm->CCGR2, 1 << MXC_CCM_CCGR2_CG14_OFFSET);
+		clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_USBOH3_60M(1));
 }
 
 #ifdef CONFIG_I2C_MXC

arch/arm/cpu/armv7/mx5/clock.c +4 -4

 	if (enable)
 		setbits_le32(&mxc_ccm->CCGR1, mask);
 	else

@@ -132,9 +133,9 @@ void set_usb_phy1_clk(void)
 void enable_usb_phy1_clk(unsigned char enable)
 {
 	if (enable)
-		setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
+		setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY1(1));
 	else
-		clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG5_OFFSET);
+		clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY1(1));
 }
 
 void set_usb_phy2_clk(void)

@@ -145,9 +146,9 @@ void set_usb_phy2_clk(void)
 void enable_usb_phy2_clk(unsigned char enable)
 {
 	if (enable)
-		setbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
+		setbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY2(1));
 	else
-		clrbits_le32(&mxc_ccm->CCGR4, 1 << MXC_CCM_CCGR4_CG6_OFFSET);
+		clrbits_le32(&mxc_ccm->CCGR4, MXC_CCM_CCGR4_USB_PHY2(1));
 }
 
 /*

arch/arm/include/asm/arch-mx5/crm_regs.h +275 -4

index ab0e818..d5eb303 100644
@@ -286,10 +286,281 @@ struct mxc_ccm_reg {
 /* Define the bits in register CCGRx */
 #define MXC_CCM_CCGR_CG_MASK				0x3
 
-#define MXC_CCM_CCGR4_CG5_OFFSET			10
-#define MXC_CCM_CCGR4_CG6_OFFSET			12
-#define MXC_CCM_CCGR5_CG5_OFFSET			10
-#define MXC_CCM_CCGR2_CG14_OFFSET			28
+#define MXC_CCM_CCGR0_ARM_BUS_OFFSET			0
+#define MXC_CCM_CCGR0_ARM_BUS(v)			(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR0_ARM_AXI_OFFSET			2
+#define MXC_CCM_CCGR0_ARM_AXI(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET			4
+#define MXC_CCM_CCGR0_ARM_DEBUG(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR0_TZIC_OFFSET			6
+#define MXC_CCM_CCGR0_TZIC(v)				(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR0_DAP_OFFSET			8
+#define MXC_CCM_CCGR0_DAP(v)				(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR0_TPIU_OFFSET			10
+#define MXC_CCM_CCGR0_TPIU(v)				(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR0_CTI2_OFFSET			12
+#define MXC_CCM_CCGR0_CTI2(v)				(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR0_CTI3_OFFSET			14
+#define MXC_CCM_CCGR0_CTI3(v)				(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR0_AHBMUX1_OFFSET			16
+#define MXC_CCM_CCGR0_AHBMUX1(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR0_AHBMUX2_OFFSET			18
+#define MXC_CCM_CCGR0_AHBMUX2(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR0_ROMCP_OFFSET			20
+#define MXC_CCM_CCGR0_ROMCP(v)				(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR0_ROM_OFFSET			22
+#define MXC_CCM_CCGR0_ROM(v)				(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET			24
+#define MXC_CCM_CCGR0_AIPS_TZ1(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET			26
+#define MXC_CCM_CCGR0_AIPS_TZ2(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR0_AHB_MAX_OFFSET			28
+#define MXC_CCM_CCGR0_AHB_MAX(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR0_IIM_OFFSET			30
+#define MXC_CCM_CCGR0_IIM(v)				(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR1_TMAX1_OFFSET			0
+#define MXC_CCM_CCGR1_TMAX1(v)				(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR1_TMAX2_OFFSET			2
+#define MXC_CCM_CCGR1_TMAX2(v)				(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR1_TMAX3_OFFSET			4
+#define MXC_CCM_CCGR1_TMAX3(v)				(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR1_UART1_IPG_OFFSET			6
+#define MXC_CCM_CCGR1_UART1_IPG(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR1_UART1_PER_OFFSET			8
+#define MXC_CCM_CCGR1_UART1_PER(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR1_UART2_IPG_OFFSET			10
+#define MXC_CCM_CCGR1_UART2_IPG(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR1_UART2_PER_OFFSET			12
+#define MXC_CCM_CCGR1_UART2_PER(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR1_UART3_IPG_OFFSET			14
+#define MXC_CCM_CCGR1_UART3_IPG(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR1_UART3_PER_OFFSET			16
+#define MXC_CCM_CCGR1_UART3_PER(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR1_I2C1_OFFSET			18
+#define MXC_CCM_CCGR1_I2C1(v)				(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR1_I2C2_OFFSET			20
+#define MXC_CCM_CCGR1_I2C2(v)				(((v) & 0x3) << 20)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET			22
+#define MXC_CCM_CCGR1_HSI2C_IPG(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET		24
+#define MXC_CCM_CCGR1_HSI2C_SERIAL(v)			(((v) & 0x3) << 24)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR1_I2C3_OFFSET			22
+#define MXC_CCM_CCGR1_I2C3(v)				(((v) & 0x3) << 22)
+#endif
+#define MXC_CCM_CCGR1_FIRI_IPG_OFFSET			26
+#define MXC_CCM_CCGR1_FIRI_IPG(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET		28
+#define MXC_CCM_CCGR1_FIRI_SERIAL(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR1_SCC_OFFSET			30
+#define MXC_CCM_CCGR1_SCC(v)				(((v) & 0x3) << 30)
+
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR2_USB_PHY_OFFSET			0
+#define MXC_CCM_CCGR2_USB_PHY(v)			(((v) & 0x3) << 0)
+#endif
+#define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET			2
+#define MXC_CCM_CCGR2_EPIT1_IPG(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR2_EPIT1_HF_OFFSET			4
+#define MXC_CCM_CCGR2_EPIT1_HF(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET			6
+#define MXC_CCM_CCGR2_EPIT2_IPG(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR2_EPIT2_HF_OFFSET			8
+#define MXC_CCM_CCGR2_EPIT2_HF(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR2_PWM1_IPG_OFFSET			10
+#define MXC_CCM_CCGR2_PWM1_IPG(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR2_PWM1_HF_OFFSET			12
+#define MXC_CCM_CCGR2_PWM1_HF(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR2_PWM2_IPG_OFFSET			14
+#define MXC_CCM_CCGR2_PWM2_IPG(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR2_PWM2_HF_OFFSET			16
+#define MXC_CCM_CCGR2_PWM2_HF(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR2_GPT_IPG_OFFSET			18
+#define MXC_CCM_CCGR2_GPT_IPG(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR2_GPT_HF_OFFSET			20
+#define MXC_CCM_CCGR2_GPT_HF(v)				(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR2_OWIRE_OFFSET			22
+#define MXC_CCM_CCGR2_OWIRE(v)				(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR2_FEC_OFFSET			24
+#define MXC_CCM_CCGR2_FEC(v)				(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET		26
+#define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR2_USBOH3_60M_OFFSET			28
+#define MXC_CCM_CCGR2_USBOH3_60M(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR2_TVE_OFFSET			30
+#define MXC_CCM_CCGR2_TVE(v)				(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET			0
+#define MXC_CCM_CCGR3_ESDHC1_IPG(v)			(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET			2
+#define MXC_CCM_CCGR3_ESDHC1_PER(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET			4
+#define MXC_CCM_CCGR3_ESDHC2_IPG(v)			(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET			6
+#define MXC_CCM_CCGR3_ESDHC2_PER(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET			8
+#define MXC_CCM_CCGR3_ESDHC3_IPG(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET			10
+#define MXC_CCM_CCGR3_ESDHC3_PER(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET			12
+#define MXC_CCM_CCGR3_ESDHC4_IPG(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET			14
+#define MXC_CCM_CCGR3_ESDHC4_PER(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR3_SSI1_IPG_OFFSET			16
+#define MXC_CCM_CCGR3_SSI1_IPG(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR3_SSI1_SSI_OFFSET			18
+#define MXC_CCM_CCGR3_SSI1_SSI(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR3_SSI2_IPG_OFFSET			20
+#define MXC_CCM_CCGR3_SSI2_IPG(v)			(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR3_SSI2_SSI_OFFSET			22
+#define MXC_CCM_CCGR3_SSI2_SSI(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR3_SSI3_IPG_OFFSET			24
+#define MXC_CCM_CCGR3_SSI3_IPG(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR3_SSI3_SSI_OFFSET			26
+#define MXC_CCM_CCGR3_SSI3_SSI(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR3_SSI_EXT1_OFFSET			28
+#define MXC_CCM_CCGR3_SSI_EXT1(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR3_SSI_EXT2_OFFSET			30
+#define MXC_CCM_CCGR3_SSI_EXT2(v)			(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR4_PATA_OFFSET			0
+#define MXC_CCM_CCGR4_PATA(v)				(((v) & 0x3) << 0)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR4_SIM_IPG_OFFSET			2
+#define MXC_CCM_CCGR4_SIM_IPG(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET			4
+#define MXC_CCM_CCGR4_SIM_SERIAL(v)			(((v) & 0x3) << 4)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR4_SATA_OFFSET			2
+#define MXC_CCM_CCGR4_SATA(v)				(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR4_CAN2_IPG_OFFSET			6
+#define MXC_CCM_CCGR4_CAN2_IPG(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET		8
+#define MXC_CCM_CCGR4_CAN2_SERIAL(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR4_USB_PHY1_OFFSET			10
+#define MXC_CCM_CCGR4_USB_PHY1(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR4_USB_PHY2_OFFSET			12
+#define MXC_CCM_CCGR4_USB_PHY2(v)			(((v) & 0x3) << 12)
+#endif
+#define MXC_CCM_CCGR4_SAHARA_OFFSET			14
+#define MXC_CCM_CCGR4_SAHARA(v)				(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR4_RTIC_OFFSET			16
+#define MXC_CCM_CCGR4_RTIC(v)				(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET			18
+#define MXC_CCM_CCGR4_ECSPI1_IPG(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET			20
+#define MXC_CCM_CCGR4_ECSPI1_PER(v)			(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET			22
+#define MXC_CCM_CCGR4_ECSPI2_IPG(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET			24
+#define MXC_CCM_CCGR4_ECSPI2_PER(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR4_CSPI_IPG_OFFSET			26
+#define MXC_CCM_CCGR4_CSPI_IPG(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR4_SRTC_OFFSET			28
+#define MXC_CCM_CCGR4_SRTC(v)				(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR4_SDMA_OFFSET			30
+#define MXC_CCM_CCGR4_SDMA(v)				(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR5_SPBA_OFFSET			0
+#define MXC_CCM_CCGR5_SPBA(v)				(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR5_GPU_OFFSET			2
+#define MXC_CCM_CCGR5_GPU(v)				(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR5_GARB_OFFSET			4
+#define MXC_CCM_CCGR5_GARB(v)				(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR5_VPU_OFFSET			6
+#define MXC_CCM_CCGR5_VPU(v)				(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR5_VPU_REF_OFFSET			8
+#define MXC_CCM_CCGR5_VPU_REF(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR5_IPU_OFFSET			10
+#define MXC_CCM_CCGR5_IPU(v)				(((v) & 0x3) << 10)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR5_IPUMUX12_OFFSET			12
+#define MXC_CCM_CCGR5_IPUMUX12(v)			(((v) & 0x3) << 12)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR5_IPUMUX1_OFFSET			12
+#define MXC_CCM_CCGR5_IPUMUX1(v)			(((v) & 0x3) << 12)
+#endif
+#define MXC_CCM_CCGR5_EMI_FAST_OFFSET			14
+#define MXC_CCM_CCGR5_EMI_FAST(v)			(((v) & 0x3) << 14)
+#define MXC_CCM_CCGR5_EMI_SLOW_OFFSET			16
+#define MXC_CCM_CCGR5_EMI_SLOW(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR5_EMI_INT1_OFFSET			18
+#define MXC_CCM_CCGR5_EMI_INT1(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR5_EMI_ENFC_OFFSET			20
+#define MXC_CCM_CCGR5_EMI_ENFC(v)			(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR5_EMI_WRCK_OFFSET			22
+#define MXC_CCM_CCGR5_EMI_WRCK(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR5_GPC_IPG_OFFSET			24
+#define MXC_CCM_CCGR5_GPC_IPG(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR5_SPDIF0_OFFSET			26
+#define MXC_CCM_CCGR5_SPDIF0(v)				(((v) & 0x3) << 26)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR5_SPDIF1_OFFSET			28
+#define MXC_CCM_CCGR5_SPDIF1(v)				(((v) & 0x3) << 28)
+#endif
+#define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET			30
+#define MXC_CCM_CCGR5_SPDIF_IPG(v)			(((v) & 0x3) << 30)
+
+#if defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_IPUMUX2_OFFSET			0
+#define MXC_CCM_CCGR6_IPUMUX2(v)			(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR6_OCRAM_OFFSET			2
+#define MXC_CCM_CCGR6_OCRAM(v)				(((v) & 0x3) << 2)
+#endif
+#define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET			4
+#define MXC_CCM_CCGR6_CSI_MCLK1(v)			(((v) & 0x3) << 4)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET			6
+#define MXC_CCM_CCGR6_CSI_MCLK2(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR6_EMI_GARB_OFFSET			8
+#define MXC_CCM_CCGR6_EMI_GARB(v)			(((v) & 0x3) << 8)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_EMI_INT2_OFFSET			8
+#define MXC_CCM_CCGR6_EMI_INT2(v)			(((v) & 0x3) << 8)
+#endif
+#define MXC_CCM_CCGR6_IPU_DI0_OFFSET			10
+#define MXC_CCM_CCGR6_IPU_DI0(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR6_IPU_DI1_OFFSET			12
+#define MXC_CCM_CCGR6_IPU_DI1(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR6_GPU2D_OFFSET			14
+#define MXC_CCM_CCGR6_GPU2D(v)				(((v) & 0x3) << 14)
+#if defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_ESAI_IPG_OFFSET			16
+#define MXC_CCM_CCGR6_ESAI_IPG(v)			(((v) & 0x3) << 16)
+#define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET			18
+#define MXC_CCM_CCGR6_ESAI_ROOT(v)			(((v) & 0x3) << 18)
+#define MXC_CCM_CCGR6_CAN1_IPG_OFFSET			20
+#define MXC_CCM_CCGR6_CAN1_IPG(v)			(((v) & 0x3) << 20)
+#define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET		22
+#define MXC_CCM_CCGR6_CAN1_SERIAL(v)			(((v) & 0x3) << 22)
+#define MXC_CCM_CCGR6_PL301_4X1_OFFSET			24
+#define MXC_CCM_CCGR6_PL301_4X1(v)			(((v) & 0x3) << 24)
+#define MXC_CCM_CCGR6_PL301_2X2_OFFSET			26
+#define MXC_CCM_CCGR6_PL301_2X2(v)			(((v) & 0x3) << 26)
+#define MXC_CCM_CCGR6_LDB_DI0_OFFSET			28
+#define MXC_CCM_CCGR6_LDB_DI0(v)			(((v) & 0x3) << 28)
+#define MXC_CCM_CCGR6_LDB_DI1_OFFSET			30
+#define MXC_CCM_CCGR6_LDB_DI1(v)			(((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR7_ASRC_IPG_OFFSET			0
+#define MXC_CCM_CCGR7_ASRC_IPG(v)			(((v) & 0x3) << 0)
+#define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET			2
+#define MXC_CCM_CCGR7_ASRC_ASRCK(v)			(((v) & 0x3) << 2)
+#define MXC_CCM_CCGR7_MLB_OFFSET			4
+#define MXC_CCM_CCGR7_MLB(v)				(((v) & 0x3) << 4)
+#define MXC_CCM_CCGR7_IEEE1588_OFFSET			6
+#define MXC_CCM_CCGR7_IEEE1588(v)			(((v) & 0x3) << 6)
+#define MXC_CCM_CCGR7_UART4_IPG_OFFSET			8
+#define MXC_CCM_CCGR7_UART4_IPG(v)			(((v) & 0x3) << 8)
+#define MXC_CCM_CCGR7_UART4_PER_OFFSET			10
+#define MXC_CCM_CCGR7_UART4_PER(v)			(((v) & 0x3) << 10)
+#define MXC_CCM_CCGR7_UART5_IPG_OFFSET			12
+#define MXC_CCM_CCGR7_UART5_IPG(v)			(((v) & 0x3) << 12)
+#define MXC_CCM_CCGR7_UART5_PER_OFFSET			14
+#define MXC_CCM_CCGR7_UART5_PER(v)			(((v) & 0x3) << 14)
+#endif
 
 /* Define the bits in register CLPCR */
 #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS                 (0x1 << 18)

drivers/video/ipu_common.c +0 -0

index 2020da9..7869d65 100644

The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks have different clock gate control bit-fields.

The existing code was correct only for i.MX53, so this patch fixes the i.MX51 use case.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Jana Rapava <[email protected]>

Cc Wolfgang Grandegger <[email protected]>

Cc Igor Grinberg <[email protected]>

The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks have different clock gate control bit-fields.

The existing code was correct only for i.MX53, so this patch fixes the i.MX51 use case.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Jana Rapava <[email protected]>

Cc Wolfgang Grandegger <[email protected]>

Cc Igor Grinberg <[email protected]>

---
This patch supersedes http://patchwork.ozlabs.org/patch/177403/ . Changes for v2:
- Split patch into 3 parts (the 3, 4 and 5 from this v2 series).
- Merge the various set_usb_phy*_clk() functions (they were identical).

 .../arch/arm/cpu/armv7/mx5/clock.c                 |   20 +++++++++++++-------
 .../arch/arm/include/asm/arch-mx5/clock.h          |    7 ++++++-
 .../drivers/usb/host/ehci-mx5.c                    |    6 +++++-
 3 files changed, 24 insertions(+), 9 deletions(-)

arch/arm/cpu/armv7/mx5/clock.c +0 -0

index df7e5cd..f727cfa 100644
@@ -126,11 +126,21 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 }

arch/arm/cpu/armv7/mx5/clock.c +3 -6

+#elif defined(CONFIG_MX53)
 void enable_usb_phy1_clk(unsigned char enable)
 {
 	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;

@@ -140,11 +150,6 @@ void enable_usb_phy1_clk(unsigned char enable)
 			MXC_CCM_CCGR4_USB_PHY1(cg));
 }
 
-void set_usb_phy2_clk(void)
-{
-	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
-}
-
 void enable_usb_phy2_clk(unsigned char enable)
 {
 	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;

@@ -153,6 +158,7 @@ void enable_usb_phy2_clk(unsigned char enable)
 			MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
 			MXC_CCM_CCGR4_USB_PHY2(cg));
 }
+#endif
 
 /*
  * Calculate the frequency of PLLn.

@@ -803,7 +809,7 @@ void mxc_set_sata_internal_clock(void)
 	u32 *tmp_base =
 		(u32 *)(IIM_BASE_ADDR + 0x180c);
 
-	set_usb_phy1_clk();
+	set_usb_phy_clk();
 
 	clrsetbits_le32(tmp_base, 0x6, 0x4);
 }

arch/arm/include/asm/arch-mx5/clock.h +0 -0

index 55e3b51..e4ca417 100644
@@ -56,8 +56,13 @@ u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);

arch/arm/include/asm/arch-mx5/clock.h +0 -0

 void set_usboh3_clk(void);
 void enable_usboh3_clk(unsigned char enable);
 void mxc_set_sata_internal_clock(void);

drivers/usb/host/ehci-mx5.c +0 -0

index 58cdcbe..5bf89f0 100644

drivers/usb/host/ehci-mx5.c +0 -0

 	mdelay(1);
 
 	/* Do board specific initialization */

Hi Beno?t,

please, see a minor #ifdef comment below

Quoted 35 lines · Beno?t Th?baudeau

The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks
have different clock gate control bit-fields.

The existing code was correct only for i.MX53, so this patch fixes the i.MX51
use case.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Jana Rapava <[email protected]>

Cc Wolfgang Grandegger <[email protected]>

Cc Igor Grinberg <[email protected]>

---
This patch supersedes http://patchwork.ozlabs.org/patch/177403/ . Changes for v2:
- Split patch into 3 parts (the 3, 4 and 5 from this v2 series).
- Merge the various set_usb_phy*_clk() functions (they were identical).

 .../arch/arm/cpu/armv7/mx5/clock.c                 |   20
 +++++++++++++-------
 .../arch/arm/include/asm/arch-mx5/clock.h          |    7 ++++++-
 .../drivers/usb/host/ehci-mx5.c                    |    6 +++++-
 3 files changed, 24 insertions(+), 9 deletions(-)

(quoted diff) +0 -0

u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index df7e5cd..f727cfa 100644

arch/arm/cpu/armv7/mx5/clock.c +0 -0

@@ -126,11 +126,21 @@ int enable_i2c_clk(unsigned char enable,
 unsigned i2c_num)
 }

arch/arm/cpu/armv7/mx5/clock.c int enable_i2c_clk(unsigned char enable, · line 136

Quoted 10 lines

arch/arm/cpu/armv7/mx5/clock.c +3 -1

 #endif
 
-void set_usb_phy1_clk(void)
+void set_usb_phy_clk(void)
 {
 	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
 }
 
+#if defined(CONFIG_MX51)
+void enable_usb_phy_clk(unsigned char enable)

I think the same name as the MX53 case will do better, see explanation below.

arch/arm/cpu/armv7/mx5/clock.c int enable_i2c_clk(unsigned char enable, unsigned i2c_num) · line 142

Quoted 8 lines

arch/arm/cpu/armv7/mx5/clock.c +7 -0

+{
+	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON :
 MXC_CCM_CCGR_CG_OFF;
+
+	clrsetbits_le32(&mxc_ccm->CCGR2,
+			MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
+			MXC_CCM_CCGR2_USB_PHY(cg));
+}

I would add here (again explanation below):
void enable_usb_phy2_clk(unsigned char enable)

{
	/* MX51 has a single USB PHY clock, so do nothing here */
}

Quoted 43 lines

arch/arm/cpu/armv7/mx5/clock.c +1 -0

+#elif defined(CONFIG_MX53)
 void enable_usb_phy1_clk(unsigned char enable)

{

arch/arm/cpu/armv7/mx5/clock.c +0 -5

 	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON :
 	MXC_CCM_CCGR_CG_OFF;

@@ -140,11 +150,6 @@ void enable_usb_phy1_clk(unsigned char enable)
 			MXC_CCM_CCGR4_USB_PHY1(cg));
 }
 
-void set_usb_phy2_clk(void)
-{
-	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
-}
-
 void enable_usb_phy2_clk(unsigned char enable)
 {
 	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON :

arch/arm/cpu/armv7/mx5/clock.c +2 -1

 	MXC_CCM_CCGR_CG_OFF;

@@ -153,6 +158,7 @@ void enable_usb_phy2_clk(unsigned char enable)
 			MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
 			MXC_CCM_CCGR4_USB_PHY2(cg));
 }
+#endif
 
 /*
  * Calculate the frequency of PLLn.

@@ -803,7 +809,7 @@ void mxc_set_sata_internal_clock(void)
 	u32 *tmp_base =
 		(u32 *)(IIM_BASE_ADDR + 0x180c);
 
-	set_usb_phy1_clk();
+	set_usb_phy_clk();
 
 	clrsetbits_le32(tmp_base, 0x6, 0x4);
 }

diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h index 55e3b51..e4ca417 100644

arch/arm/include/asm/arch-mx5/clock.h +0 -0

@@ -56,8 +56,13 @@ u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);

arch/arm/include/asm/arch-mx5/clock.h u32 imx_get_uartclk(void); · line 65

Quoted 10 lines

arch/arm/include/asm/arch-mx5/clock.h +6 -1

 unsigned int mxc_get_clock(enum mxc_clock clk);
 int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
-void set_usb_phy2_clk(void);
+void set_usb_phy_clk(void);
+#if defined(CONFIG_MX51)
+void enable_usb_phy_clk(unsigned char enable);
+#elif defined(CONFIG_MX53)
+void enable_usb_phy1_clk(unsigned char enable);
 void enable_usb_phy2_clk(unsigned char enable);
+#endif

If you follow my suggestion above, then here you will only have:
-void set_usb_phy2_clk(void);
+void set_usb_phy_clk(void);
+void enable_usb_phy1_clk(unsigned char enable);

and no complicating with #ifdefs needed.

Quoted 10 lines

arch/arm/include/asm/arch-mx5/clock.h +0 -0

 void set_usboh3_clk(void);
 void enable_usboh3_clk(unsigned char enable);
 void mxc_set_sata_internal_clock(void);

(quoted diff) +0 -0

u-boot-imx-e1eb75b/drivers/usb/host/ehci-mx5.c
index 58cdcbe..5bf89f0 100644

drivers/usb/host/ehci-mx5.c +0 -0

@@ -221,8 +221,12 @@ int ehci_hcd_init(void)
 

drivers/usb/host/ehci-mx5.c int ehci_hcd_init(void) · line 229

Quoted 9 lines

drivers/usb/host/ehci-mx5.c +5 -1

 	set_usboh3_clk();
 	enable_usboh3_clk(1);
-	set_usb_phy2_clk();
+	set_usb_phy_clk();
+#if defined(CONFIG_MX51) && CONFIG_MXC_USB_PORT == 0
+	enable_usb_phy_clk(1);
+#elif defined(CONFIG_MX53)
 	enable_usb_phy2_clk(1);
+#endif

same here, it should be much cleaner.

Quoted 4 lines

drivers/usb/host/ehci-mx5.c +0 -0

 	mdelay(1);
 
 	/* Do board specific initialization */

Hi Igor,

Quoted 152 lines · Igor Grinberg

Hi Beno?t,

please, see a minor #ifdef comment below

Quoted 35 lines · Beno?t Th?baudeau

The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks
have different clock gate control bit-fields.

The existing code was correct only for i.MX53, so this patch fixes the i.MX51
use case.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Jana Rapava <[email protected]>

Cc Wolfgang Grandegger <[email protected]>

Cc Igor Grinberg <[email protected]>

---
This patch supersedes http://patchwork.ozlabs.org/patch/177403/ . Changes for v2:
- Split patch into 3 parts (the 3, 4 and 5 from this v2 series).
- Merge the various set_usb_phy*_clk() functions (they were identical).

 .../arch/arm/cpu/armv7/mx5/clock.c                 |   20
 +++++++++++++-------
 .../arch/arm/include/asm/arch-mx5/clock.h          |    7 ++++++-
 .../drivers/usb/host/ehci-mx5.c                    |    6 +++++-
 3 files changed, 24 insertions(+), 9 deletions(-)

(quoted diff) +0 -0

u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index df7e5cd..f727cfa 100644

arch/arm/cpu/armv7/mx5/clock.c +0 -0

@@ -126,11 +126,21 @@ int enable_i2c_clk(unsigned char enable,
 unsigned i2c_num)
 }

arch/arm/cpu/armv7/mx5/clock.c int enable_i2c_clk(unsigned char enable, · line 136

Quoted 10 lines

arch/arm/cpu/armv7/mx5/clock.c +3 -1

 #endif
 
-void set_usb_phy1_clk(void)
+void set_usb_phy_clk(void)
 {
 	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
 }
 
+#if defined(CONFIG_MX51)
+void enable_usb_phy_clk(unsigned char enable)

I think the same name as the MX53 case will do better, see explanation below.

arch/arm/cpu/armv7/mx5/clock.c int enable_i2c_clk(unsigned char enable, unsigned i2c_num) · line 142

Quoted 8 lines

arch/arm/cpu/armv7/mx5/clock.c +7 -0

+{
+	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON :
 MXC_CCM_CCGR_CG_OFF;
+
+	clrsetbits_le32(&mxc_ccm->CCGR2,
+			MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
+			MXC_CCM_CCGR2_USB_PHY(cg));
+}

I would add here (again explanation below):
void enable_usb_phy2_clk(unsigned char enable)

{
	/* MX51 has a single USB PHY clock, so do nothing here */
}

Quoted 43 lines

arch/arm/cpu/armv7/mx5/clock.c +1 -0

+#elif defined(CONFIG_MX53)
 void enable_usb_phy1_clk(unsigned char enable)

{

arch/arm/cpu/armv7/mx5/clock.c +0 -5

 	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON :
 	MXC_CCM_CCGR_CG_OFF;

@@ -140,11 +150,6 @@ void enable_usb_phy1_clk(unsigned char enable)
 			MXC_CCM_CCGR4_USB_PHY1(cg));
 }
 
-void set_usb_phy2_clk(void)
-{
-	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
-}
-
 void enable_usb_phy2_clk(unsigned char enable)
 {
 	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON :

arch/arm/cpu/armv7/mx5/clock.c +2 -1

 	MXC_CCM_CCGR_CG_OFF;

@@ -153,6 +158,7 @@ void enable_usb_phy2_clk(unsigned char enable)
 			MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
 			MXC_CCM_CCGR4_USB_PHY2(cg));
 }
+#endif
 
 /*
  * Calculate the frequency of PLLn.

@@ -803,7 +809,7 @@ void mxc_set_sata_internal_clock(void)
 	u32 *tmp_base =
 		(u32 *)(IIM_BASE_ADDR + 0x180c);
 
-	set_usb_phy1_clk();
+	set_usb_phy_clk();
 
 	clrsetbits_le32(tmp_base, 0x6, 0x4);
 }

diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h index 55e3b51..e4ca417 100644

arch/arm/include/asm/arch-mx5/clock.h +0 -0

@@ -56,8 +56,13 @@ u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);

arch/arm/include/asm/arch-mx5/clock.h u32 imx_get_uartclk(void); · line 65

Quoted 10 lines

arch/arm/include/asm/arch-mx5/clock.h +6 -1

 unsigned int mxc_get_clock(enum mxc_clock clk);
 int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
-void set_usb_phy2_clk(void);
+void set_usb_phy_clk(void);
+#if defined(CONFIG_MX51)
+void enable_usb_phy_clk(unsigned char enable);
+#elif defined(CONFIG_MX53)
+void enable_usb_phy1_clk(unsigned char enable);
 void enable_usb_phy2_clk(unsigned char enable);
+#endif

If you follow my suggestion above, then here you will only have:
-void set_usb_phy2_clk(void);
+void set_usb_phy_clk(void);
+void enable_usb_phy1_clk(unsigned char enable);

and no complicating with #ifdefs needed.

Quoted 9 lines

arch/arm/include/asm/arch-mx5/clock.h +0 -0

 void set_usboh3_clk(void);
 void enable_usboh3_clk(unsigned char enable);
 void mxc_set_sata_internal_clock(void);

(quoted diff) +0 -0

u-boot-imx-e1eb75b/drivers/usb/host/ehci-mx5.c
index 58cdcbe..5bf89f0 100644

drivers/usb/host/ehci-mx5.c int ehci_hcd_init(void) · line 229

Quoted 10 lines

drivers/usb/host/ehci-mx5.c +5 -1

@@ -221,8 +221,12 @@ int ehci_hcd_init(void)
 
 	set_usboh3_clk();
 	enable_usboh3_clk(1);
-	set_usb_phy2_clk();
+	set_usb_phy_clk();
+#if defined(CONFIG_MX51) && CONFIG_MXC_USB_PORT == 0
+	enable_usb_phy_clk(1);
+#elif defined(CONFIG_MX53)
 	enable_usb_phy2_clk(1);
+#endif

same here, it should be much cleaner.

Quoted 4 lines

drivers/usb/host/ehci-mx5.c int ehci_hcd_init(void) · line 232

Quoted 4 lines

drivers/usb/host/ehci-mx5.c +0 -0

 	mdelay(1);
 
 	/* Do board specific initialization */

Indeed. In clock.h, the #ifdefs could anyway be removed with the naming from my patch. The only difference would be an error at link time rather than at compile time if these functions were called for the wrong i.MX5. If we change the naming as you suggest, it's not a problem for set_usb_phy1_clk(), but for enable_usb_phy2_clk() I think that it would not really make sense. My point is that ehci-mx5.c should be cleaned even more deeply in order to initialize the USB PHYs corresponding to the selected EHCI ports, and not all (or only some for i.MX53) the PHYs at the beginning of ehci_hcd_init(). Also, calling enable_usb_phy2_clk() for i.MX51 would not make sense, even if it does nothing, because it would be confusing. So this solution has both advantages and drawbacks.

Stefano, Marek, what do you think?

Quoted 178 lines · Beno?t Th?baudeau

Hi Igor,

Quoted 144 lines · Igor Grinberg

Hi Beno?t,

please, see a minor #ifdef comment below

Quoted 37 lines · Beno?t Th?baudeau

The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks
have different clock gate control bit-fields.

The existing code was correct only for i.MX53, so this patch fixes
the i.MX51
use case.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Jana Rapava <[email protected]>

Cc Wolfgang Grandegger <[email protected]>

Cc Igor Grinberg <[email protected]>

---
This patch supersedes http://patchwork.ozlabs.org/patch/177403/ . Changes for v2:
- Split patch into 3 parts (the 3, 4 and 5 from this v2 series).
- Merge the various set_usb_phy*_clk() functions (they were identical).

 .../arch/arm/cpu/armv7/mx5/clock.c                 |   20
 +++++++++++++-------
 .../arch/arm/include/asm/arch-mx5/clock.h          |    7
 ++++++-
 .../drivers/usb/host/ehci-mx5.c                    |    6 +++++-
 3 files changed, 24 insertions(+), 9 deletions(-)

(quoted diff) +0 -0

u-boot-imx-e1eb75b/arch/arm/cpu/armv7/mx5/clock.c
index df7e5cd..f727cfa 100644

arch/arm/cpu/armv7/mx5/clock.c +0 -0

@@ -126,11 +126,21 @@ int enable_i2c_clk(unsigned char enable,
 unsigned i2c_num)
 }

arch/arm/cpu/armv7/mx5/clock.c int enable_i2c_clk(unsigned char enable, · line 136

Quoted 10 lines

arch/arm/cpu/armv7/mx5/clock.c +3 -1

 #endif
 
-void set_usb_phy1_clk(void)
+void set_usb_phy_clk(void)
 {
 	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
 }
 
+#if defined(CONFIG_MX51)
+void enable_usb_phy_clk(unsigned char enable)

I think the same name as the MX53 case will do better, see explanation below.

arch/arm/cpu/armv7/mx5/clock.c int enable_i2c_clk(unsigned char enable, unsigned i2c_num) · line 142

Quoted 8 lines

arch/arm/cpu/armv7/mx5/clock.c +7 -0

+{
+	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON :
 MXC_CCM_CCGR_CG_OFF;
+
+	clrsetbits_le32(&mxc_ccm->CCGR2,
+			MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
+			MXC_CCM_CCGR2_USB_PHY(cg));
+}

I would add here (again explanation below):
void enable_usb_phy2_clk(unsigned char enable)

{
	/* MX51 has a single USB PHY clock, so do nothing here */
}

Quoted 45 lines

arch/arm/cpu/armv7/mx5/clock.c +1 -0

+#elif defined(CONFIG_MX53)
 void enable_usb_phy1_clk(unsigned char enable)

{

arch/arm/cpu/armv7/mx5/clock.c +0 -5

 	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON :
 	MXC_CCM_CCGR_CG_OFF;

@@ -140,11 +150,6 @@ void enable_usb_phy1_clk(unsigned char
 enable)
 			MXC_CCM_CCGR4_USB_PHY1(cg));
 }
 
-void set_usb_phy2_clk(void)
-{
-	clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
-}
-
 void enable_usb_phy2_clk(unsigned char enable)
 {

arch/arm/cpu/armv7/mx5/clock.c +1 -0

 	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON :
 	MXC_CCM_CCGR_CG_OFF;

@@ -153,6 +158,7 @@ void enable_usb_phy2_clk(unsigned char
 enable)
 			MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
 			MXC_CCM_CCGR4_USB_PHY2(cg));
 }
+#endif
 
 /*

* Calculate the frequency of PLLn.

arch/arm/cpu/armv7/mx5/clock.c +1 -1

@@ -803,7 +809,7 @@ void mxc_set_sata_internal_clock(void)
 	u32 *tmp_base =
 		(u32 *)(IIM_BASE_ADDR + 0x180c);
 
-	set_usb_phy1_clk();
+	set_usb_phy_clk();
 
 	clrsetbits_le32(tmp_base, 0x6, 0x4);
 }

diff --git u-boot-imx-e1eb75b.orig/arch/arm/include/asm/arch-mx5/clock.h u-boot-imx-e1eb75b/arch/arm/include/asm/arch-mx5/clock.h index 55e3b51..e4ca417 100644

arch/arm/include/asm/arch-mx5/clock.h +0 -0

@@ -56,8 +56,13 @@ u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);

arch/arm/include/asm/arch-mx5/clock.h u32 imx_get_uartclk(void); · line 65

Quoted 10 lines

arch/arm/include/asm/arch-mx5/clock.h +6 -1

 unsigned int mxc_get_clock(enum mxc_clock clk);
 int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
-void set_usb_phy2_clk(void);
+void set_usb_phy_clk(void);
+#if defined(CONFIG_MX51)
+void enable_usb_phy_clk(unsigned char enable);
+#elif defined(CONFIG_MX53)
+void enable_usb_phy1_clk(unsigned char enable);
 void enable_usb_phy2_clk(unsigned char enable);
+#endif

If you follow my suggestion above, then here you will only have:
-void set_usb_phy2_clk(void);
+void set_usb_phy_clk(void);
+void enable_usb_phy1_clk(unsigned char enable);

and no complicating with #ifdefs needed.

Quoted 10 lines

arch/arm/include/asm/arch-mx5/clock.h +0 -0

 void set_usboh3_clk(void);
 void enable_usboh3_clk(unsigned char enable);
 void mxc_set_sata_internal_clock(void);

(quoted diff) +0 -0

u-boot-imx-e1eb75b/drivers/usb/host/ehci-mx5.c
index 58cdcbe..5bf89f0 100644

drivers/usb/host/ehci-mx5.c +0 -0

@@ -221,8 +221,12 @@ int ehci_hcd_init(void)
 

Quoted 16 lines

drivers/usb/host/ehci-mx5.c int ehci_hcd_init(void) · line 229

Quoted 9 lines

drivers/usb/host/ehci-mx5.c +5 -1

 	set_usboh3_clk();
 	enable_usboh3_clk(1);
-	set_usb_phy2_clk();
+	set_usb_phy_clk();
+#if defined(CONFIG_MX51) && CONFIG_MXC_USB_PORT == 0
+	enable_usb_phy_clk(1);
+#elif defined(CONFIG_MX53)
 	enable_usb_phy2_clk(1);
+#endif

same here, it should be much cleaner.

Quoted 4 lines

drivers/usb/host/ehci-mx5.c +0 -0

 	mdelay(1);
 
 	/* Do board specific initialization */

Indeed. In clock.h, the #ifdefs could anyway be removed with the naming from my patch. The only difference would be an error at link time rather than at compile time if these functions were called for the wrong i.MX5. If we change the naming as you suggest, it's not a problem for set_usb_phy1_clk(), but for enable_usb_phy2_clk() I think that it would not really make sense. My point is that ehci-mx5.c should be cleaned even more deeply in order to initialize the USB PHYs corresponding to the selected EHCI ports, and not all (or only some for i.MX53) the PHYs at the beginning of ehci_hcd_init(). Also, calling enable_usb_phy2_clk() for i.MX51 would not make sense, even if it does nothing, because it would be confusing. So this solution has both advantages and drawbacks.