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perf/x86: enable Intel Cedarview Atom suppport

PATCH In review Stephane Eranian 2 participants 4 messages Aug 20, 2012 – Sep 4, 2012

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Stephane Eranian

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#0 lore raw

PATCH 1/1 perf/x86: enable Intel Cedarview Atom suppport

This patch enables perf_events support for Intel Cedarview Atom (model 54) processors. Support includes PEBS and LBR. Tested on my Atom N2600 netbook.

Signed-off-by Stephane Eranian <[email protected]>

---

arch/x86/kernel/cpu/perf_event_intel.c +1 -0
index 7f2739e..0d3d63a 100644
@@ -2008,6 +2008,7 @@ __init int intel_pmu_init(void)
 		break;
 
 	case 28: /* Atom */
+	case 54: /* Cedariew */
 		memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
arch/x86/kernel/cpu/perf_event_intel_lbr.c +2 -1
index 520b426..da02e9c 100644
@@ -686,7 +686,8 @@ void intel_pmu_lbr_init_atom(void)
 	 * to have an operational LBR which can freeze
 	 * on PMU interrupt
 	 */
-	if (boot_cpu_data.x86_mask < 10) {
+	if (boot_cpu_data.x86_model == 28
+	    && boot_cpu_data.x86_mask < 10) {
 		pr_cont("LBR disabled due to erratum");
 		return;
 	}
#1 lore raw

arch/x86/kernel/cpu/perf_event_intel.c __init int intel_pmu_init(void) · line 2011

Quoted 9 lines
arch/x86/kernel/cpu/perf_event_intel.c +1 -0
index 7f2739e..0d3d63a 100644
@@ -2008,6 +2008,7 @@ __init int intel_pmu_init(void)
 		break;
 
 	case 28: /* Atom */
+	case 54: /* Cedariew */

Ack. We currently miss some more 32nm Atoms too, will send patches soon.

Quoted 8 lines
arch/x86/kernel/cpu/perf_event_intel.c +0 -0
 		memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
arch/x86/kernel/cpu/perf_event_intel_lbr.c +0 -0
index 520b426..da02e9c 100644

arch/x86/kernel/cpu/perf_event_intel_lbr.c void intel_pmu_lbr_init_atom(void) · line 690

Quoted 6 lines
arch/x86/kernel/cpu/perf_event_intel_lbr.c +2 -1
@@ -686,7 +686,8 @@ void intel_pmu_lbr_init_atom(void)
 	 * to have an operational LBR which can freeze
 	 * on PMU interrupt
 	 */
-	if (boot_cpu_data.x86_mask < 10) {
+	if (boot_cpu_data.x86_model == 28
+	    && boot_cpu_data.x86_mask < 10) {

Is that correct?

-Andi

Signature · 1 line
[email protected] -- Speaking for myself only.
author
#2 lore raw
Quoted 15 lines · Andi Kleen

arch/x86/kernel/cpu/perf_event_intel.c __init int intel_pmu_init(void) · line 2011

Quoted 9 lines
arch/x86/kernel/cpu/perf_event_intel.c +1 -0
index 7f2739e..0d3d63a 100644
@@ -2008,6 +2008,7 @@ __init int intel_pmu_init(void)
              break;
 
      case 28: /* Atom */
+     case 54: /* Cedariew */

Ack. We currently miss some more 32nm Atoms too, will send patches soon.

Quoted 3 lines
arch/x86/kernel/cpu/perf_event_intel.c +0 -0
              memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
                     sizeof(hw_cache_event_ids));
Quoted 14 lines

arch/x86/kernel/cpu/perf_event_intel_lbr.c void intel_pmu_lbr_init_atom(void) · line 690

Quoted 11 lines
arch/x86/kernel/cpu/perf_event_intel_lbr.c +2 -1
index 520b426..da02e9c 100644
@@ -686,7 +686,8 @@ void intel_pmu_lbr_init_atom(void)
       * to have an operational LBR which can freeze
       * on PMU interrupt
       */
-     if (boot_cpu_data.x86_mask < 10) {
+     if (boot_cpu_data.x86_model == 28
+         && boot_cpu_data.x86_mask < 10) {

Is that correct?

Yes, had to do that to re-enable LBR on Cedarview.
The < 10 is a trick to disable LBR on very old Atom (prior to N4xx generation).

author
#3 lore raw

[tip:perf/urgent] perf/x86: Enable Intel Cedarview Atom suppport

In reply to Stephane Eranian
Commit-ID:  3ec18cd8b8f8395d0df604c62ab3bc2cf3a966b4
Gitweb:     http://git.kernel.org/tip/3ec18cd8b8f8395d0df604c62ab3bc2cf3a966b4
Author:     Stephane Eranian <[email protected]>
AuthorDate: Mon, 20 Aug 2012 11:24:21 +0200
Committer:  Ingo Molnar <[email protected]>
CommitDate: Tue, 4 Sep 2012 17:29:23 +0200

perf/x86: Enable Intel Cedarview Atom suppport

This patch enables perf_events support for Intel Cedarview Atom (model 54) processors. Support includes PEBS and LBR. Tested on my Atom N2600 netbook.

Signed-off-by Stephane Eranian <[email protected]>
Signed-off-by Peter Zijlstra <[email protected]>
Link http://lkml.kernel.org/r/20120820092421.GA11284@quad open here
Signed-off-by Ingo Molnar <[email protected]>
---
 arch/x86/kernel/cpu/perf_event_intel.c     |    1 +
 arch/x86/kernel/cpu/perf_event_intel_lbr.c |    3 ++-
 2 files changed, 3 insertions(+), 1 deletions(-)
arch/x86/kernel/cpu/perf_event_intel.c +1 -0
index 7f2739e..0d3d63a 100644
@@ -2008,6 +2008,7 @@ __init int intel_pmu_init(void)
 		break;
 
 	case 28: /* Atom */
+	case 54: /* Cedariew */
 		memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
arch/x86/kernel/cpu/perf_event_intel_lbr.c +2 -1
index 520b426..da02e9c 100644
@@ -686,7 +686,8 @@ void intel_pmu_lbr_init_atom(void)
 	 * to have an operational LBR which can freeze
 	 * on PMU interrupt
 	 */
-	if (boot_cpu_data.x86_mask < 10) {
+	if (boot_cpu_data.x86_model == 28
+	    && boot_cpu_data.x86_mask < 10) {
 		pr_cont("LBR disabled due to erratum");
 		return;
 	}