BAR0/1 & enumeration

As newbie to the pcie world, I'm seeking help for understanding this:

How does the bios during enumeration finds whether BAR0/1 is set for pointing to the config-space of its function or to memory space for memory transactions?

Thanks!

BARs point to either memory or I/O space (discriminated by the bottom bit of the register). They never point to config space (indeed, since they are found in config space, that wouldn't make sense).

Matthew Wilcox				Intel Open Source Technology Centre
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours.  We can't possibly take such
a retrograde step."

Not really.

I'm working on a NTB. NTBs are Type-0 headers, like any PCIe end point. BAR0/1 on NTB can be set as base address for the config-space of its function OR as based address of the memory space for memory transactions.

Hence my initial question. Looking fwd to some hint.

The genefic PCI/PCIe framework doesn't do any thing special for NTB device, just treat it as a normal PCI device. The issue you mentioned must be handled by BIOS/OS driver with device specific knowledge. --Gerry