Renesas ARM-based SoC: r8a7740 SoC for 3.7
Hi Olof, Hi Arnd,
please consider the following documentation enhancement for the r8a7740 SoC from Morimoto-san for inclusion in 3.7.
----------------------------------------------------------------
The following changes since commit fea7a08acb13524b47711625eebea40a0ede69a0:
Linux 3.6-rc3 (2012-08-22 13:29:06 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git r8a7740
for you to fetch changes up to a6e7c110f972d7ca5c6eb288f5e64d5659b44dc0:
ARM: shmobile: r8a7740: add USB24 clock explain and sample code (2012-08-27 17:43:22 +0900)
----------------------------------------------------------------
Kuninori Morimoto (1):
ARM: shmobile: r8a7740: add USB24 clock explain and sample code
arch/arm/mach-shmobile/clock-r8a7740.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
PATCH 1/1 ARM: shmobile: r8a7740: add USB24 clock explain and sample code
From: Kuninori Morimoto <[email protected]>
USBCKCR is controlling USB parent clock and divide rate. This parent clock is used as a "usb24s" from other devices, but the "divide rate" is not used.
Further, this clock itself is known as "usb24".
So, to set this clock is a little confusable.
This patch adds quick explain and sample code for this clock.
--- arch/arm/mach-shmobile/clock-r8a7740.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
arch/arm/mach-shmobile/clock-r8a7740.c +16 -0
@@ -188,6 +188,22 @@ static struct clk pllc1_div2_clk = { };/* USB clock */ +/* +* USBCKCR is controlling usb24 clock +* bit[7] : parent clock +* bit[6] : clock divide rate +* And this bit[7] is used as a "usb24s" from other devices. +* (Video clock / Sub clock / SPU clock) +* You can controll this clock as a below. +* +* struct clk *usb24 = clk_get(dev, "usb24"); +* struct clk *usb24s = clk_get(NULL, "usb24s"); +* struct clk *system = clk_get(NULL, "system_clk"); +* int rate = clk_get_rate(system); +* +* clk_set_parent(usb24s, system); // for bit[7] +* clk_set_rate(usb24, rate / 2); // for bit[6] +*/ static struct clk *usb24s_parents[] = { [0 ] = &system_clk, [1 ] = &extal2_clk
Signature · 1 line
1.7.10.2.484.gcd07cc5
PATCH 1/1 ARM: shmobile: r8a7740: add USB24 clock explain and sample code
Hi,
A couple of comments below.
Quoted 21 lines · Simon Horman
From: Kuninori Morimoto <[email protected]>
USBCKCR is controlling USB parent clock and divide rate. This parent clock is used as a "usb24s" from other devices, but the "divide rate" is not used.
Further, this clock itself is known as "usb24".
So, to set this clock is a little confusable.
This patch adds quick explain and sample code for this clock.Cc Damian Hobson-Garcia <[email protected]>Signed-off-by Kuninori Morimoto <[email protected]>Signed-off-by Simon Horman <[email protected]>--- arch/arm/mach-shmobile/clock-r8a7740.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)arch/arm/mach-shmobile/clock-r8a7740.c +0
-0
arch/arm/mach-shmobile/clock-r8a7740.c static struct clk pllc1_div2_clk = { · line 194
Quoted 7 lines
arch/arm/mach-shmobile/clock-r8a7740.c +4
-0@@ -188,6 +188,22 @@ static struct clk pllc1_div2_clk = { };/* USB clock */ +/* +* USBCKCR is controlling usb24 clock +* bit[7] : parent clock +* bit[6] : clock divide rate
The divisor is either 1 or 2 in this case, for bit[6] values of 0 and 1?
arch/arm/mach-shmobile/clock-r8a7740.c static struct clk pllc1_div2_clk = { · line 195
Quoted 1 line
arch/arm/mach-shmobile/clock-r8a7740.c +1
-0+* And this bit[7] is used as a "usb24s" from other devices.
Sorry, I don't follow the explanation here.
This is how I interpret the current code, can you confirm if it's accurate?
usb24 is the (potentially) divided output from usb24s, while usb24s is at a fixed pass-through rate from the parent if enabled. Both share the same enable bit. In other words, usb24 is a directly derived, potentially divided-by-two rate from usb24s?
arch/arm/mach-shmobile/clock-r8a7740.c static struct clk pllc1_div2_clk = { · line 205
Quoted 10 lines
arch/arm/mach-shmobile/clock-r8a7740.c +10
-0+* (Video clock / Sub clock / SPU clock) +* You can controll this clock as a below. +* +* struct clk *usb24 = clk_get(dev, "usb24"); +* struct clk *usb24s = clk_get(NULL, "usb24s"); +* struct clk *system = clk_get(NULL, "system_clk"); +* int rate = clk_get_rate(system); +* +* clk_set_parent(usb24s, system); // for bit[7] +* clk_set_rate(usb24, rate / 2); // for bit[6]
This is just standard clk infrastructure usage, I don't think there's need to include the example code here.
-Olof
PATCH 1/1 ARM: shmobile: r8a7740: add USB24 clock explain and sample code
Hi Olof
Thank you for checking patch
Quoted 24 lines · Simon Horman
Quoted 23 lines
From: Kuninori Morimoto <[email protected]>
USBCKCR is controlling USB parent clock and divide rate. This parent clock is used as a "usb24s" from other devices, but the "divide rate" is not used.
Further, this clock itself is known as "usb24".
So, to set this clock is a little confusable.
This patch adds quick explain and sample code for this clock.Cc Damian Hobson-Garcia <[email protected]>Signed-off-by Kuninori Morimoto <[email protected]>Signed-off-by Simon Horman <[email protected]>--- arch/arm/mach-shmobile/clock-r8a7740.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)arch/arm/mach-shmobile/clock-r8a7740.c +0
-0@@ -188,6 +188,22 @@ static struct clk pllc1_div2_clk = { };
Quoted 7 lines
arch/arm/mach-shmobile/clock-r8a7740.c static struct clk pllc1_div2_clk = { · line 194
Quoted 5 lines
arch/arm/mach-shmobile/clock-r8a7740.c +4
-0/* USB clock */ +/* +* USBCKCR is controlling usb24 clock +* bit[7] : parent clock +* bit[6] : clock divide rate The divisor is either 1 or 2 in this case, for bit[6] values of 0 and 1?
Yes.
if (0 == bit[6]) clock is 1/2
if (1 == bit[6]) clock is 1/1
Quoted 10 lines
arch/arm/mach-shmobile/clock-r8a7740.c static struct clk pllc1_div2_clk = { · line 195
Quoted 1 line
arch/arm/mach-shmobile/clock-r8a7740.c +1
-0+* And this bit[7] is used as a "usb24s" from other devices. Sorry, I don't follow the explanation here.
This is how I interpret the current code, can you confirm if it's accurate?
usb24 is the (potentially) divided output from usb24s, while usb24s is at a fixed pass-through rate from the parent if enabled. Both share the same enable bit. In other words, usb24 is a directly derived, potentially divided-by-two rate from usb24s?
clcok A ---+ bit[7] bit[6]
|- select -> usb24s -+--> divide (1/1 or 1/2) -> usb24
clock B ---+ |
+--> other clocks ->Quoted 11 lines
arch/arm/mach-shmobile/clock-r8a7740.c static struct clk pllc1_div2_clk = { · line 205
Quoted 10 lines
arch/arm/mach-shmobile/clock-r8a7740.c +10
-0+* (Video clock / Sub clock / SPU clock) +* You can controll this clock as a below. +* +* struct clk *usb24 = clk_get(dev, "usb24"); +* struct clk *usb24s = clk_get(NULL, "usb24s"); +* struct clk *system = clk_get(NULL, "system_clk"); +* int rate = clk_get_rate(system); +* +* clk_set_parent(usb24s, system); // for bit[7] +* clk_set_rate(usb24, rate / 2); // for bit[6]
Quoted 2 lines
This is just standard clk infrastructure usage, I don't think there's need to include the example code here.
Ahh.. 50% yes.
_If_ this usb24/usb24s explanation on datasheet is same as other clocks, it is easy to understand and can use clk_set_rate().
But this setting style of these 2 clock is very special case on our datasheet. Maybe first case.
So, I added sample setting code here,
since it is difficult to understand how to set the clock from datasheet/clock tree and clock-r8a7740.c
Best regards
---
Kuninori Morimoto