ARM: Add Altera SOCFPGA Cyclone5

PATCH Superseded dinguyen at altera.com 5 participants 14 messages Aug 31, 2012 – Sep 25, 2012

Subsystems (2)

Arm (32-bit) Arm/actions semi architecture

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dinguyen at altera.com

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2012-08-31 23:39 UTC #0 lore raw

PATCH v2 1/1 ARM: Add Altera SOCFPGA Cyclone5

From: Dinh Nguyen <[email protected]>

Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.

Applied on top of trini/WIP/spl-improvements v6

Signed-off-by Dinh Nguyen <[email protected]>

Signed-off-by Chin Liang See <[email protected]>

Signed-off-by Pavel Machek <[email protected]>

---
 MAINTAINERS                                        |    5 +
 arch/arm/cpu/armv7/socfpga/Makefile                |   51 +++++
 arch/arm/cpu/armv7/socfpga/config.mk               |   16 ++
 arch/arm/cpu/armv7/socfpga/lowlevel_init.S         |   77 +++++++
 arch/arm/cpu/armv7/socfpga/misc.c                  |   54 +++++
 arch/arm/cpu/armv7/socfpga/spl.c                   |   48 ++++
 arch/arm/cpu/armv7/socfpga/timer.c                 |  105 +++++++++
 arch/arm/cpu/armv7/socfpga/u-boot-spl.lds          |   57 +++++
 arch/arm/include/asm/arch-socfpga/reset_manager.h  |   37 +++
 .../include/asm/arch-socfpga/socfpga_base_addrs.h  |   27 +++
 arch/arm/include/asm/arch-socfpga/spl.h            |   26 +++
 arch/arm/include/asm/arch-socfpga/timer.h          |   29 +++
 board/altera/socfpga_cyclone5/Makefile             |   50 ++++
 board/altera/socfpga_cyclone5/socfpga_cyclone5.c   |   85 +++++++
 boards.cfg                                         |    1 +
 include/common.h                                   |    2 +-
 include/configs/socfpga_cyclone5.h                 |  240 ++++++++++++++++++++
 17 files changed, 909 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/cpu/armv7/socfpga/Makefile
 create mode 100644 arch/arm/cpu/armv7/socfpga/config.mk
 create mode 100644 arch/arm/cpu/armv7/socfpga/lowlevel_init.S
 create mode 100644 arch/arm/cpu/armv7/socfpga/misc.c
 create mode 100644 arch/arm/cpu/armv7/socfpga/spl.c
 create mode 100644 arch/arm/cpu/armv7/socfpga/timer.c
 create mode 100644 arch/arm/cpu/armv7/socfpga/u-boot-spl.lds
 create mode 100644 arch/arm/include/asm/arch-socfpga/reset_config.h
 create mode 100644 arch/arm/include/asm/arch-socfpga/reset_manager.h
 create mode 100644 arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
 create mode 100644 arch/arm/include/asm/arch-socfpga/spl.h
 create mode 100644 arch/arm/include/asm/arch-socfpga/timer.h
 create mode 100644 board/altera/socfpga_cyclone5/Makefile
 create mode 100644 board/altera/socfpga_cyclone5/socfpga_cyclone5.c
 create mode 100644 include/configs/socfpga_cyclone5.h

MAINTAINERS +5 -0

index c5a6f2f..df48dea 100644
@@ -765,6 +765,11 @@ Nagendra T S  <[email protected]>
 
    am3517_crane    ARM ARMV7 (AM35x SoC)
 
+Dinh Nguyen <[email protected]>
+Chin Liang See <[email protected]>
+
+	socfpga		socfpga_cyclone5
+
 Kyungmin Park <[email protected]>
 
 	apollon		ARM1136EJS

arch/arm/cpu/armv7/socfpga/Makefile new file +51 -0

51 lines not on this page · raw message

arch/arm/cpu/armv7/socfpga/config.mk new file +16 -0

new file mode 100644
index 0000000..b72ed1e
@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+ifndef CONFIG_SPL_BUILD
+ALL-y	+= $(obj)u-boot.img
+endif

arch/arm/cpu/armv7/socfpga/lowlevel_init.S new file +77 -0

77 lines not on this page · raw message

arch/arm/cpu/armv7/socfpga/misc.c new file +54 -0

54 lines not on this page · raw message

arch/arm/cpu/armv7/socfpga/spl.c new file +48 -0

48 lines not on this page · raw message

arch/arm/cpu/armv7/socfpga/timer.c new file +105 -0

105 lines not on this page · raw message

arch/arm/cpu/armv7/socfpga/u-boot-spl.lds new file +57 -0

57 lines not on this page · raw message

arch/arm/include/asm/arch-socfpga/reset_config.h new file +0 -0

new file mode 100644
index 0000000..e69de29

arch/arm/include/asm/arch-socfpga/reset_manager.h new file +37 -0

new file mode 100644
index 0000000..d9d2c1c
@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef	_RESET_MANAGER_H_
+#define	_RESET_MANAGER_H_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+struct socfpga_reset_manager {
+	u32	padding1;
+	u32	ctrl;
+	u32	padding2;
+	u32	padding3;
+	u32	mpu_mod_reset;
+	u32	per_mod_reset;
+	u32	per2_mod_reset;
+	u32	brg_mod_reset;
+};
+
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+
+#endif /* _RESET_MANAGER_H_ */

arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h new file +27 -0

new file mode 100644
index 0000000..f353eb2
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_BASE_ADDRS_H_
+#define _SOCFPGA_BASE_ADDRS_H_
+
+#define SOCFPGA_L3REGS_ADDRESS 0xff800000
+#define SOCFPGA_UART0_ADDRESS 0xffc02000
+#define SOCFPGA_UART1_ADDRESS 0xffc03000
+#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+
+#endif /* _SOCFPGA_BASE_ADDRS_H_ */

arch/arm/include/asm/arch-socfpga/spl.h new file +26 -0

new file mode 100644
index 0000000..c2014c5
@@ -0,0 +1,26 @@
+/*
+ *  Copyright (C) 2012 Pavel Machek <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_SPL_H_
+#define _SOCFPGA_SPL_H_
+
+/* Symbols from linker script */
+extern void __malloc_start, __malloc_end, __stack_start;
+
+#define BOOT_DEVICE_RAM 1
+
+#endif

arch/arm/include/asm/arch-socfpga/timer.h new file +29 -0

new file mode 100644
index 0000000..830c94a
@@ -0,0 +1,29 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_TIMER_H_
+#define _SOCFPGA_TIMER_H_
+
+struct socfpga_timer {
+	u32	load_val;
+	u32	curr_val;
+	u32	ctrl;
+	u32	eoi;
+	u32	int_stat;
+};
+
+#endif

board/altera/socfpga_cyclone5/Makefile new file +50 -0

50 lines not on this page · raw message

board/altera/socfpga_cyclone5/socfpga_cyclone5.c new file +85 -0

85 lines not on this page · raw message

boards.cfg +1 -0

index fdb84ad..1b5c860 100644
@@ -261,6 +261,7 @@ seaboard                     arm         armv7       seaboard            nvidia
 ventana                      arm         armv7       ventana             nvidia         tegra2
 whistler                     arm         armv7       whistler            nvidia         tegra2
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
+socfpga_cyclone5              arm         armv7      socfpga_cyclone5    altera		    socfpga
 actux1_4_16                  arm         ixp         actux1              -              -           actux1:FLASH2X2
 actux1_4_32                  arm         ixp         actux1              -              -           actux1:FLASH2X2,RAM_32MB
 actux1_8_16                  arm         ixp         actux1              -              -           actux1:FLASH1X8

include/common.h +1 -1

index 55025c0..e57301f 100644
@@ -582,7 +582,7 @@ int	checkicache   (void);
 int	checkdcache   (void);
 void	upmconfig     (unsigned int, unsigned int *, unsigned int);
 ulong	get_tbclk     (void);
-void	reset_cpu     (ulong addr);
+void	reset_cpu     (ulong addr) __attribute__((noreturn));
 #if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
 void ft_cpu_setup(void *blob, bd_t *bd);
 #ifdef CONFIG_PCI

include/configs/socfpga_cyclone5.h new file +240 -0

240 lines not on this page · raw message

Signature · 1 line

1.7.9.5

Marek Vasut

2012-08-31 22:47 UTC #1 lore raw

PATCH v2 1/1 ARM: Add Altera SOCFPGA Cyclone5

Dear dinguyen at altera.com,

Quoted 5 lines

From: Dinh Nguyen <[email protected]>
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
Applied on top of trini/WIP/spl-improvements v6

[...]

__noreturn attribute to reset_cpu() is still missing, but that's a minor thing.

All in all, the code is really nice! Very good job! :-)

Reviewed-by Marek Vasut <[email protected]>

Best regards,
Marek Vasut

Pavel Machek

2012-09-11 00:17 UTC #2 lore raw

PATCH 1/1 make reset_cpu nonreturn.

Hi!

Quoted 8 lines

Quoted 5 lines
From: Dinh Nguyen <[email protected]>
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
Applied on top of trini/WIP/spl-improvements v6
[...]
__noreturn attribute to reset_cpu() is still missing, but that's a minor thing.

Hmm, I thought about it, but I guess the right solution is below.

---

reset_cpu should never return, annotate it as such.

Signed-off-by Pavel Machek <[email protected]>

include/common.h +1 -1

index 55025c0..e57301f 100644
@@ -582,7 +582,7 @@ int	checkicache   (void);
 int	checkdcache   (void);
 void	upmconfig     (unsigned int, unsigned int *, unsigned int);
 ulong	get_tbclk     (void);
-void	reset_cpu     (ulong addr);
+void	reset_cpu     (ulong addr) __attribute__((noreturn));
 #if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
 void ft_cpu_setup(void *blob, bd_t *bd);
 #ifdef CONFIG_PCI

Signature · 2 lines

(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Pavel Machek

2012-09-12 09:16 UTC #4 lore raw

PATCH 1/1 make reset_cpu nonreturn.

Hi!

Quoted 8 lines

Quoted 8 lines
Quoted 8 lines
Quoted 5 lines
From: Dinh Nguyen <[email protected]>
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
Applied on top of trini/WIP/spl-improvements v6
[...]

Quoted 7 lines

Quoted 4 lines
Quoted 2 lines
__noreturn attribute to reset_cpu() is still missing, but that's a minor thing.
Hmm, I thought about it, but I guess the right solution is below.
You sure it's propagated through to the function (aka. that it's not ignored) ? If so, WFM.

I think so. It is actually when optimizing the caller when "nonreturn" is important...
Pavel

Signature · 2 lines

(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Pavel Machek

2012-09-11 00:21 UTC #5 lore raw

PATCH v2 1/1 ARM: Add Altera SOCFPGA Cyclone5

In reply to Marek Vasut

Hi!

Quoted 9 lines

Quoted 5 lines
From: Dinh Nguyen <[email protected]>
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
Applied on top of trini/WIP/spl-improvements v6
[...]
__noreturn attribute to reset_cpu() is still missing, but that's a minor thing.

Plus, I guess these should be deleted. We already have prototype in common....

arch/arm/include/asm/arch-kirkwood/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-orion5x/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-socfpga/reset_manager.h:void reset_cpu(ulong addr);

What needs to be done to get the socfpga patches merged?
Pavel

Signature · 2 lines

(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Stefan Roese

2012-09-11 05:53 UTC #6 lore raw

PATCH v2 1/1 ARM: Add Altera SOCFPGA Cyclone5

Hi Pavel,

Quoted 10 lines · Pavel Machek

Quoted 9 lines
Quoted 5 lines
From: Dinh Nguyen <[email protected]>
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
Applied on top of trini/WIP/spl-improvements v6
[...]
__noreturn attribute to reset_cpu() is still missing, but that's a minor thing.

Quoted 6 lines

Plus, I guess these should be deleted. We already have prototype in common....
arch/arm/include/asm/arch-kirkwood/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-orion5x/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-socfpga/reset_manager.h:void reset_cpu(ulong addr);

Yes, good catch.

Quoted 1 line

What needs to be done to get the socfpga patches merged?

As the patches are based upon the SPL framework patches from Tom Rini, Tom's patches need to get included first. AFAICT, this SPL framework will not go into mainline for the upcoming release, but will be pushed into next, once it opens.

Thanks,
Stefan

Pavel Machek

2012-09-12 09:23 UTC #7 lore raw

PATCH v2 1/1 ARM: Add Altera SOCFPGA Cyclone5

Hi!

Quoted 18 lines · Pavel Machek

Quoted 10 lines
Quoted 9 lines
Quoted 5 lines
From: Dinh Nguyen <[email protected]>
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
Applied on top of trini/WIP/spl-improvements v6
[...]
__noreturn attribute to reset_cpu() is still missing, but that's a minor thing.
Quoted 6 lines
Plus, I guess these should be deleted. We already have prototype in common....
arch/arm/include/asm/arch-kirkwood/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-orion5x/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-socfpga/reset_manager.h:void reset_cpu(ulong addr);

Quoted 8 lines

Yes, good catch.
Quoted 1 line
What needs to be done to get the socfpga patches merged?
As the patches are based upon the SPL framework patches from Tom Rini, Tom's patches need to get included first. AFAICT, this SPL framework will not go into mainline for the upcoming release, but will be pushed into next, once it opens.

Would it make sense to push the changes without SPL, then? SPL is minority...
Pavel

MAINTAINERS +5 -0

index c5a6f2f..df48dea 100644
@@ -765,6 +765,11 @@ Nagendra T S  <[email protected]>
 
    am3517_crane    ARM ARMV7 (AM35x SoC)
 
+Dinh Nguyen <[email protected]>
+Chin Liang See <[email protected]>
+
+	socfpga		socfpga_cyclone5
+
 Kyungmin Park <[email protected]>
 
 	apollon		ARM1136EJS

arch/arm/cpu/armv7/socfpga/Makefile new file +50 -0

50 lines not on this page · raw message

arch/arm/cpu/armv7/socfpga/config.mk new file +16 -0

new file mode 100644
index 0000000..b72ed1e
@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+ifndef CONFIG_SPL_BUILD
+ALL-y	+= $(obj)u-boot.img
+endif

arch/arm/cpu/armv7/socfpga/lowlevel_init.S new file +70 -0

70 lines not on this page · raw message

arch/arm/cpu/armv7/socfpga/misc.c new file +54 -0

54 lines not on this page · raw message

arch/arm/cpu/armv7/socfpga/timer.c new file +105 -0

105 lines not on this page · raw message

arch/arm/include/asm/arch-socfpga/reset_config.h new file +0 -0

new file mode 100644
index 0000000..e69de29

arch/arm/include/asm/arch-socfpga/reset_manager.h new file +37 -0

new file mode 100644
index 0000000..d9d2c1c
@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef	_RESET_MANAGER_H_
+#define	_RESET_MANAGER_H_
+
+void reset_cpu(ulong addr);
+void reset_deassert_peripherals_handoff(void);
+
+struct socfpga_reset_manager {
+	u32	padding1;
+	u32	ctrl;
+	u32	padding2;
+	u32	padding3;
+	u32	mpu_mod_reset;
+	u32	per_mod_reset;
+	u32	per2_mod_reset;
+	u32	brg_mod_reset;
+};
+
+#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
+
+#endif /* _RESET_MANAGER_H_ */

arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h new file +27 -0

new file mode 100644
index 0000000..f353eb2
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_BASE_ADDRS_H_
+#define _SOCFPGA_BASE_ADDRS_H_
+
+#define SOCFPGA_L3REGS_ADDRESS 0xff800000
+#define SOCFPGA_UART0_ADDRESS 0xffc02000
+#define SOCFPGA_UART1_ADDRESS 0xffc03000
+#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+
+#endif /* _SOCFPGA_BASE_ADDRS_H_ */

arch/arm/include/asm/arch-socfpga/timer.h new file +29 -0

new file mode 100644
index 0000000..830c94a
@@ -0,0 +1,29 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _SOCFPGA_TIMER_H_
+#define _SOCFPGA_TIMER_H_
+
+struct socfpga_timer {
+	u32	load_val;
+	u32	curr_val;
+	u32	ctrl;
+	u32	eoi;
+	u32	int_stat;
+};
+
+#endif

board/altera/socfpga_cyclone5/Makefile new file +50 -0

50 lines not on this page · raw message

board/altera/socfpga_cyclone5/socfpga_cyclone5.c new file +85 -0

85 lines not on this page · raw message

boards.cfg +1 -0

index fdb84ad..1b5c860 100644
@@ -261,6 +261,7 @@ seaboard                     arm         armv7       seaboard            nvidia
 ventana                      arm         armv7       ventana             nvidia         tegra2
 whistler                     arm         armv7       whistler            nvidia         tegra2
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
+socfpga_cyclone5              arm         armv7      socfpga_cyclone5    altera		    socfpga

v actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2

 actux1_4_32                  arm         ixp         actux1              -              -           actux1:FLASH2X2,RAM_32MB
 actux1_8_16                  arm         ixp         actux1              -              -           actux1:FLASH1X8

include/configs/socfpga_cyclone5.h new file +199 -0

199 lines not on this page · raw message

Signature · 2 lines

(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Tom Rini

2012-09-12 16:56 UTC #8 lore raw

PATCH v2 1/1 ARM: Add Altera SOCFPGA Cyclone5

In reply to Stefan Roese

Quoted 20 lines · Stefan Roese

Hi Pavel,
Quoted 10 lines · Pavel Machek
Quoted 9 lines
Quoted 5 lines
From: Dinh Nguyen <[email protected]>
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
Applied on top of trini/WIP/spl-improvements v6
[...]
__noreturn attribute to reset_cpu() is still missing, but that's a minor thing.
Quoted 6 lines
Plus, I guess these should be deleted. We already have prototype in common....
arch/arm/include/asm/arch-kirkwood/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-orion5x/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-socfpga/reset_manager.h:void reset_cpu(ulong addr);

Quoted 8 lines

Yes, good catch.
Quoted 1 line
What needs to be done to get the socfpga patches merged?
As the patches are based upon the SPL framework patches from Tom Rini, Tom's patches need to get included first. AFAICT, this SPL framework will not go into mainline for the upcoming release, but will be pushed into next, once it opens.

I posted the first series by the end of the merge window with the intention of getting it into this release. So long as there are no objections (I haven't seen any further comments), I plan to merge it soon (after working over the backlog of pull request).

Signature · 1 line

Tom

Stefan Roese

2012-09-13 06:51 UTC #9 lore raw

PATCH v2 1/1 ARM: Add Altera SOCFPGA Cyclone5

Quoted 30 lines · Tom Rini

Quoted 20 lines · Stefan Roese
Hi Pavel,
Quoted 10 lines · Pavel Machek
Quoted 9 lines
Quoted 5 lines
From: Dinh Nguyen <[email protected]>
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
Applied on top of trini/WIP/spl-improvements v6
[...]
__noreturn attribute to reset_cpu() is still missing, but that's a minor thing.
Quoted 6 lines
Plus, I guess these should be deleted. We already have prototype in common....
arch/arm/include/asm/arch-kirkwood/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-orion5x/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-socfpga/reset_manager.h:void reset_cpu(ulong addr);
Quoted 8 lines
Yes, good catch.
Quoted 1 line
What needs to be done to get the socfpga patches merged?
As the patches are based upon the SPL framework patches from Tom Rini, Tom's patches need to get included first. AFAICT, this SPL framework will not go into mainline for the upcoming release, but will be pushed into next, once it opens.

Quoted 4 lines

I posted the first series by the end of the merge window with the intention of getting it into this release. So long as there are no objections (I haven't seen any further comments), I plan to merge it soon (after working over the backlog of pull request).

Even better. I'll rebase my powerpc SPL support once the SPL framework is in master.

Thanks,
Stefan

Marek Vasut

2012-09-11 06:54 UTC #10 lore raw

PATCH v2 1/1 ARM: Add Altera SOCFPGA Cyclone5

In reply to Pavel Machek

Dear Pavel Machek,

Quoted 13 lines

Hi!
Quoted 10 lines
Quoted 5 lines
From: Dinh Nguyen <[email protected]>
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
Applied on top of trini/WIP/spl-improvements v6
[...]
__noreturn attribute to reset_cpu() is still missing, but that's a minor thing.

Quoted 7 lines

Plus, I guess these should be deleted. We already have prototype in common....
arch/arm/include/asm/arch-kirkwood/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-orion5x/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-socfpga/reset_manager.h:void reset_cpu(ulong addr);

Agreed.

Quoted 1 line

What needs to be done to get the socfpga patches merged?

I'd say, sacrifice a chicken :-) The patches look quite fine :-)

Quoted 1 line

Pavel

Best regards,
Marek Vasut

Pavel Machek

2012-09-25 12:26 UTC #11 lore raw

PATCH v2 1/1 ARM: Add Altera SOCFPGA Cyclone5

Quoted 23 lines · Marek Vasut

Dear Pavel Machek,
Quoted 13 lines
Hi!
Quoted 10 lines
Quoted 5 lines
From: Dinh Nguyen <[email protected]>
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
Applied on top of trini/WIP/spl-improvements v6
[...]
__noreturn attribute to reset_cpu() is still missing, but that's a minor thing.
Quoted 7 lines
Plus, I guess these should be deleted. We already have prototype in common....
arch/arm/include/asm/arch-kirkwood/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-orion5x/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-socfpga/reset_manager.h:void reset_cpu(ulong addr);

Quoted 5 lines

Agreed.
Quoted 1 line
What needs to be done to get the socfpga patches merged?
I'd say, sacrifice a chicken :-) The patches look quite fine :-)

Will guinea pig do the trick? I'll ask around ;-).
Pavel

Signature · 2 lines

(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

Marek Vasut

2012-09-25 13:58 UTC #12 lore raw

PATCH v2 1/1 ARM: Add Altera SOCFPGA Cyclone5

Dear Pavel Machek,

[...]

Quoted 5 lines

Quoted 3 lines
Quoted 1 line
What needs to be done to get the socfpga patches merged?
I'd say, sacrifice a chicken :-) The patches look quite fine :-)
Will guinea pig do the trick? I'll ask around ;-).

No, but don't worry, I had KFC recently ... I believe the sacrificial potential doesn't get lost by making the chicken into Longer %^)

btw. -next is now open too, so it really can be merged now ... though I wont object even into stable.

Best regards,
Marek Vasut

Tom Rini

2012-09-12 17:02 UTC #13 lore raw

PATCH v2 1/1 ARM: Add Altera SOCFPGA Cyclone5

In reply to Pavel Machek

Quoted 12 lines · Pavel Machek

Hi!
Quoted 9 lines
Quoted 5 lines
From: Dinh Nguyen <[email protected]>
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
Applied on top of trini/WIP/spl-improvements v6
[...]
__noreturn attribute to reset_cpu() is still missing, but that's a minor thing.

Quoted 8 lines

Plus, I guess these should be deleted. We already have prototype in common....
arch/arm/include/asm/arch-kirkwood/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-orion5x/cpu.h:void reset_cpu(unsigned long ignored); arch/arm/include/asm/arch-socfpga/reset_manager.h:void reset_cpu(ulong addr);
What needs to be done to get the socfpga patches merged?

Please do a v2 of the common.h patch that removes these SoC declarations and confirm that MAKEALL -s kirkwood -s orion5x compiles without new warnings. Thanks!

Signature · 1 line

Tom