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Add basic address decoding support for Marvell 370/XP

PATCH Superseded Thomas Petazzoni 4 participants 27 messages Sep 11, 2012 – Oct 17, 2012

Subsystems (5)
Device tree bindings Arm (32-bit) Arm sub-architectures Arm/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SoC support +1 more subsystems
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Thomas Petazzoni

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#0 lore raw

PATCH v4 1/1 Add basic address decoding support for Marvell 370/XP

Andrew, Jason, Gr?gory,

Here is a patch set that introduces basic support for address decoding on Armada 370 and Armada XP. The aim of this basic support is essentially to be able to configure a window to remap the BootROM, which is needed to startup the secondary CPUs for the SMP support.

As we had discussed already, the address decoding configuration is not described in the Device Tree, it is for now hardcoded on a per-SoC basis. We might later discuss how to extend this to the Device Tree.

The patch set is relatively long, as it refactors some existing Dove/Kirkwood/MV78xx0/Orion code to use void __iomem pointers instead of unsigned long, as per the request of Arnd Bergmann and Olof Johansson.

This patch set is split in several parts:

(1) Patches 1-4 replaces binary or operators used in register address definitions by plus operators. This is necessary because followup patches change the base addresses constants to void __iomem pointers, and binary or arithmetic on pointers is not allowed. Also, using the plus operator to add an offset to a base address is much more traditional. In our case, the binary or operator and plus operator seem equivalent, as the low-order bits of the base addresses that were being or'ed with an offset were all zero.

(2) Patches 5-9 use the IOMEM() macro to turn the various base virtual addresses constants into void __iomem pointers. This naturally makes all derived constants (virtual addresses of specific registers or units) as void __iomem pointers as well. The patches also adjust the code to take into this change. It adds a few temporary "(unsigned long)" casts that are removed by the following patches that rework a few plat-orion APIs. These temporary casts are necessary to make the patch set properly bisectable, without having a single big patch that does the complete IOMEM() conversion. At the end of the patch set, the only (unsigned long) casts that remain are the one in the map_desc[] array definitions, and those ones are expected.

(3) Patches 10-13 rework some plat-orion APIs so that they use void __iomem pointers instead of unsigned long for virtual addresses. Those patches also remove the now useless "(unsigned long)" casts added in step (2) above.

(4) Patch 14 introduces PLAT_ORION_LEGACY, which allows the Marvell 370/XP platforms to be part of PLAT_ORION, and therefore re-use the existing address decoding code.

(5) Patch 15 makes a small change to an address decoding structure so that we can define at runtime the virtual address of the configuration registers. This is needed as on Armada 370/XP the address decoding "controller" is declared in the Device Tree.

(6) Patch 16 adds the 370/XP address decoding code itself. For now, it only maps the BootROM on Armada XP.

(7) Patch 17 adds the necessary DT code to instantiate the address decoding "controller".

This patch set has been:

* Built, boot tested on Armada XP. The operation of the address mapping support has been tested as well.

* Built tested only on Dove, Kirkwood, Orion5x and MV78xx0.

Changes since v3:
* As per the request of Olof Johansson, use void __iomem pointers everywhere instead of introducing more casts in the patch set. This change has significantly increased the patch set size, though (going from 5 patches in v3 to 17 patches in v4)

Changes since v2:
* Remove one more useless (void __iomem *) cast in the Armada 370/XP addr-map.c file, as noticed by Arnd Bergmann.

Changes since v1:
* Use void __iomem * in addr-map code. Suggested by Arnd Bergmann.
* Add Acked-by on patches 2->5 from Gr?gory Cl?ment

Thanks,

Thomas Petazzoni

author
#1 lore raw

PATCH v4 1/17 arm: mach-dove: use plus instead of or for address definitions

Since we are going to use IOMEM() to define many base virtual addresses, we can no longer use binary or to define the individual register addresses ("binary or" arithmetic on pointers is not allowed). Instead, use the more conventional plus operator to do so.

The binary or operators were actually not useful because the low-order bits of the base address were always zero, so the usage of the binary or operators was effectively identical to a plus operator.

Signed-off-by Thomas Petazzoni <[email protected]>
---
 arch/arm/mach-dove/include/mach/bridge-regs.h |   16 ++--
 arch/arm/mach-dove/include/mach/dove.h        |  118 ++++++++++++-------------
 2 files changed, 67 insertions(+), 67 deletions(-)
arch/arm/mach-dove/include/mach/bridge-regs.h +8 -8
index f953bb5..99f259e 100644
@@ -13,22 +13,22 @@
 
 #include <mach/dove.h>
 
-#define CPU_CONFIG		(BRIDGE_VIRT_BASE | 0x0000)
+#define CPU_CONFIG		(BRIDGE_VIRT_BASE + 0x0000)
 
-#define CPU_CONTROL		(BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL		(BRIDGE_VIRT_BASE + 0x0104)
 #define  CPU_CTRL_PCIE0_LINK	0x00000001
 #define  CPU_RESET		0x00000002
 #define  CPU_CTRL_PCIE1_LINK	0x00000008
 
-#define RSTOUTn_MASK		(BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK		(BRIDGE_VIRT_BASE + 0x0108)
 #define  SOFT_RESET_OUT_EN	0x00000004
 
-#define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE + 0x010c)
 #define  SOFT_RESET		0x00000001
 
 #define  BRIDGE_INT_TIMER1_CLR	(~0x0004)
 
-#define IRQ_VIRT_BASE		(BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_LOW_OFF	0x0000
 #define IRQ_MASK_LOW_OFF	0x0004
 #define FIQ_MASK_LOW_OFF	0x0008

@@ -47,9 +47,9 @@
 #define ENDPOINT_MASK_HIGH	(IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
 #define PCIE_INTERRUPT_MASK	(IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
 
-#define POWER_MANAGEMENT	(BRIDGE_VIRT_BASE | 0x011c)
+#define POWER_MANAGEMENT	(BRIDGE_VIRT_BASE + 0x011c)
 
-#define TIMER_VIRT_BASE		(BRIDGE_VIRT_BASE | 0x0300)
-#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0300)
+#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
 
 #endif
arch/arm/mach-dove/include/mach/dove.h +59 -59

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#2 lore raw

PATCH v4 2/17 arm: mach-kirkwood: use plus instead of or for address definitions

In reply to Thomas Petazzoni

Since we are going to use IOMEM() to define many base virtual addresses, we can no longer use binary or to define the individual register addresses ("binary or" arithmetic on pointers is not allowed). Instead, use the more conventional plus operator to do so.

The binary or operators were actually not useful because the low-order bits of the base address were always zero, so the usage of the binary or operators was effectively identical to a plus operator.

Signed-off-by Thomas Petazzoni <[email protected]>
---
 arch/arm/mach-kirkwood/include/mach/bridge-regs.h |   20 ++--
 arch/arm/mach-kirkwood/include/mach/kirkwood.h    |  110 ++++++++++-----------
 2 files changed, 65 insertions(+), 65 deletions(-)
arch/arm/mach-kirkwood/include/mach/bridge-regs.h +10 -10
index a115142..5c82b7d 100644
@@ -13,37 +13,37 @@
 
 #include <mach/kirkwood.h>
 
-#define CPU_CONFIG		(BRIDGE_VIRT_BASE | 0x0100)
+#define CPU_CONFIG		(BRIDGE_VIRT_BASE + 0x0100)
 #define CPU_CONFIG_ERROR_PROP	0x00000004
 
-#define CPU_CONTROL		(BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL		(BRIDGE_VIRT_BASE + 0x0104)
 #define CPU_RESET		0x00000002
 
-#define RSTOUTn_MASK		(BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK		(BRIDGE_VIRT_BASE + 0x0108)
 #define WDT_RESET_OUT_EN	0x00000002
 #define SOFT_RESET_OUT_EN	0x00000004
 
-#define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE + 0x010c)
 #define SOFT_RESET		0x00000001
 
-#define BRIDGE_CAUSE		(BRIDGE_VIRT_BASE | 0x0110)
+#define BRIDGE_CAUSE		(BRIDGE_VIRT_BASE + 0x0110)
 #define WDT_INT_REQ		0x0008
 
 #define BRIDGE_INT_TIMER1_CLR	(~0x0004)
 
-#define IRQ_VIRT_BASE		(BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_LOW_OFF	0x0000
 #define IRQ_MASK_LOW_OFF	0x0004
 #define IRQ_CAUSE_HIGH_OFF	0x0010
 #define IRQ_MASK_HIGH_OFF	0x0014
 
-#define TIMER_VIRT_BASE		(BRIDGE_VIRT_BASE | 0x0300)
-#define TIMER_PHYS_BASE		(BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0300)
+#define TIMER_PHYS_BASE		(BRIDGE_PHYS_BASE + 0x0300)
 
-#define L2_CONFIG_REG		(BRIDGE_VIRT_BASE | 0x0128)
+#define L2_CONFIG_REG		(BRIDGE_VIRT_BASE + 0x0128)
 #define L2_WRITETHROUGH		0x00000010
 
-#define CLOCK_GATING_CTRL	(BRIDGE_VIRT_BASE | 0x11c)
+#define CLOCK_GATING_CTRL	(BRIDGE_VIRT_BASE + 0x11c)
 #define CGC_BIT_GE0		(0)
 #define CGC_BIT_PEX0		(2)
 #define CGC_BIT_USB0		(3)
arch/arm/mach-kirkwood/include/mach/kirkwood.h +55 -55

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#3 lore raw

PATCH v4 3/17 arm: mach-mv78xx0: use plus instead of or for address definitions

In reply to Thomas Petazzoni

Since we are going to use IOMEM() to define many base virtual addresses, we can no longer use binary or to define the individual register addresses ("binary or" arithmetic on pointers is not allowed). Instead, use the more conventional plus operator to do so.

The binary or operators were actually not useful because the low-order bits of the base address were always zero, so the usage of the binary or operators was effectively identical to a plus operator.

Signed-off-by Thomas Petazzoni <[email protected]>
---
 arch/arm/mach-mv78xx0/include/mach/bridge-regs.h |   12 ++--
 arch/arm/mach-mv78xx0/include/mach/mv78xx0.h     |   82 +++++++++++-----------
 2 files changed, 47 insertions(+), 47 deletions(-)
arch/arm/mach-mv78xx0/include/mach/bridge-regs.h +6 -6
index eb187e0..5f03484 100644
@@ -11,18 +11,18 @@
 
 #include <mach/mv78xx0.h>
 
-#define CPU_CONTROL		(BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL		(BRIDGE_VIRT_BASE + 0x0104)
 #define L2_WRITETHROUGH		0x00020000
 
-#define RSTOUTn_MASK		(BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK		(BRIDGE_VIRT_BASE + 0x0108)
 #define SOFT_RESET_OUT_EN	0x00000004
 
-#define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE + 0x010c)
 #define SOFT_RESET		0x00000001
 
 #define BRIDGE_INT_TIMER1_CLR	(~0x0004)
 
-#define IRQ_VIRT_BASE		(BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_ERR_OFF	0x0000
 #define IRQ_CAUSE_LOW_OFF	0x0004
 #define IRQ_CAUSE_HIGH_OFF	0x0008

@@ -30,7 +30,7 @@
 #define IRQ_MASK_LOW_OFF	0x0010
 #define IRQ_MASK_HIGH_OFF	0x0014
 
-#define TIMER_VIRT_BASE		(BRIDGE_VIRT_BASE | 0x0300)
-#define TIMER_PHYS_BASE		(BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_VIRT_BASE		(BRIDGE_VIRT_BASE + 0x0300)
+#define TIMER_PHYS_BASE		(BRIDGE_PHYS_BASE + 0x0300)
 
 #endif
arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +41 -41

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#4 lore raw

PATCH v4 4/17 arm: mach-orion5x: use plus instead of or for address definitions

In reply to Thomas Petazzoni

Since we are going to use IOMEM() to define many base virtual addresses, we can no longer use binary or to define the individual register addresses ("binary or" arithmetic on pointers is not allowed). Instead, use the more conventional plus operator to do so.

The binary or operators were actually not useful because the low-order bits of the base address were always zero, so the usage of the binary or operators was effectively identical to a plus operator.

Signed-off-by Thomas Petazzoni <[email protected]>
---
 arch/arm/mach-orion5x/include/mach/bridge-regs.h |   20 ++++-----
 arch/arm/mach-orion5x/include/mach/orion5x.h     |   52 +++++++++++-----------
 arch/arm/mach-orion5x/pci.c                      |    2 +-
 3 files changed, 37 insertions(+), 37 deletions(-)
arch/arm/mach-orion5x/include/mach/bridge-regs.h +10 -10
index 11a3c1e..461fd69 100644
@@ -13,27 +13,27 @@
 
 #include <mach/orion5x.h>
 
-#define CPU_CONF		(ORION5X_BRIDGE_VIRT_BASE | 0x100)
+#define CPU_CONF		(ORION5X_BRIDGE_VIRT_BASE + 0x100)
 
-#define CPU_CTRL		(ORION5X_BRIDGE_VIRT_BASE | 0x104)
+#define CPU_CTRL		(ORION5X_BRIDGE_VIRT_BASE + 0x104)
 
-#define RSTOUTn_MASK		(ORION5X_BRIDGE_VIRT_BASE | 0x108)
+#define RSTOUTn_MASK		(ORION5X_BRIDGE_VIRT_BASE + 0x108)
 #define WDT_RESET_OUT_EN	0x0002
 
-#define CPU_SOFT_RESET		(ORION5X_BRIDGE_VIRT_BASE | 0x10c)
+#define CPU_SOFT_RESET		(ORION5X_BRIDGE_VIRT_BASE + 0x10c)
 
-#define BRIDGE_CAUSE		(ORION5X_BRIDGE_VIRT_BASE | 0x110)
+#define BRIDGE_CAUSE		(ORION5X_BRIDGE_VIRT_BASE + 0x110)
 
-#define POWER_MNG_CTRL_REG	(ORION5X_BRIDGE_VIRT_BASE | 0x11C)
+#define POWER_MNG_CTRL_REG	(ORION5X_BRIDGE_VIRT_BASE + 0x11C)
 
 #define WDT_INT_REQ		0x0008
 
 #define BRIDGE_INT_TIMER1_CLR	(~0x0004)
 
-#define MAIN_IRQ_CAUSE		(ORION5X_BRIDGE_VIRT_BASE | 0x200)
+#define MAIN_IRQ_CAUSE		(ORION5X_BRIDGE_VIRT_BASE + 0x200)
 
-#define MAIN_IRQ_MASK		(ORION5X_BRIDGE_VIRT_BASE | 0x204)
+#define MAIN_IRQ_MASK		(ORION5X_BRIDGE_VIRT_BASE + 0x204)
 
-#define TIMER_VIRT_BASE		(ORION5X_BRIDGE_VIRT_BASE | 0x300)
-#define TIMER_PHYS_BASE		(ORION5X_BRIDGE_PHYS_BASE | 0x300)
+#define TIMER_VIRT_BASE		(ORION5X_BRIDGE_VIRT_BASE + 0x300)
+#define TIMER_PHYS_BASE		(ORION5X_BRIDGE_PHYS_BASE + 0x300)
 #endif
arch/arm/mach-orion5x/include/mach/orion5x.h +26 -26

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arch/arm/mach-orion5x/pci.c +1 -1
index cb19e16..b36f928 100644
@@ -198,7 +198,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
 /*****************************************************************************
  * PCI controller
  ****************************************************************************/
-#define ORION5X_PCI_REG(x)	(ORION5X_PCI_VIRT_BASE | (x))
+#define ORION5X_PCI_REG(x)	(ORION5X_PCI_VIRT_BASE + (x))
 #define PCI_MODE		ORION5X_PCI_REG(0xd00)
 #define PCI_CMD			ORION5X_PCI_REG(0xc00)
 #define PCI_P2P_CONF		ORION5X_PCI_REG(0x1d14)
Signature · 1 line
1.7.9.5
author
#5 lore raw

PATCH v4 5/17 arm: mach-dove: use IOMEM() for base address definitions

In reply to Thomas Petazzoni

We now define all virtual base address constants using IOMEM() so that those are naturally typed as void __iomem pointers, and we do the necessary adjustements in the mach-dove code.

Note that we introduce a few temporary additional "unsigned long" casts when calling into plat-orion functions. Those are removed by followup patches converting plat-orion functions to void __iomem pointers as well.

Signed-off-by Thomas Petazzoni <[email protected]>
---
 arch/arm/mach-dove/addr-map.c          |    2 +-
 arch/arm/mach-dove/common.c            |   25 +++++++++++++++----------
 arch/arm/mach-dove/include/mach/dove.h |   12 ++++++------
 arch/arm/mach-dove/irq.c               |   10 +++++-----
 arch/arm/mach-dove/mpp.c               |    3 ++-
 arch/arm/mach-dove/pcie.c              |    6 +++---
 6 files changed, 32 insertions(+), 26 deletions(-)
arch/arm/mach-dove/addr-map.c +1 -1
index 2a06c01..b92c9c7 100644
@@ -47,7 +47,7 @@ static inline void __iomem *ddr_map_sc(int i)
 static struct __initdata orion_addr_map_cfg addr_map_cfg = {
 	.num_wins = 8,
 	.remappable_wins = 4,
-	.bridge_virt_base = BRIDGE_VIRT_BASE,
+	.bridge_virt_base = (unsigned long) BRIDGE_VIRT_BASE,
 };
 
 static const struct __initdata orion_addr_map_info addr_map_info[] = {
arch/arm/mach-dove/common.c +15 -10
index 6321567..533fd81 100644
@@ -40,22 +40,22 @@ static int get_tclk(void);
  ****************************************************************************/
 static struct map_desc dove_io_desc[] __initdata = {
 	{
-		.virtual	= DOVE_SB_REGS_VIRT_BASE,
+		.virtual	= (unsigned long) DOVE_SB_REGS_VIRT_BASE,
 		.pfn		= __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
 		.length		= DOVE_SB_REGS_SIZE,
 		.type		= MT_DEVICE,
 	}, {
-		.virtual	= DOVE_NB_REGS_VIRT_BASE,
+		.virtual	= (unsigned long) DOVE_NB_REGS_VIRT_BASE,
 		.pfn		= __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
 		.length		= DOVE_NB_REGS_SIZE,
 		.type		= MT_DEVICE,
 	}, {
-		.virtual	= DOVE_PCIE0_IO_VIRT_BASE,
+		.virtual	= (unsigned long) DOVE_PCIE0_IO_VIRT_BASE,
 		.pfn		= __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
 		.length		= DOVE_PCIE0_IO_SIZE,
 		.type		= MT_DEVICE,
 	}, {
-		.virtual	= DOVE_PCIE1_IO_VIRT_BASE,
+		.virtual	= (unsigned long) DOVE_PCIE1_IO_VIRT_BASE,
 		.pfn		= __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
 		.length		= DOVE_PCIE1_IO_SIZE,
 		.type		= MT_DEVICE,

@@ -128,7 +128,8 @@ void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
  ****************************************************************************/
 void __init dove_uart0_init(void)
 {
-	orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
+	orion_uart0_init((unsigned long) DOVE_UART0_VIRT_BASE,
+			 DOVE_UART0_PHYS_BASE,
 			 IRQ_DOVE_UART_0, tclk);
 }
 

@@ -137,7 +138,8 @@ void __init dove_uart0_init(void)
  ****************************************************************************/
 void __init dove_uart1_init(void)
 {
-	orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
+	orion_uart1_init((unsigned long) DOVE_UART1_VIRT_BASE,
+			 DOVE_UART1_PHYS_BASE,
 			 IRQ_DOVE_UART_1, tclk);
 }
 

@@ -146,7 +148,8 @@ void __init dove_uart1_init(void)
  ****************************************************************************/
 void __init dove_uart2_init(void)
 {
-	orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
+	orion_uart2_init((unsigned long) DOVE_UART2_VIRT_BASE,
+			 DOVE_UART2_PHYS_BASE,
 			 IRQ_DOVE_UART_2, tclk);
 }
 

@@ -155,7 +158,8 @@ void __init dove_uart2_init(void)
  ****************************************************************************/
 void __init dove_uart3_init(void)
 {
-	orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
+	orion_uart3_init((unsigned long) DOVE_UART3_VIRT_BASE,
+			 DOVE_UART3_PHYS_BASE,
 			 IRQ_DOVE_UART_3, tclk);
 }
 

@@ -185,7 +189,7 @@ void __init dove_i2c_init(void)
  ****************************************************************************/
 void __init dove_init_early(void)
 {
-	orion_time_set_base(TIMER_VIRT_BASE);
+	orion_time_set_base((unsigned long) TIMER_VIRT_BASE);
 }
 
 static int get_tclk(void)

@@ -196,7 +200,8 @@ static int get_tclk(void)
 
 static void __init dove_timer_init(void)
 {
-	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+	orion_time_init((unsigned long) BRIDGE_VIRT_BASE,
+			BRIDGE_INT_TIMER1_CLR,
 			IRQ_DOVE_BRIDGE, get_tclk());
 }
arch/arm/mach-dove/include/mach/dove.h +6 -6
index cccfd1d..735dd2e 100644
@@ -25,7 +25,7 @@
  */
 
 #define DOVE_CESA_PHYS_BASE		0xc8000000
-#define DOVE_CESA_VIRT_BASE		0xfdb00000
+#define DOVE_CESA_VIRT_BASE		IOMEM(0xfdb00000)
 #define DOVE_CESA_SIZE			SZ_1M
 
 #define DOVE_PCIE0_MEM_PHYS_BASE	0xe0000000

@@ -38,24 +38,24 @@
 #define DOVE_BOOTROM_SIZE		SZ_128M
 
 #define DOVE_SCRATCHPAD_PHYS_BASE	0xf0000000
-#define DOVE_SCRATCHPAD_VIRT_BASE	0xfdd00000
+#define DOVE_SCRATCHPAD_VIRT_BASE	IOMEM(0xfdd00000)
 #define DOVE_SCRATCHPAD_SIZE		SZ_1M
 
 #define DOVE_SB_REGS_PHYS_BASE		0xf1000000
-#define DOVE_SB_REGS_VIRT_BASE		0xfde00000
+#define DOVE_SB_REGS_VIRT_BASE		IOMEM(0xfde00000)
 #define DOVE_SB_REGS_SIZE		SZ_8M
 
 #define DOVE_NB_REGS_PHYS_BASE		0xf1800000
-#define DOVE_NB_REGS_VIRT_BASE		0xfe600000
+#define DOVE_NB_REGS_VIRT_BASE		IOMEM(0xfe600000)
 #define DOVE_NB_REGS_SIZE		SZ_8M
 
 #define DOVE_PCIE0_IO_PHYS_BASE		0xf2000000
-#define DOVE_PCIE0_IO_VIRT_BASE		0xfee00000
+#define DOVE_PCIE0_IO_VIRT_BASE		IOMEM(0xfee00000)
 #define DOVE_PCIE0_IO_BUS_BASE		0x00000000
 #define DOVE_PCIE0_IO_SIZE		SZ_1M
 
 #define DOVE_PCIE1_IO_PHYS_BASE		0xf2100000
-#define DOVE_PCIE1_IO_VIRT_BASE		0xfef00000
+#define DOVE_PCIE1_IO_VIRT_BASE		IOMEM(0xfef00000)
 #define DOVE_PCIE1_IO_BUS_BASE		0x00100000
 #define DOVE_PCIE1_IO_SIZE		SZ_1M
arch/arm/mach-dove/irq.c +5 -5
index 9bc97a5..4ce306a 100644
@@ -99,19 +99,19 @@ void __init dove_init_irq(void)
 {
 	int i;
 
-	orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
-	orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+	orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
+	orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
 
 	/*
 	 * Initialize gpiolib for GPIOs 0-71.
 	 */
-	orion_gpio_init(NULL, 0, 32, (void __iomem *)DOVE_GPIO_LO_VIRT_BASE, 0,
+	orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
 			IRQ_DOVE_GPIO_START, gpio0_irqs);
 
-	orion_gpio_init(NULL, 32, 32, (void __iomem *)DOVE_GPIO_HI_VIRT_BASE, 0,
+	orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
 			IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
 
-	orion_gpio_init(NULL, 64, 8, (void __iomem *)DOVE_GPIO2_VIRT_BASE, 0,
+	orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
 			IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
 
 	/*
arch/arm/mach-dove/mpp.c +2 -1
index 7f70afc..fc04ebe 100644
@@ -151,7 +151,8 @@ void __init dove_mpp_conf(unsigned int *mpp_list,
 	dove_mpp_dump_regs();
 
 	/* Use platform code for pins 0-23 */
-	orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE);
+	orion_mpp_conf(mpp_list, 0, MPP_MAX,
+		       (unsigned long) DOVE_MPP_VIRT_BASE);
 
 	dove_mpp_conf_grp(mpp_grp_list);
 	dove_mpp_cfg_au1(grp_au1_52_57);
arch/arm/mach-dove/pcie.c +3 -3
index 47921b0..b372441 100644
@@ -197,18 +197,18 @@ static struct hw_pci dove_pci __initdata = {
 	.map_irq	= dove_pcie_map_irq,
 };
 
-static void __init add_pcie_port(int index, unsigned long base)
+static void __init add_pcie_port(int index, void __iomem *base)
 {
 	printk(KERN_INFO "Dove PCIe port %d: ", index);
 
-	if (orion_pcie_link_up((void __iomem *)base)) {
+	if (orion_pcie_link_up(base)) {
 		struct pcie_port *pp = &pcie_port[num_pcie_ports++];
 
 		printk(KERN_INFO "link up\n");
 
 		pp->index = index;
 		pp->root_bus_nr = -1;
-		pp->base = (void __iomem *)base;
+		pp->base = base;
 		spin_lock_init(&pp->conf_lock);
 		memset(pp->res, 0, sizeof(pp->res));
 	} else {
Signature · 1 line
1.7.9.5
author
#6 lore raw

PATCH v4 6/17 arm: mach-kirkwood: use IOMEM() for base address definitions

In reply to Thomas Petazzoni

We now define all virtual base address constants using IOMEM() so that those are naturally typed as void __iomem pointers, and we do the necessary adjustements in the mach-kirkwood code.

Note that we introduce a few temporary additional "unsigned long" casts when calling into plat-orion functions. Those are removed by followup patches converting plat-orion functions to void __iomem pointers as well.

Signed-off-by Thomas Petazzoni <[email protected]>
---
 arch/arm/mach-kirkwood/addr-map.c              |    2 +-
 arch/arm/mach-kirkwood/common.c                |   23 ++++++++++++-----------
 arch/arm/mach-kirkwood/include/mach/kirkwood.h |    6 +++---
 arch/arm/mach-kirkwood/irq.c                   |    9 +++++----
 arch/arm/mach-kirkwood/mpp.c                   |    3 ++-
 arch/arm/mach-kirkwood/pcie.c                  |   12 ++++++------
 arch/arm/mach-kirkwood/ts41x-setup.c           |    3 ++-
 7 files changed, 31 insertions(+), 27 deletions(-)
arch/arm/mach-kirkwood/addr-map.c +1 -1
index e9a7180..1b8c75c 100644
@@ -41,7 +41,7 @@
 static struct __initdata orion_addr_map_cfg addr_map_cfg = {
 	.num_wins = 8,
 	.remappable_wins = 4,
-	.bridge_virt_base = BRIDGE_VIRT_BASE,
+	.bridge_virt_base = (unsigned long) BRIDGE_VIRT_BASE,
 };
 
 static const struct __initdata orion_addr_map_info addr_map_info[] = {
arch/arm/mach-kirkwood/common.c +12 -11
index 1201191..75bc04d 100644
@@ -42,17 +42,17 @@
  ****************************************************************************/
 static struct map_desc kirkwood_io_desc[] __initdata = {
 	{
-		.virtual	= KIRKWOOD_PCIE_IO_VIRT_BASE,
+		.virtual	= (unsigned long) KIRKWOOD_PCIE_IO_VIRT_BASE,
 		.pfn		= __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
 		.length		= KIRKWOOD_PCIE_IO_SIZE,
 		.type		= MT_DEVICE,
 	}, {
-		.virtual	= KIRKWOOD_PCIE1_IO_VIRT_BASE,
+		.virtual	= (unsigned long) KIRKWOOD_PCIE1_IO_VIRT_BASE,
 		.pfn		= __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
 		.length		= KIRKWOOD_PCIE1_IO_SIZE,
 		.type		= MT_DEVICE,
 	}, {
-		.virtual	= KIRKWOOD_REGS_VIRT_BASE,
+		.virtual	= (unsigned long) KIRKWOOD_REGS_VIRT_BASE,
 		.pfn		= __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
 		.length		= KIRKWOOD_REGS_SIZE,
 		.type		= MT_DEVICE,

@@ -215,8 +215,7 @@ static struct clk *tclk;
 
 static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
 {
-	return clk_register_gate(NULL, name, "tclk", 0,
-				 (void __iomem *)CLOCK_GATING_CTRL,
+	return clk_register_gate(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
 				 bit_idx, 0, &gating_lock);
 }
 

@@ -225,8 +224,7 @@ static struct clk __init *kirkwood_register_gate_fn(const char *name,
 						    void (*fn_en)(void),
 						    void (*fn_dis)(void))
 {
-	return clk_register_gate_fn(NULL, name, "tclk", 0,
-				    (void __iomem *)CLOCK_GATING_CTRL,
+	return clk_register_gate_fn(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
 				    bit_idx, 0, &gating_lock, fn_en, fn_dis);
 }
 

@@ -458,7 +456,8 @@ void __init kirkwood_i2c_init(void)
 
 void __init kirkwood_uart0_init(void)
 {
-	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
+	orion_uart0_init((unsigned long) UART0_VIRT_BASE,
+			 UART0_PHYS_BASE,
 			 IRQ_KIRKWOOD_UART_0, tclk);
 }
 

@@ -468,7 +467,8 @@ void __init kirkwood_uart0_init(void)
  ****************************************************************************/
 void __init kirkwood_uart1_init(void)
 {
-	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
+	orion_uart1_init((unsigned long) UART1_VIRT_BASE,
+			 UART1_PHYS_BASE,
 			 IRQ_KIRKWOOD_UART_1, tclk);
 }
 

@@ -516,7 +516,7 @@ void __init kirkwood_wdt_init(void)
  ****************************************************************************/
 void __init kirkwood_init_early(void)
 {
-	orion_time_set_base(TIMER_VIRT_BASE);
+	orion_time_set_base((unsigned long) TIMER_VIRT_BASE);
 
 	/*
 	 * Some Kirkwood devices allocate their coherent buffers from atomic

@@ -545,7 +545,8 @@ static void __init kirkwood_timer_init(void)
 {
 	kirkwood_tclk = kirkwood_find_tclk();
 
-	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+	orion_time_init((unsigned long) BRIDGE_VIRT_BASE,
+			BRIDGE_INT_TIMER1_CLR,
 			IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
 }
arch/arm/mach-kirkwood/include/mach/kirkwood.h +3 -3
index 9695592..d3ea682 100644
@@ -37,17 +37,17 @@
 #define KIRKWOOD_NAND_MEM_SIZE		SZ_1K
 
 #define KIRKWOOD_PCIE1_IO_PHYS_BASE	0xf3000000
-#define KIRKWOOD_PCIE1_IO_VIRT_BASE	0xfef00000
+#define KIRKWOOD_PCIE1_IO_VIRT_BASE	IOMEM(0xfef00000)
 #define KIRKWOOD_PCIE1_IO_BUS_BASE	0x00100000
 #define KIRKWOOD_PCIE1_IO_SIZE		SZ_1M
 
 #define KIRKWOOD_PCIE_IO_PHYS_BASE	0xf2000000
-#define KIRKWOOD_PCIE_IO_VIRT_BASE	0xfee00000
+#define KIRKWOOD_PCIE_IO_VIRT_BASE	IOMEM(0xfee00000)
 #define KIRKWOOD_PCIE_IO_BUS_BASE	0x00000000
 #define KIRKWOOD_PCIE_IO_SIZE		SZ_1M
 
 #define KIRKWOOD_REGS_PHYS_BASE		0xf1000000
-#define KIRKWOOD_REGS_VIRT_BASE		0xfed00000
+#define KIRKWOOD_REGS_VIRT_BASE		IOMEM(0xfed00000)
 #define KIRKWOOD_REGS_SIZE		SZ_1M
 
 #define KIRKWOOD_PCIE_MEM_PHYS_BASE	0xe0000000
arch/arm/mach-kirkwood/irq.c +5 -4
index 720063f..f4ac804 100644
@@ -10,6 +10,7 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <mach/bridge-regs.h>
 #include <plat/irq.h>
 

@@ -29,14 +30,14 @@ static int __initdata gpio1_irqs[4] = {
 
 void __init kirkwood_init_irq(void)
 {
-	orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
-	orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+	orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
+	orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
 
 	/*
 	 * Initialize gpiolib for GPIOs 0-49.
 	 */
-	orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_LOW_VIRT_BASE, 0,
+	orion_gpio_init(NULL, 0, 32, GPIO_LOW_VIRT_BASE, 0,
 			IRQ_KIRKWOOD_GPIO_START, gpio0_irqs);
-	orion_gpio_init(NULL, 32, 18, (void __iomem *)GPIO_HIGH_VIRT_BASE, 0,
+	orion_gpio_init(NULL, 32, 18, GPIO_HIGH_VIRT_BASE, 0,
 			IRQ_KIRKWOOD_GPIO_START + 32, gpio1_irqs);
 }
arch/arm/mach-kirkwood/mpp.c +2 -1
index 0c6ad63..6774279 100644
@@ -38,5 +38,6 @@ static unsigned int __init kirkwood_variant(void)
 void __init kirkwood_mpp_conf(unsigned int *mpp_list)
 {
 	orion_mpp_conf(mpp_list, kirkwood_variant(),
-		       MPP_MAX, DEV_BUS_VIRT_BASE);
+		       MPP_MAX,
+		       (unsigned long) DEV_BUS_VIRT_BASE);
 }
arch/arm/mach-kirkwood/pcie.c +6 -6
index 6e8b2ef..df6399d 100644
@@ -47,8 +47,8 @@ void kirkwood_enable_pcie(void)
 void kirkwood_pcie_id(u32 *dev, u32 *rev)
 {
 	kirkwood_enable_pcie();
-	*dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
-	*rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
+	*dev = orion_pcie_dev_id(PCIE_VIRT_BASE);
+	*rev = orion_pcie_rev(PCIE_VIRT_BASE);
 }
 
 struct pcie_port {

@@ -133,7 +133,7 @@ static struct pci_ops pcie_ops = {
 
 static void __init pcie0_ioresources_init(struct pcie_port *pp)
 {
-	pp->base = (void __iomem *)PCIE_VIRT_BASE;
+	pp->base = PCIE_VIRT_BASE;
 	pp->irq	= IRQ_KIRKWOOD_PCIE;
 
 	/*

@@ -155,7 +155,7 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp)
 
 static void __init pcie1_ioresources_init(struct pcie_port *pp)
 {
-	pp->base = (void __iomem *)PCIE1_VIRT_BASE;
+	pp->base = PCIE1_VIRT_BASE;
 	pp->irq	= IRQ_KIRKWOOD_PCIE1;
 
 	/*

@@ -273,11 +273,11 @@ static struct hw_pci kirkwood_pci __initdata = {
 	.map_irq	= kirkwood_pcie_map_irq,
 };
 
-static void __init add_pcie_port(int index, unsigned long base)
+static void __init add_pcie_port(int index, void __iomem *base)
 {
 	printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
 
-	if (orion_pcie_link_up((void __iomem *)base)) {
+	if (orion_pcie_link_up(base)) {
 		printk(KERN_INFO "link up\n");
 		pcie_port_map[num_pcie_ports++] = index;
 	} else
arch/arm/mach-kirkwood/ts41x-setup.c +2 -1
index 5bbca26..367a940 100644
@@ -20,6 +20,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/io.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>

@@ -161,7 +162,7 @@ static int __init ts41x_pci_init(void)
 		 * (Marvell 88sx7042/sata_mv) is known to stop working
 		 * after a few minutes.
 		 */
-		orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE);
+		orion_pcie_reset(PCIE_VIRT_BASE);
 
 		kirkwood_pcie_id(&dev, &rev);
 		if (dev == MV88F6282_DEV_ID)
Signature · 1 line
1.7.9.5
author
#7 lore raw

PATCH v4 7/17 arm: mach-mv78xx0: use IOMEM() for base address definitions

In reply to Thomas Petazzoni

We now define all virtual base address constants using IOMEM() so that those are naturally typed as void __iomem pointers, and we do the necessary adjustements in the mach-mv78xx0 code.

Note that we introduce a few temporary additional "unsigned long" casts when calling into plat-orion functions. Those are removed by followup patches converting plat-orion functions to void __iomem pointers as well.

Signed-off-by Thomas Petazzoni <[email protected]>
---
 arch/arm/mach-mv78xx0/addr-map.c             |    2 +-
 arch/arm/mach-mv78xx0/common.c               |   23 ++++++++++++++---------
 arch/arm/mach-mv78xx0/include/mach/mv78xx0.h |    6 +++---
 arch/arm/mach-mv78xx0/irq.c                  |    9 +++++----
 arch/arm/mach-mv78xx0/mpp.c                  |    3 ++-
 arch/arm/mach-mv78xx0/pcie.c                 |   12 ++++++------
 6 files changed, 31 insertions(+), 24 deletions(-)
arch/arm/mach-mv78xx0/addr-map.c +1 -1
index a9bc841..3358f07 100644
@@ -47,7 +47,7 @@ static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, i
 	 * so we don't need to take that into account here.
 	 */
 
-	return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
+	return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win);
 }
 
 /*
arch/arm/mach-mv78xx0/common.c +14 -9
index 3057f7d..c4e3458 100644
@@ -130,17 +130,17 @@ static int get_tclk(void)
  ****************************************************************************/
 static struct map_desc mv78xx0_io_desc[] __initdata = {
 	{
-		.virtual	= MV78XX0_CORE_REGS_VIRT_BASE,
+		.virtual	= (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
 		.pfn		= 0,
 		.length		= MV78XX0_CORE_REGS_SIZE,
 		.type		= MT_DEVICE,
 	}, {
-		.virtual	= MV78XX0_PCIE_IO_VIRT_BASE(0),
+		.virtual	= (unsigned long) MV78XX0_PCIE_IO_VIRT_BASE(0),
 		.pfn		= __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
 		.length		= MV78XX0_PCIE_IO_SIZE * 8,
 		.type		= MT_DEVICE,
 	}, {
-		.virtual	= MV78XX0_REGS_VIRT_BASE,
+		.virtual	= (unsigned long) MV78XX0_REGS_VIRT_BASE,
 		.pfn		= __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
 		.length		= MV78XX0_REGS_SIZE,
 		.type		= MT_DEVICE,

@@ -300,7 +300,8 @@ void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
  ****************************************************************************/
 void __init mv78xx0_uart0_init(void)
 {
-	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
+	orion_uart0_init((unsigned long) UART0_VIRT_BASE,
+			 UART0_PHYS_BASE,
 			 IRQ_MV78XX0_UART_0, tclk);
 }
 

@@ -310,7 +311,8 @@ void __init mv78xx0_uart0_init(void)
  ****************************************************************************/
 void __init mv78xx0_uart1_init(void)
 {
-	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
+	orion_uart1_init((unsigned long) UART1_VIRT_BASE,
+			 UART1_PHYS_BASE,
 			 IRQ_MV78XX0_UART_1, tclk);
 }
 

@@ -320,7 +322,8 @@ void __init mv78xx0_uart1_init(void)
  ****************************************************************************/
 void __init mv78xx0_uart2_init(void)
 {
-	orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
+	orion_uart2_init((unsigned long) UART2_VIRT_BASE,
+			 UART2_PHYS_BASE,
 			 IRQ_MV78XX0_UART_2, tclk);
 }
 

@@ -329,7 +332,8 @@ void __init mv78xx0_uart2_init(void)
  ****************************************************************************/
 void __init mv78xx0_uart3_init(void)
 {
-	orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
+	orion_uart3_init((unsigned long) UART3_VIRT_BASE,
+			 UART3_PHYS_BASE,
 			 IRQ_MV78XX0_UART_3, tclk);
 }
 

@@ -338,12 +342,13 @@ void __init mv78xx0_uart3_init(void)
  ****************************************************************************/
 void __init mv78xx0_init_early(void)
 {
-	orion_time_set_base(TIMER_VIRT_BASE);
+	orion_time_set_base((unsigned long) TIMER_VIRT_BASE);
 }
 
 static void mv78xx0_timer_init(void)
 {
-	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+	orion_time_init((unsigned long) BRIDGE_VIRT_BASE,
+			BRIDGE_INT_TIMER1_CLR,
 			IRQ_MV78XX0_TIMER_1, get_tclk());
 }
arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +3 -3
index a86e79e..62405e8 100644
@@ -41,16 +41,16 @@
  */
 #define MV78XX0_CORE0_REGS_PHYS_BASE	0xf1020000
 #define MV78XX0_CORE1_REGS_PHYS_BASE	0xf1024000
-#define MV78XX0_CORE_REGS_VIRT_BASE	0xfe400000
+#define MV78XX0_CORE_REGS_VIRT_BASE	IOMEM(0xfe400000)
 #define MV78XX0_CORE_REGS_PHYS_BASE	0xfe400000
 #define MV78XX0_CORE_REGS_SIZE		SZ_16K
 
 #define MV78XX0_PCIE_IO_PHYS_BASE(i)	(0xf0800000 + ((i) << 20))
-#define MV78XX0_PCIE_IO_VIRT_BASE(i)	(0xfe700000 + ((i) << 20))
+#define MV78XX0_PCIE_IO_VIRT_BASE(i)	IOMEM(0xfe700000 + ((i) << 20))
 #define MV78XX0_PCIE_IO_SIZE		SZ_1M
 
 #define MV78XX0_REGS_PHYS_BASE		0xf1000000
-#define MV78XX0_REGS_VIRT_BASE		0xfef00000
+#define MV78XX0_REGS_VIRT_BASE		IOMEM(0xfef00000)
 #define MV78XX0_REGS_SIZE		SZ_1M
 
 #define MV78XX0_PCIE_MEM_PHYS_BASE	0xc0000000
arch/arm/mach-mv78xx0/irq.c +5 -4
index eff9a75..b5c40c4 100644
@@ -10,6 +10,7 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <mach/bridge-regs.h>
 #include <plat/irq.h>
 #include "common.h"

@@ -23,16 +24,16 @@ static int __initdata gpio0_irqs[4] = {
 
 void __init mv78xx0_init_irq(void)
 {
-	orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
-	orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
-	orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
+	orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
+	orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
+	orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);
 
 	/*
 	 * Initialize gpiolib for GPIOs 0-31.  (The GPIO interrupt mask
 	 * registers for core #1 are at an offset of 0x18 from those of
 	 * core #0.)
 	 */
-	orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE,
+	orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE,
 			mv78xx0_core_index() ? 0x18 : 0,
 			IRQ_MV78XX0_GPIO_START, gpio0_irqs);
 }
arch/arm/mach-mv78xx0/mpp.c +2 -1
index df50342..4da82f8 100644
@@ -33,5 +33,6 @@ static unsigned int __init mv78xx0_variant(void)
 void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
 {
 	orion_mpp_conf(mpp_list, mv78xx0_variant(),
-		       MPP_MAX, DEV_BUS_VIRT_BASE);
+		       MPP_MAX,
+		       (unsigned long) DEV_BUS_VIRT_BASE);
 }
arch/arm/mach-mv78xx0/pcie.c +6 -6
index 2e56e86..e2940fb 100644
@@ -36,8 +36,8 @@ static struct resource pcie_mem_space;
 
 void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
 {
-	*dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE);
-	*rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE);
+	*dev = orion_pcie_dev_id(PCIE00_VIRT_BASE);
+	*rev = orion_pcie_rev(PCIE00_VIRT_BASE);
 }
 
 static void __init mv78xx0_pcie_preinit(void)

@@ -267,11 +267,11 @@ static struct hw_pci mv78xx0_pci __initdata = {
 	.map_irq	= mv78xx0_pcie_map_irq,
 };
 
-static void __init add_pcie_port(int maj, int min, unsigned long base)
+static void __init add_pcie_port(int maj, int min, void __iomem *base)
 {
 	printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
 
-	if (orion_pcie_link_up((void __iomem *)base)) {
+	if (orion_pcie_link_up(base)) {
 		struct pcie_port *pp = &pcie_port[num_pcie_ports++];
 
 		printk("link up\n");

@@ -279,7 +279,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base)
 		pp->maj = maj;
 		pp->min = min;
 		pp->root_bus_nr = -1;
-		pp->base = (void __iomem *)base;
+		pp->base = base;
 		spin_lock_init(&pp->conf_lock);
 		memset(pp->res, 0, sizeof(pp->res));
 	} else {

@@ -293,7 +293,7 @@ void __init mv78xx0_pcie_init(int init_port0, int init_port1)
 
 	if (init_port0) {
 		add_pcie_port(0, 0, PCIE00_VIRT_BASE);
-		if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {
+		if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) {
 			add_pcie_port(0, 1, PCIE01_VIRT_BASE);
 			add_pcie_port(0, 2, PCIE02_VIRT_BASE);
 			add_pcie_port(0, 3, PCIE03_VIRT_BASE);
Signature · 1 line
1.7.9.5
author
#8 lore raw

PATCH v4 8/17 arm: mach-orion5x: use IOMEM() for base address definitions

In reply to Thomas Petazzoni

We now define all virtual base address constants using IOMEM() so that those are naturally typed as void __iomem pointers, and we do the necessary adjustements in the mach-orion5x code.

Note that we introduce a few temporary additional "unsigned long" casts when calling into plat-orion functions. Those are removed by followup patches converting plat-orion functions to void __iomem pointers as well.

Signed-off-by Thomas Petazzoni <[email protected]>
---
 arch/arm/mach-orion5x/addr-map.c             |    2 +-
 arch/arm/mach-orion5x/common.c               |   19 +++++++++++--------
 arch/arm/mach-orion5x/dns323-setup.c         |    2 +-
 arch/arm/mach-orion5x/include/mach/orion5x.h |    8 ++++----
 arch/arm/mach-orion5x/irq.c                  |    5 +++--
 arch/arm/mach-orion5x/mpp.c                  |    3 ++-
 arch/arm/mach-orion5x/pci.c                  |    4 ++--
 7 files changed, 24 insertions(+), 19 deletions(-)
arch/arm/mach-orion5x/addr-map.c +1 -1
index eaac83d..d309f53 100644
@@ -79,7 +79,7 @@ static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
 static struct orion_addr_map_cfg addr_map_cfg __initdata = {
 	.num_wins = 8,
 	.cpu_win_can_remap = cpu_win_can_remap,
-	.bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,
+	.bridge_virt_base = (unsigned long) ORION5X_BRIDGE_VIRT_BASE,
 };
 
 static const struct __initdata orion_addr_map_info addr_map_info[] = {
arch/arm/mach-orion5x/common.c +11 -8
index 410291c..a890cb0 100644
@@ -42,22 +42,22 @@
  ****************************************************************************/
 static struct map_desc orion5x_io_desc[] __initdata = {
 	{
-		.virtual	= ORION5X_REGS_VIRT_BASE,
+		.virtual	= (unsigned long) ORION5X_REGS_VIRT_BASE,
 		.pfn		= __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
 		.length		= ORION5X_REGS_SIZE,
 		.type		= MT_DEVICE,
 	}, {
-		.virtual	= ORION5X_PCIE_IO_VIRT_BASE,
+		.virtual	= (unsigned long) ORION5X_PCIE_IO_VIRT_BASE,
 		.pfn		= __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
 		.length		= ORION5X_PCIE_IO_SIZE,
 		.type		= MT_DEVICE,
 	}, {
-		.virtual	= ORION5X_PCI_IO_VIRT_BASE,
+		.virtual	= (unsigned long) ORION5X_PCI_IO_VIRT_BASE,
 		.pfn		= __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
 		.length		= ORION5X_PCI_IO_SIZE,
 		.type		= MT_DEVICE,
 	}, {
-		.virtual	= ORION5X_PCIE_WA_VIRT_BASE,
+		.virtual	= (unsigned long) ORION5X_PCIE_WA_VIRT_BASE,
 		.pfn		= __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
 		.length		= ORION5X_PCIE_WA_SIZE,
 		.type		= MT_DEVICE,

@@ -156,7 +156,8 @@ void __init orion5x_spi_init()
  ****************************************************************************/
 void __init orion5x_uart0_init(void)
 {
-	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
+	orion_uart0_init((unsigned long) UART0_VIRT_BASE,
+			 UART0_PHYS_BASE,
 			 IRQ_ORION5X_UART0, tclk);
 }
 

@@ -165,7 +166,8 @@ void __init orion5x_uart0_init(void)
  ****************************************************************************/
 void __init orion5x_uart1_init(void)
 {
-	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
+	orion_uart1_init((unsigned long) UART1_VIRT_BASE,
+			 UART1_PHYS_BASE,
 			 IRQ_ORION5X_UART1, tclk);
 }
 

@@ -203,7 +205,7 @@ void __init orion5x_wdt_init(void)
  ****************************************************************************/
 void __init orion5x_init_early(void)
 {
-	orion_time_set_base(TIMER_VIRT_BASE);
+	orion_time_set_base((unsigned long) TIMER_VIRT_BASE);
 }
 
 int orion5x_tclk;

@@ -224,7 +226,8 @@ static void __init orion5x_timer_init(void)
 {
 	orion5x_tclk = orion5x_find_tclk();
 
-	orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+	orion_time_init((unsigned long) ORION5X_BRIDGE_VIRT_BASE,
+			BRIDGE_INT_TIMER1_CLR,
 			IRQ_ORION5X_BRIDGE, orion5x_tclk);
 }
arch/arm/mach-orion5x/dns323-setup.c +1 -1
index d470864..3a5e6fc 100644
@@ -700,7 +700,7 @@ static void __init dns323_init(void)
 		 * Note: AFAIK, rev B1 needs the same treatement but I'll let
 		 * somebody else test it.
 		 */
-		writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c);
+		writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c);
 		break;
 	}
 }
arch/arm/mach-orion5x/include/mach/orion5x.h +4 -4
index 87bd378..6fd38ab 100644
@@ -37,16 +37,16 @@
  * fe000000	f0000000	16M	PCIe WA space (Orion-1/Orion-NAS only)
  ****************************************************************************/
 #define ORION5X_REGS_PHYS_BASE		0xf1000000
-#define ORION5X_REGS_VIRT_BASE		0xfdd00000
+#define ORION5X_REGS_VIRT_BASE		IOMEM(0xfdd00000)
 #define ORION5X_REGS_SIZE		SZ_1M
 
 #define ORION5X_PCIE_IO_PHYS_BASE	0xf2000000
-#define ORION5X_PCIE_IO_VIRT_BASE	0xfde00000
+#define ORION5X_PCIE_IO_VIRT_BASE	IOMEM(0xfde00000)
 #define ORION5X_PCIE_IO_BUS_BASE	0x00000000
 #define ORION5X_PCIE_IO_SIZE		SZ_1M
 
 #define ORION5X_PCI_IO_PHYS_BASE	0xf2100000
-#define ORION5X_PCI_IO_VIRT_BASE	0xfdf00000
+#define ORION5X_PCI_IO_VIRT_BASE	IOMEM(0xfdf00000)
 #define ORION5X_PCI_IO_BUS_BASE		0x00100000
 #define ORION5X_PCI_IO_SIZE		SZ_1M
 

@@ -55,7 +55,7 @@
 
 /* Relevant only for Orion-1/Orion-NAS */
 #define ORION5X_PCIE_WA_PHYS_BASE	0xf0000000
-#define ORION5X_PCIE_WA_VIRT_BASE	0xfe000000
+#define ORION5X_PCIE_WA_VIRT_BASE	IOMEM(0xfe000000)
 #define ORION5X_PCIE_WA_SIZE		SZ_16M
 
 #define ORION5X_PCIE_MEM_PHYS_BASE	0xe0000000
arch/arm/mach-orion5x/irq.c +3 -2
index 17da709..bf9ff4f 100644
@@ -12,6 +12,7 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <mach/bridge-regs.h>
 #include <plat/irq.h>
 

@@ -24,11 +25,11 @@ static int __initdata gpio0_irqs[4] = {
 
 void __init orion5x_init_irq(void)
 {
-	orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
+	orion_irq_init(0, MAIN_IRQ_MASK);
 
 	/*
 	 * Initialize gpiolib for GPIOs 0-31.
 	 */
-	orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE, 0,
+	orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, 0,
 			IRQ_ORION5X_GPIO_START, gpio0_irqs);
 }
arch/arm/mach-orion5x/mpp.c +2 -1
index 5b70026..30f5ef6 100644
@@ -40,5 +40,6 @@ static unsigned int __init orion5x_variant(void)
 void __init orion5x_mpp_conf(unsigned int *mpp_list)
 {
 	orion_mpp_conf(mpp_list, orion5x_variant(),
-		       MPP_MAX, ORION5X_DEV_BUS_VIRT_BASE);
+		       MPP_MAX,
+		       (unsigned long) ORION5X_DEV_BUS_VIRT_BASE);
 }
arch/arm/mach-orion5x/pci.c +2 -2
index b36f928..b0822a8 100644
@@ -38,7 +38,7 @@
 /*****************************************************************************
  * PCIe controller
  ****************************************************************************/
-#define PCIE_BASE	((void __iomem *)ORION5X_PCIE_VIRT_BASE)
+#define PCIE_BASE	(ORION5X_PCIE_VIRT_BASE)
 
 void __init orion5x_pcie_id(u32 *dev, u32 *rev)
 {

@@ -111,7 +111,7 @@ static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	}
 
-	ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
+	ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE,
 				    bus, devfn, where, size, val);
 
 	return ret;
Signature · 1 line
1.7.9.5
author
#9 lore raw

PATCH v4 9/17 arm: mach-mvebu: use IOMEM() for base address definitions

In reply to Thomas Petazzoni

We now define all virtual base address constants using IOMEM() so that those are naturally typed as void __iomem pointers, and we do the necessary adjustements in the mach-mvebu code.

Signed-off-by Thomas Petazzoni <[email protected]>
---
 arch/arm/mach-mvebu/armada-370-xp.c              |    2 +-
 arch/arm/mach-mvebu/include/mach/armada-370-xp.h |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/mach-mvebu/armada-370-xp.c +1 -1
index 4ef923b..dfe635b 100644
@@ -25,7 +25,7 @@
 
 static struct map_desc armada_370_xp_io_desc[] __initdata = {
 	{
-		.virtual	= ARMADA_370_XP_REGS_VIRT_BASE,
+		.virtual	= (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE,
 		.pfn		= __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
 		.length		= ARMADA_370_XP_REGS_SIZE,
 		.type		= MT_DEVICE,
arch/arm/mach-mvebu/include/mach/armada-370-xp.h +1 -1
index 25f0ca8..aac9beb 100644
@@ -16,7 +16,7 @@
 #define __MACH_ARMADA_370_XP_H
 
 #define ARMADA_370_XP_REGS_PHYS_BASE	0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE	0xfeb00000
+#define ARMADA_370_XP_REGS_VIRT_BASE	IOMEM(0xfeb00000)
 #define ARMADA_370_XP_REGS_SIZE		SZ_1M
 
 #endif /* __MACH_ARMADA_370_XP_H */
Signature · 1 line
1.7.9.5
author
#10 lore raw

PATCH v4 10/17 arm: plat-orion: use void __iomem pointers for UART registration functions

In reply to Thomas Petazzoni

The registration functions for UARTs now take void __iomem pointers, so we remove the temporary "unsigned long" casts from the mach-*/common.c files.

Signed-off-by Thomas Petazzoni <[email protected]>
---
 arch/arm/mach-dove/common.c               |   12 ++++--------
 arch/arm/mach-kirkwood/common.c           |    6 ++----
 arch/arm/mach-mv78xx0/common.c            |   12 ++++--------
 arch/arm/mach-orion5x/common.c            |    6 ++----
 arch/arm/plat-orion/common.c              |   12 ++++++------
 arch/arm/plat-orion/include/plat/common.h |    8 ++++----
 6 files changed, 22 insertions(+), 34 deletions(-)
arch/arm/mach-dove/common.c +4 -8
index 533fd81..ba55f63 100644
@@ -128,8 +128,7 @@ void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
  ****************************************************************************/
 void __init dove_uart0_init(void)
 {
-	orion_uart0_init((unsigned long) DOVE_UART0_VIRT_BASE,
-			 DOVE_UART0_PHYS_BASE,
+	orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
 			 IRQ_DOVE_UART_0, tclk);
 }
 

@@ -138,8 +137,7 @@ void __init dove_uart0_init(void)
  ****************************************************************************/
 void __init dove_uart1_init(void)
 {
-	orion_uart1_init((unsigned long) DOVE_UART1_VIRT_BASE,
-			 DOVE_UART1_PHYS_BASE,
+	orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
 			 IRQ_DOVE_UART_1, tclk);
 }
 

@@ -148,8 +146,7 @@ void __init dove_uart1_init(void)
  ****************************************************************************/
 void __init dove_uart2_init(void)
 {
-	orion_uart2_init((unsigned long) DOVE_UART2_VIRT_BASE,
-			 DOVE_UART2_PHYS_BASE,
+	orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
 			 IRQ_DOVE_UART_2, tclk);
 }
 

@@ -158,8 +155,7 @@ void __init dove_uart2_init(void)
  ****************************************************************************/
 void __init dove_uart3_init(void)
 {
-	orion_uart3_init((unsigned long) DOVE_UART3_VIRT_BASE,
-			 DOVE_UART3_PHYS_BASE,
+	orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
 			 IRQ_DOVE_UART_3, tclk);
 }
arch/arm/mach-kirkwood/common.c +2 -4
index 75bc04d..defceca 100644
@@ -456,8 +456,7 @@ void __init kirkwood_i2c_init(void)
 
 void __init kirkwood_uart0_init(void)
 {
-	orion_uart0_init((unsigned long) UART0_VIRT_BASE,
-			 UART0_PHYS_BASE,
+	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
 			 IRQ_KIRKWOOD_UART_0, tclk);
 }
 

@@ -467,8 +466,7 @@ void __init kirkwood_uart0_init(void)
  ****************************************************************************/
 void __init kirkwood_uart1_init(void)
 {
-	orion_uart1_init((unsigned long) UART1_VIRT_BASE,
-			 UART1_PHYS_BASE,
+	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
 			 IRQ_KIRKWOOD_UART_1, tclk);
 }
arch/arm/mach-mv78xx0/common.c +4 -8
index c4e3458..fcda4a4 100644
@@ -300,8 +300,7 @@ void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
  ****************************************************************************/
 void __init mv78xx0_uart0_init(void)
 {
-	orion_uart0_init((unsigned long) UART0_VIRT_BASE,
-			 UART0_PHYS_BASE,
+	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
 			 IRQ_MV78XX0_UART_0, tclk);
 }
 

@@ -311,8 +310,7 @@ void __init mv78xx0_uart0_init(void)
  ****************************************************************************/
 void __init mv78xx0_uart1_init(void)
 {
-	orion_uart1_init((unsigned long) UART1_VIRT_BASE,
-			 UART1_PHYS_BASE,
+	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
 			 IRQ_MV78XX0_UART_1, tclk);
 }
 

@@ -322,8 +320,7 @@ void __init mv78xx0_uart1_init(void)
  ****************************************************************************/
 void __init mv78xx0_uart2_init(void)
 {
-	orion_uart2_init((unsigned long) UART2_VIRT_BASE,
-			 UART2_PHYS_BASE,
+	orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
 			 IRQ_MV78XX0_UART_2, tclk);
 }
 

@@ -332,8 +329,7 @@ void __init mv78xx0_uart2_init(void)
  ****************************************************************************/
 void __init mv78xx0_uart3_init(void)
 {
-	orion_uart3_init((unsigned long) UART3_VIRT_BASE,
-			 UART3_PHYS_BASE,
+	orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
 			 IRQ_MV78XX0_UART_3, tclk);
 }
arch/arm/mach-orion5x/common.c +2 -4
index a890cb0..79f9ffb 100644
@@ -156,8 +156,7 @@ void __init orion5x_spi_init()
  ****************************************************************************/
 void __init orion5x_uart0_init(void)
 {
-	orion_uart0_init((unsigned long) UART0_VIRT_BASE,
-			 UART0_PHYS_BASE,
+	orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
 			 IRQ_ORION5X_UART0, tclk);
 }
 

@@ -166,8 +165,7 @@ void __init orion5x_uart0_init(void)
  ****************************************************************************/
 void __init orion5x_uart1_init(void)
 {
-	orion_uart1_init((unsigned long) UART1_VIRT_BASE,
-			 UART1_PHYS_BASE,
+	orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
 			 IRQ_ORION5X_UART1, tclk);
 }
arch/arm/plat-orion/common.c +6 -6
index b8b747a..5bed711 100644
@@ -86,13 +86,13 @@ static void __init uart_complete(
 	struct platform_device *orion_uart,
 	struct plat_serial8250_port *data,
 	struct resource *resources,
-	unsigned int membase,
+	void __iomem *membase,
 	resource_size_t mapbase,
 	unsigned int irq,
 	struct clk *clk)
 {
 	data->mapbase = mapbase;
-	data->membase = (void __iomem *)membase;
+	data->membase = membase;
 	data->irq = irq;
 	data->uartclk = uart_get_clk_rate(clk);
 	orion_uart->dev.platform_data = data;

@@ -120,7 +120,7 @@ static struct platform_device orion_uart0 = {
 	.id			= PLAT8250_DEV_PLATFORM,
 };
 
-void __init orion_uart0_init(unsigned int membase,
+void __init orion_uart0_init(void __iomem *membase,
 			     resource_size_t mapbase,
 			     unsigned int irq,
 			     struct clk *clk)

@@ -148,7 +148,7 @@ static struct platform_device orion_uart1 = {
 	.id			= PLAT8250_DEV_PLATFORM1,
 };
 
-void __init orion_uart1_init(unsigned int membase,
+void __init orion_uart1_init(void __iomem *membase,
 			     resource_size_t mapbase,
 			     unsigned int irq,
 			     struct clk *clk)

@@ -176,7 +176,7 @@ static struct platform_device orion_uart2 = {
 	.id			= PLAT8250_DEV_PLATFORM2,
 };
 
-void __init orion_uart2_init(unsigned int membase,
+void __init orion_uart2_init(void __iomem *membase,
 			     resource_size_t mapbase,
 			     unsigned int irq,
 			     struct clk *clk)

@@ -204,7 +204,7 @@ static struct platform_device orion_uart3 = {
 	.id			= 3,
 };
 
-void __init orion_uart3_init(unsigned int membase,
+void __init orion_uart3_init(void __iomem *membase,
 			     resource_size_t mapbase,
 			     unsigned int irq,
 			     struct clk *clk)
arch/arm/plat-orion/include/plat/common.h +4 -4
index ae2377e..6bbc3fe 100644
@@ -13,22 +13,22 @@
 
 struct dsa_platform_data;
 
-void __init orion_uart0_init(unsigned int membase,
+void __init orion_uart0_init(void __iomem *membase,
 			     resource_size_t mapbase,
 			     unsigned int irq,
 			     struct clk *clk);
 
-void __init orion_uart1_init(unsigned int membase,
+void __init orion_uart1_init(void __iomem *membase,
 			     resource_size_t mapbase,
 			     unsigned int irq,
 			     struct clk *clk);
 
-void __init orion_uart2_init(unsigned int membase,
+void __init orion_uart2_init(void __iomem *membase,
 			     resource_size_t mapbase,
 			     unsigned int irq,
 			     struct clk *clk);
 
-void __init orion_uart3_init(unsigned int membase,
+void __init orion_uart3_init(void __iomem *membase,
 			     resource_size_t mapbase,
 			     unsigned int irq,
 			     struct clk *clk);
Signature · 1 line
1.7.9.5
author
#11 lore raw

PATCH v4 11/17 arm: plat-orion: use void __iomem pointers for MPP functions

In reply to Thomas Petazzoni

The registration function for MPP now takes void __iomem pointers, so we remove the temporary "unsigned long" casts from the mach-*/mpp.c files.

Signed-off-by Thomas Petazzoni <[email protected]>
---
 arch/arm/mach-dove/mpp.c               |    3 +--
 arch/arm/mach-kirkwood/mpp.c           |    3 +--
 arch/arm/mach-mv78xx0/mpp.c            |    3 +--
 arch/arm/mach-orion5x/mpp.c            |    3 +--
 arch/arm/plat-orion/include/plat/mpp.h |    2 +-
 arch/arm/plat-orion/mpp.c              |    6 +++---
 6 files changed, 8 insertions(+), 12 deletions(-)
arch/arm/mach-dove/mpp.c +1 -2
index fc04ebe..7f70afc 100644
@@ -151,8 +151,7 @@ void __init dove_mpp_conf(unsigned int *mpp_list,
 	dove_mpp_dump_regs();
 
 	/* Use platform code for pins 0-23 */
-	orion_mpp_conf(mpp_list, 0, MPP_MAX,
-		       (unsigned long) DOVE_MPP_VIRT_BASE);
+	orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE);
 
 	dove_mpp_conf_grp(mpp_grp_list);
 	dove_mpp_cfg_au1(grp_au1_52_57);
arch/arm/mach-kirkwood/mpp.c +1 -2
index 6774279..0c6ad63 100644
@@ -38,6 +38,5 @@ static unsigned int __init kirkwood_variant(void)
 void __init kirkwood_mpp_conf(unsigned int *mpp_list)
 {
 	orion_mpp_conf(mpp_list, kirkwood_variant(),
-		       MPP_MAX,
-		       (unsigned long) DEV_BUS_VIRT_BASE);
+		       MPP_MAX, DEV_BUS_VIRT_BASE);
 }
arch/arm/mach-mv78xx0/mpp.c +1 -2
index 4da82f8..df50342 100644
@@ -33,6 +33,5 @@ static unsigned int __init mv78xx0_variant(void)
 void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
 {
 	orion_mpp_conf(mpp_list, mv78xx0_variant(),
-		       MPP_MAX,
-		       (unsigned long) DEV_BUS_VIRT_BASE);
+		       MPP_MAX, DEV_BUS_VIRT_BASE);
 }
arch/arm/mach-orion5x/mpp.c +1 -2
index 30f5ef6..5b70026 100644
@@ -40,6 +40,5 @@ static unsigned int __init orion5x_variant(void)
 void __init orion5x_mpp_conf(unsigned int *mpp_list)
 {
 	orion_mpp_conf(mpp_list, orion5x_variant(),
-		       MPP_MAX,
-		       (unsigned long) ORION5X_DEV_BUS_VIRT_BASE);
+		       MPP_MAX, ORION5X_DEV_BUS_VIRT_BASE);
 }
arch/arm/plat-orion/include/plat/mpp.h +1 -1
index 723adce..254552f 100644
@@ -29,6 +29,6 @@
 #define MPP_OUTPUT_MASK		GENERIC_MPP(0, 0x0, 0, 1)
 
 void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
-			   unsigned int mpp_max, unsigned int dev_bus);
+			   unsigned int mpp_max, void __iomem *dev_bus);
 
 #endif
arch/arm/plat-orion/mpp.c +3 -3
index 3b1e17b..20d4208 100644
@@ -17,15 +17,15 @@
 #include <plat/mpp.h>
 
 /* Address of the ith MPP control register */
-static __init unsigned long mpp_ctrl_addr(unsigned int i,
-					  unsigned long dev_bus)
+static __init void __iomem *mpp_ctrl_addr(unsigned int i,
+					  void __iomem *dev_bus)
 {
 	return dev_bus + (i) * 4;
 }
 
 
 void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
-			   unsigned int mpp_max, unsigned int dev_bus)
+			   unsigned int mpp_max, void __iomem *dev_bus)
 {
 	unsigned int mpp_nr_regs = (1 + mpp_max/8);
 	u32 mpp_ctrl[mpp_nr_regs];
Signature · 1 line
1.7.9.5
author
#12 lore raw

PATCH v4 12/17 arm: plat-orion: use void __iomem pointers for time functions

In reply to Thomas Petazzoni

The functions for time management now take void __iomem pointers, so we remove the temporary "unsigned long" casts from the mach-*/common.c files.

Signed-off-by Thomas Petazzoni <[email protected]>
---
 arch/arm/mach-dove/common.c             |    5 ++---
 arch/arm/mach-kirkwood/common.c         |    5 ++---
 arch/arm/mach-mv78xx0/common.c          |    5 ++---
 arch/arm/mach-orion5x/common.c          |    5 ++---
 arch/arm/plat-orion/include/plat/time.h |    4 ++--
 arch/arm/plat-orion/time.c              |    8 ++++----
 6 files changed, 14 insertions(+), 18 deletions(-)
arch/arm/mach-dove/common.c +2 -3
index ba55f63..cb65599 100644
@@ -185,7 +185,7 @@ void __init dove_i2c_init(void)
  ****************************************************************************/
 void __init dove_init_early(void)
 {
-	orion_time_set_base((unsigned long) TIMER_VIRT_BASE);
+	orion_time_set_base(TIMER_VIRT_BASE);
 }
 
 static int get_tclk(void)

@@ -196,8 +196,7 @@ static int get_tclk(void)
 
 static void __init dove_timer_init(void)
 {
-	orion_time_init((unsigned long) BRIDGE_VIRT_BASE,
-			BRIDGE_INT_TIMER1_CLR,
+	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 			IRQ_DOVE_BRIDGE, get_tclk());
 }
arch/arm/mach-kirkwood/common.c +2 -3
index defceca..55bf919 100644
@@ -514,7 +514,7 @@ void __init kirkwood_wdt_init(void)
  ****************************************************************************/
 void __init kirkwood_init_early(void)
 {
-	orion_time_set_base((unsigned long) TIMER_VIRT_BASE);
+	orion_time_set_base(TIMER_VIRT_BASE);
 
 	/*
 	 * Some Kirkwood devices allocate their coherent buffers from atomic

@@ -543,8 +543,7 @@ static void __init kirkwood_timer_init(void)
 {
 	kirkwood_tclk = kirkwood_find_tclk();
 
-	orion_time_init((unsigned long) BRIDGE_VIRT_BASE,
-			BRIDGE_INT_TIMER1_CLR,
+	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 			IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
 }
arch/arm/mach-mv78xx0/common.c +2 -3
index fcda4a4..f123517 100644
@@ -338,13 +338,12 @@ void __init mv78xx0_uart3_init(void)
  ****************************************************************************/
 void __init mv78xx0_init_early(void)
 {
-	orion_time_set_base((unsigned long) TIMER_VIRT_BASE);
+	orion_time_set_base(TIMER_VIRT_BASE);
 }
 
 static void mv78xx0_timer_init(void)
 {
-	orion_time_init((unsigned long) BRIDGE_VIRT_BASE,
-			BRIDGE_INT_TIMER1_CLR,
+	orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 			IRQ_MV78XX0_TIMER_1, get_tclk());
 }
arch/arm/mach-orion5x/common.c +2 -3
index 79f9ffb..58b754f 100644
@@ -203,7 +203,7 @@ void __init orion5x_wdt_init(void)
  ****************************************************************************/
 void __init orion5x_init_early(void)
 {
-	orion_time_set_base((unsigned long) TIMER_VIRT_BASE);
+	orion_time_set_base(TIMER_VIRT_BASE);
 }
 
 int orion5x_tclk;

@@ -224,8 +224,7 @@ static void __init orion5x_timer_init(void)
 {
 	orion5x_tclk = orion5x_find_tclk();
 
-	orion_time_init((unsigned long) ORION5X_BRIDGE_VIRT_BASE,
-			BRIDGE_INT_TIMER1_CLR,
+	orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 			IRQ_ORION5X_BRIDGE, orion5x_tclk);
 }
arch/arm/plat-orion/include/plat/time.h +2 -2
index 4d5f1f6..07527e4 100644
@@ -11,9 +11,9 @@
 #ifndef __PLAT_TIME_H
 #define __PLAT_TIME_H
 
-void orion_time_set_base(u32 timer_base);
+void orion_time_set_base(void __iomem *timer_base);
 
-void orion_time_init(u32 bridge_base, u32 bridge_timer1_clr_mask,
+void orion_time_init(void __iomem *bridge_base, u32 bridge_timer1_clr_mask,
 		     unsigned int irq, unsigned int tclk);
arch/arm/plat-orion/time.c +4 -4
index 1ed8d13..0f4fa86 100644
@@ -180,13 +180,13 @@ static struct irqaction orion_timer_irq = {
 };
 
 void __init
-orion_time_set_base(u32 _timer_base)
+orion_time_set_base(void __iomem *_timer_base)
 {
-	timer_base = (void __iomem *)_timer_base;
+	timer_base = _timer_base;
 }
 
 void __init
-orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
+orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
 		unsigned int irq, unsigned int tclk)
 {
 	u32 u;

@@ -194,7 +194,7 @@ orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
 	/*
 	 * Set SoC-specific data.
 	 */
-	bridge_base = (void __iomem *)_bridge_base;
+	bridge_base = _bridge_base;
 	bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
 
 	ticks_per_jiffy = (tclk + HZ/2) / HZ;
Signature · 1 line
1.7.9.5
author
#13 lore raw

PATCH v4 13/17 arm: plat-orion: use void __iomem pointers for addr-map functions

In reply to Thomas Petazzoni

The functions for address mapping management now take void __iomem pointers, so we remove the temporary "unsigned long" casts from the mach-*/common.c files.

Signed-off-by Thomas Petazzoni <[email protected]>
---
 arch/arm/mach-dove/addr-map.c               |    2 +-
 arch/arm/mach-kirkwood/addr-map.c           |    5 +++--
 arch/arm/mach-mv78xx0/addr-map.c            |    4 ++--
 arch/arm/mach-orion5x/addr-map.c            |    5 +++--
 arch/arm/plat-orion/addr-map.c              |   11 ++++-------
 arch/arm/plat-orion/include/plat/addr-map.h |    4 ++--
 6 files changed, 15 insertions(+), 16 deletions(-)
arch/arm/mach-dove/addr-map.c +1 -1
index b92c9c7..2a06c01 100644
@@ -47,7 +47,7 @@ static inline void __iomem *ddr_map_sc(int i)
 static struct __initdata orion_addr_map_cfg addr_map_cfg = {
 	.num_wins = 8,
 	.remappable_wins = 4,
-	.bridge_virt_base = (unsigned long) BRIDGE_VIRT_BASE,
+	.bridge_virt_base = BRIDGE_VIRT_BASE,
 };
 
 static const struct __initdata orion_addr_map_info addr_map_info[] = {
arch/arm/mach-kirkwood/addr-map.c +3 -2
index 1b8c75c..8f0d162 100644
@@ -41,7 +41,7 @@
 static struct __initdata orion_addr_map_cfg addr_map_cfg = {
 	.num_wins = 8,
 	.remappable_wins = 4,
-	.bridge_virt_base = (unsigned long) BRIDGE_VIRT_BASE,
+	.bridge_virt_base = BRIDGE_VIRT_BASE,
 };
 
 static const struct __initdata orion_addr_map_info addr_map_info[] = {

@@ -86,5 +86,6 @@ void __init kirkwood_setup_cpu_mbus(void)
 	/*
 	 * Setup MBUS dram target info.
 	 */
-	orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE);
+	orion_setup_cpu_mbus_target(&addr_map_cfg,
+				    (void __iomem *) DDR_WINDOW_CPU_BASE);
 }
arch/arm/mach-mv78xx0/addr-map.c +2 -2
index 3358f07..a51fc24 100644
@@ -71,10 +71,10 @@ void __init mv78xx0_setup_cpu_mbus(void)
 	 */
 	if (mv78xx0_core_index() == 0)
 		orion_setup_cpu_mbus_target(&addr_map_cfg,
-					    DDR_WINDOW_CPU0_BASE);
+					    (void __iomem *) DDR_WINDOW_CPU0_BASE);
 	else
 		orion_setup_cpu_mbus_target(&addr_map_cfg,
-					    DDR_WINDOW_CPU1_BASE);
+					    (void __iomem *) DDR_WINDOW_CPU1_BASE);
 }
 
 void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
arch/arm/mach-orion5x/addr-map.c +3 -2
index d309f53..b5efc0f 100644
@@ -79,7 +79,7 @@ static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
 static struct orion_addr_map_cfg addr_map_cfg __initdata = {
 	.num_wins = 8,
 	.cpu_win_can_remap = cpu_win_can_remap,
-	.bridge_virt_base = (unsigned long) ORION5X_BRIDGE_VIRT_BASE,
+	.bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,
 };
 
 static const struct __initdata orion_addr_map_info addr_map_info[] = {

@@ -113,7 +113,8 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
 	/*
 	 * Setup MBUS dram target info.
 	 */
-	orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE);
+	orion_setup_cpu_mbus_target(&addr_map_cfg,
+				    (void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE);
 }
 
 void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
arch/arm/plat-orion/addr-map.c +4 -7
index 367ca89..a7b8060 100644
@@ -48,7 +48,7 @@ EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
 static void __init __iomem *
 orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
 {
-	return (void __iomem *)(cfg->bridge_virt_base + (win << 4));
+	return cfg->bridge_virt_base + (win << 4);
 }
 
 /*

@@ -143,19 +143,16 @@ void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
  * Setup MBUS dram target info.
  */
 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
-					const u32 ddr_window_cpu_base)
+					const void __iomem *ddr_window_cpu_base)
 {
-	void __iomem *addr;
 	int i;
 	int cs;
 
 	orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 
-	addr = (void __iomem *)ddr_window_cpu_base;
-
 	for (i = 0, cs = 0; i < 4; i++) {
-		u32 base = readl(addr + DDR_BASE_CS_OFF(i));
-		u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
+		u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i));
+		u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i));
 
 		/*
 		 * Chip select enabled?
arch/arm/plat-orion/include/plat/addr-map.h +2 -2
index fd556f7..0a746fd 100644
@@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info;
 struct orion_addr_map_cfg {
 	const int num_wins;	/* Total number of windows */
 	const int remappable_wins;
-	const u32 bridge_virt_base;
+	void __iomem * const bridge_virt_base;
 
 	/* If NULL, the default cpu_win_can_remap will be used, using
 	   the value in remappable_wins */

@@ -49,5 +49,5 @@ void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
 				const u8 attr, const int remap);
 
 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
-					const u32 ddr_window_cpu_base);
+					const void __iomem *ddr_window_cpu_base);
 #endif
Signature · 1 line
1.7.9.5
author
#14 lore raw

PATCH v4 14/17 arm: plat-orion: introduce PLAT_ORION_LEGACY hidden config option

In reply to Thomas Petazzoni

Until now, the PLAT_ORION configuration option was common to all the Marvell EBU SoCs, and selecting this option had the effect of enabling the MPP code, GPIO code, address decoding and PCIe code from plat-orion, as well as providing access to driver-specific header files from plat-orion/include.

However, the Armada 370 and XP SoCs will not use the MPP and GPIO code (instead some proper pinctrl and gpio drivers are in preparation), and generally, we want to move away from plat-orion and instead have everything in mach-mvebu.

That said, in the mean time, we want to leverage the driver-specific headers as well as the address decoding code, so we introduce PLAT_ORION_LEGACY. The older Marvell SoCs need to select PLAT_ORION_LEGACY, while the newer Marvell SoCs need to select PLAT_ORION. Of course, when PLAT_ORION_LEGACY is selected, it automatically selects PLAT_ORION.

Then, with just PLAT_ORION, you have the address decoding code plus the driver-specific headers. If you add PLAT_ORION_LEGACY to this, you gain the old MPP, GPIO and PCIe code.

Again, this is only a temporary solution until we make all Marvell EBU platforms converge into the mach-mvebu directory. This solution avoids duplicating the existing address decoding code into mach-mvebu.

Signed-off-by Thomas Petazzoni <[email protected]>
Acked-by Gregory CLEMENT <[email protected]>
---
 arch/arm/Kconfig             |   13 +++++++++----
 arch/arm/plat-orion/Makefile |    9 ++++-----
 2 files changed, 13 insertions(+), 9 deletions(-)
arch/arm/Kconfig +9 -4
index 2f88d8d..a4eab57 100644
@@ -567,6 +567,7 @@ config ARCH_MVEBU
 	select GENERIC_IRQ_CHIP
 	select IRQ_DOMAIN
 	select COMMON_CLK
+	select PLAT_ORION
 	help
 	  Support for the Marvell SoC Family with device tree support
 

@@ -577,7 +578,7 @@ config ARCH_DOVE
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select PLAT_ORION_LEGACY
 	help
 	  Support for the Marvell Dove SoC 88AP510
 

@@ -588,7 +589,7 @@ config ARCH_KIRKWOOD
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select PLAT_ORION_LEGACY
 	help
 	  Support for the following Marvell Kirkwood series SoCs:
 	  88F6180, 88F6192 and 88F6281.

@@ -615,7 +616,7 @@ config ARCH_MV78XX0
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select PLAT_ORION_LEGACY
 	help
 	  Support for the following Marvell MV78xx0 series SoCs:
 	  MV781x0, MV782x0.

@@ -628,7 +629,7 @@ config ARCH_ORION5X
 	select ARCH_REQUIRE_GPIOLIB
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
-	select PLAT_ORION
+	select PLAT_ORION_LEGACY
 	help
 	  Support for the following Marvell Orion 5x series SoCs:
 	  Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),

@@ -1148,6 +1149,10 @@ config PLAT_ORION
 	select IRQ_DOMAIN
 	select COMMON_CLK
 
+config PLAT_ORION_LEGACY
+	bool
+	select PLAT_ORION
+
 config PLAT_PXA
 	bool
arch/arm/plat-orion/Makefile +4 -5
index c20ce0f..1251e5b 100644
@@ -2,9 +2,8 @@
 # Makefile for the linux kernel.
 #
 
-obj-y	:= irq.o pcie.o time.o common.o mpp.o addr-map.o
-obj-m	:=
-obj-n	:=
-obj-	:=
+obj-y                             += addr-map.o
 
-obj-$(CONFIG_GENERIC_GPIO) += gpio.o
+orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
+obj-$(CONFIG_PLAT_ORION_LEGACY)   += irq.o pcie.o time.o common.o mpp.o
+obj-$(CONFIG_PLAT_ORION_LEGACY)   += $(orion-gpio-y)
Signature · 1 line
1.7.9.5
author
#15 lore raw

PATCH v4 15/17 arm: plat-orion: make bridge_virt_base non-const to support DT use case

In reply to Thomas Petazzoni

For the Armada 370 and XP SoCs where the DT is used, we need to fill at runtime the bridge_virt_base field on the orion_addr_map_cfg. Therefore, remove the 'const' qualifier on this field.

Signed-off-by Thomas Petazzoni <[email protected]>
Acked-by Gregory CLEMENT <[email protected]>
---
 arch/arm/plat-orion/include/plat/addr-map.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/plat-orion/include/plat/addr-map.h +1 -1
index 0a746fd..ec63e4a 100644
@@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info;
 struct orion_addr_map_cfg {
 	const int num_wins;	/* Total number of windows */
 	const int remappable_wins;
-	void __iomem * const bridge_virt_base;
+	void __iomem *bridge_virt_base;
 
 	/* If NULL, the default cpu_win_can_remap will be used, using
 	   the value in remappable_wins */
Signature · 1 line
1.7.9.5
author
#16 lore raw

PATCH v4 16/17 arm: mvebu: add basic address decoding support to Armada 370/XP

In reply to Thomas Petazzoni

This commit adds basic support for address decoding configuration for the Armada 370 and Armada XP SoCs, re-using the infrastructure provided in plat-orion.

For now, only a BootROM window is configured on Armada XP, which is needed to get the non-boot CPUs started and is therefore a requirement for SMP support.

Signed-off-by Thomas Petazzoni <[email protected]>
Acked-by Gregory CLEMENT <[email protected]>
---
 arch/arm/mach-mvebu/Makefile   |    2 +-
 arch/arm/mach-mvebu/addr-map.c |  134 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 135 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-mvebu/addr-map.c
arch/arm/mach-mvebu/Makefile +1 -1
index e61d2b8..2143558 100644
@@ -1,2 +1,2 @@
 obj-y += system-controller.o
-obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o
arch/arm/mach-mvebu/addr-map.c new file +134 -0

134 lines not on this page · raw message

Signature · 1 line
1.7.9.5
author
#17 lore raw

PATCH v4 17/17 arm: mvebu: add address decoding controller to the DT

In reply to Thomas Petazzoni
Signed-off-by Thomas Petazzoni <[email protected]>
Acked-by Gregory CLEMENT <[email protected]>
---
 arch/arm/boot/dts/armada-370-xp.dtsi |    5 +++++
 1 file changed, 5 insertions(+)
arch/arm/boot/dts/armada-370-xp.dtsi +5 -0
index 6b6b932..16cc82c 100644
@@ -63,6 +63,11 @@
 			       reg = <0xd0020300 0x30>;
 			       interrupts = <37>, <38>, <39>, <40>;
 		};
+
+		addr-decoding at d0020000 {
+			compatible = "marvell,armada-addr-decoding-controller";
+			reg = <0xd0020000 0x258>;
+		};
 	};
 };
Signature · 1 line
1.7.9.5
#18 lore raw

PATCH v4 1/1 Add basic address decoding support for Marvell 370/XP

In reply to Thomas Petazzoni
Quoted 7 lines · Thomas Petazzoni

Andrew, Jason, Gr?gory,

Here is a patch set that introduces basic support for address decoding on Armada 370 and Armada XP. The aim of this basic support is essentially to be able to configure a window to remap the BootROM, which is needed to startup the secondary CPUs for the SMP support.

Quoted 8 lines

As we had discussed already, the address decoding configuration is not described in the Device Tree, it is for now hardcoded on a per-SoC basis. We might later discuss how to extend this to the Device Tree.

The patch set is relatively long, as it refactors some existing Dove/Kirkwood/MV78xx0/Orion code to use void __iomem pointers instead of unsigned long, as per the request of Arnd Bergmann and Olof Johansson.

Excellent!

Acked-by Arnd Bergmann <[email protected]>

Just one small comment for the very last patch:

Quoted 3 lines

(7) Patch 17 adds the necessary DT code to instantiate the address decoding "controller".

This one seems to lack a device tree binding document.

author
#19 lore raw

PATCH v4 1/1 Add basic address decoding support for Marvell 370/XP

Le Tue, 11 Sep 2012 13:10:00 +0000,
Arnd Bergmann <[email protected]> a ?crit :

Quoted 3 lines

Excellent!

Acked-by Arnd Bergmann <[email protected]>

Thanks!

Quoted 7 lines

Just one small comment for the very last patch:

Quoted 3 lines

(7) Patch 17 adds the necessary DT code to instantiate the address decoding "controller".

This one seems to lack a device tree binding document.

Good point, I'll add some documentation.

Thanks again,

Thomas

Signature · 4 lines
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
author
#20 lore raw

PATCH v4 1/1 Add basic address decoding support for Marvell 370/XP

In reply to Arnd Bergmann

Arnd,

Le Tue, 11 Sep 2012 13:10:00 +0000,
Arnd Bergmann <[email protected]> a ?crit :

Quoted 3 lines

Excellent!

Acked-by Arnd Bergmann <[email protected]>

Related to this patch set, I have a question: wouldn't it make sense to make the .virtual field of struct map_desc anvoid __iomem pointer as well instead of an unsigned long? This would avoid all the (unsigned long) casts in map_descs array definitions, and would be a bit more consistent, no?

Thomas

Signature · 4 lines
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
#21 lore raw

PATCH v4 1/1 Add basic address decoding support for Marvell 370/XP

Quoted 5 lines · Thomas Petazzoni

Le Tue, 11 Sep 2012 13:10:00 +0000,
Arnd Bergmann <[email protected]> a ?crit :

Quoted 2 lines

Excellent!

Quoted 8 lines
Quoted 1 line
Acked-by Arnd Bergmann <[email protected]>

Related to this patch set, I have a question: wouldn't it make sense to make the .virtual field of struct map_desc anvoid __iomem pointer as well instead of an unsigned long? This would avoid all the (unsigned long) casts in map_descs array definitions, and would be a bit more consistent, no?

I've actually tried this before, and got stuck at the point where we set up mappings that are not __iomem in mm/mmu.c: We have a bunch of calls to create_mapping that are not at all related to MMIO access, and as Russell pointed out back then, those should not take an __iomem pointer.

We can probably solve this by changing the prototype for create_mapping to

static void __init create_mapping(unsigned long virtual, unsigned long pfn,

			        unsigned long length, unsigned int type);

and leave a single type cast in the iotable_init() function. There are a few callers that we'd have to change manually then:

arch/arm/mm/dma-mapping.c:dma_contiguous_remap() arch/arm/kernel/tcm.c:tcm_init() arch/arm/mach-davinci/d*.c:SRAM_VIRT arch/arm/mach-omap2/io.c:MT_MEMORY_SO arch/arm/mach-omap2/omap4-common.c:OMAP4_DRAM_BARRIER_VA

My feeling is that we can special-case dma_contiguous_remap by introducing a different helper like

extern void __init create_dma_ready_mapping(unsigned long virtual, size_t length);

and add casts to __iomem for the other four.

Arnd

author
#22 lore raw

PATCH v4 1/1 Add basic address decoding support for Marvell 370/XP

In reply to Thomas Petazzoni

Andrew, Jason,

Do you have any comments on this patch series? It has received a:

Acked-by Arnd Bergmann <[email protected]>

with the only comment being the missing DT binding documentation. And therefore wanted to see if you had other comments about the patches before I send a v5 that includes the requested DT binding documentation.

Thanks!

Thomas

Quoted 91 lines · Thomas Petazzoni

Andrew, Jason, Gr?gory,

Here is a patch set that introduces basic support for address decoding on Armada 370 and Armada XP. The aim of this basic support is essentially to be able to configure a window to remap the BootROM, which is needed to startup the secondary CPUs for the SMP support.

As we had discussed already, the address decoding configuration is not described in the Device Tree, it is for now hardcoded on a per-SoC basis. We might later discuss how to extend this to the Device Tree.

The patch set is relatively long, as it refactors some existing Dove/Kirkwood/MV78xx0/Orion code to use void __iomem pointers instead of unsigned long, as per the request of Arnd Bergmann and Olof Johansson.

This patch set is split in several parts:

(1) Patches 1-4 replaces binary or operators used in register address definitions by plus operators. This is necessary because followup patches change the base addresses constants to void __iomem pointers, and binary or arithmetic on pointers is not allowed. Also, using the plus operator to add an offset to a base address is much more traditional. In our case, the binary or operator and plus operator seem equivalent, as the low-order bits of the base addresses that were being or'ed with an offset were all zero.

(2) Patches 5-9 use the IOMEM() macro to turn the various base virtual addresses constants into void __iomem pointers. This naturally makes all derived constants (virtual addresses of specific registers or units) as void __iomem pointers as well. The patches also adjust the code to take into this change. It adds a few temporary "(unsigned long)" casts that are removed by the following patches that rework a few plat-orion APIs. These temporary casts are necessary to make the patch set properly bisectable, without having a single big patch that does the complete IOMEM() conversion. At the end of the patch set, the only (unsigned long) casts that remain are the one in the map_desc[] array definitions, and those ones are expected.

(3) Patches 10-13 rework some plat-orion APIs so that they use void __iomem pointers instead of unsigned long for virtual addresses. Those patches also remove the now useless "(unsigned long)" casts added in step (2) above.

(4) Patch 14 introduces PLAT_ORION_LEGACY, which allows the Marvell 370/XP platforms to be part of PLAT_ORION, and therefore re-use the existing address decoding code.

(5) Patch 15 makes a small change to an address decoding structure so that we can define at runtime the virtual address of the configuration registers. This is needed as on Armada 370/XP the address decoding "controller" is declared in the Device Tree.

(6) Patch 16 adds the 370/XP address decoding code itself. For now, it only maps the BootROM on Armada XP.

(7) Patch 17 adds the necessary DT code to instantiate the address decoding "controller".

This patch set has been:

* Built, boot tested on Armada XP. The operation of the address mapping support has been tested as well.

* Built tested only on Dove, Kirkwood, Orion5x and MV78xx0.

Changes since v3:
* As per the request of Olof Johansson, use void __iomem pointers everywhere instead of introducing more casts in the patch set. This change has significantly increased the patch set size, though (going from 5 patches in v3 to 17 patches in v4)

Changes since v2:
* Remove one more useless (void __iomem *) cast in the Armada 370/XP addr-map.c file, as noticed by Arnd Bergmann.

Changes since v1:
* Use void __iomem * in addr-map code. Suggested by Arnd Bergmann.
* Add Acked-by on patches 2->5 from Gr?gory Cl?ment

Thanks,

Thomas Petazzoni

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Signature · 4 lines
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
#23 lore raw

PATCH v4 1/1 Add basic address decoding support for Marvell 370/XP

Quoted 11 lines · Thomas Petazzoni

Andrew, Jason,

Do you have any comments on this patch series? It has received a:

Acked-by Arnd Bergmann <[email protected]>

with the only comment being the missing DT binding documentation. And therefore wanted to see if you had other comments about the patches before I send a v5 that includes the requested DT binding documentation.

Thanks!

I have no complaints, but I'm relying on Andrew and the list atm.

thx,

Jason.

maintainer
#24 lore raw

PATCH v4 1/1 Add basic address decoding support for Marvell 370/XP

In reply to Thomas Petazzoni
Quoted 7 lines · Thomas Petazzoni

Andrew, Jason, Gr??gory,

Here is a patch set that introduces basic support for address decoding on Armada 370 and Armada XP. The aim of this basic support is essentially to be able to configure a window to remap the BootROM, which is needed to startup the secondary CPUs for the SMP support.

Quoted 8 lines

As we had discussed already, the address decoding configuration is not described in the Device Tree, it is for now hardcoded on a per-SoC basis. We might later discuss how to extend this to the Device Tree.

The patch set is relatively long, as it refactors some existing Dove/Kirkwood/MV78xx0/Orion code to use void __iomem pointers instead of unsigned long, as per the request of Arnd Bergmann and Olof Johansson.

Hi Thomas

I boot tested it on a kirkwood and an orion5x. No obvious smoke, the ethernet interfaces still work, etc....

Tested-by Andrew Lunn <[email protected]>
Quoted 71 lines

This patch set is split in several parts:

(1) Patches 1-4 replaces binary or operators used in register address definitions by plus operators. This is necessary because followup patches change the base addresses constants to void __iomem pointers, and binary or arithmetic on pointers is not allowed. Also, using the plus operator to add an offset to a base address is much more traditional. In our case, the binary or operator and plus operator seem equivalent, as the low-order bits of the base addresses that were being or'ed with an offset were all zero.

(2) Patches 5-9 use the IOMEM() macro to turn the various base virtual addresses constants into void __iomem pointers. This naturally makes all derived constants (virtual addresses of specific registers or units) as void __iomem pointers as well. The patches also adjust the code to take into this change. It adds a few temporary "(unsigned long)" casts that are removed by the following patches that rework a few plat-orion APIs. These temporary casts are necessary to make the patch set properly bisectable, without having a single big patch that does the complete IOMEM() conversion. At the end of the patch set, the only (unsigned long) casts that remain are the one in the map_desc[] array definitions, and those ones are expected.

(3) Patches 10-13 rework some plat-orion APIs so that they use void __iomem pointers instead of unsigned long for virtual addresses. Those patches also remove the now useless "(unsigned long)" casts added in step (2) above.

(4) Patch 14 introduces PLAT_ORION_LEGACY, which allows the Marvell 370/XP platforms to be part of PLAT_ORION, and therefore re-use the existing address decoding code.

(5) Patch 15 makes a small change to an address decoding structure so that we can define at runtime the virtual address of the configuration registers. This is needed as on Armada 370/XP the address decoding "controller" is declared in the Device Tree.

(6) Patch 16 adds the 370/XP address decoding code itself. For now, it only maps the BootROM on Armada XP.

(7) Patch 17 adds the necessary DT code to instantiate the address decoding "controller".

This patch set has been:

* Built, boot tested on Armada XP. The operation of the address mapping support has been tested as well.

* Built tested only on Dove, Kirkwood, Orion5x and MV78xx0.

Changes since v3:
* As per the request of Olof Johansson, use void __iomem pointers everywhere instead of introducing more casts in the patch set. This change has significantly increased the patch set size, though (going from 5 patches in v3 to 17 patches in v4)

Changes since v2:
* Remove one more useless (void __iomem *) cast in the Armada 370/XP addr-map.c file, as noticed by Arnd Bergmann.

Changes since v1:
* Use void __iomem * in addr-map code. Suggested by Arnd Bergmann.
* Add Acked-by on patches 2->5 from Gr??gory Cl??ment

Thanks,

Thomas Petazzoni

author
#25 lore raw

PATCH v4 1/1 Add basic address decoding support for Marvell 370/XP

Dear Andrew Lunn,

Quoted 4 lines · Andrew Lunn

I boot tested it on a kirkwood and an orion5x. No obvious smoke, the ethernet interfaces still work, etc....

Tested-by Andrew Lunn <[email protected]>

Excellent, thanks!

I'll be posting early next week the DT binding documentation that Arnd has rightfully requested. I was waiting for other comments, but it looks like it is the only that I have received on this series, so I'll got ahead and sent just a separate DT binding documentation patch.

Best regards,

Thomas

Signature · 4 lines
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
#26 lore raw

PATCH v4 1/1 Add basic address decoding support for Marvell 370/XP

Quoted 7 lines · Thomas Petazzoni

Dear Andrew Lunn,

Quoted 3 lines · Andrew Lunn

I boot tested it on a kirkwood and an orion5x. No obvious smoke, the ethernet interfaces still work, etc....

Quoted 9 lines
Quoted 1 line
Tested-by Andrew Lunn <[email protected]>

Excellent, thanks!

I'll be posting early next week the DT binding documentation that Arnd has rightfully requested. I was waiting for other comments, but it looks like it is the only that I have received on this series, so I'll got ahead and sent just a separate DT binding documentation patch.

Thomas,

What is the status of this?

thx,

Jason.