powerpc: fix typo in PTRS_PER_PUD
PATCH 1/1 powerpc: fix typo in PTRS_PER_PUD
PTRS_PER_PUD should be based on PUD_INDEX_SIZE, not PMD_INDEX_SIZE. We got away with it because PUD and PMD had the same index size, but this is no longer true with Aneesh's patchset to support a 46-bit user effective address space.
Signed-off-by Scott Wood <[email protected]>
--- arch/powerpc/include/asm/pgtable-ppc64-4k.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/powerpc/include/asm/pgtable-ppc64-4k.h +1 -1
@@ -19,7 +19,7 @@#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) -#define PTRS_PER_PUD (1 << PMD_INDEX_SIZE) +#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)/* PMD_SHIFT determines what a second-level page table entry can map */
Signature · 1 line
1.7.9.5
Quoted 4 lines · Scott Wood
PTRS_PER_PUDshould be based onPUD_INDEX_SIZE, notPMD_INDEX_SIZE. We got away with it because PUD and PMD had the same index size, but this is no longer true with Aneesh's patchset to support a 46-bit user effective address space.
Ah, my typo :-) Cool, I'll make sure to apply that before Aneesh patches.
Thanks,
Ben.
Quoted 18 lines
Signed-off-by Scott Wood <[email protected]>--- arch/powerpc/include/asm/pgtable-ppc64-4k.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/powerpc/include/asm/pgtable-ppc64-4k.h +1
-1@@ -19,7 +19,7 @@#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) -#define PTRS_PER_PUD (1 << PMD_INDEX_SIZE) +#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)/* PMD_SHIFT determines what a second-level page table entry can map */