Move OMAP2+ over to use COMMON clock
Subsystems (18)
PATCH 25/29 ARM: omap3: clk: Cleanup !CONFIG_COMMON_CLK parts
In reply to Rajendra NayakClean all #ifdef's added to OMAP3 clock code to make it COMMON clk ready, not that CONFIG_COMMON_CLK is enabled.
Signed-off-by Rajendra Nayak <[email protected]>
--- arch/arm/mach-omap2/clkt34xx_dpll3m2.c | 13 ------ arch/arm/mach-omap2/clock.h | 16 ------- arch/arm/mach-omap2/clock34xx.c | 68 +------------------------------- arch/arm/mach-omap2/clock3517.c | 34 +--------------- arch/arm/mach-omap2/clock36xx.c | 19 --------- arch/arm/mach-omap2/clock36xx.h | 4 -- arch/arm/mach-omap2/clock3xxx.c | 8 ---- arch/arm/mach-omap2/clock3xxx.h | 5 -- 8 files changed, 3 insertions(+), 164 deletions(-)
arch/arm/mach-omap2/clkt34xx_dpll3m2.c +0 -13
@@ -47,15 +47,10 @@* Program the DPLL M2 divider with the rounded target rate. Returns * -EINVAL upon error, or 0 upon success. */ -#ifdef CONFIG_COMMON_CLK int omap3_core_dpll_m2_set_rate (struct clk_hw *hw,unsigned long rate,unsigned long parent_rate) {struct clk_hw_omap *clk =to_clk_hw_omap (hw); -#else -int omap3_core_dpll_m2_set_rate (struct clk *clk,unsigned long rate) -{ -#endif u32 new_div =0 ;u32 unlock_dll =0 ;u32 c;
@@ -73,11 +68,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)return -EINVAL ; sdrcrate =__clk_get_rate (sdrc_ick_p); -#ifdef CONFIG_COMMON_CLK clkrate =__clk_get_rate (hw->clk); -#else - clkrate =__clk_get_rate (clk); -#endif if (rate > clkrate) sdrcrate <<= ((rate / clkrate) >>1 );else
@@ -128,10 +119,6 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr, 0, 0, 0, 0); -#ifndef CONFIG_COMMON_CLK - clk->rate = rate; -#endif -return 0 ; }
arch/arm/mach-omap2/clock.h +0 -16
@@ -93,13 +93,8 @@ int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,int omap2_clksel_set_parent (struct clk_hw *hw,u8 field_val);/* clkt_iclk.c public functions */ -#ifdef CONFIG_COMMON_CLK extern void omap2_clkt_iclk_allow_idle (struct clk_hw_omap *clk);extern void omap2_clkt_iclk_deny_idle (struct clk_hw_omap *clk); -#else -extern void omap2_clkt_iclk_allow_idle (struct clk *clk); -extern void omap2_clkt_iclk_deny_idle (struct clk *clk); -#endif u8 omap2_init_dpll_parent (struct clk_hw *hw);unsigned long omap2_get_dpll_rate (struct clk_hw_omap *clk);
@@ -162,7 +157,6 @@ extern const struct clksel_rate gfx_l3_rates[];extern const struct clksel_rate dsp_ick_rates[];extern struct clk dummy_ck; -#ifdef CONFIG_COMMON_CLK extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;extern const struct clk_hw_omap_ops clkhwops_iclk_wait;extern const struct clk_hw_omap_ops clkhwops_wait;
@@ -180,15 +174,5 @@ extern const struct clk_hw_omap_ops clkhwops_apll54;extern const struct clk_hw_omap_ops clkhwops_apll96;extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait; -#else -extern const struct clkops clkops_omap2_iclk_dflt_wait; -extern const struct clkops clkops_omap2_iclk_dflt; -extern const struct clkops clkops_omap2_iclk_idle_only; -extern const struct clkops clkops_omap2_mdmclk_dflt_wait; -extern const struct clkops clkops_omap2xxx_dpll_ops; -extern const struct clkops clkops_omap3_noncore_dpll_ops; -extern const struct clkops clkops_omap3_core_dpll_ops; -extern const struct clkops clkops_omap4_dpllmx_ops; -#endif /* CONFIG_COMMON_CLK */ #endif
arch/arm/mach-omap2/clock34xx.c +2 -66
122 lines not on this page · raw message
arch/arm/mach-omap2/clock3517.c +1 -33
@@ -49,11 +49,7 @@* in the enable register itsel at a bit offset of 4 from the enable * bit. A value of 1 indicates that clock is enabled. */ -#ifdef CONFIG_COMMON_CLK static void am35xx_clk_find_idlest (struct clk_hw_omap *clk, -#else -static void am35xx_clk_find_idlest (struct clk *clk, -#endifvoid __iomem **idlest_reg,u8 *idlest_bit,u8 *idlest_val)
@@ -77,11 +73,7 @@ static void am35xx_clk_find_idlest(struct clk *clk,* associate this type of code with per-module data structures to * avoid this issue, and remove the casts. No return value. */ -#ifdef CONFIG_COMMON_CLK static void am35xx_clk_find_companion (struct clk_hw_omap *clk,void __iomem **other_reg, -#else -static void am35xx_clk_find_companion (struct clk *clk,void __iomem **other_reg, -#endifu8 *other_bit) { *other_reg = (__force void __iomem *)(clk->enable_reg);
@@ -90,19 +82,10 @@ static void am35xx_clk_find_companion(struct clk *clk, void __iomem **other_reg,else *other_bit = clk->enable_bit -AM35XX_IPSS_ICK_FCK_OFFSET ; } -#ifdef CONFIG_COMMON_CLK const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait = { .find_idlest = am35xx_clk_find_idlest, .find_companion = am35xx_clk_find_companion, }; -#else -const struct clkops clkops_am35xx_ipss_module_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = am35xx_clk_find_idlest, - .find_companion = am35xx_clk_find_companion, -}; -#endif /** * am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS
@@ -115,11 +98,7 @@ const struct clkops clkops_am35xx_ipss_module_wait = {* CM_{I,F}CLKEN bit. Pass back the correct info via @idlest_reg * and @idlest_bit. No return value. */ -#ifdef CONFIG_COMMON_CLK static void am35xx_clk_ipss_find_idlest (struct clk_hw_omap *clk, -#else -static void am35xx_clk_ipss_find_idlest (struct clk *clk, -#endifvoid __iomem **idlest_reg,u8 *idlest_bit,u8 *idlest_val)
@@ -131,21 +110,10 @@ static void am35xx_clk_ipss_find_idlest(struct clk *clk, *idlest_bit =AM35XX_ST_IPSS_SHIFT ; *idlest_val =OMAP34XX_CM_IDLEST_VAL ; } -#ifdef CONFIG_COMMON_CLK +const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, .find_idlest = am35xx_clk_ipss_find_idlest, .find_companion = omap2_clk_dflt_find_companion, }; -#else -const struct clkops clkops_am35xx_ipss_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = am35xx_clk_ipss_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, - .allow_idle = omap2_clkt_iclk_allow_idle, - .deny_idle = omap2_clkt_iclk_deny_idle, -}; -#endif -
arch/arm/mach-omap2/clock36xx.c +0 -19
@@ -39,28 +39,18 @@* (Any other value different from the Read value) to the * corresponding CM_CLKSEL register will refresh the dividers. */ -#ifdef CONFIG_COMMON_CLK int omap36xx_pwrdn_clk_enable_with_hsdiv_restore (struct clk_hw *clk) {struct clk_hw_omap *parent;struct clk_hw *parent_hw; -#else -static int omap36xx_pwrdn_clk_enable_with_hsdiv_restore (struct clk *clk) -{ -struct clk *parent; -#endif u32 dummy_v, orig_v, clksel_shift;int ret;/* Clear PWRDN bit of HSDIVIDER */ ret =omap2_dflt_clk_enable (clk); -#ifdef CONFIG_COMMON_CLK parent_hw =__clk_get_hw (__clk_get_parent (clk->clk)); parent =to_clk_hw_omap (parent_hw); -#else - parent = clk->parent; -#endif /* Restore the dividers */ if (!ret) {
@@ -78,12 +68,3 @@ static int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk *clk)return ret; } - -#ifndef CONFIG_COMMON_CLK -const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore = { - .enable = omap36xx_pwrdn_clk_enable_with_hsdiv_restore, - .disable = omap2_dflt_clk_disable, - .find_companion = omap2_clk_dflt_find_companion, - .find_idlest = omap2_clk_dflt_find_idlest, -}; -#endif
arch/arm/mach-omap2/clock36xx.h +0 -4
@@ -8,10 +8,6 @@#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H#define __ARCH_ARM_MACH_OMAP2_CLOCK36XX_H -#ifdef CONFIG_COMMON_CLK extern int omap36xx_pwrdn_clk_enable_with_hsdiv_restore (struct clk_hw *hw); -#else -extern const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; -#endif #endif
arch/arm/mach-omap2/clock3xxx.c +0 -8
@@ -40,12 +40,8 @@/* needed by omap3_core_dpll_m2_set_rate() */ struct clk *sdrc_ick_p, *arm_fck_p; -#ifdef CONFIG_COMMON_CLK int omap3_dpll4_set_rate (struct clk_hw *hw,unsigned long rate,unsigned long parent_rate) -#else -int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) -#endif {/* * According to the 12-5 CDP code from TI, "Limitation 2.5"
@@ -58,11 +54,7 @@ int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)return -EINVAL ; } -#ifdef CONFIG_COMMON_CLK return omap3_noncore_dpll_set_rate (hw, rate, parent_rate); -#else -return omap3_noncore_dpll_set_rate (clk, rate); -#endif }void __init omap3_clk_lock_dpll5 (void )
arch/arm/mach-omap2/clock3xxx.h +0 -5
@@ -9,15 +9,10 @@#define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_Hint omap3xxx_clk_init (void ); -#ifdef CONFIG_COMMON_CLK int omap3_dpll4_set_rate (struct clk_hw *clk,unsigned long rate,unsigned long parent_rate);int omap3_core_dpll_m2_set_rate (struct clk_hw *clk,unsigned long rate,unsigned long parent_rate); -#else -int omap3_dpll4_set_rate (struct clk *clk,unsigned long rate); -int omap3_core_dpll_m2_set_rate (struct clk *clk,unsigned long rate); -#endif void omap3_clk_lock_dpll5 (void );extern struct clk *sdrc_ick_p;
Signature · 1 line
1.7.1
PATCH 26/29 ARM: omap2: clk: Cleanup !CONFIG_COMMON_CLK parts
In reply to Rajendra NayakClean all #ifdef's added to OMAP2 clock code to make it COMMON clk ready, not that CONFIG_COMMON_CLK is enabled.
Signed-off-by Rajendra Nayak <[email protected]>
--- arch/arm/mach-omap2/clkt2xxx_apll.c | 54 -------------------------- arch/arm/mach-omap2/clkt2xxx_dpll.c | 16 -------- arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 18 --------- arch/arm/mach-omap2/clkt2xxx_osc.c | 20 --------- arch/arm/mach-omap2/clkt2xxx_sys.c | 8 ---- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 16 -------- arch/arm/mach-omap2/clock2430.c | 13 ------ arch/arm/mach-omap2/clock2xxx.h | 19 --------- arch/arm/mach-omap2/pm24xx.c | 8 ---- 9 files changed, 0 insertions(+), 172 deletions(-)
arch/arm/mach-omap2/clkt2xxx_apll.c +0 -54
@@ -43,14 +43,9 @@ void __iomem *cm_idlest_pll;/* Private functions */ /* Enable an APLL if off */ -#ifdef CONFIG_COMMON_CLK static int omap2_clk_apll_enable (struct clk_hw *hw,u32 status_mask) {struct clk_hw_omap *clk =to_clk_hw_omap (hw); -#else -static int omap2_clk_apll_enable (struct clk *clk,u32 status_mask) -{ -#endif u32 cval, apll_mask; apll_mask =EN_APLL_LOCKED << clk->enable_bit;
@@ -65,11 +60,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)omap2_cm_write_mod_reg (cval,PLL_MOD ,CM_CLKEN );omap2_cm_wait_idlest (cm_idlest_pll, status_mask, -#ifdef CONFIG_COMMON_CLKOMAP24XX_CM_IDLEST_VAL ,__clk_get_name (hw->clk)); -#else - OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk)); -#endif /* * REVISIT: Should we return an error code if omap2_wait_clock_ready()
@@ -78,69 +69,40 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)return 0 ; } -#ifdef CONFIG_COMMON_CLKint omap2_clk_apll96_enable (struct clk_hw *clk) -#else -static int omap2_clk_apll96_enable(struct clk *clk) -#endif {return omap2_clk_apll_enable (clk,OMAP24XX_ST_96M_APLL_MASK ); } -#ifdef CONFIG_COMMON_CLKint omap2_clk_apll54_enable (struct clk_hw *clk) -#else -static int omap2_clk_apll54_enable(struct clk *clk) -#endif {return omap2_clk_apll_enable (clk,OMAP24XX_ST_54M_APLL_MASK ); } -#ifdef CONFIG_COMMON_CLKvoid _apll96_allow_idle (struct clk_hw_omap *clk) -#else -static void _apll96_allow_idle(struct clk *clk) -#endif {omap2xxx_cm_set_apll96_auto_low_power_stop (); } -#ifdef CONFIG_COMMON_CLKvoid _apll96_deny_idle (struct clk_hw_omap *clk) -#else -static void _apll96_deny_idle(struct clk *clk) -#endif {omap2xxx_cm_set_apll96_disable_autoidle (); } -#ifdef CONFIG_COMMON_CLKvoid _apll54_allow_idle (struct clk_hw_omap *clk) -#else -static void _apll54_allow_idle(struct clk *clk) -#endif {omap2xxx_cm_set_apll54_auto_low_power_stop (); } -#ifdef CONFIG_COMMON_CLKvoid _apll54_deny_idle (struct clk_hw_omap *clk) -#else -static void _apll54_deny_idle(struct clk *clk) -#endif {omap2xxx_cm_set_apll54_disable_autoidle (); }/* Stop APLL */ -#ifdef CONFIG_COMMON_CLKvoid omap2_clk_apll_disable (struct clk_hw *hw) {struct clk_hw_omap *clk =to_clk_hw_omap (hw); -#else -static void omap2_clk_apll_disable(struct clk *clk) -{ -#endifu32 cval; cval =omap2_cm_read_mod_reg (PLL_MOD ,CM_CLKEN );
@@ -149,7 +111,6 @@ static void omap2_clk_apll_disable(struct clk *clk) }/* Public data */ -#ifdef CONFIG_COMMON_CLK const struct clk_hw_omap_ops clkhwops_apll54 = { .allow_idle = _apll54_allow_idle, .deny_idle = _apll54_deny_idle,
@@ -159,21 +120,6 @@ const struct clk_hw_omap_ops clkhwops_apll96 = { .allow_idle = _apll96_allow_idle, .deny_idle = _apll96_deny_idle, }; -#else -const struct clkops clkops_apll96 = { - .enable = omap2_clk_apll96_enable, - .disable = omap2_clk_apll_disable, - .allow_idle = _apll96_allow_idle, - .deny_idle = _apll96_deny_idle, -}; - -const struct clkops clkops_apll54 = { - .enable = omap2_clk_apll54_enable, - .disable = omap2_clk_apll_disable, - .allow_idle = _apll54_allow_idle, - .deny_idle = _apll54_deny_idle, -}; -#endif /* Public functions */
arch/arm/mach-omap2/clkt2xxx_dpll.c +0 -16
@@ -31,11 +31,7 @@* REVISIT: DPLL can optionally enter low-power bypass by writing 0x1 * instead. Add some mechanism to optionally enter this mode. */ -#ifdef CONFIG_COMMON_CLK void _allow_idle (struct clk_hw_omap *clk) -#else -static void _allow_idle(struct clk *clk) -#endif {if (!clk || !clk->dpll_data)return ;
@@ -49,11 +45,7 @@ static void _allow_idle(struct clk *clk)* * Disable DPLL automatic idle control. No return value. */ -#ifdef CONFIG_COMMON_CLK void _deny_idle (struct clk_hw_omap *clk) -#else -static void _deny_idle(struct clk *clk) -#endif {if (!clk || !clk->dpll_data)return ;
@@ -63,15 +55,7 @@ static void _deny_idle(struct clk *clk)/* Public data */ -#ifdef CONFIG_COMMON_CLK const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = { .allow_idle = _allow_idle, .deny_idle = _deny_idle, }; -#else -const struct clkops clkops_omap2xxx_dpll_ops = { - .allow_idle = _allow_idle, - .deny_idle = _deny_idle, -}; -#endif -
arch/arm/mach-omap2/clkt2xxx_dpllcore.c +0 -18
@@ -47,11 +47,7 @@* struct clk *dpll_ck, which is a composite clock of dpll_ck and * core_ck. */ -#ifdef CONFIG_COMMON_CLK unsigned long omap2xxx_clk_get_core_rate (struct clk_hw_omap *clk) -#else -unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) -#endif {long long core_clk;u32 v;
@@ -102,36 +98,22 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) } -#ifdef CONFIG_COMMON_CLK unsigned long omap2_dpllcore_recalc (struct clk_hw *hw,unsigned long parent_rate) {struct clk_hw_omap *clk =to_clk_hw_omap (hw); -#else -unsigned long omap2_dpllcore_recalc (struct clk *clk) -{ -#endif return omap2xxx_clk_get_core_rate (clk); } -#ifdef CONFIG_COMMON_CLK int omap2_reprogram_dpllcore (struct clk_hw *hw,unsigned long rate,unsigned long parent_rate) {struct clk_hw_omap *clk =to_clk_hw_omap (hw); -#else -int omap2_reprogram_dpllcore (struct clk *clk,unsigned long rate) -{ -#endif u32 cur_rate, low, mult, div, valid_rate, done_rate;u32 bypass =0 ;struct prcm_config tmpset;const struct dpll_data *dd; -#ifdef CONFIG_COMMON_CLK cur_rate =omap2xxx_clk_get_core_rate (to_clk_hw_omap (dclk_hw)); -#else - cur_rate =omap2xxx_clk_get_core_rate (dclk); -#endif mult =omap2_cm_read_mod_reg (PLL_MOD ,CM_CLKSEL2 ); mult &=OMAP24XX_CORE_CLK_SRC_MASK ;
arch/arm/mach-omap2/clkt2xxx_osc.c +0 -20
@@ -37,11 +37,7 @@* clk_enable/clk_disable()-based usecounting for osc_ck should be * replaced with autoidle-based usecounting. */ -#ifdef CONFIG_COMMON_CLK int omap2_enable_osc_ck (struct clk_hw *clk) -#else -static int omap2_enable_osc_ck(struct clk *clk) -#endif {u32 pcc;
@@ -59,11 +55,7 @@ static int omap2_enable_osc_ck(struct clk *clk)* clk_enable/clk_disable()-based usecounting for osc_ck should be * replaced with autoidle-based usecounting. */ -#ifdef CONFIG_COMMON_CLK void omap2_disable_osc_ck (struct clk_hw *clk) -#else -static void omap2_disable_osc_ck(struct clk *clk) -#endif {u32 pcc;
@@ -72,19 +64,7 @@ static void omap2_disable_osc_ck(struct clk *clk)__raw_writel (pcc |OMAP_AUTOEXTCLKMODE_MASK , prcm_clksrc_ctrl); } -#ifndef CONFIG_COMMON_CLK -const struct clkops clkops_oscck = { - .enable = omap2_enable_osc_ck, - .disable = omap2_disable_osc_ck, -}; -#endif - -#ifdef CONFIG_COMMON_CLK unsigned long omap2_osc_clk_recalc (struct clk_hw *clk,unsigned long parent_rate) -#else -unsigned long omap2_osc_clk_recalc(struct clk *clk) -#endif {return omap2xxx_get_apll_clkin () *omap2xxx_get_sysclkdiv (); } -
arch/arm/mach-omap2/clkt2xxx_sys.c +0 -8
@@ -42,15 +42,7 @@ u32 omap2xxx_get_sysclkdiv(void)return div; } -#ifdef CONFIG_COMMON_CLK unsigned long omap2xxx_sys_clk_recalc (struct clk_hw *clk,unsigned long parent_rate) {return parent_rate /omap2xxx_get_sysclkdiv (); } -#else -unsigned long omap2xxx_sys_clk_recalc (struct clk *clk) -{ -return clk->parent->rate /omap2xxx_get_sysclkdiv (); -} -#endif -
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +0 -16
@@ -53,11 +53,7 @@ const struct prcm_config *rate_table;* * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. */ -#ifdef CONFIG_COMMON_CLK unsigned long omap2_table_mpu_recalc (struct clk_hw *clk,unsigned long parent_rate) -#else -unsigned long omap2_table_mpu_recalc(struct clk *clk) -#endif {return curr_prcm_set->mpu_speed; }
@@ -69,12 +65,8 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)* Some might argue L3-DDR, others ARM, others IVA. This code is simple and * just uses the ARM rates. */ -#ifdef CONFIG_COMMON_CLK long omap2_round_to_table_rate (struct clk_hw *hw,unsigned long rate,unsigned long *parent_rate) -#else -long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) -#endif {const struct prcm_config *ptr;long highest_rate;
@@ -97,12 +89,8 @@ long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) }/* Sets basic clocks based on the specified rate */ -#ifdef CONFIG_COMMON_CLK int omap2_select_table_rate (struct clk_hw *hw,unsigned long rate,unsigned long parent_rate) -#else -int omap2_select_table_rate(struct clk *clk, unsigned long rate) -#endif {u32 cur_rate, done_rate, bypass =0 , tmp;const struct prcm_config *prcm;
@@ -129,11 +117,7 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate) } curr_prcm_set = prcm; -#ifdef CONFIG_COMMON_CLK cur_rate =omap2xxx_clk_get_core_rate (to_clk_hw_omap (dclk_hw)); -#else - cur_rate =omap2xxx_clk_get_core_rate (dclk); -#endif if (prcm->dpll_speed == cur_rate /2 ) {omap2xxx_sdrc_reprogram (CORE_CLK_SRC_DPLL ,1 );
arch/arm/mach-omap2/clock2430.c +0 -13
@@ -42,11 +42,7 @@* passes back the correct CM_IDLEST register address for I2CHS * modules. No return value. */ -#ifdef CONFIG_COMMON_CLK static void omap2430_clk_i2chs_find_idlest (struct clk_hw_omap *clk, -#else -static void omap2430_clk_i2chs_find_idlest (struct clk *clk, -#endifvoid __iomem **idlest_reg,u8 *idlest_bit,u8 *idlest_val)
@@ -57,16 +53,7 @@ static void omap2430_clk_i2chs_find_idlest(struct clk *clk, }/* 2430 I2CHS has non-standard IDLEST register */ -#ifdef CONFIG_COMMON_CLK const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait = { .find_idlest = omap2430_clk_i2chs_find_idlest, .find_companion = omap2_clk_dflt_find_companion, }; -#else -const struct clkops clkops_omap2430_i2chs_wait = { - .enable = omap2_dflt_clk_enable, - .disable = omap2_dflt_clk_disable, - .find_idlest = omap2430_clk_i2chs_find_idlest, - .find_companion = omap2_clk_dflt_find_companion, -}; -#endif
arch/arm/mach-omap2/clock2xxx.h +0 -19
@@ -8,7 +8,6 @@#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H#define __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H -#ifdef CONFIG_COMMON_CLK #include <linux/clk-provider.h> #include "clock.h"
@@ -21,16 +20,6 @@ unsigned long omap2_osc_clk_recalc(struct clk_hw *clk, unsigned long parent_rateunsigned long omap2_dpllcore_recalc (struct clk_hw *hw,unsigned long parent_rate);int omap2_reprogram_dpllcore (struct clk_hw *clk,unsigned long rate,unsigned long parent_rate);unsigned long omap2xxx_clk_get_core_rate (struct clk_hw_omap *clk); -#else -unsigned long omap2_table_mpu_recalc (struct clk *clk); -int omap2_select_table_rate (struct clk *clk,unsigned long rate); -long omap2_round_to_table_rate (struct clk *clk,unsigned long rate); -unsigned long omap2xxx_sys_clk_recalc (struct clk *clk); -unsigned long omap2_osc_clk_recalc (struct clk *clk); -unsigned long omap2_dpllcore_recalc (struct clk *clk); -int omap2_reprogram_dpllcore (struct clk *clk,unsigned long rate); -unsigned long omap2xxx_clk_get_core_rate (struct clk *clk); -#endif u32 omap2xxx_get_apll_clkin (void );u32 omap2xxx_get_sysclkdiv (void );void omap2xxx_clk_prepare_for_reboot (void );
@@ -50,8 +39,6 @@ int omap2430_clk_init(void);extern void __iomem *prcm_clksrc_ctrl, *cm_idlest_pll;extern struct clk *dclk; - -#ifdef CONFIG_COMMON_CLK extern struct clk_hw *dclk_hw;int omap2_enable_osc_ck (struct clk_hw *hw);void omap2_disable_osc_ck (struct clk_hw *hw);
@@ -64,11 +51,5 @@ void _apll54_deny_idle(struct clk_hw_omap *hw);void omap2_clk_apll_disable (struct clk_hw *hw);void _allow_idle (struct clk_hw_omap *hw);void _deny_idle (struct clk_hw_omap *hw); -#else -extern const struct clkops clkops_omap2430_i2chs_wait; -extern const struct clkops clkops_oscck; -extern const struct clkops clkops_apll96; -extern const struct clkops clkops_apll54; -#endif #endif
arch/arm/mach-omap2/pm24xx.c +0 -8
@@ -25,11 +25,7 @@#include <linux/sysfs.h> #include <linux/module.h> #include <linux/delay.h> -#ifdef CONFIG_COMMON_CLK #include <linux/clk-provider.h> -#else -#include <linux/clk.h> -#endif #include <linux/irq.h> #include <linux/time.h> #include <linux/gpio.h>
@@ -206,11 +202,7 @@ static int omap2_can_sleep(void) {if (omap2_fclks_active ())return 0 ; -#ifdef CONFIG_COMMON_CLK if (__clk_is_enabled (osc_ck)) -#else - if (osc_ck->usecount > 1) -#endif return 0 ;if (omap_dma_running ())return 0 ;
Signature · 1 line
1.7.1
PATCH 27/29 ARM: omap4: clk: Delete old OMAP clock data
In reply to Rajendra NayakNow that we have switched to using new common clk
data for OMAP4, delete the old one.
Signed-off-by Rajendra Nayak <[email protected]>
--- arch/arm/mach-omap2/clock44xx_data.c | 3472 ---------------------------------- 1 files changed, 0 insertions(+), 3472 deletions(-) delete mode 100644 arch/arm/mach-omap2/clock44xx_data.c
arch/arm/mach-omap2/clock44xx_data.c deleted +0 -3472
@@ -1,3472 +0,0 @@ -/* -* OMAP4 Clock data -* -* Copyright (C) 2009-2010 Texas Instruments, Inc. -* Copyright (C) 2009-2010 Nokia Corporation -* -* Paul Walmsley (paul at pwsan.com) -* Rajendra Nayak (rnayak at ti.com) -* Benoit Cousson (b-cousson at ti.com) -* -* This file is automatically generated from the OMAP hardware databases. -* We respectfully ask that any modifications to this file be coordinated -* with the public linux-omap at vger.kernel.org mailing list and the -* authors above to ensure that the autogeneration scripts are kept -* up-to-date with the file contents. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License version 2 as -* published by the Free Software Foundation. -* -* XXX Some of the ES1 clocks have been removed/changed; once support -* is added for discriminating clocks by ES level, these should be added back -* in. -*/ - -#include <linux/kernel.h> -#include <linux/list.h> -#include <linux/clk.h> -#include <linux/io.h> - -#include <plat/hardware.h> -#include <plat/clkdev_omap.h> - -#include "iomap.h" -#include "clock.h" -#include "clock44xx.h" -#include "cm1_44xx.h" -#include "cm2_44xx.h" -#include "cm-regbits-44xx.h" -#include "prm44xx.h" -#include "prm-regbits-44xx.h" -#include "control.h" -#include "scrm44xx.h" - -/* OMAP4 modulemode control */ -#define OMAP4430_MODULEMODE_HWCTRL 0 -#define OMAP4430_MODULEMODE_SWCTRL 1 - -/* Root clocks */ - -static struct clk extalt_clkin_ck = { - .name ="extalt_clkin_ck" , - .rate =59000000 , - .ops = &clkops_null, -}; - -static struct clk pad_clks_ck = { - .name ="pad_clks_ck" , - .rate =12000000 , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_CLKSEL_ABE , - .enable_bit =OMAP4430_PAD_CLKS_GATE_SHIFT , -}; - -static struct clk pad_slimbus_core_clks_ck = { - .name ="pad_slimbus_core_clks_ck" , - .rate =12000000 , - .ops = &clkops_null, -}; - -static struct clk secure_32k_clk_src_ck = { - .name ="secure_32k_clk_src_ck" , - .rate =32768 , - .ops = &clkops_null, -}; - -static struct clk slimbus_clk = { - .name ="slimbus_clk" , - .rate =12000000 , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_CLKSEL_ABE , - .enable_bit =OMAP4430_SLIMBUS_CLK_GATE_SHIFT , -}; - -static struct clk sys_32k_ck = { - .name ="sys_32k_ck" , - .rate =32768 , - .ops = &clkops_null, -}; - -static struct clk virt_12000000_ck = { - .name ="virt_12000000_ck" , - .ops = &clkops_null, - .rate =12000000 , -}; - -static struct clk virt_13000000_ck = { - .name ="virt_13000000_ck" , - .ops = &clkops_null, - .rate =13000000 , -}; - -static struct clk virt_16800000_ck = { - .name ="virt_16800000_ck" , - .ops = &clkops_null, - .rate =16800000 , -}; - -static struct clk virt_19200000_ck = { - .name ="virt_19200000_ck" , - .ops = &clkops_null, - .rate =19200000 , -}; - -static struct clk virt_26000000_ck = { - .name ="virt_26000000_ck" , - .ops = &clkops_null, - .rate =26000000 , -}; - -static struct clk virt_27000000_ck = { - .name ="virt_27000000_ck" , - .ops = &clkops_null, - .rate =27000000 , -}; - -static struct clk virt_38400000_ck = { - .name ="virt_38400000_ck" , - .ops = &clkops_null, - .rate =38400000 , -}; - -static const struct clksel_rate div_1_0_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_4430 }, - { .div =0 }, -}; - -static const struct clksel_rate div_1_1_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_4430 }, - { .div =0 }, -}; - -static const struct clksel_rate div_1_2_rates[] = { - { .div =1 , .val =2 , .flags =RATE_IN_4430 }, - { .div =0 }, -}; - -static const struct clksel_rate div_1_3_rates[] = { - { .div =1 , .val =3 , .flags =RATE_IN_4430 }, - { .div =0 }, -}; - -static const struct clksel_rate div_1_4_rates[] = { - { .div =1 , .val =4 , .flags =RATE_IN_4430 }, - { .div =0 }, -}; - -static const struct clksel_rate div_1_5_rates[] = { - { .div =1 , .val =5 , .flags =RATE_IN_4430 }, - { .div =0 }, -}; - -static const struct clksel_rate div_1_6_rates[] = { - { .div =1 , .val =6 , .flags =RATE_IN_4430 }, - { .div =0 }, -}; - -static const struct clksel_rate div_1_7_rates[] = { - { .div =1 , .val =7 , .flags =RATE_IN_4430 }, - { .div =0 }, -}; - -static const struct clksel sys_clkin_sel[] = { - { .parent = &virt_12000000_ck, .rates = div_1_1_rates }, - { .parent = &virt_13000000_ck, .rates = div_1_2_rates }, - { .parent = &virt_16800000_ck, .rates = div_1_3_rates }, - { .parent = &virt_19200000_ck, .rates = div_1_4_rates }, - { .parent = &virt_26000000_ck, .rates = div_1_5_rates }, - { .parent = &virt_27000000_ck, .rates = div_1_6_rates }, - { .parent = &virt_38400000_ck, .rates = div_1_7_rates }, - { .parent =NULL }, -}; - -static struct clk sys_clkin_ck = { - .name ="sys_clkin_ck" , - .rate =38400000 , - .clksel = sys_clkin_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_SYS_CLKSEL , - .clksel_mask =OMAP4430_SYS_CLKSEL_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk tie_low_clock_ck = { - .name ="tie_low_clock_ck" , - .rate =0 , - .ops = &clkops_null, -}; - -static struct clk utmi_phy_clkout_ck = { - .name ="utmi_phy_clkout_ck" , - .rate =60000000 , - .ops = &clkops_null, -}; - -static struct clk xclk60mhsp1_ck = { - .name ="xclk60mhsp1_ck" , - .rate =60000000 , - .ops = &clkops_null, -}; - -static struct clk xclk60mhsp2_ck = { - .name ="xclk60mhsp2_ck" , - .rate =60000000 , - .ops = &clkops_null, -}; - -static struct clk xclk60motg_ck = { - .name ="xclk60motg_ck" , - .rate =60000000 , - .ops = &clkops_null, -}; - -/* Module clocks and DPLL outputs */ - -static const struct clksel abe_dpll_bypass_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, - { .parent =NULL }, -}; - -static struct clk abe_dpll_bypass_clk_mux_ck = { - .name ="abe_dpll_bypass_clk_mux_ck" , - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk abe_dpll_refclk_mux_ck = { - .name ="abe_dpll_refclk_mux_ck" , - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_ABE_PLL_REF_CLKSEL , - .clksel_mask =OMAP4430_CLKSEL_0_0_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -/* DPLL_ABE */ -static struct dpll_data dpll_abe_dd = { - .mult_div1_reg =OMAP4430_CM_CLKSEL_DPLL_ABE , - .clk_bypass = &abe_dpll_bypass_clk_mux_ck, - .clk_ref = &abe_dpll_refclk_mux_ck, - .control_reg =OMAP4430_CM_CLKMODE_DPLL_ABE , - .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), - .autoidle_reg =OMAP4430_CM_AUTOIDLE_DPLL_ABE , - .idlest_reg =OMAP4430_CM_IDLEST_DPLL_ABE , - .mult_mask =OMAP4430_DPLL_MULT_MASK , - .div1_mask =OMAP4430_DPLL_DIV_MASK , - .enable_mask =OMAP4430_DPLL_EN_MASK , - .autoidle_mask =OMAP4430_AUTO_DPLL_MODE_MASK , - .idlest_mask =OMAP4430_ST_DPLL_CLK_MASK , - .max_multiplier =2047 , - .max_divider =128 , - .min_divider =1 , -}; - - -static struct clk dpll_abe_ck = { - .name ="dpll_abe_ck" , - .parent = &abe_dpll_refclk_mux_ck, - .dpll_data = &dpll_abe_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap4_dpll_regm4xen_recalc, - .round_rate = &omap4_dpll_regm4xen_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -static struct clk dpll_abe_x2_ck = { - .name ="dpll_abe_x2_ck" , - .parent = &dpll_abe_ck, - .clksel_reg =OMAP4430_CM_DIV_M2_DPLL_ABE , - .flags =CLOCK_CLKOUTX2 , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap3_clkoutx2_recalc, -}; - -static const struct clksel_rate div31_1to31_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_4430 }, - { .div =2 , .val =2 , .flags =RATE_IN_4430 }, - { .div =3 , .val =3 , .flags =RATE_IN_4430 }, - { .div =4 , .val =4 , .flags =RATE_IN_4430 }, - { .div =5 , .val =5 , .flags =RATE_IN_4430 }, - { .div =6 , .val =6 , .flags =RATE_IN_4430 }, - { .div =7 , .val =7 , .flags =RATE_IN_4430 }, - { .div =8 , .val =8 , .flags =RATE_IN_4430 }, - { .div =9 , .val =9 , .flags =RATE_IN_4430 }, - { .div =10 , .val =10 , .flags =RATE_IN_4430 }, - { .div =11 , .val =11 , .flags =RATE_IN_4430 }, - { .div =12 , .val =12 , .flags =RATE_IN_4430 }, - { .div =13 , .val =13 , .flags =RATE_IN_4430 }, - { .div =14 , .val =14 , .flags =RATE_IN_4430 }, - { .div =15 , .val =15 , .flags =RATE_IN_4430 }, - { .div =16 , .val =16 , .flags =RATE_IN_4430 }, - { .div =17 , .val =17 , .flags =RATE_IN_4430 }, - { .div =18 , .val =18 , .flags =RATE_IN_4430 }, - { .div =19 , .val =19 , .flags =RATE_IN_4430 }, - { .div =20 , .val =20 , .flags =RATE_IN_4430 }, - { .div =21 , .val =21 , .flags =RATE_IN_4430 }, - { .div =22 , .val =22 , .flags =RATE_IN_4430 }, - { .div =23 , .val =23 , .flags =RATE_IN_4430 }, - { .div =24 , .val =24 , .flags =RATE_IN_4430 }, - { .div =25 , .val =25 , .flags =RATE_IN_4430 }, - { .div =26 , .val =26 , .flags =RATE_IN_4430 }, - { .div =27 , .val =27 , .flags =RATE_IN_4430 }, - { .div =28 , .val =28 , .flags =RATE_IN_4430 }, - { .div =29 , .val =29 , .flags =RATE_IN_4430 }, - { .div =30 , .val =30 , .flags =RATE_IN_4430 }, - { .div =31 , .val =31 , .flags =RATE_IN_4430 }, - { .div =0 }, -}; - -static const struct clksel dpll_abe_m2x2_div[] = { - { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates }, - { .parent =NULL }, -}; - -static struct clk dpll_abe_m2x2_ck = { - .name ="dpll_abe_m2x2_ck" , - .parent = &dpll_abe_x2_ck, - .clksel = dpll_abe_m2x2_div, - .clksel_reg =OMAP4430_CM_DIV_M2_DPLL_ABE , - .clksel_mask =OMAP4430_DPLL_CLKOUT_DIV_MASK , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk abe_24m_fclk = { - .name ="abe_24m_fclk" , - .parent = &dpll_abe_m2x2_ck, - .ops = &clkops_null, - .fixed_div =8 , - .recalc = &omap_fixed_divisor_recalc, -}; - -static const struct clksel_rate div3_1to4_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_4430 }, - { .div =2 , .val =1 , .flags =RATE_IN_4430 }, - { .div =4 , .val =2 , .flags =RATE_IN_4430 }, - { .div =0 }, -}; - -static const struct clksel abe_clk_div[] = { - { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates }, - { .parent =NULL }, -}; - -static struct clk abe_clk = { - .name ="abe_clk" , - .parent = &dpll_abe_m2x2_ck, - .clksel = abe_clk_div, - .clksel_reg =OMAP4430_CM_CLKSEL_ABE , - .clksel_mask =OMAP4430_CLKSEL_OPP_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel_rate div2_1to2_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_4430 }, - { .div =2 , .val =1 , .flags =RATE_IN_4430 }, - { .div =0 }, -}; - -static const struct clksel aess_fclk_div[] = { - { .parent = &abe_clk, .rates = div2_1to2_rates }, - { .parent =NULL }, -}; - -static struct clk aess_fclk = { - .name ="aess_fclk" , - .parent = &abe_clk, - .clksel = aess_fclk_div, - .clksel_reg =OMAP4430_CM1_ABE_AESS_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_AESS_FCLK_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_abe_m3x2_ck = { - .name ="dpll_abe_m3x2_ck" , - .parent = &dpll_abe_x2_ck, - .clksel = dpll_abe_m2x2_div, - .clksel_reg =OMAP4430_CM_DIV_M3_DPLL_ABE , - .clksel_mask =OMAP4430_DPLL_CLKOUTHIF_DIV_MASK , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel core_hsd_byp_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates }, - { .parent =NULL }, -}; - -static struct clk core_hsd_byp_clk_mux_ck = { - .name ="core_hsd_byp_clk_mux_ck" , - .parent = &sys_clkin_ck, - .clksel = core_hsd_byp_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_CLKSEL_DPLL_CORE , - .clksel_mask =OMAP4430_DPLL_BYP_CLKSEL_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -/* DPLL_CORE */ -static struct dpll_data dpll_core_dd = { - .mult_div1_reg =OMAP4430_CM_CLKSEL_DPLL_CORE , - .clk_bypass = &core_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, - .control_reg =OMAP4430_CM_CLKMODE_DPLL_CORE , - .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), - .autoidle_reg =OMAP4430_CM_AUTOIDLE_DPLL_CORE , - .idlest_reg =OMAP4430_CM_IDLEST_DPLL_CORE , - .mult_mask =OMAP4430_DPLL_MULT_MASK , - .div1_mask =OMAP4430_DPLL_DIV_MASK , - .enable_mask =OMAP4430_DPLL_EN_MASK , - .autoidle_mask =OMAP4430_AUTO_DPLL_MODE_MASK , - .idlest_mask =OMAP4430_ST_DPLL_CLK_MASK , - .max_multiplier =2047 , - .max_divider =128 , - .min_divider =1 , -}; - - -static struct clk dpll_core_ck = { - .name ="dpll_core_ck" , - .parent = &sys_clkin_ck, - .dpll_data = &dpll_core_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_core_dpll_ops, - .recalc = &omap3_dpll_recalc, -}; - -static struct clk dpll_core_x2_ck = { - .name ="dpll_core_x2_ck" , - .parent = &dpll_core_ck, - .flags =CLOCK_CLKOUTX2 , - .ops = &clkops_null, - .recalc = &omap3_clkoutx2_recalc, -}; - -static const struct clksel dpll_core_m6x2_div[] = { - { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, - { .parent =NULL }, -}; - -static struct clk dpll_core_m6x2_ck = { - .name ="dpll_core_m6x2_ck" , - .parent = &dpll_core_x2_ck, - .clksel = dpll_core_m6x2_div, - .clksel_reg =OMAP4430_CM_DIV_M6_DPLL_CORE , - .clksel_mask =OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel dbgclk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, - { .parent =NULL }, -}; - -static struct clk dbgclk_mux_ck = { - .name ="dbgclk_mux_ck" , - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static const struct clksel dpll_core_m2_div[] = { - { .parent = &dpll_core_ck, .rates = div31_1to31_rates }, - { .parent =NULL }, -}; - -static struct clk dpll_core_m2_ck = { - .name ="dpll_core_m2_ck" , - .parent = &dpll_core_ck, - .clksel = dpll_core_m2_div, - .clksel_reg =OMAP4430_CM_DIV_M2_DPLL_CORE , - .clksel_mask =OMAP4430_DPLL_CLKOUT_DIV_MASK , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk ddrphy_ck = { - .name ="ddrphy_ck" , - .parent = &dpll_core_m2_ck, - .ops = &clkops_null, - .fixed_div =2 , - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk dpll_core_m5x2_ck = { - .name ="dpll_core_m5x2_ck" , - .parent = &dpll_core_x2_ck, - .clksel = dpll_core_m6x2_div, - .clksel_reg =OMAP4430_CM_DIV_M5_DPLL_CORE , - .clksel_mask =OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel div_core_div[] = { - { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates }, - { .parent =NULL }, -}; - -static struct clk div_core_ck = { - .name ="div_core_ck" , - .parent = &dpll_core_m5x2_ck, - .clksel = div_core_div, - .clksel_reg =OMAP4430_CM_CLKSEL_CORE , - .clksel_mask =OMAP4430_CLKSEL_CORE_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel_rate div4_1to8_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_4430 }, - { .div =2 , .val =1 , .flags =RATE_IN_4430 }, - { .div =4 , .val =2 , .flags =RATE_IN_4430 }, - { .div =8 , .val =3 , .flags =RATE_IN_4430 }, - { .div =0 }, -}; - -static const struct clksel div_iva_hs_clk_div[] = { - { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates }, - { .parent =NULL }, -}; - -static struct clk div_iva_hs_clk = { - .name ="div_iva_hs_clk" , - .parent = &dpll_core_m5x2_ck, - .clksel = div_iva_hs_clk_div, - .clksel_reg =OMAP4430_CM_BYPCLK_DPLL_IVA , - .clksel_mask =OMAP4430_CLKSEL_0_1_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk div_mpu_hs_clk = { - .name ="div_mpu_hs_clk" , - .parent = &dpll_core_m5x2_ck, - .clksel = div_iva_hs_clk_div, - .clksel_reg =OMAP4430_CM_BYPCLK_DPLL_MPU , - .clksel_mask =OMAP4430_CLKSEL_0_1_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_core_m4x2_ck = { - .name ="dpll_core_m4x2_ck" , - .parent = &dpll_core_x2_ck, - .clksel = dpll_core_m6x2_div, - .clksel_reg =OMAP4430_CM_DIV_M4_DPLL_CORE , - .clksel_mask =OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dll_clk_div_ck = { - .name ="dll_clk_div_ck" , - .parent = &dpll_core_m4x2_ck, - .ops = &clkops_null, - .fixed_div =2 , - .recalc = &omap_fixed_divisor_recalc, -}; - -static const struct clksel dpll_abe_m2_div[] = { - { .parent = &dpll_abe_ck, .rates = div31_1to31_rates }, - { .parent =NULL }, -}; - -static struct clk dpll_abe_m2_ck = { - .name ="dpll_abe_m2_ck" , - .parent = &dpll_abe_ck, - .clksel = dpll_abe_m2_div, - .clksel_reg =OMAP4430_CM_DIV_M2_DPLL_ABE , - .clksel_mask =OMAP4430_DPLL_CLKOUT_DIV_MASK , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_core_m3x2_ck = { - .name ="dpll_core_m3x2_ck" , - .parent = &dpll_core_x2_ck, - .clksel = dpll_core_m6x2_div, - .clksel_reg =OMAP4430_CM_DIV_M3_DPLL_CORE , - .clksel_mask =OMAP4430_DPLL_CLKOUTHIF_DIV_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .enable_reg =OMAP4430_CM_DIV_M3_DPLL_CORE , - .enable_bit =OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT , -}; - -static struct clk dpll_core_m7x2_ck = { - .name ="dpll_core_m7x2_ck" , - .parent = &dpll_core_x2_ck, - .clksel = dpll_core_m6x2_div, - .clksel_reg =OMAP4430_CM_DIV_M7_DPLL_CORE , - .clksel_mask =OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel iva_hsd_byp_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &div_iva_hs_clk, .rates = div_1_1_rates }, - { .parent =NULL }, -}; - -static struct clk iva_hsd_byp_clk_mux_ck = { - .name ="iva_hsd_byp_clk_mux_ck" , - .parent = &sys_clkin_ck, - .clksel = iva_hsd_byp_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_CLKSEL_DPLL_IVA , - .clksel_mask =OMAP4430_DPLL_BYP_CLKSEL_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -/* DPLL_IVA */ -static struct dpll_data dpll_iva_dd = { - .mult_div1_reg =OMAP4430_CM_CLKSEL_DPLL_IVA , - .clk_bypass = &iva_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, - .control_reg =OMAP4430_CM_CLKMODE_DPLL_IVA , - .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), - .autoidle_reg =OMAP4430_CM_AUTOIDLE_DPLL_IVA , - .idlest_reg =OMAP4430_CM_IDLEST_DPLL_IVA , - .mult_mask =OMAP4430_DPLL_MULT_MASK , - .div1_mask =OMAP4430_DPLL_DIV_MASK , - .enable_mask =OMAP4430_DPLL_EN_MASK , - .autoidle_mask =OMAP4430_AUTO_DPLL_MODE_MASK , - .idlest_mask =OMAP4430_ST_DPLL_CLK_MASK , - .max_multiplier =2047 , - .max_divider =128 , - .min_divider =1 , -}; - - -static struct clk dpll_iva_ck = { - .name ="dpll_iva_ck" , - .parent = &sys_clkin_ck, - .dpll_data = &dpll_iva_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -static struct clk dpll_iva_x2_ck = { - .name ="dpll_iva_x2_ck" , - .parent = &dpll_iva_ck, - .flags =CLOCK_CLKOUTX2 , - .ops = &clkops_null, - .recalc = &omap3_clkoutx2_recalc, -}; - -static const struct clksel dpll_iva_m4x2_div[] = { - { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates }, - { .parent =NULL }, -}; - -static struct clk dpll_iva_m4x2_ck = { - .name ="dpll_iva_m4x2_ck" , - .parent = &dpll_iva_x2_ck, - .clksel = dpll_iva_m4x2_div, - .clksel_reg =OMAP4430_CM_DIV_M4_DPLL_IVA , - .clksel_mask =OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_iva_m5x2_ck = { - .name ="dpll_iva_m5x2_ck" , - .parent = &dpll_iva_x2_ck, - .clksel = dpll_iva_m4x2_div, - .clksel_reg =OMAP4430_CM_DIV_M5_DPLL_IVA , - .clksel_mask =OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -/* DPLL_MPU */ -static struct dpll_data dpll_mpu_dd = { - .mult_div1_reg =OMAP4430_CM_CLKSEL_DPLL_MPU , - .clk_bypass = &div_mpu_hs_clk, - .clk_ref = &sys_clkin_ck, - .control_reg =OMAP4430_CM_CLKMODE_DPLL_MPU , - .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), - .autoidle_reg =OMAP4430_CM_AUTOIDLE_DPLL_MPU , - .idlest_reg =OMAP4430_CM_IDLEST_DPLL_MPU , - .mult_mask =OMAP4430_DPLL_MULT_MASK , - .div1_mask =OMAP4430_DPLL_DIV_MASK , - .enable_mask =OMAP4430_DPLL_EN_MASK , - .autoidle_mask =OMAP4430_AUTO_DPLL_MODE_MASK , - .idlest_mask =OMAP4430_ST_DPLL_CLK_MASK , - .max_multiplier =2047 , - .max_divider =128 , - .min_divider =1 , -}; - - -static struct clk dpll_mpu_ck = { - .name ="dpll_mpu_ck" , - .parent = &sys_clkin_ck, - .dpll_data = &dpll_mpu_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -static const struct clksel dpll_mpu_m2_div[] = { - { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates }, - { .parent =NULL }, -}; - -static struct clk dpll_mpu_m2_ck = { - .name ="dpll_mpu_m2_ck" , - .parent = &dpll_mpu_ck, - .clksel = dpll_mpu_m2_div, - .clksel_reg =OMAP4430_CM_DIV_M2_DPLL_MPU , - .clksel_mask =OMAP4430_DPLL_CLKOUT_DIV_MASK , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk per_hs_clk_div_ck = { - .name ="per_hs_clk_div_ck" , - .parent = &dpll_abe_m3x2_ck, - .ops = &clkops_null, - .fixed_div =2 , - .recalc = &omap_fixed_divisor_recalc, -}; - -static const struct clksel per_hsd_byp_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates }, - { .parent =NULL }, -}; - -static struct clk per_hsd_byp_clk_mux_ck = { - .name ="per_hsd_byp_clk_mux_ck" , - .parent = &sys_clkin_ck, - .clksel = per_hsd_byp_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_CLKSEL_DPLL_PER , - .clksel_mask =OMAP4430_DPLL_BYP_CLKSEL_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -/* DPLL_PER */ -static struct dpll_data dpll_per_dd = { - .mult_div1_reg =OMAP4430_CM_CLKSEL_DPLL_PER , - .clk_bypass = &per_hsd_byp_clk_mux_ck, - .clk_ref = &sys_clkin_ck, - .control_reg =OMAP4430_CM_CLKMODE_DPLL_PER , - .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), - .autoidle_reg =OMAP4430_CM_AUTOIDLE_DPLL_PER , - .idlest_reg =OMAP4430_CM_IDLEST_DPLL_PER , - .mult_mask =OMAP4430_DPLL_MULT_MASK , - .div1_mask =OMAP4430_DPLL_DIV_MASK , - .enable_mask =OMAP4430_DPLL_EN_MASK , - .autoidle_mask =OMAP4430_AUTO_DPLL_MODE_MASK , - .idlest_mask =OMAP4430_ST_DPLL_CLK_MASK , - .max_multiplier =2047 , - .max_divider =128 , - .min_divider =1 , -}; - - -static struct clk dpll_per_ck = { - .name ="dpll_per_ck" , - .parent = &sys_clkin_ck, - .dpll_data = &dpll_per_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, -}; - -static const struct clksel dpll_per_m2_div[] = { - { .parent = &dpll_per_ck, .rates = div31_1to31_rates }, - { .parent =NULL }, -}; - -static struct clk dpll_per_m2_ck = { - .name ="dpll_per_m2_ck" , - .parent = &dpll_per_ck, - .clksel = dpll_per_m2_div, - .clksel_reg =OMAP4430_CM_DIV_M2_DPLL_PER , - .clksel_mask =OMAP4430_DPLL_CLKOUT_DIV_MASK , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_per_x2_ck = { - .name ="dpll_per_x2_ck" , - .parent = &dpll_per_ck, - .clksel_reg =OMAP4430_CM_DIV_M2_DPLL_PER , - .flags =CLOCK_CLKOUTX2 , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap3_clkoutx2_recalc, -}; - -static const struct clksel dpll_per_m2x2_div[] = { - { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, - { .parent =NULL }, -}; - -static struct clk dpll_per_m2x2_ck = { - .name ="dpll_per_m2x2_ck" , - .parent = &dpll_per_x2_ck, - .clksel = dpll_per_m2x2_div, - .clksel_reg =OMAP4430_CM_DIV_M2_DPLL_PER , - .clksel_mask =OMAP4430_DPLL_CLKOUT_DIV_MASK , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_per_m3x2_ck = { - .name ="dpll_per_m3x2_ck" , - .parent = &dpll_per_x2_ck, - .clksel = dpll_per_m2x2_div, - .clksel_reg =OMAP4430_CM_DIV_M3_DPLL_PER , - .clksel_mask =OMAP4430_DPLL_CLKOUTHIF_DIV_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .enable_reg =OMAP4430_CM_DIV_M3_DPLL_PER , - .enable_bit =OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT , -}; - -static struct clk dpll_per_m4x2_ck = { - .name ="dpll_per_m4x2_ck" , - .parent = &dpll_per_x2_ck, - .clksel = dpll_per_m2x2_div, - .clksel_reg =OMAP4430_CM_DIV_M4_DPLL_PER , - .clksel_mask =OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_per_m5x2_ck = { - .name ="dpll_per_m5x2_ck" , - .parent = &dpll_per_x2_ck, - .clksel = dpll_per_m2x2_div, - .clksel_reg =OMAP4430_CM_DIV_M5_DPLL_PER , - .clksel_mask =OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_per_m6x2_ck = { - .name ="dpll_per_m6x2_ck" , - .parent = &dpll_per_x2_ck, - .clksel = dpll_per_m2x2_div, - .clksel_reg =OMAP4430_CM_DIV_M6_DPLL_PER , - .clksel_mask =OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk dpll_per_m7x2_ck = { - .name ="dpll_per_m7x2_ck" , - .parent = &dpll_per_x2_ck, - .clksel = dpll_per_m2x2_div, - .clksel_reg =OMAP4430_CM_DIV_M7_DPLL_PER , - .clksel_mask =OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk usb_hs_clk_div_ck = { - .name ="usb_hs_clk_div_ck" , - .parent = &dpll_abe_m3x2_ck, - .ops = &clkops_null, - .fixed_div =3 , - .recalc = &omap_fixed_divisor_recalc, -}; - -/* DPLL_USB */ -static struct dpll_data dpll_usb_dd = { - .mult_div1_reg =OMAP4430_CM_CLKSEL_DPLL_USB , - .clk_bypass = &usb_hs_clk_div_ck, - .flags =DPLL_J_TYPE , - .clk_ref = &sys_clkin_ck, - .control_reg =OMAP4430_CM_CLKMODE_DPLL_USB , - .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), - .autoidle_reg =OMAP4430_CM_AUTOIDLE_DPLL_USB , - .idlest_reg =OMAP4430_CM_IDLEST_DPLL_USB , - .mult_mask =OMAP4430_DPLL_MULT_USB_MASK , - .div1_mask =OMAP4430_DPLL_DIV_0_7_MASK , - .enable_mask =OMAP4430_DPLL_EN_MASK , - .autoidle_mask =OMAP4430_AUTO_DPLL_MODE_MASK , - .idlest_mask =OMAP4430_ST_DPLL_CLK_MASK , - .sddiv_mask =OMAP4430_DPLL_SD_DIV_MASK , - .max_multiplier =4095 , - .max_divider =256 , - .min_divider =1 , -}; - - -static struct clk dpll_usb_ck = { - .name ="dpll_usb_ck" , - .parent = &sys_clkin_ck, - .dpll_data = &dpll_usb_dd, - .init = &omap2_init_dpll_parent, - .ops = &clkops_omap3_noncore_dpll_ops, - .recalc = &omap3_dpll_recalc, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .clkdm_name ="l3_init_clkdm" , -}; - -static struct clk dpll_usb_clkdcoldo_ck = { - .name ="dpll_usb_clkdcoldo_ck" , - .parent = &dpll_usb_ck, - .clksel_reg =OMAP4430_CM_CLKDCOLDO_DPLL_USB , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &followparent_recalc, -}; - -static const struct clksel dpll_usb_m2_div[] = { - { .parent = &dpll_usb_ck, .rates = div31_1to31_rates }, - { .parent =NULL }, -}; - -static struct clk dpll_usb_m2_ck = { - .name ="dpll_usb_m2_ck" , - .parent = &dpll_usb_ck, - .clksel = dpll_usb_m2_div, - .clksel_reg =OMAP4430_CM_DIV_M2_DPLL_USB , - .clksel_mask =OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK , - .ops = &clkops_omap4_dpllmx_ops, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel ducati_clk_mux_sel[] = { - { .parent = &div_core_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates }, - { .parent =NULL }, -}; - -static struct clk ducati_clk_mux_ck = { - .name ="ducati_clk_mux_ck" , - .parent = &div_core_ck, - .clksel = ducati_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT , - .clksel_mask =OMAP4430_CLKSEL_0_0_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk func_12m_fclk = { - .name ="func_12m_fclk" , - .parent = &dpll_per_m2x2_ck, - .ops = &clkops_null, - .fixed_div =16 , - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk func_24m_clk = { - .name ="func_24m_clk" , - .parent = &dpll_per_m2_ck, - .ops = &clkops_null, - .fixed_div =4 , - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk func_24mc_fclk = { - .name ="func_24mc_fclk" , - .parent = &dpll_per_m2x2_ck, - .ops = &clkops_null, - .fixed_div =8 , - .recalc = &omap_fixed_divisor_recalc, -}; - -static const struct clksel_rate div2_4to8_rates[] = { - { .div =4 , .val =0 , .flags =RATE_IN_4430 }, - { .div =8 , .val =1 , .flags =RATE_IN_4430 }, - { .div =0 }, -}; - -static const struct clksel func_48m_fclk_div[] = { - { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates }, - { .parent =NULL }, -}; - -static struct clk func_48m_fclk = { - .name ="func_48m_fclk" , - .parent = &dpll_per_m2x2_ck, - .clksel = func_48m_fclk_div, - .clksel_reg =OMAP4430_CM_SCALE_FCLK , - .clksel_mask =OMAP4430_SCALE_FCLK_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk func_48mc_fclk = { - .name ="func_48mc_fclk" , - .parent = &dpll_per_m2x2_ck, - .ops = &clkops_null, - .fixed_div =4 , - .recalc = &omap_fixed_divisor_recalc, -}; - -static const struct clksel_rate div2_2to4_rates[] = { - { .div =2 , .val =0 , .flags =RATE_IN_4430 }, - { .div =4 , .val =1 , .flags =RATE_IN_4430 }, - { .div =0 }, -}; - -static const struct clksel func_64m_fclk_div[] = { - { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates }, - { .parent =NULL }, -}; - -static struct clk func_64m_fclk = { - .name ="func_64m_fclk" , - .parent = &dpll_per_m4x2_ck, - .clksel = func_64m_fclk_div, - .clksel_reg =OMAP4430_CM_SCALE_FCLK , - .clksel_mask =OMAP4430_SCALE_FCLK_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel func_96m_fclk_div[] = { - { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates }, - { .parent =NULL }, -}; - -static struct clk func_96m_fclk = { - .name ="func_96m_fclk" , - .parent = &dpll_per_m2x2_ck, - .clksel = func_96m_fclk_div, - .clksel_reg =OMAP4430_CM_SCALE_FCLK , - .clksel_mask =OMAP4430_SCALE_FCLK_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel_rate div2_1to8_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_4430 }, - { .div =8 , .val =1 , .flags =RATE_IN_4430 }, - { .div =0 }, -}; - -static const struct clksel init_60m_fclk_div[] = { - { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates }, - { .parent =NULL }, -}; - -static struct clk init_60m_fclk = { - .name ="init_60m_fclk" , - .parent = &dpll_usb_m2_ck, - .clksel = init_60m_fclk_div, - .clksel_reg =OMAP4430_CM_CLKSEL_USB_60MHZ , - .clksel_mask =OMAP4430_CLKSEL_0_0_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel l3_div_div[] = { - { .parent = &div_core_ck, .rates = div2_1to2_rates }, - { .parent =NULL }, -}; - -static struct clk l3_div_ck = { - .name ="l3_div_ck" , - .parent = &div_core_ck, - .clksel = l3_div_div, - .clksel_reg =OMAP4430_CM_CLKSEL_CORE , - .clksel_mask =OMAP4430_CLKSEL_L3_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel l4_div_div[] = { - { .parent = &l3_div_ck, .rates = div2_1to2_rates }, - { .parent =NULL }, -}; - -static struct clk l4_div_ck = { - .name ="l4_div_ck" , - .parent = &l3_div_ck, - .clksel = l4_div_div, - .clksel_reg =OMAP4430_CM_CLKSEL_CORE , - .clksel_mask =OMAP4430_CLKSEL_L4_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk lp_clk_div_ck = { - .name ="lp_clk_div_ck" , - .parent = &dpll_abe_m2x2_ck, - .ops = &clkops_null, - .fixed_div =16 , - .recalc = &omap_fixed_divisor_recalc, -}; - -static const struct clksel l4_wkup_clk_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &lp_clk_div_ck, .rates = div_1_1_rates }, - { .parent =NULL }, -}; - -static struct clk l4_wkup_clk_mux_ck = { - .name ="l4_wkup_clk_mux_ck" , - .parent = &sys_clkin_ck, - .clksel = l4_wkup_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_L4_WKUP_CLKSEL , - .clksel_mask =OMAP4430_CLKSEL_0_0_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate div2_2to1_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_4430 }, - { .div =2 , .val =0 , .flags =RATE_IN_4430 }, - { .div =0 }, -}; - -static const struct clksel ocp_abe_iclk_div[] = { - { .parent = &aess_fclk, .rates = div2_2to1_rates }, - { .parent =NULL }, -}; - -static struct clk mpu_periphclk = { - .name ="mpu_periphclk" , - .parent = &dpll_mpu_ck, - .ops = &clkops_null, - .fixed_div =2 , - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk ocp_abe_iclk = { - .name ="ocp_abe_iclk" , - .parent = &aess_fclk, - .clksel = ocp_abe_iclk_div, - .clksel_reg =OMAP4430_CM1_ABE_AESS_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_AESS_FCLK_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk per_abe_24m_fclk = { - .name ="per_abe_24m_fclk" , - .parent = &dpll_abe_m2_ck, - .ops = &clkops_null, - .fixed_div =4 , - .recalc = &omap_fixed_divisor_recalc, -}; - -static const struct clksel per_abe_nc_fclk_div[] = { - { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates }, - { .parent =NULL }, -}; - -static struct clk per_abe_nc_fclk = { - .name ="per_abe_nc_fclk" , - .parent = &dpll_abe_m2_ck, - .clksel = per_abe_nc_fclk_div, - .clksel_reg =OMAP4430_CM_SCALE_FCLK , - .clksel_mask =OMAP4430_SCALE_FCLK_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel pmd_stm_clock_mux_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, - { .parent = &tie_low_clock_ck, .rates = div_1_2_rates }, - { .parent =NULL }, -}; - -static struct clk pmd_stm_clock_mux_ck = { - .name ="pmd_stm_clock_mux_ck" , - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static struct clk pmd_trace_clk_mux_ck = { - .name ="pmd_trace_clk_mux_ck" , - .parent = &sys_clkin_ck, - .ops = &clkops_null, - .recalc = &followparent_recalc, -}; - -static const struct clksel syc_clk_div_div[] = { - { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, - { .parent =NULL }, -}; - -static struct clk syc_clk_div_ck = { - .name ="syc_clk_div_ck" , - .parent = &sys_clkin_ck, - .clksel = syc_clk_div_div, - .clksel_reg =OMAP4430_CM_ABE_DSS_SYS_CLKSEL , - .clksel_mask =OMAP4430_CLKSEL_0_0_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -/* Leaf clocks controlled by modules */ - -static struct clk aes1_fck = { - .name ="aes1_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4SEC_AES1_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_secure_clkdm" , - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk aes2_fck = { - .name ="aes2_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4SEC_AES2_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_secure_clkdm" , - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk aess_fck = { - .name ="aess_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM1_ABE_AESS_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="abe_clkdm" , - .parent = &aess_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk bandgap_fclk = { - .name ="bandgap_fclk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_WKUP_BANDGAP_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT , - .clkdm_name ="l4_wkup_clkdm" , - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk des3des_fck = { - .name ="des3des_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4SEC_DES3DES_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_secure_clkdm" , - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static const struct clksel dmic_sync_mux_sel[] = { - { .parent = &abe_24m_fclk, .rates = div_1_0_rates }, - { .parent = &syc_clk_div_ck, .rates = div_1_1_rates }, - { .parent = &func_24m_clk, .rates = div_1_2_rates }, - { .parent =NULL }, -}; - -static struct clk dmic_sync_mux_ck = { - .name ="dmic_sync_mux_ck" , - .parent = &abe_24m_fclk, - .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM1_ABE_DMIC_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel func_dmic_abe_gfclk_sel[] = { - { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent =NULL }, -}; - -/* Merged func_dmic_abe_gfclk into dmic */ -static struct clk dmic_fck = { - .name ="dmic_fck" , - .parent = &dmic_sync_mux_ck, - .clksel = func_dmic_abe_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM1_ABE_DMIC_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_SOURCE_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM1_ABE_DMIC_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="abe_clkdm" , -}; - -static struct clk dsp_fck = { - .name ="dsp_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_TESLA_TESLA_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .clkdm_name ="tesla_clkdm" , - .parent = &dpll_iva_m4x2_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dss_sys_clk = { - .name ="dss_sys_clk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_DSS_DSS_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT , - .clkdm_name ="l3_dss_clkdm" , - .parent = &syc_clk_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dss_tv_clk = { - .name ="dss_tv_clk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_DSS_DSS_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_TV_CLK_SHIFT , - .clkdm_name ="l3_dss_clkdm" , - .parent = &extalt_clkin_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dss_dss_clk = { - .name ="dss_dss_clk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_DSS_DSS_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_DSSCLK_SHIFT , - .clkdm_name ="l3_dss_clkdm" , - .parent = &dpll_per_m5x2_ck, - .recalc = &followparent_recalc, -}; - -static const struct clksel_rate div3_8to32_rates[] = { - { .div =8 , .val =0 , .flags =RATE_IN_4460 }, - { .div =16 , .val =1 , .flags =RATE_IN_4460 }, - { .div =32 , .val =2 , .flags =RATE_IN_4460 }, - { .div =0 }, -}; - -static const struct clksel div_ts_div[] = { - { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates }, - { .parent =NULL }, -}; - -static struct clk div_ts_ck = { - .name ="div_ts_ck" , - .parent = &l4_wkup_clk_mux_ck, - .clksel = div_ts_div, - .clksel_reg =OMAP4430_CM_WKUP_BANDGAP_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_24_25_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk bandgap_ts_fclk = { - .name ="bandgap_ts_fclk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_WKUP_BANDGAP_CLKCTRL , - .enable_bit =OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT , - .clkdm_name ="l4_wkup_clkdm" , - .parent = &div_ts_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dss_48mhz_clk = { - .name ="dss_48mhz_clk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_DSS_DSS_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT , - .clkdm_name ="l3_dss_clkdm" , - .parent = &func_48mc_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk dss_fck = { - .name ="dss_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_DSS_DSS_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l3_dss_clkdm" , - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk efuse_ctrl_cust_fck = { - .name ="efuse_ctrl_cust_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_cefuse_clkdm" , - .parent = &sys_clkin_ck, - .recalc = &followparent_recalc, -}; - -static struct clk emif1_fck = { - .name ="emif1_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .flags =ENABLE_ON_INIT , - .clkdm_name ="l3_emif_clkdm" , - .parent = &ddrphy_ck, - .recalc = &followparent_recalc, -}; - -static struct clk emif2_fck = { - .name ="emif2_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .flags =ENABLE_ON_INIT , - .clkdm_name ="l3_emif_clkdm" , - .parent = &ddrphy_ck, - .recalc = &followparent_recalc, -}; - -static const struct clksel fdif_fclk_div[] = { - { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates }, - { .parent =NULL }, -}; - -/* Merged fdif_fclk into fdif */ -static struct clk fdif_fck = { - .name ="fdif_fck" , - .parent = &dpll_per_m4x2_ck, - .clksel = fdif_fclk_div, - .clksel_reg =OMAP4430_CM_CAM_FDIF_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_FCLK_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .enable_reg =OMAP4430_CM_CAM_FDIF_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="iss_clkdm" , -}; - -static struct clk fpka_fck = { - .name ="fpka_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_secure_clkdm" , - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio1_dbclk = { - .name ="gpio1_dbclk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_WKUP_GPIO1_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_DBCLK_SHIFT , - .clkdm_name ="l4_wkup_clkdm" , - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio1_ick = { - .name ="gpio1_ick" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_WKUP_GPIO1_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .clkdm_name ="l4_wkup_clkdm" , - .parent = &l4_wkup_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio2_dbclk = { - .name ="gpio2_dbclk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_GPIO2_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_DBCLK_SHIFT , - .clkdm_name ="l4_per_clkdm" , - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio2_ick = { - .name ="gpio2_ick" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_GPIO2_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio3_dbclk = { - .name ="gpio3_dbclk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_GPIO3_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_DBCLK_SHIFT , - .clkdm_name ="l4_per_clkdm" , - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio3_ick = { - .name ="gpio3_ick" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_GPIO3_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio4_dbclk = { - .name ="gpio4_dbclk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_GPIO4_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_DBCLK_SHIFT , - .clkdm_name ="l4_per_clkdm" , - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio4_ick = { - .name ="gpio4_ick" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_GPIO4_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio5_dbclk = { - .name ="gpio5_dbclk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_GPIO5_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_DBCLK_SHIFT , - .clkdm_name ="l4_per_clkdm" , - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio5_ick = { - .name ="gpio5_ick" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_GPIO5_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio6_dbclk = { - .name ="gpio6_dbclk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_GPIO6_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_DBCLK_SHIFT , - .clkdm_name ="l4_per_clkdm" , - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio6_ick = { - .name ="gpio6_ick" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_GPIO6_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gpmc_ick = { - .name ="gpmc_ick" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3_2_GPMC_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .flags =ENABLE_ON_INIT , - .clkdm_name ="l3_2_clkdm" , - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static const struct clksel sgx_clk_mux_sel[] = { - { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, - { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, - { .parent =NULL }, -}; - -/* Merged sgx_clk_mux into gpu */ -static struct clk gpu_fck = { - .name ="gpu_fck" , - .parent = &dpll_core_m7x2_ck, - .clksel = sgx_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_GFX_GFX_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_SGX_FCLK_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM_GFX_GFX_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l3_gfx_clkdm" , -}; - -static struct clk hdq1w_fck = { - .name ="hdq1w_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_HDQ1W_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &func_12m_fclk, - .recalc = &followparent_recalc, -}; - -static const struct clksel hsi_fclk_div[] = { - { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, - { .parent =NULL }, -}; - -/* Merged hsi_fclk into hsi */ -static struct clk hsi_fck = { - .name ="hsi_fck" , - .parent = &dpll_per_m2x2_ck, - .clksel = hsi_fclk_div, - .clksel_reg =OMAP4430_CM_L3INIT_HSI_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_24_25_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, - .enable_reg =OMAP4430_CM_L3INIT_HSI_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .clkdm_name ="l3_init_clkdm" , -}; - -static struct clk i2c1_fck = { - .name ="i2c1_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_I2C1_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk i2c2_fck = { - .name ="i2c2_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_I2C2_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk i2c3_fck = { - .name ="i2c3_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_I2C3_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk i2c4_fck = { - .name ="i2c4_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_I2C4_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk ipu_fck = { - .name ="ipu_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_DUCATI_DUCATI_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .clkdm_name ="ducati_clkdm" , - .parent = &ducati_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -static struct clk iss_ctrlclk = { - .name ="iss_ctrlclk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_CAM_ISS_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT , - .clkdm_name ="iss_clkdm" , - .parent = &func_96m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk iss_fck = { - .name ="iss_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_CAM_ISS_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="iss_clkdm" , - .parent = &ducati_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -static struct clk iva_fck = { - .name ="iva_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_IVAHD_IVAHD_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .clkdm_name ="ivahd_clkdm" , - .parent = &dpll_iva_m5x2_ck, - .recalc = &followparent_recalc, -}; - -static struct clk kbd_fck = { - .name ="kbd_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_wkup_clkdm" , - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk l3_instr_ick = { - .name ="l3_instr_ick" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .flags =ENABLE_ON_INIT , - .clkdm_name ="l3_instr_clkdm" , - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk l3_main_3_ick = { - .name ="l3_main_3_ick" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INSTR_L3_3_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .flags =ENABLE_ON_INIT , - .clkdm_name ="l3_instr_clkdm" , - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk mcasp_sync_mux_ck = { - .name ="mcasp_sync_mux_ck" , - .parent = &abe_24m_fclk, - .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM1_ABE_MCASP_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel func_mcasp_abe_gfclk_sel[] = { - { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent =NULL }, -}; - -/* Merged func_mcasp_abe_gfclk into mcasp */ -static struct clk mcasp_fck = { - .name ="mcasp_fck" , - .parent = &mcasp_sync_mux_ck, - .clksel = func_mcasp_abe_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM1_ABE_MCASP_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_SOURCE_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM1_ABE_MCASP_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="abe_clkdm" , -}; - -static struct clk mcbsp1_sync_mux_ck = { - .name ="mcbsp1_sync_mux_ck" , - .parent = &abe_24m_fclk, - .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM1_ABE_MCBSP1_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel func_mcbsp1_gfclk_sel[] = { - { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent =NULL }, -}; - -/* Merged func_mcbsp1_gfclk into mcbsp1 */ -static struct clk mcbsp1_fck = { - .name ="mcbsp1_fck" , - .parent = &mcbsp1_sync_mux_ck, - .clksel = func_mcbsp1_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM1_ABE_MCBSP1_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_SOURCE_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM1_ABE_MCBSP1_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="abe_clkdm" , -}; - -static struct clk mcbsp2_sync_mux_ck = { - .name ="mcbsp2_sync_mux_ck" , - .parent = &abe_24m_fclk, - .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM1_ABE_MCBSP2_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel func_mcbsp2_gfclk_sel[] = { - { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent =NULL }, -}; - -/* Merged func_mcbsp2_gfclk into mcbsp2 */ -static struct clk mcbsp2_fck = { - .name ="mcbsp2_fck" , - .parent = &mcbsp2_sync_mux_ck, - .clksel = func_mcbsp2_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM1_ABE_MCBSP2_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_SOURCE_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM1_ABE_MCBSP2_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="abe_clkdm" , -}; - -static struct clk mcbsp3_sync_mux_ck = { - .name ="mcbsp3_sync_mux_ck" , - .parent = &abe_24m_fclk, - .clksel = dmic_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM1_ABE_MCBSP3_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel func_mcbsp3_gfclk_sel[] = { - { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent = &slimbus_clk, .rates = div_1_2_rates }, - { .parent =NULL }, -}; - -/* Merged func_mcbsp3_gfclk into mcbsp3 */ -static struct clk mcbsp3_fck = { - .name ="mcbsp3_fck" , - .parent = &mcbsp3_sync_mux_ck, - .clksel = func_mcbsp3_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM1_ABE_MCBSP3_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_SOURCE_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM1_ABE_MCBSP3_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="abe_clkdm" , -}; - -static const struct clksel mcbsp4_sync_mux_sel[] = { - { .parent = &func_96m_fclk, .rates = div_1_0_rates }, - { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates }, - { .parent =NULL }, -}; - -static struct clk mcbsp4_sync_mux_ck = { - .name ="mcbsp4_sync_mux_ck" , - .parent = &func_96m_fclk, - .clksel = mcbsp4_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_L4PER_MCBSP4_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel per_mcbsp4_gfclk_sel[] = { - { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates }, - { .parent = &pad_clks_ck, .rates = div_1_1_rates }, - { .parent =NULL }, -}; - -/* Merged per_mcbsp4_gfclk into mcbsp4 */ -static struct clk mcbsp4_fck = { - .name ="mcbsp4_fck" , - .parent = &mcbsp4_sync_mux_ck, - .clksel = per_mcbsp4_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_L4PER_MCBSP4_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_SOURCE_24_24_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM_L4PER_MCBSP4_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , -}; - -static struct clk mcpdm_fck = { - .name ="mcpdm_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM1_ABE_PDM_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="abe_clkdm" , - .parent = &pad_clks_ck, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi1_fck = { - .name ="mcspi1_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_MCSPI1_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi2_fck = { - .name ="mcspi2_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_MCSPI2_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi3_fck = { - .name ="mcspi3_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_MCSPI3_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi4_fck = { - .name ="mcspi4_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_MCSPI4_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static const struct clksel hsmmc1_fclk_sel[] = { - { .parent = &func_64m_fclk, .rates = div_1_0_rates }, - { .parent = &func_96m_fclk, .rates = div_1_1_rates }, - { .parent =NULL }, -}; - -/* Merged hsmmc1_fclk into mmc1 */ -static struct clk mmc1_fck = { - .name ="mmc1_fck" , - .parent = &func_64m_fclk, - .clksel = hsmmc1_fclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_L3INIT_MMC1_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM_L3INIT_MMC1_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l3_init_clkdm" , -}; - -/* Merged hsmmc2_fclk into mmc2 */ -static struct clk mmc2_fck = { - .name ="mmc2_fck" , - .parent = &func_64m_fclk, - .clksel = hsmmc1_fclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_L3INIT_MMC2_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM_L3INIT_MMC2_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l3_init_clkdm" , -}; - -static struct clk mmc3_fck = { - .name ="mmc3_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_MMCSD3_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk mmc4_fck = { - .name ="mmc4_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_MMCSD4_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk mmc5_fck = { - .name ="mmc5_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_MMCSD5_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk ocp2scp_usb_phy_phy_48m = { - .name ="ocp2scp_usb_phy_phy_48m" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_PHY_48M_SHIFT , - .clkdm_name ="l3_init_clkdm" , - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk ocp2scp_usb_phy_ick = { - .name ="ocp2scp_usb_phy_ick" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .clkdm_name ="l3_init_clkdm" , - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk ocp_wp_noc_ick = { - .name ="ocp_wp_noc_ick" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .flags =ENABLE_ON_INIT , - .clkdm_name ="l3_instr_clkdm" , - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk rng_ick = { - .name ="rng_ick" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4SEC_RNG_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .clkdm_name ="l4_secure_clkdm" , - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk sha2md5_fck = { - .name ="sha2md5_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_secure_clkdm" , - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk sl2if_ick = { - .name ="sl2if_ick" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_IVAHD_SL2_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .clkdm_name ="ivahd_clkdm" , - .parent = &dpll_iva_m5x2_ck, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus1_fclk_1 = { - .name ="slimbus1_fclk_1" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_FCLK1_SHIFT , - .clkdm_name ="abe_clkdm" , - .parent = &func_24m_clk, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus1_fclk_0 = { - .name ="slimbus1_fclk_0" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_FCLK0_SHIFT , - .clkdm_name ="abe_clkdm" , - .parent = &abe_24m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus1_fclk_2 = { - .name ="slimbus1_fclk_2" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_FCLK2_SHIFT , - .clkdm_name ="abe_clkdm" , - .parent = &pad_clks_ck, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus1_slimbus_clk = { - .name ="slimbus1_slimbus_clk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT , - .clkdm_name ="abe_clkdm" , - .parent = &slimbus_clk, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus1_fck = { - .name ="slimbus1_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="abe_clkdm" , - .parent = &ocp_abe_iclk, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus2_fclk_1 = { - .name ="slimbus2_fclk_1" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT , - .clkdm_name ="l4_per_clkdm" , - .parent = &per_abe_24m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus2_fclk_0 = { - .name ="slimbus2_fclk_0" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT , - .clkdm_name ="l4_per_clkdm" , - .parent = &func_24mc_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus2_slimbus_clk = { - .name ="slimbus2_slimbus_clk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT , - .clkdm_name ="l4_per_clkdm" , - .parent = &pad_slimbus_core_clks_ck, - .recalc = &followparent_recalc, -}; - -static struct clk slimbus2_fck = { - .name ="slimbus2_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk smartreflex_core_fck = { - .name ="smartreflex_core_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_ALWON_SR_CORE_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_ao_clkdm" , - .parent = &l4_wkup_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -static struct clk smartreflex_iva_fck = { - .name ="smartreflex_iva_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_ALWON_SR_IVA_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_ao_clkdm" , - .parent = &l4_wkup_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -static struct clk smartreflex_mpu_fck = { - .name ="smartreflex_mpu_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_ALWON_SR_MPU_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_ao_clkdm" , - .parent = &l4_wkup_clk_mux_ck, - .recalc = &followparent_recalc, -}; - -/* Merged dmt1_clk_mux into timer1 */ -static struct clk timer1_fck = { - .name ="timer1_fck" , - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_WKUP_TIMER1_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM_WKUP_TIMER1_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_wkup_clkdm" , -}; - -/* Merged cm2_dm10_mux into timer10 */ -static struct clk timer10_fck = { - .name ="timer10_fck" , - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , -}; - -/* Merged cm2_dm11_mux into timer11 */ -static struct clk timer11_fck = { - .name ="timer11_fck" , - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , -}; - -/* Merged cm2_dm2_mux into timer2 */ -static struct clk timer2_fck = { - .name ="timer2_fck" , - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , -}; - -/* Merged cm2_dm3_mux into timer3 */ -static struct clk timer3_fck = { - .name ="timer3_fck" , - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , -}; - -/* Merged cm2_dm4_mux into timer4 */ -static struct clk timer4_fck = { - .name ="timer4_fck" , - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , -}; - -static const struct clksel timer5_sync_mux_sel[] = { - { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, - { .parent = &sys_32k_ck, .rates = div_1_1_rates }, - { .parent =NULL }, -}; - -/* Merged timer5_sync_mux into timer5 */ -static struct clk timer5_fck = { - .name ="timer5_fck" , - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM1_ABE_TIMER5_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM1_ABE_TIMER5_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="abe_clkdm" , -}; - -/* Merged timer6_sync_mux into timer6 */ -static struct clk timer6_fck = { - .name ="timer6_fck" , - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM1_ABE_TIMER6_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM1_ABE_TIMER6_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="abe_clkdm" , -}; - -/* Merged timer7_sync_mux into timer7 */ -static struct clk timer7_fck = { - .name ="timer7_fck" , - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM1_ABE_TIMER7_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM1_ABE_TIMER7_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="abe_clkdm" , -}; - -/* Merged timer8_sync_mux into timer8 */ -static struct clk timer8_fck = { - .name ="timer8_fck" , - .parent = &syc_clk_div_ck, - .clksel = timer5_sync_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM1_ABE_TIMER8_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM1_ABE_TIMER8_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="abe_clkdm" , -}; - -/* Merged cm2_dm9_mux into timer9 */ -static struct clk timer9_fck = { - .name ="timer9_fck" , - .parent = &sys_clkin_ck, - .clksel = abe_dpll_bypass_clk_mux_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_MASK , - .ops = &clkops_omap2_dflt, - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , -}; - -static struct clk uart1_fck = { - .name ="uart1_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_UART1_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk uart2_fck = { - .name ="uart2_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_UART2_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk uart3_fck = { - .name ="uart3_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_UART3_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk uart4_fck = { - .name ="uart4_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L4PER_UART4_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_per_clkdm" , - .parent = &func_48m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_fs_fck = { - .name ="usb_host_fs_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l3_init_clkdm" , - .parent = &func_48mc_fclk, - .recalc = &followparent_recalc, -}; - -static const struct clksel utmi_p1_gfclk_sel[] = { - { .parent = &init_60m_fclk, .rates = div_1_0_rates }, - { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, - { .parent =NULL }, -}; - -static struct clk utmi_p1_gfclk = { - .name ="utmi_p1_gfclk" , - .parent = &init_60m_fclk, - .clksel = utmi_p1_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_UTMI_P1_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk usb_host_hs_utmi_p1_clk = { - .name ="usb_host_hs_utmi_p1_clk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT , - .clkdm_name ="l3_init_clkdm" , - .parent = &utmi_p1_gfclk, - .recalc = &followparent_recalc, -}; - -static const struct clksel utmi_p2_gfclk_sel[] = { - { .parent = &init_60m_fclk, .rates = div_1_0_rates }, - { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, - { .parent =NULL }, -}; - -static struct clk utmi_p2_gfclk = { - .name ="utmi_p2_gfclk" , - .parent = &init_60m_fclk, - .clksel = utmi_p2_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_UTMI_P2_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk usb_host_hs_utmi_p2_clk = { - .name ="usb_host_hs_utmi_p2_clk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT , - .clkdm_name ="l3_init_clkdm" , - .parent = &utmi_p2_gfclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_utmi_p3_clk = { - .name ="usb_host_hs_utmi_p3_clk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT , - .clkdm_name ="l3_init_clkdm" , - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_hsic480m_p1_clk = { - .name ="usb_host_hs_hsic480m_p1_clk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT , - .clkdm_name ="l3_init_clkdm" , - .parent = &dpll_usb_m2_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_hsic60m_p1_clk = { - .name ="usb_host_hs_hsic60m_p1_clk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT , - .clkdm_name ="l3_init_clkdm" , - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_hsic60m_p2_clk = { - .name ="usb_host_hs_hsic60m_p2_clk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT , - .clkdm_name ="l3_init_clkdm" , - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_hsic480m_p2_clk = { - .name ="usb_host_hs_hsic480m_p2_clk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT , - .clkdm_name ="l3_init_clkdm" , - .parent = &dpll_usb_m2_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_func48mclk = { - .name ="usb_host_hs_func48mclk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT , - .clkdm_name ="l3_init_clkdm" , - .parent = &func_48mc_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_host_hs_fck = { - .name ="usb_host_hs_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l3_init_clkdm" , - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static const struct clksel otg_60m_gfclk_sel[] = { - { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates }, - { .parent = &xclk60motg_ck, .rates = div_1_1_rates }, - { .parent =NULL }, -}; - -static struct clk otg_60m_gfclk = { - .name ="otg_60m_gfclk" , - .parent = &utmi_phy_clkout_ck, - .clksel = otg_60m_gfclk_sel, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_60M_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk usb_otg_hs_xclk = { - .name ="usb_otg_hs_xclk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_XCLK_SHIFT , - .clkdm_name ="l3_init_clkdm" , - .parent = &otg_60m_gfclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_otg_hs_ick = { - .name ="usb_otg_hs_ick" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .clkdm_name ="l3_init_clkdm" , - .parent = &l3_div_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usb_phy_cm_clk32k = { - .name ="usb_phy_cm_clk32k" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_ALWON_USBPHY_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_CLK32K_SHIFT , - .clkdm_name ="l4_ao_clkdm" , - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usb_tll_hs_usb_ch2_clk = { - .name ="usb_tll_hs_usb_ch2_clk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT , - .clkdm_name ="l3_init_clkdm" , - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_tll_hs_usb_ch0_clk = { - .name ="usb_tll_hs_usb_ch0_clk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT , - .clkdm_name ="l3_init_clkdm" , - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_tll_hs_usb_ch1_clk = { - .name ="usb_tll_hs_usb_ch1_clk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT , - .clkdm_name ="l3_init_clkdm" , - .parent = &init_60m_fclk, - .recalc = &followparent_recalc, -}; - -static struct clk usb_tll_hs_ick = { - .name ="usb_tll_hs_ick" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .clkdm_name ="l3_init_clkdm" , - .parent = &l4_div_ck, - .recalc = &followparent_recalc, -}; - -static const struct clksel_rate div2_14to18_rates[] = { - { .div =14 , .val =0 , .flags =RATE_IN_4430 }, - { .div =18 , .val =1 , .flags =RATE_IN_4430 }, - { .div =0 }, -}; - -static const struct clksel usim_fclk_div[] = { - { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates }, - { .parent =NULL }, -}; - -static struct clk usim_ck = { - .name ="usim_ck" , - .parent = &dpll_per_m4x2_ck, - .clksel = usim_fclk_div, - .clksel_reg =OMAP4430_CM_WKUP_USIM_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_DIV_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk usim_fclk = { - .name ="usim_fclk" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_WKUP_USIM_CLKCTRL , - .enable_bit =OMAP4430_OPTFCLKEN_FCLK_SHIFT , - .clkdm_name ="l4_wkup_clkdm" , - .parent = &usim_ck, - .recalc = &followparent_recalc, -}; - -static struct clk usim_fck = { - .name ="usim_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_WKUP_USIM_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_HWCTRL , - .clkdm_name ="l4_wkup_clkdm" , - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk wd_timer2_fck = { - .name ="wd_timer2_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM_WKUP_WDT2_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="l4_wkup_clkdm" , - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -static struct clk wd_timer3_fck = { - .name ="wd_timer3_fck" , - .ops = &clkops_omap2_dflt, - .enable_reg =OMAP4430_CM1_ABE_WDT3_CLKCTRL , - .enable_bit =OMAP4430_MODULEMODE_SWCTRL , - .clkdm_name ="abe_clkdm" , - .parent = &sys_32k_ck, - .recalc = &followparent_recalc, -}; - -/* Remaining optional clocks */ -static const struct clksel stm_clk_div_div[] = { - { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, - { .parent =NULL }, -}; - -static struct clk stm_clk_div_ck = { - .name ="stm_clk_div_ck" , - .parent = &pmd_stm_clock_mux_ck, - .clksel = stm_clk_div_div, - .clksel_reg =OMAP4430_CM_EMU_DEBUGSS_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_PMD_STM_CLK_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static const struct clksel trace_clk_div_div[] = { - { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, - { .parent =NULL }, -}; - -static struct clk trace_clk_div_ck = { - .name ="trace_clk_div_ck" , - .parent = &pmd_trace_clk_mux_ck, - .clksel = trace_clk_div_div, - .clksel_reg =OMAP4430_CM_EMU_DEBUGSS_CLKCTRL , - .clksel_mask =OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -/* SCRM aux clk nodes */ - -static const struct clksel auxclk_src_sel[] = { - { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, - { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, - { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, - { .parent =NULL }, -}; - -static const struct clksel_rate div16_1to16_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_4430 }, - { .div =2 , .val =1 , .flags =RATE_IN_4430 }, - { .div =3 , .val =2 , .flags =RATE_IN_4430 }, - { .div =4 , .val =3 , .flags =RATE_IN_4430 }, - { .div =5 , .val =4 , .flags =RATE_IN_4430 }, - { .div =6 , .val =5 , .flags =RATE_IN_4430 }, - { .div =7 , .val =6 , .flags =RATE_IN_4430 }, - { .div =8 , .val =7 , .flags =RATE_IN_4430 }, - { .div =9 , .val =8 , .flags =RATE_IN_4430 }, - { .div =10 , .val =9 , .flags =RATE_IN_4430 }, - { .div =11 , .val =10 , .flags =RATE_IN_4430 }, - { .div =12 , .val =11 , .flags =RATE_IN_4430 }, - { .div =13 , .val =12 , .flags =RATE_IN_4430 }, - { .div =14 , .val =13 , .flags =RATE_IN_4430 }, - { .div =15 , .val =14 , .flags =RATE_IN_4430 }, - { .div =16 , .val =15 , .flags =RATE_IN_4430 }, - { .div =0 }, -}; - -static struct clk auxclk0_src_ck = { - .name ="auxclk0_src_ck" , - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, - .clksel = auxclk_src_sel, - .clksel_reg =OMAP4_SCRM_AUXCLK0 , - .clksel_mask =OMAP4_SRCSELECT_MASK , - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4_SCRM_AUXCLK0 , - .enable_bit =OMAP4_ENABLE_SHIFT , -}; - -static const struct clksel auxclk0_sel[] = { - { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates }, - { .parent =NULL }, -}; - -static struct clk auxclk0_ck = { - .name ="auxclk0_ck" , - .parent = &auxclk0_src_ck, - .clksel = auxclk0_sel, - .clksel_reg =OMAP4_SCRM_AUXCLK0 , - .clksel_mask =OMAP4_CLKDIV_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk auxclk1_src_ck = { - .name ="auxclk1_src_ck" , - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, - .clksel = auxclk_src_sel, - .clksel_reg =OMAP4_SCRM_AUXCLK1 , - .clksel_mask =OMAP4_SRCSELECT_MASK , - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4_SCRM_AUXCLK1 , - .enable_bit =OMAP4_ENABLE_SHIFT , -}; - -static const struct clksel auxclk1_sel[] = { - { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates }, - { .parent =NULL }, -}; - -static struct clk auxclk1_ck = { - .name ="auxclk1_ck" , - .parent = &auxclk1_src_ck, - .clksel = auxclk1_sel, - .clksel_reg =OMAP4_SCRM_AUXCLK1 , - .clksel_mask =OMAP4_CLKDIV_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk auxclk2_src_ck = { - .name ="auxclk2_src_ck" , - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, - .clksel = auxclk_src_sel, - .clksel_reg =OMAP4_SCRM_AUXCLK2 , - .clksel_mask =OMAP4_SRCSELECT_MASK , - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4_SCRM_AUXCLK2 , - .enable_bit =OMAP4_ENABLE_SHIFT , -}; - -static const struct clksel auxclk2_sel[] = { - { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates }, - { .parent =NULL }, -}; - -static struct clk auxclk2_ck = { - .name ="auxclk2_ck" , - .parent = &auxclk2_src_ck, - .clksel = auxclk2_sel, - .clksel_reg =OMAP4_SCRM_AUXCLK2 , - .clksel_mask =OMAP4_CLKDIV_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk auxclk3_src_ck = { - .name ="auxclk3_src_ck" , - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, - .clksel = auxclk_src_sel, - .clksel_reg =OMAP4_SCRM_AUXCLK3 , - .clksel_mask =OMAP4_SRCSELECT_MASK , - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4_SCRM_AUXCLK3 , - .enable_bit =OMAP4_ENABLE_SHIFT , -}; - -static const struct clksel auxclk3_sel[] = { - { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates }, - { .parent =NULL }, -}; - -static struct clk auxclk3_ck = { - .name ="auxclk3_ck" , - .parent = &auxclk3_src_ck, - .clksel = auxclk3_sel, - .clksel_reg =OMAP4_SCRM_AUXCLK3 , - .clksel_mask =OMAP4_CLKDIV_MASK , - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate, -}; - -static struct clk auxclk4_src_ck = { - .name ="auxclk4_src_ck" , - .parent = &sys_clkin_ck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_omap2_dflt, - .clksel = auxclk_src_sel, - .clksel_reg =OMAP4_SCRM_AUXCLK4 , - .clksel_mask =OMAP4_SRCSELECT_MASK , - .recalc = &omap2_clksel_recalc, - .enable_reg =OMAP4_SCRM_AUXCLK4 , - .enable_bit =OMAP4_ENABLE_SHIFT , -}; - -static const struct clksel auxclk4_sel[] = { - { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates }, - { .parent =NULL },
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1.7.1
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PATCH 28/29 ARM: omap3: clk: Delete old OMAP clock data
In reply to Rajendra NayakNow that we have switched to using new common clk
data for OMAP3, delete the old one.
Signed-off-by Rajendra Nayak <[email protected]>
--- arch/arm/mach-omap2/clock3xxx_data.c | 3601 ---------------------------------- 1 files changed, 0 insertions(+), 3601 deletions(-) delete mode 100644 arch/arm/mach-omap2/clock3xxx_data.c
arch/arm/mach-omap2/clock3xxx_data.c deleted +0 -3601
@@ -1,3601 +0,0 @@ -/* -* OMAP3 clock data -* -* Copyright (C) 2007-2010, 2012 Texas Instruments, Inc. -* Copyright (C) 2007-2011 Nokia Corporation -* -* Written by Paul Walmsley -* With many device clock fixes by Kevin Hilman and Jouni H??gander -* DPLL bypass clock support added by Roman Tereshonkov -* -*/ - -/* -* Virtual clocks are introduced as convenient tools. -* They are sources for other clocks and not supposed -* to be requested from drivers directly. -*/ - -#include <linux/kernel.h> -#include <linux/clk.h> -#include <linux/list.h> -#include <linux/io.h> - -#include <plat/hardware.h> -#include <plat/clkdev_omap.h> - -#include "iomap.h" -#include "clock.h" -#include "clock3xxx.h" -#include "clock34xx.h" -#include "clock36xx.h" -#include "clock3517.h" -#include "cm2xxx_3xxx.h" -#include "cm-regbits-34xx.h" -#include "prm2xxx_3xxx.h" -#include "prm-regbits-34xx.h" -#include "control.h" - -/* -* clocks -*/ - -#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR - -/* Maximum DPLL multiplier, divider values for OMAP3 */ -#define OMAP3_MAX_DPLL_MULT 2047 -#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095 -#define OMAP3_MAX_DPLL_DIV 128 - -/* -* DPLL1 supplies clock to the MPU. -* DPLL2 supplies clock to the IVA2. -* DPLL3 supplies CORE domain clocks. -* DPLL4 supplies peripheral clocks. -* DPLL5 supplies other peripheral clocks (USBHOST, USIM). -*/ - -/* Forward declarations for DPLL bypass clocks */ -static struct clk dpll1_fck; -static struct clk dpll2_fck; - -/* PRM CLOCKS */ - -/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ -static struct clk omap_32k_fck = { - .name ="omap_32k_fck" , - .ops = &clkops_null, - .rate =32768 , -}; - -static struct clk secure_32k_fck = { - .name ="secure_32k_fck" , - .ops = &clkops_null, - .rate =32768 , -}; - -/* Virtual source clocks for osc_sys_ck */ -static struct clk virt_12m_ck = { - .name ="virt_12m_ck" , - .ops = &clkops_null, - .rate =12000000 , -}; - -static struct clk virt_13m_ck = { - .name ="virt_13m_ck" , - .ops = &clkops_null, - .rate =13000000 , -}; - -static struct clk virt_16_8m_ck = { - .name ="virt_16_8m_ck" , - .ops = &clkops_null, - .rate =16800000 , -}; - -static struct clk virt_19_2m_ck = { - .name ="virt_19_2m_ck" , - .ops = &clkops_null, - .rate =19200000 , -}; - -static struct clk virt_26m_ck = { - .name ="virt_26m_ck" , - .ops = &clkops_null, - .rate =26000000 , -}; - -static struct clk virt_38_4m_ck = { - .name ="virt_38_4m_ck" , - .ops = &clkops_null, - .rate =38400000 , -}; - -static const struct clksel_rate osc_sys_12m_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel_rate osc_sys_13m_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel_rate osc_sys_16_8m_rates[] = { - { .div =1 , .val =5 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =0 } -}; - -static const struct clksel_rate osc_sys_19_2m_rates[] = { - { .div =1 , .val =2 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel_rate osc_sys_26m_rates[] = { - { .div =1 , .val =3 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel_rate osc_sys_38_4m_rates[] = { - { .div =1 , .val =4 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel osc_sys_clksel[] = { - { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, - { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, - { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, - { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, - { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, - { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, - { .parent =NULL }, -}; - -/* Oscillator clock */ -/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ -static struct clk osc_sys_ck = { - .name ="osc_sys_ck" , - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP3430_PRM_CLKSEL , - .clksel_mask =OMAP3430_SYS_CLKIN_SEL_MASK , - .clksel = osc_sys_clksel, -/* REVISIT: deal with autoextclkmode? */ - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate div2_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_3XXX }, - { .div =2 , .val =2 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel sys_clksel[] = { - { .parent = &osc_sys_ck, .rates = div2_rates }, - { .parent =NULL } -}; - -/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ -/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ -static struct clk sys_ck = { - .name ="sys_ck" , - .ops = &clkops_null, - .parent = &osc_sys_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP3430_PRM_CLKSRC_CTRL , - .clksel_mask =OMAP_SYSCLKDIV_MASK , - .clksel = sys_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk sys_altclk = { - .name ="sys_altclk" , - .ops = &clkops_null, -}; - -/* Optional external clock input for some McBSPs */ -static struct clk mcbsp_clks = { - .name ="mcbsp_clks" , - .ops = &clkops_null, -}; - -/* PRM EXTERNAL CLOCK OUTPUT */ - -static struct clk sys_clkout1 = { - .name ="sys_clkout1" , - .ops = &clkops_omap2_dflt, - .parent = &osc_sys_ck, - .enable_reg =OMAP3430_PRM_CLKOUT_CTRL , - .enable_bit =OMAP3430_CLKOUT_EN_SHIFT , - .recalc = &followparent_recalc, -}; - -/* DPLLS */ - -/* CM CLOCKS */ - -static const struct clksel_rate div16_dpll_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_3XXX }, - { .div =2 , .val =2 , .flags =RATE_IN_3XXX }, - { .div =3 , .val =3 , .flags =RATE_IN_3XXX }, - { .div =4 , .val =4 , .flags =RATE_IN_3XXX }, - { .div =5 , .val =5 , .flags =RATE_IN_3XXX }, - { .div =6 , .val =6 , .flags =RATE_IN_3XXX }, - { .div =7 , .val =7 , .flags =RATE_IN_3XXX }, - { .div =8 , .val =8 , .flags =RATE_IN_3XXX }, - { .div =9 , .val =9 , .flags =RATE_IN_3XXX }, - { .div =10 , .val =10 , .flags =RATE_IN_3XXX }, - { .div =11 , .val =11 , .flags =RATE_IN_3XXX }, - { .div =12 , .val =12 , .flags =RATE_IN_3XXX }, - { .div =13 , .val =13 , .flags =RATE_IN_3XXX }, - { .div =14 , .val =14 , .flags =RATE_IN_3XXX }, - { .div =15 , .val =15 , .flags =RATE_IN_3XXX }, - { .div =16 , .val =16 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel_rate dpll4_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_3XXX }, - { .div =2 , .val =2 , .flags =RATE_IN_3XXX }, - { .div =3 , .val =3 , .flags =RATE_IN_3XXX }, - { .div =4 , .val =4 , .flags =RATE_IN_3XXX }, - { .div =5 , .val =5 , .flags =RATE_IN_3XXX }, - { .div =6 , .val =6 , .flags =RATE_IN_3XXX }, - { .div =7 , .val =7 , .flags =RATE_IN_3XXX }, - { .div =8 , .val =8 , .flags =RATE_IN_3XXX }, - { .div =9 , .val =9 , .flags =RATE_IN_3XXX }, - { .div =10 , .val =10 , .flags =RATE_IN_3XXX }, - { .div =11 , .val =11 , .flags =RATE_IN_3XXX }, - { .div =12 , .val =12 , .flags =RATE_IN_3XXX }, - { .div =13 , .val =13 , .flags =RATE_IN_3XXX }, - { .div =14 , .val =14 , .flags =RATE_IN_3XXX }, - { .div =15 , .val =15 , .flags =RATE_IN_3XXX }, - { .div =16 , .val =16 , .flags =RATE_IN_3XXX }, - { .div =17 , .val =17 , .flags =RATE_IN_36XX }, - { .div =18 , .val =18 , .flags =RATE_IN_36XX }, - { .div =19 , .val =19 , .flags =RATE_IN_36XX }, - { .div =20 , .val =20 , .flags =RATE_IN_36XX }, - { .div =21 , .val =21 , .flags =RATE_IN_36XX }, - { .div =22 , .val =22 , .flags =RATE_IN_36XX }, - { .div =23 , .val =23 , .flags =RATE_IN_36XX }, - { .div =24 , .val =24 , .flags =RATE_IN_36XX }, - { .div =25 , .val =25 , .flags =RATE_IN_36XX }, - { .div =26 , .val =26 , .flags =RATE_IN_36XX }, - { .div =27 , .val =27 , .flags =RATE_IN_36XX }, - { .div =28 , .val =28 , .flags =RATE_IN_36XX }, - { .div =29 , .val =29 , .flags =RATE_IN_36XX }, - { .div =30 , .val =30 , .flags =RATE_IN_36XX }, - { .div =31 , .val =31 , .flags =RATE_IN_36XX }, - { .div =32 , .val =32 , .flags =RATE_IN_36XX }, - { .div =0 } -}; - -/* DPLL1 */ -/* MPU clock source */ -/* Type: DPLL */ -static struct dpll_data dpll1_dd = { - .mult_div1_reg =OMAP_CM_REGADDR (MPU_MOD ,OMAP3430_CM_CLKSEL1_PLL ), - .mult_mask =OMAP3430_MPU_DPLL_MULT_MASK , - .div1_mask =OMAP3430_MPU_DPLL_DIV_MASK , - .clk_bypass = &dpll1_fck, - .clk_ref = &sys_ck, - .freqsel_mask =OMAP3430_MPU_DPLL_FREQSEL_MASK , - .control_reg =OMAP_CM_REGADDR (MPU_MOD ,OMAP3430_CM_CLKEN_PLL ), - .enable_mask =OMAP3430_EN_MPU_DPLL_MASK , - .modes = (1 <<DPLL_LOW_POWER_BYPASS ) | (1 <<DPLL_LOCKED ), - .auto_recal_bit =OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT , - .recal_en_bit =OMAP3430_MPU_DPLL_RECAL_EN_SHIFT , - .recal_st_bit =OMAP3430_MPU_DPLL_ST_SHIFT , - .autoidle_reg =OMAP_CM_REGADDR (MPU_MOD ,OMAP3430_CM_AUTOIDLE_PLL ), - .autoidle_mask =OMAP3430_AUTO_MPU_DPLL_MASK , - .idlest_reg =OMAP_CM_REGADDR (MPU_MOD ,OMAP3430_CM_IDLEST_PLL ), - .idlest_mask =OMAP3430_ST_MPU_CLK_MASK , - .max_multiplier =OMAP3_MAX_DPLL_MULT , - .min_divider =1 , - .max_divider =OMAP3_MAX_DPLL_DIV , -}; - -static struct clk dpll1_ck = { - .name ="dpll1_ck" , - .ops = &clkops_omap3_noncore_dpll_ops, - .parent = &sys_ck, - .dpll_data = &dpll1_dd, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .clkdm_name ="dpll1_clkdm" , - .recalc = &omap3_dpll_recalc, -}; - -/* -* This virtual clock provides the CLKOUTX2 output from the DPLL if the -* DPLL isn't bypassed. -*/ -static struct clk dpll1_x2_ck = { - .name ="dpll1_x2_ck" , - .ops = &clkops_null, - .parent = &dpll1_ck, - .recalc = &omap3_clkoutx2_recalc, -}; - -/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ -static const struct clksel div16_dpll1_x2m2_clksel[] = { - { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, - { .parent =NULL } -}; - -/* -* Does not exist in the TRM - needed to separate the M2 divider from -* bypass selection in mpu_ck -*/ -static struct clk dpll1_x2m2_ck = { - .name ="dpll1_x2m2_ck" , - .ops = &clkops_null, - .parent = &dpll1_x2_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (MPU_MOD ,OMAP3430_CM_CLKSEL2_PLL ), - .clksel_mask =OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK , - .clksel = div16_dpll1_x2m2_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* DPLL2 */ -/* IVA2 clock source */ -/* Type: DPLL */ - -static struct dpll_data dpll2_dd = { - .mult_div1_reg =OMAP_CM_REGADDR (OMAP3430_IVA2_MOD ,OMAP3430_CM_CLKSEL1_PLL ), - .mult_mask =OMAP3430_IVA2_DPLL_MULT_MASK , - .div1_mask =OMAP3430_IVA2_DPLL_DIV_MASK , - .clk_bypass = &dpll2_fck, - .clk_ref = &sys_ck, - .freqsel_mask =OMAP3430_IVA2_DPLL_FREQSEL_MASK , - .control_reg =OMAP_CM_REGADDR (OMAP3430_IVA2_MOD ,OMAP3430_CM_CLKEN_PLL ), - .enable_mask =OMAP3430_EN_IVA2_DPLL_MASK , - .modes = (1 <<DPLL_LOW_POWER_STOP ) | (1 <<DPLL_LOCKED ) | - (1 <<DPLL_LOW_POWER_BYPASS ), - .auto_recal_bit =OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT , - .recal_en_bit =OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT , - .recal_st_bit =OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT , - .autoidle_reg =OMAP_CM_REGADDR (OMAP3430_IVA2_MOD ,OMAP3430_CM_AUTOIDLE_PLL ), - .autoidle_mask =OMAP3430_AUTO_IVA2_DPLL_MASK , - .idlest_reg =OMAP_CM_REGADDR (OMAP3430_IVA2_MOD ,OMAP3430_CM_IDLEST_PLL ), - .idlest_mask =OMAP3430_ST_IVA2_CLK_MASK , - .max_multiplier =OMAP3_MAX_DPLL_MULT , - .min_divider =1 , - .max_divider =OMAP3_MAX_DPLL_DIV , -}; - -static struct clk dpll2_ck = { - .name ="dpll2_ck" , - .ops = &clkops_omap3_noncore_dpll_ops, - .parent = &sys_ck, - .dpll_data = &dpll2_dd, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .clkdm_name ="dpll2_clkdm" , - .recalc = &omap3_dpll_recalc, -}; - -static const struct clksel div16_dpll2_m2x2_clksel[] = { - { .parent = &dpll2_ck, .rates = div16_dpll_rates }, - { .parent =NULL } -}; - -/* -* The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT -* or CLKOUTX2. CLKOUT seems most plausible. -*/ -static struct clk dpll2_m2_ck = { - .name ="dpll2_m2_ck" , - .ops = &clkops_null, - .parent = &dpll2_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_IVA2_MOD , -OMAP3430_CM_CLKSEL2_PLL ), - .clksel_mask =OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK , - .clksel = div16_dpll2_m2x2_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* -* DPLL3 -* Source clock for all interfaces and for some device fclks -* REVISIT: Also supports fast relock bypass - not included below -*/ -static struct dpll_data dpll3_dd = { - .mult_div1_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKSEL1 ), - .mult_mask =OMAP3430_CORE_DPLL_MULT_MASK , - .div1_mask =OMAP3430_CORE_DPLL_DIV_MASK , - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .freqsel_mask =OMAP3430_CORE_DPLL_FREQSEL_MASK , - .control_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKEN ), - .enable_mask =OMAP3430_EN_CORE_DPLL_MASK , - .auto_recal_bit =OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT , - .recal_en_bit =OMAP3430_CORE_DPLL_RECAL_EN_SHIFT , - .recal_st_bit =OMAP3430_CORE_DPLL_ST_SHIFT , - .autoidle_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_AUTOIDLE ), - .autoidle_mask =OMAP3430_AUTO_CORE_DPLL_MASK , - .idlest_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_IDLEST ), - .idlest_mask =OMAP3430_ST_CORE_CLK_MASK , - .max_multiplier =OMAP3_MAX_DPLL_MULT , - .min_divider =1 , - .max_divider =OMAP3_MAX_DPLL_DIV , -}; - -static struct clk dpll3_ck = { - .name ="dpll3_ck" , - .ops = &clkops_omap3_core_dpll_ops, - .parent = &sys_ck, - .dpll_data = &dpll3_dd, - .round_rate = &omap2_dpll_round_rate, - .clkdm_name ="dpll3_clkdm" , - .recalc = &omap3_dpll_recalc, -}; - -/* -* This virtual clock provides the CLKOUTX2 output from the DPLL if the -* DPLL isn't bypassed -*/ -static struct clk dpll3_x2_ck = { - .name ="dpll3_x2_ck" , - .ops = &clkops_null, - .parent = &dpll3_ck, - .recalc = &omap3_clkoutx2_recalc, -}; - -static const struct clksel_rate div31_dpll3_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_3XXX }, - { .div =2 , .val =2 , .flags =RATE_IN_3XXX }, - { .div =3 , .val =3 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =4 , .val =4 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =5 , .val =5 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =6 , .val =6 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =7 , .val =7 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =8 , .val =8 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =9 , .val =9 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =10 , .val =10 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =11 , .val =11 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =12 , .val =12 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =13 , .val =13 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =14 , .val =14 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =15 , .val =15 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =16 , .val =16 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =17 , .val =17 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =18 , .val =18 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =19 , .val =19 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =20 , .val =20 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =21 , .val =21 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =22 , .val =22 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =23 , .val =23 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =24 , .val =24 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =25 , .val =25 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =26 , .val =26 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =27 , .val =27 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =28 , .val =28 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =29 , .val =29 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =30 , .val =30 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =31 , .val =31 , .flags =RATE_IN_3430ES2PLUS_36XX }, - { .div =0 }, -}; - -static const struct clksel div31_dpll3m2_clksel[] = { - { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, - { .parent =NULL } -}; - -/* DPLL3 output M2 - primary control point for CORE speed */ -static struct clk dpll3_m2_ck = { - .name ="dpll3_m2_ck" , - .ops = &clkops_null, - .parent = &dpll3_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK , - .clksel = div31_dpll3m2_clksel, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap3_core_dpll_m2_set_rate, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk core_ck = { - .name ="core_ck" , - .ops = &clkops_null, - .parent = &dpll3_m2_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dpll3_m2x2_ck = { - .name ="dpll3_m2x2_ck" , - .ops = &clkops_null, - .parent = &dpll3_m2_ck, - .recalc = &omap3_clkoutx2_recalc, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static const struct clksel div16_dpll3_clksel[] = { - { .parent = &dpll3_ck, .rates = div16_dpll_rates }, - { .parent =NULL } -}; - -/* This virtual clock is the source for dpll3_m3x2_ck */ -static struct clk dpll3_m3_ck = { - .name ="dpll3_m3_ck" , - .ops = &clkops_null, - .parent = &dpll3_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_EMU_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP3430_DIV_DPLL3_MASK , - .clksel = div16_dpll3_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static struct clk dpll3_m3x2_ck = { - .name ="dpll3_m3x2_ck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll3_m3_ck, - .enable_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKEN ), - .enable_bit =OMAP3430_PWRDN_EMU_CORE_SHIFT , - .flags =INVERT_ENABLE , - .clkdm_name ="dpll3_clkdm" , - .recalc = &omap3_clkoutx2_recalc, -}; - -static struct clk emu_core_alwon_ck = { - .name ="emu_core_alwon_ck" , - .ops = &clkops_null, - .parent = &dpll3_m3x2_ck, - .recalc = &followparent_recalc, -}; - -/* DPLL4 */ -/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ -/* Type: DPLL */ -static struct dpll_data dpll4_dd; - -static struct dpll_data dpll4_dd_34xx__initdata = { - .mult_div1_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKSEL2 ), - .mult_mask =OMAP3430_PERIPH_DPLL_MULT_MASK , - .div1_mask =OMAP3430_PERIPH_DPLL_DIV_MASK , - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .freqsel_mask =OMAP3430_PERIPH_DPLL_FREQSEL_MASK , - .control_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKEN ), - .enable_mask =OMAP3430_EN_PERIPH_DPLL_MASK , - .modes = (1 <<DPLL_LOW_POWER_STOP ) | (1 <<DPLL_LOCKED ), - .auto_recal_bit =OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT , - .recal_en_bit =OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT , - .recal_st_bit =OMAP3430_PERIPH_DPLL_ST_SHIFT , - .autoidle_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_AUTOIDLE ), - .autoidle_mask =OMAP3430_AUTO_PERIPH_DPLL_MASK , - .idlest_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_IDLEST ), - .idlest_mask =OMAP3430_ST_PERIPH_CLK_MASK , - .max_multiplier =OMAP3_MAX_DPLL_MULT , - .min_divider =1 , - .max_divider =OMAP3_MAX_DPLL_DIV , -}; - -static struct dpll_data dpll4_dd_3630__initdata = { - .mult_div1_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKSEL2 ), - .mult_mask =OMAP3630_PERIPH_DPLL_MULT_MASK , - .div1_mask =OMAP3430_PERIPH_DPLL_DIV_MASK , - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .control_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKEN ), - .enable_mask =OMAP3430_EN_PERIPH_DPLL_MASK , - .modes = (1 <<DPLL_LOW_POWER_STOP ) | (1 <<DPLL_LOCKED ), - .auto_recal_bit =OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT , - .recal_en_bit =OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT , - .recal_st_bit =OMAP3430_PERIPH_DPLL_ST_SHIFT , - .autoidle_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_AUTOIDLE ), - .autoidle_mask =OMAP3430_AUTO_PERIPH_DPLL_MASK , - .idlest_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_IDLEST ), - .idlest_mask =OMAP3430_ST_PERIPH_CLK_MASK , - .dco_mask =OMAP3630_PERIPH_DPLL_DCO_SEL_MASK , - .sddiv_mask =OMAP3630_PERIPH_DPLL_SD_DIV_MASK , - .max_multiplier =OMAP3630_MAX_JTYPE_DPLL_MULT , - .min_divider =1 , - .max_divider =OMAP3_MAX_DPLL_DIV , - .flags =DPLL_J_TYPE -}; - -static struct clk dpll4_ck = { - .name ="dpll4_ck" , - .ops = &clkops_omap3_noncore_dpll_ops, - .parent = &sys_ck, - .dpll_data = &dpll4_dd, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_dpll4_set_rate, - .clkdm_name ="dpll4_clkdm" , - .recalc = &omap3_dpll_recalc, -}; - -/* -* This virtual clock provides the CLKOUTX2 output from the DPLL if the -* DPLL isn't bypassed -- -* XXX does this serve any downstream clocks? -*/ -static struct clk dpll4_x2_ck = { - .name ="dpll4_x2_ck" , - .ops = &clkops_null, - .parent = &dpll4_ck, - .recalc = &omap3_clkoutx2_recalc, -}; - -static const struct clksel dpll4_clksel[] = { - { .parent = &dpll4_ck, .rates = dpll4_rates }, - { .parent =NULL } -}; - -/* This virtual clock is the source for dpll4_m2x2_ck */ -static struct clk dpll4_m2_ck = { - .name ="dpll4_m2_ck" , - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (PLL_MOD ,OMAP3430_CM_CLKSEL3 ), - .clksel_mask =OMAP3630_DIV_96M_MASK , - .clksel = dpll4_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static struct clk dpll4_m2x2_ck = { - .name ="dpll4_m2x2_ck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll4_m2_ck, - .enable_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKEN ), - .enable_bit =OMAP3430_PWRDN_96M_SHIFT , - .flags =INVERT_ENABLE , - .clkdm_name ="dpll4_clkdm" , - .recalc = &omap3_clkoutx2_recalc, -}; - -/* -* DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as -* PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM: -* 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and -* CM_96K_(F)CLK. -*/ - -/* Adding 192MHz Clock node needed by SGX */ -static struct clk omap_192m_alwon_fck = { - .name ="omap_192m_alwon_fck" , - .ops = &clkops_null, - .parent = &dpll4_m2x2_ck, - .recalc = &followparent_recalc, -}; - -static const struct clksel_rate omap_96m_alwon_fck_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_36XX }, - { .div =2 , .val =2 , .flags =RATE_IN_36XX }, - { .div =0 } -}; - -static const struct clksel omap_96m_alwon_fck_clksel[] = { - { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates }, - { .parent =NULL } -}; - -static const struct clksel_rate omap_96m_dpll_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel_rate omap_96m_sys_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static struct clk omap_96m_alwon_fck = { - .name ="omap_96m_alwon_fck" , - .ops = &clkops_null, - .parent = &dpll4_m2x2_ck, - .recalc = &followparent_recalc, -}; - -static struct clk omap_96m_alwon_fck_3630 = { - .name ="omap_96m_alwon_fck" , - .parent = &omap_192m_alwon_fck, - .init = &omap2_init_clksel_parent, - .ops = &clkops_null, - .recalc = &omap2_clksel_recalc, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3630_CLKSEL_96M_MASK , - .clksel = omap_96m_alwon_fck_clksel -}; - -static struct clk cm_96m_fck = { - .name ="cm_96m_fck" , - .ops = &clkops_null, - .parent = &omap_96m_alwon_fck, - .recalc = &followparent_recalc, -}; - -static const struct clksel omap_96m_fck_clksel[] = { - { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, - { .parent = &sys_ck, .rates = omap_96m_sys_rates }, - { .parent =NULL } -}; - -static struct clk omap_96m_fck = { - .name ="omap_96m_fck" , - .ops = &clkops_null, - .parent = &sys_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP3430_SOURCE_96M_MASK , - .clksel = omap_96m_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* This virtual clock is the source for dpll4_m3x2_ck */ -static struct clk dpll4_m3_ck = { - .name ="dpll4_m3_ck" , - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_DSS_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3630_CLKSEL_TV_MASK , - .clksel = dpll4_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static struct clk dpll4_m3x2_ck = { - .name ="dpll4_m3x2_ck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll4_m3_ck, - .enable_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKEN ), - .enable_bit =OMAP3430_PWRDN_TV_SHIFT , - .flags =INVERT_ENABLE , - .clkdm_name ="dpll4_clkdm" , - .recalc = &omap3_clkoutx2_recalc, -}; - -static const struct clksel_rate omap_54m_d4m3x2_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel_rate omap_54m_alt_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel omap_54m_clksel[] = { - { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, - { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, - { .parent =NULL } -}; - -static struct clk omap_54m_fck = { - .name ="omap_54m_fck" , - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP3430_SOURCE_54M_MASK , - .clksel = omap_54m_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate omap_48m_cm96m_rates[] = { - { .div =2 , .val =0 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel_rate omap_48m_alt_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel omap_48m_clksel[] = { - { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates }, - { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, - { .parent =NULL } -}; - -static struct clk omap_48m_fck = { - .name ="omap_48m_fck" , - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP3430_SOURCE_48M_MASK , - .clksel = omap_48m_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk omap_12m_fck = { - .name ="omap_12m_fck" , - .ops = &clkops_null, - .parent = &omap_48m_fck, - .fixed_div =4 , - .recalc = &omap_fixed_divisor_recalc, -}; - -/* This virtual clock is the source for dpll4_m4x2_ck */ -static struct clk dpll4_m4_ck = { - .name ="dpll4_m4_ck" , - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_DSS_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3630_CLKSEL_DSS1_MASK , - .clksel = dpll4_clksel, - .recalc = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static struct clk dpll4_m4x2_ck = { - .name ="dpll4_m4x2_ck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll4_m4_ck, - .enable_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKEN ), - .enable_bit =OMAP3430_PWRDN_DSS1_SHIFT , - .flags =INVERT_ENABLE , - .clkdm_name ="dpll4_clkdm" , - .recalc = &omap3_clkoutx2_recalc, -}; - -/* This virtual clock is the source for dpll4_m5x2_ck */ -static struct clk dpll4_m5_ck = { - .name ="dpll4_m5_ck" , - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_CAM_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3630_CLKSEL_CAM_MASK , - .clksel = dpll4_clksel, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate, - .recalc = &omap2_clksel_recalc, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static struct clk dpll4_m5x2_ck = { - .name ="dpll4_m5x2_ck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll4_m5_ck, - .enable_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKEN ), - .enable_bit =OMAP3430_PWRDN_CAM_SHIFT , - .flags =INVERT_ENABLE , - .clkdm_name ="dpll4_clkdm" , - .recalc = &omap3_clkoutx2_recalc, -}; - -/* This virtual clock is the source for dpll4_m6x2_ck */ -static struct clk dpll4_m6_ck = { - .name ="dpll4_m6_ck" , - .ops = &clkops_null, - .parent = &dpll4_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_EMU_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP3630_DIV_DPLL4_MASK , - .clksel = dpll4_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* The PWRDN bit is apparently only available on 3430ES2 and above */ -static struct clk dpll4_m6x2_ck = { - .name ="dpll4_m6x2_ck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll4_m6_ck, - .enable_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKEN ), - .enable_bit =OMAP3430_PWRDN_EMU_PERIPH_SHIFT , - .flags =INVERT_ENABLE , - .clkdm_name ="dpll4_clkdm" , - .recalc = &omap3_clkoutx2_recalc, -}; - -static struct clk emu_per_alwon_ck = { - .name ="emu_per_alwon_ck" , - .ops = &clkops_null, - .parent = &dpll4_m6x2_ck, - .recalc = &followparent_recalc, -}; - -/* DPLL5 */ -/* Supplies 120MHz clock, USIM source clock */ -/* Type: DPLL */ -/* 3430ES2 only */ -static struct dpll_data dpll5_dd = { - .mult_div1_reg =OMAP_CM_REGADDR (PLL_MOD ,OMAP3430ES2_CM_CLKSEL4 ), - .mult_mask =OMAP3430ES2_PERIPH2_DPLL_MULT_MASK , - .div1_mask =OMAP3430ES2_PERIPH2_DPLL_DIV_MASK , - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .freqsel_mask =OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK , - .control_reg =OMAP_CM_REGADDR (PLL_MOD ,OMAP3430ES2_CM_CLKEN2 ), - .enable_mask =OMAP3430ES2_EN_PERIPH2_DPLL_MASK , - .modes = (1 <<DPLL_LOW_POWER_STOP ) | (1 <<DPLL_LOCKED ), - .auto_recal_bit =OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT , - .recal_en_bit =OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT , - .recal_st_bit =OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT , - .autoidle_reg =OMAP_CM_REGADDR (PLL_MOD ,OMAP3430ES2_CM_AUTOIDLE2_PLL ), - .autoidle_mask =OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK , - .idlest_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_IDLEST2 ), - .idlest_mask =OMAP3430ES2_ST_PERIPH2_CLK_MASK , - .max_multiplier =OMAP3_MAX_DPLL_MULT , - .min_divider =1 , - .max_divider =OMAP3_MAX_DPLL_DIV , -}; - -static struct clk dpll5_ck = { - .name ="dpll5_ck" , - .ops = &clkops_omap3_noncore_dpll_ops, - .parent = &sys_ck, - .dpll_data = &dpll5_dd, - .round_rate = &omap2_dpll_round_rate, - .set_rate = &omap3_noncore_dpll_set_rate, - .clkdm_name ="dpll5_clkdm" , - .recalc = &omap3_dpll_recalc, -}; - -static const struct clksel div16_dpll5_clksel[] = { - { .parent = &dpll5_ck, .rates = div16_dpll_rates }, - { .parent =NULL } -}; - -static struct clk dpll5_m2_ck = { - .name ="dpll5_m2_ck" , - .ops = &clkops_null, - .parent = &dpll5_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (PLL_MOD ,OMAP3430ES2_CM_CLKSEL5 ), - .clksel_mask =OMAP3430ES2_DIV_120M_MASK , - .clksel = div16_dpll5_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* CM EXTERNAL CLOCK OUTPUTS */ - -static const struct clksel_rate clkout2_src_core_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel_rate clkout2_src_sys_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel_rate clkout2_src_96m_rates[] = { - { .div =1 , .val =2 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel_rate clkout2_src_54m_rates[] = { - { .div =1 , .val =3 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel clkout2_src_clksel[] = { - { .parent = &core_ck, .rates = clkout2_src_core_rates }, - { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, - { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates }, - { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, - { .parent =NULL } -}; - -static struct clk clkout2_src_ck = { - .name ="clkout2_src_ck" , - .ops = &clkops_omap2_dflt, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP3430_CM_CLKOUT_CTRL , - .enable_bit =OMAP3430_CLKOUT2_EN_SHIFT , - .clksel_reg =OMAP3430_CM_CLKOUT_CTRL , - .clksel_mask =OMAP3430_CLKOUT2SOURCE_MASK , - .clksel = clkout2_src_clksel, - .clkdm_name ="core_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate sys_clkout2_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_3XXX }, - { .div =2 , .val =1 , .flags =RATE_IN_3XXX }, - { .div =4 , .val =2 , .flags =RATE_IN_3XXX }, - { .div =8 , .val =3 , .flags =RATE_IN_3XXX }, - { .div =16 , .val =4 , .flags =RATE_IN_3XXX }, - { .div =0 }, -}; - -static const struct clksel sys_clkout2_clksel[] = { - { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, - { .parent =NULL }, -}; - -static struct clk sys_clkout2 = { - .name ="sys_clkout2" , - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP3430_CM_CLKOUT_CTRL , - .clksel_mask =OMAP3430_CLKOUT2_DIV_MASK , - .clksel = sys_clkout2_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -/* CM OUTPUT CLOCKS */ - -static struct clk corex2_fck = { - .name ="corex2_fck" , - .ops = &clkops_null, - .parent = &dpll3_m2x2_ck, - .recalc = &followparent_recalc, -}; - -/* DPLL power domain clock controls */ - -static const struct clksel_rate div4_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_3XXX }, - { .div =2 , .val =2 , .flags =RATE_IN_3XXX }, - { .div =4 , .val =4 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel div4_core_clksel[] = { - { .parent = &core_ck, .rates = div4_rates }, - { .parent =NULL } -}; - -/* -* REVISIT: Are these in DPLL power domain or CM power domain? docs -* may be inconsistent here? -*/ -static struct clk dpll1_fck = { - .name ="dpll1_fck" , - .ops = &clkops_null, - .parent = &core_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (MPU_MOD ,OMAP3430_CM_CLKSEL1_PLL ), - .clksel_mask =OMAP3430_MPU_CLK_SRC_MASK , - .clksel = div4_core_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mpu_ck = { - .name ="mpu_ck" , - .ops = &clkops_null, - .parent = &dpll1_x2m2_ck, - .recalc = &followparent_recalc, -}; - -/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ -static const struct clksel_rate arm_fck_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_3XXX }, - { .div =2 , .val =1 , .flags =RATE_IN_3XXX }, - { .div =0 }, -}; - -static const struct clksel arm_fck_clksel[] = { - { .parent = &mpu_ck, .rates = arm_fck_rates }, - { .parent =NULL } -}; - -static struct clk arm_fck = { - .name ="arm_fck" , - .ops = &clkops_null, - .parent = &mpu_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (MPU_MOD ,OMAP3430_CM_IDLEST_PLL ), - .clksel_mask =OMAP3430_ST_MPU_CLK_MASK , - .clksel = arm_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* XXX What about neon_clkdm ? */ - -/* -* REVISIT: This clock is never specifically defined in the 3430 TRM, -* although it is referenced - so this is a guess -*/ -static struct clk emu_mpu_alwon_ck = { - .name ="emu_mpu_alwon_ck" , - .ops = &clkops_null, - .parent = &mpu_ck, - .recalc = &followparent_recalc, -}; - -static struct clk dpll2_fck = { - .name ="dpll2_fck" , - .ops = &clkops_null, - .parent = &core_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_IVA2_MOD ,OMAP3430_CM_CLKSEL1_PLL ), - .clksel_mask =OMAP3430_IVA2_CLK_SRC_MASK , - .clksel = div4_core_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk iva2_ck = { - .name ="iva2_ck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll2_m2_ck, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_IVA2_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT , - .clkdm_name ="iva2_clkdm" , - .recalc = &followparent_recalc, -}; - -/* Common interface clocks */ - -static const struct clksel div2_core_clksel[] = { - { .parent = &core_ck, .rates = div2_rates }, - { .parent =NULL } -}; - -static struct clk l3_ick = { - .name ="l3_ick" , - .ops = &clkops_null, - .parent = &core_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430_CLKSEL_L3_MASK , - .clksel = div2_core_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel div2_l3_clksel[] = { - { .parent = &l3_ick, .rates = div2_rates }, - { .parent =NULL } -}; - -static struct clk l4_ick = { - .name ="l4_ick" , - .ops = &clkops_null, - .parent = &l3_ick, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430_CLKSEL_L4_MASK , - .clksel = div2_l3_clksel, - .recalc = &omap2_clksel_recalc, - -}; - -static const struct clksel div2_l4_clksel[] = { - { .parent = &l4_ick, .rates = div2_rates }, - { .parent =NULL } -}; - -static struct clk rm_ick = { - .name ="rm_ick" , - .ops = &clkops_null, - .parent = &l4_ick, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430_CLKSEL_RM_MASK , - .clksel = div2_l4_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* GFX power domain */ - -/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ - -static const struct clksel gfx_l3_clksel[] = { - { .parent = &l3_ick, .rates = gfx_l3_rates }, - { .parent =NULL } -}; - -/* -* Virtual parent clock for gfx_l3_ick and gfx_l3_fck -* This interface clock does not have a CM_AUTOIDLE bit -*/ -static struct clk gfx_l3_ck = { - .name ="gfx_l3_ck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &l3_ick, - .enable_reg =OMAP_CM_REGADDR (GFX_MOD ,CM_ICLKEN ), - .enable_bit =OMAP_EN_GFX_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk gfx_l3_fck = { - .name ="gfx_l3_fck" , - .ops = &clkops_null, - .parent = &gfx_l3_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (GFX_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP_CLKSEL_GFX_MASK , - .clksel = gfx_l3_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gfx_l3_ick = { - .name ="gfx_l3_ick" , - .ops = &clkops_null, - .parent = &gfx_l3_ck, - .recalc = &followparent_recalc, -}; - -static struct clk gfx_cg1_ck = { - .name ="gfx_cg1_ck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &gfx_l3_fck,/* REVISIT: correct? */ - .enable_reg =OMAP_CM_REGADDR (GFX_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430ES1_EN_2D_SHIFT , - .clkdm_name ="gfx_3430es1_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gfx_cg2_ck = { - .name ="gfx_cg2_ck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &gfx_l3_fck,/* REVISIT: correct? */ - .enable_reg =OMAP_CM_REGADDR (GFX_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430ES1_EN_3D_SHIFT , - .clkdm_name ="gfx_3430es1_clkdm" , - .recalc = &followparent_recalc, -}; - -/* SGX power domain - 3430ES2 only */ - -static const struct clksel_rate sgx_core_rates[] = { - { .div =2 , .val =5 , .flags =RATE_IN_36XX }, - { .div =3 , .val =0 , .flags =RATE_IN_3XXX }, - { .div =4 , .val =1 , .flags =RATE_IN_3XXX }, - { .div =6 , .val =2 , .flags =RATE_IN_3XXX }, - { .div =0 }, -}; - -static const struct clksel_rate sgx_192m_rates[] = { - { .div =1 , .val =4 , .flags =RATE_IN_36XX }, - { .div =0 }, -}; - -static const struct clksel_rate sgx_corex2_rates[] = { - { .div =3 , .val =6 , .flags =RATE_IN_36XX }, - { .div =5 , .val =7 , .flags =RATE_IN_36XX }, - { .div =0 }, -}; - -static const struct clksel_rate sgx_96m_rates[] = { - { .div =1 , .val =3 , .flags =RATE_IN_3XXX }, - { .div =0 }, -}; - -static const struct clksel sgx_clksel[] = { - { .parent = &core_ck, .rates = sgx_core_rates }, - { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, - { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates }, - { .parent = &corex2_fck, .rates = sgx_corex2_rates }, - { .parent =NULL } -}; - -static struct clk sgx_fck = { - .name ="sgx_fck" , - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (OMAP3430ES2_SGX_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (OMAP3430ES2_SGX_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430ES2_CLKSEL_SGX_MASK , - .clksel = sgx_clksel, - .clkdm_name ="sgx_clkdm" , - .recalc = &omap2_clksel_recalc, - .set_rate = &omap2_clksel_set_rate, - .round_rate = &omap2_clksel_round_rate -}; - -/* This interface clock does not have a CM_AUTOIDLE bit */ -static struct clk sgx_ick = { - .name ="sgx_ick" , - .ops = &clkops_omap2_dflt_wait, - .parent = &l3_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430ES2_SGX_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT , - .clkdm_name ="sgx_clkdm" , - .recalc = &followparent_recalc, -}; - -/* CORE power domain */ - -static struct clk d2d_26m_fck = { - .name ="d2d_26m_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &sys_ck, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430ES1_EN_D2D_SHIFT , - .clkdm_name ="d2d_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk modem_fck = { - .name ="modem_fck" , - .ops = &clkops_omap2_mdmclk_dflt_wait, - .parent = &sys_ck, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_MODEM_SHIFT , - .clkdm_name ="d2d_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk sad2d_ick = { - .name ="sad2d_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l3_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_SAD2D_SHIFT , - .clkdm_name ="d2d_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk mad2d_ick = { - .name ="mad2d_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l3_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN3 ), - .enable_bit =OMAP3430_EN_MAD2D_SHIFT , - .clkdm_name ="d2d_clkdm" , - .recalc = &followparent_recalc, -}; - -static const struct clksel omap343x_gpt_clksel[] = { - { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, - { .parent = &sys_ck, .rates = gpt_sys_rates }, - { .parent =NULL } -}; - -static struct clk gpt10_fck = { - .name ="gpt10_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &sys_ck, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_GPT10_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430_CLKSEL_GPT10_MASK , - .clksel = omap343x_gpt_clksel, - .clkdm_name ="core_l4_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt11_fck = { - .name ="gpt11_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &sys_ck, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_GPT11_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430_CLKSEL_GPT11_MASK , - .clksel = omap343x_gpt_clksel, - .clkdm_name ="core_l4_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -static struct clk cpefuse_fck = { - .name ="cpefuse_fck" , - .ops = &clkops_omap2_dflt, - .parent = &sys_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,OMAP3430ES2_CM_FCLKEN3 ), - .enable_bit =OMAP3430ES2_EN_CPEFUSE_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk ts_fck = { - .name ="ts_fck" , - .ops = &clkops_omap2_dflt, - .parent = &omap_32k_fck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,OMAP3430ES2_CM_FCLKEN3 ), - .enable_bit =OMAP3430ES2_EN_TS_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk usbtll_fck = { - .name ="usbtll_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &dpll5_m2_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,OMAP3430ES2_CM_FCLKEN3 ), - .enable_bit =OMAP3430ES2_EN_USBTLL_SHIFT , - .recalc = &followparent_recalc, -}; - -/* CORE 96M FCLK-derived clocks */ - -static struct clk core_96m_fck = { - .name ="core_96m_fck" , - .ops = &clkops_null, - .parent = &omap_96m_fck, - .recalc = &followparent_recalc, -}; - -static struct clk mmchs3_fck = { - .name ="mmchs3_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_96m_fck, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430ES2_EN_MMC3_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk mmchs2_fck = { - .name ="mmchs2_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_96m_fck, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_MMC2_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk mspro_fck = { - .name ="mspro_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_96m_fck, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_MSPRO_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk mmchs1_fck = { - .name ="mmchs1_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_96m_fck, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_MMC1_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk i2c3_fck = { - .name ="i2c3_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_96m_fck, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_I2C3_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk i2c2_fck = { - .name ="i2c2_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_96m_fck, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_I2C2_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk i2c1_fck = { - .name ="i2c1_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_96m_fck, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_I2C1_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -/* -* MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; -* MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. -*/ -static const struct clksel_rate common_mcbsp_96m_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel mcbsp_15_clksel[] = { - { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, - { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, - { .parent =NULL } -}; - -static struct clk mcbsp5_fck = { - .name ="mcbsp5_fck" , - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_MCBSP5_SHIFT , - .clksel_reg =OMAP343X_CTRL_REGADDR (OMAP343X_CONTROL_DEVCONF1 ), - .clksel_mask =OMAP2_MCBSP5_CLKS_MASK , - .clksel = mcbsp_15_clksel, - .clkdm_name ="core_l4_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp1_fck = { - .name ="mcbsp1_fck" , - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_MCBSP1_SHIFT , - .clksel_reg =OMAP343X_CTRL_REGADDR (OMAP2_CONTROL_DEVCONF0 ), - .clksel_mask =OMAP2_MCBSP1_CLKS_MASK , - .clksel = mcbsp_15_clksel, - .clkdm_name ="core_l4_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -/* CORE_48M_FCK-derived clocks */ - -static struct clk core_48m_fck = { - .name ="core_48m_fck" , - .ops = &clkops_null, - .parent = &omap_48m_fck, - .recalc = &followparent_recalc, -}; - -static struct clk mcspi4_fck = { - .name ="mcspi4_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_48m_fck, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_MCSPI4_SHIFT , - .recalc = &followparent_recalc, - .clkdm_name ="core_l4_clkdm" , -}; - -static struct clk mcspi3_fck = { - .name ="mcspi3_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_48m_fck, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_MCSPI3_SHIFT , - .recalc = &followparent_recalc, - .clkdm_name ="core_l4_clkdm" , -}; - -static struct clk mcspi2_fck = { - .name ="mcspi2_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_48m_fck, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_MCSPI2_SHIFT , - .recalc = &followparent_recalc, - .clkdm_name ="core_l4_clkdm" , -}; - -static struct clk mcspi1_fck = { - .name ="mcspi1_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_48m_fck, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_MCSPI1_SHIFT , - .recalc = &followparent_recalc, - .clkdm_name ="core_l4_clkdm" , -}; - -static struct clk uart2_fck = { - .name ="uart2_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_48m_fck, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_UART2_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk uart1_fck = { - .name ="uart1_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_48m_fck, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_UART1_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk fshostusb_fck = { - .name ="fshostusb_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_48m_fck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430ES1_EN_FSHOSTUSB_SHIFT , - .recalc = &followparent_recalc, -}; - -/* CORE_12M_FCK based clocks */ - -static struct clk core_12m_fck = { - .name ="core_12m_fck" , - .ops = &clkops_null, - .parent = &omap_12m_fck, - .recalc = &followparent_recalc, -}; - -static struct clk hdq_fck = { - .name ="hdq_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_12m_fck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_HDQ_SHIFT , - .recalc = &followparent_recalc, -}; - -/* DPLL3-derived clock */ - -static const struct clksel_rate ssi_ssr_corex2_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_3XXX }, - { .div =2 , .val =2 , .flags =RATE_IN_3XXX }, - { .div =3 , .val =3 , .flags =RATE_IN_3XXX }, - { .div =4 , .val =4 , .flags =RATE_IN_3XXX }, - { .div =6 , .val =6 , .flags =RATE_IN_3XXX }, - { .div =8 , .val =8 , .flags =RATE_IN_3XXX }, - { .div =0 } -}; - -static const struct clksel ssi_ssr_clksel[] = { - { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, - { .parent =NULL } -}; - -static struct clk ssi_ssr_fck_3430es1 = { - .name ="ssi_ssr_fck" , - .ops = &clkops_omap2_dflt, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_SSI_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430_CLKSEL_SSI_MASK , - .clksel = ssi_ssr_clksel, - .clkdm_name ="core_l4_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -static struct clk ssi_ssr_fck_3430es2 = { - .name ="ssi_ssr_fck" , - .ops = &clkops_omap3430es2_ssi_wait, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_SSI_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430_CLKSEL_SSI_MASK , - .clksel = ssi_ssr_clksel, - .clkdm_name ="core_l4_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -static struct clk ssi_sst_fck_3430es1 = { - .name ="ssi_sst_fck" , - .ops = &clkops_null, - .parent = &ssi_ssr_fck_3430es1, - .fixed_div =2 , - .recalc = &omap_fixed_divisor_recalc, -}; - -static struct clk ssi_sst_fck_3430es2 = { - .name ="ssi_sst_fck" , - .ops = &clkops_null, - .parent = &ssi_ssr_fck_3430es2, - .fixed_div =2 , - .recalc = &omap_fixed_divisor_recalc, -}; - - - -/* CORE_L3_ICK based clocks */ - -/* -* XXX must add clk_enable/clk_disable for these if standard code won't -* handle it -*/ -static struct clk core_l3_ick = { - .name ="core_l3_ick" , - .ops = &clkops_null, - .parent = &l3_ick, - .recalc = &followparent_recalc, -}; - -static struct clk hsotgusb_ick_3430es1 = { - .name ="hsotgusb_ick" , - .ops = &clkops_omap2_iclk_dflt, - .parent = &core_l3_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_HSOTGUSB_SHIFT , - .clkdm_name ="core_l3_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk hsotgusb_ick_3430es2 = { - .name ="hsotgusb_ick" , - .ops = &clkops_omap3430es2_iclk_hsotgusb_wait, - .parent = &core_l3_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_HSOTGUSB_SHIFT , - .clkdm_name ="core_l3_clkdm" , - .recalc = &followparent_recalc, -}; - -/* This interface clock does not have a CM_AUTOIDLE bit */ -static struct clk sdrc_ick = { - .name ="sdrc_ick" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l3_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_SDRC_SHIFT , - .flags =ENABLE_ON_INIT , - .clkdm_name ="core_l3_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpmc_fck = { - .name ="gpmc_fck" , - .ops = &clkops_null, - .parent = &core_l3_ick, - .flags =ENABLE_ON_INIT ,/* huh? */ - .recalc = &followparent_recalc, -}; - -/* SECURITY_L3_ICK based clocks */ - -static struct clk security_l3_ick = { - .name ="security_l3_ick" , - .ops = &clkops_null, - .parent = &l3_ick, - .recalc = &followparent_recalc, -}; - -static struct clk pka_ick = { - .name ="pka_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &security_l3_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN2 ), - .enable_bit =OMAP3430_EN_PKA_SHIFT , - .recalc = &followparent_recalc, -}; - -/* CORE_L4_ICK based clocks */ - -static struct clk core_l4_ick = { - .name ="core_l4_ick" , - .ops = &clkops_null, - .parent = &l4_ick, - .recalc = &followparent_recalc, -}; - -static struct clk usbtll_ick = { - .name ="usbtll_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN3 ), - .enable_bit =OMAP3430ES2_EN_USBTLL_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk mmchs3_ick = { - .name ="mmchs3_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430ES2_EN_MMC3_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -/* Intersystem Communication Registers - chassis mode only */ -static struct clk icr_ick = { - .name ="icr_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_ICR_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk aes2_ick = { - .name ="aes2_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_AES2_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk sha12_ick = { - .name ="sha12_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_SHA12_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk des2_ick = { - .name ="des2_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_DES2_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk mmchs2_ick = { - .name ="mmchs2_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_MMC2_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk mmchs1_ick = { - .name ="mmchs1_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_MMC1_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk mspro_ick = { - .name ="mspro_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_MSPRO_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk hdq_ick = { - .name ="hdq_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_HDQ_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk mcspi4_ick = { - .name ="mcspi4_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_MCSPI4_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk mcspi3_ick = { - .name ="mcspi3_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_MCSPI3_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk mcspi2_ick = { - .name ="mcspi2_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_MCSPI2_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk mcspi1_ick = { - .name ="mcspi1_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_MCSPI1_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk i2c3_ick = { - .name ="i2c3_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_I2C3_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk i2c2_ick = { - .name ="i2c2_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_I2C2_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk i2c1_ick = { - .name ="i2c1_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_I2C1_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk uart2_ick = { - .name ="uart2_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_UART2_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk uart1_ick = { - .name ="uart1_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_UART1_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpt11_ick = { - .name ="gpt11_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_GPT11_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpt10_ick = { - .name ="gpt10_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_GPT10_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp5_ick = { - .name ="mcbsp5_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_MCBSP5_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp1_ick = { - .name ="mcbsp1_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_MCBSP1_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk fac_ick = { - .name ="fac_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430ES1_EN_FAC_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk mailboxes_ick = { - .name ="mailboxes_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_MAILBOXES_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk omapctrl_ick = { - .name ="omapctrl_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_OMAPCTRL_SHIFT , - .flags =ENABLE_ON_INIT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -/* SSI_L4_ICK based clocks */ - -static struct clk ssi_l4_ick = { - .name ="ssi_l4_ick" , - .ops = &clkops_null, - .parent = &l4_ick, - .recalc = &followparent_recalc, -}; - -static struct clk ssi_ick_3430es1 = { - .name ="ssi_ick" , - .ops = &clkops_omap2_iclk_dflt, - .parent = &ssi_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_SSI_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk ssi_ick_3430es2 = { - .name ="ssi_ick" , - .ops = &clkops_omap3430es2_iclk_ssi_wait, - .parent = &ssi_l4_ick, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430_EN_SSI_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -/* REVISIT: Technically the TRM claims that this is CORE_CLK based, -* but l4_ick makes more sense to me */ - -static const struct clksel usb_l4_clksel[] = { - { .parent = &l4_ick, .rates = div2_rates }, - { .parent =NULL }, -}; - -static struct clk usb_l4_ick = { - .name ="usb_l4_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ick, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP3430ES1_EN_FSHOSTUSB_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK , - .clksel = usb_l4_clksel, - .clkdm_name ="core_l4_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -/* SECURITY_L4_ICK2 based clocks */ - -static struct clk security_l4_ick2 = { - .name ="security_l4_ick2" , - .ops = &clkops_null, - .parent = &l4_ick, - .recalc = &followparent_recalc, -}; - -static struct clk aes1_ick = { - .name ="aes1_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &security_l4_ick2, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN2 ), - .enable_bit =OMAP3430_EN_AES1_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk rng_ick = { - .name ="rng_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &security_l4_ick2, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN2 ), - .enable_bit =OMAP3430_EN_RNG_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk sha11_ick = { - .name ="sha11_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &security_l4_ick2, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN2 ), - .enable_bit =OMAP3430_EN_SHA11_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk des1_ick = { - .name ="des1_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &security_l4_ick2, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN2 ), - .enable_bit =OMAP3430_EN_DES1_SHIFT , - .recalc = &followparent_recalc, -}; - -/* DSS */ -static struct clk dss1_alwon_fck_3430es1 = { - .name ="dss1_alwon_fck" , - .ops = &clkops_omap2_dflt, - .parent = &dpll4_m4x2_ck, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_DSS_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_DSS1_SHIFT , - .clkdm_name ="dss_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk dss1_alwon_fck_3430es2 = { - .name ="dss1_alwon_fck" , - .ops = &clkops_omap3430es2_dss_usbhost_wait, - .parent = &dpll4_m4x2_ck, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_DSS_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_DSS1_SHIFT , - .clkdm_name ="dss_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk dss_tv_fck = { - .name ="dss_tv_fck" , - .ops = &clkops_omap2_dflt, - .parent = &omap_54m_fck, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_DSS_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_TV_SHIFT , - .clkdm_name ="dss_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk dss_96m_fck = { - .name ="dss_96m_fck" , - .ops = &clkops_omap2_dflt, - .parent = &omap_96m_fck, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_DSS_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_TV_SHIFT , - .clkdm_name ="dss_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk dss2_alwon_fck = { - .name ="dss2_alwon_fck" , - .ops = &clkops_omap2_dflt, - .parent = &sys_ck, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_DSS_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_DSS2_SHIFT , - .clkdm_name ="dss_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk dss_ick_3430es1 = { -/* Handles both L3 and L4 clocks */ - .name ="dss_ick" , - .ops = &clkops_omap2_iclk_dflt, - .parent = &l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_DSS_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT , - .clkdm_name ="dss_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk dss_ick_3430es2 = { -/* Handles both L3 and L4 clocks */ - .name ="dss_ick" , - .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait, - .parent = &l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_DSS_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT , - .clkdm_name ="dss_clkdm" , - .recalc = &followparent_recalc, -}; - -/* CAM */ - -static struct clk cam_mclk = { - .name ="cam_mclk" , - .ops = &clkops_omap2_dflt, - .parent = &dpll4_m5x2_ck, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_CAM_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_CAM_SHIFT , - .clkdm_name ="cam_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk cam_ick = { -/* Handles both L3 and L4 clocks */ - .name ="cam_ick" , - .ops = &clkops_omap2_iclk_dflt, - .parent = &l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_CAM_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_CAM_SHIFT , - .clkdm_name ="cam_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk csi2_96m_fck = { - .name ="csi2_96m_fck" , - .ops = &clkops_omap2_dflt, - .parent = &core_96m_fck, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_CAM_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_CSI2_SHIFT , - .clkdm_name ="cam_clkdm" , - .recalc = &followparent_recalc, -}; - -/* USBHOST - 3430ES2 only */ - -static struct clk usbhost_120m_fck = { - .name ="usbhost_120m_fck" , - .ops = &clkops_omap2_dflt, - .parent = &dpll5_m2_ck, - .enable_reg =OMAP_CM_REGADDR (OMAP3430ES2_USBHOST_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430ES2_EN_USBHOST2_SHIFT , - .clkdm_name ="usbhost_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk usbhost_48m_fck = { - .name ="usbhost_48m_fck" , - .ops = &clkops_omap3430es2_dss_usbhost_wait, - .parent = &omap_48m_fck, - .enable_reg =OMAP_CM_REGADDR (OMAP3430ES2_USBHOST_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430ES2_EN_USBHOST1_SHIFT , - .clkdm_name ="usbhost_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk usbhost_ick = { -/* Handles both L3 and L4 clocks */ - .name ="usbhost_ick" , - .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait, - .parent = &l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430ES2_USBHOST_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430ES2_EN_USBHOST_SHIFT , - .clkdm_name ="usbhost_clkdm" , - .recalc = &followparent_recalc, -}; - -/* WKUP */ - -static const struct clksel_rate usim_96m_rates[] = { - { .div =2 , .val =3 , .flags =RATE_IN_3XXX }, - { .div =4 , .val =4 , .flags =RATE_IN_3XXX }, - { .div =8 , .val =5 , .flags =RATE_IN_3XXX }, - { .div =10 , .val =6 , .flags =RATE_IN_3XXX }, - { .div =0 }, -}; - -static const struct clksel_rate usim_120m_rates[] = { - { .div =4 , .val =7 , .flags =RATE_IN_3XXX }, - { .div =8 , .val =8 , .flags =RATE_IN_3XXX }, - { .div =16 , .val =9 , .flags =RATE_IN_3XXX }, - { .div =20 , .val =10 , .flags =RATE_IN_3XXX }, - { .div =0 }, -}; - -static const struct clksel usim_clksel[] = { - { .parent = &omap_96m_fck, .rates = usim_96m_rates }, - { .parent = &dpll5_m2_ck, .rates = usim_120m_rates }, - { .parent = &sys_ck, .rates = div2_rates }, - { .parent =NULL }, -}; - -/* 3430ES2 only */ -static struct clk usim_fck = { - .name ="usim_fck" , - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430ES2_EN_USIMOCP_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430ES2_CLKSEL_USIMOCP_MASK , - .clksel = usim_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ -static struct clk gpt1_fck = { - .name ="gpt1_fck" , - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_GPT1_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430_CLKSEL_GPT1_MASK , - .clksel = omap343x_gpt_clksel, - .clkdm_name ="wkup_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -static struct clk wkup_32k_fck = { - .name ="wkup_32k_fck" , - .ops = &clkops_null, - .parent = &omap_32k_fck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio1_dbck = { - .name ="gpio1_dbck" , - .ops = &clkops_omap2_dflt, - .parent = &wkup_32k_fck, - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_GPIO1_SHIFT , - .clkdm_name ="wkup_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk wdt2_fck = { - .name ="wdt2_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &wkup_32k_fck, - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_WDT2_SHIFT , - .clkdm_name ="wkup_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk wkup_l4_ick = { - .name ="wkup_l4_ick" , - .ops = &clkops_null, - .parent = &sys_ck, - .recalc = &followparent_recalc, -}; - -/* 3430ES2 only */ -/* Never specifically named in the TRM, so we have to infer a likely name */ -static struct clk usim_ick = { - .name ="usim_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430ES2_EN_USIMOCP_SHIFT , - .clkdm_name ="wkup_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk wdt2_ick = { - .name ="wdt2_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_WDT2_SHIFT , - .clkdm_name ="wkup_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk wdt1_ick = { - .name ="wdt1_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_WDT1_SHIFT , - .clkdm_name ="wkup_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpio1_ick = { - .name ="gpio1_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_GPIO1_SHIFT , - .clkdm_name ="wkup_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk omap_32ksync_ick = { - .name ="omap_32ksync_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_32KSYNC_SHIFT , - .clkdm_name ="wkup_clkdm" , - .recalc = &followparent_recalc, -}; - -/* XXX This clock no longer exists in 3430 TRM rev F */ -static struct clk gpt12_ick = { - .name ="gpt12_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_GPT12_SHIFT , - .clkdm_name ="wkup_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpt1_ick = { - .name ="gpt1_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wkup_l4_ick, - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_GPT1_SHIFT , - .clkdm_name ="wkup_clkdm" , - .recalc = &followparent_recalc, -}; - - - -/* PER clock domain */ - -static struct clk per_96m_fck = { - .name ="per_96m_fck" , - .ops = &clkops_null, - .parent = &omap_96m_alwon_fck, - .recalc = &followparent_recalc, -}; - -static struct clk per_48m_fck = { - .name ="per_48m_fck" , - .ops = &clkops_null, - .parent = &omap_48m_fck, - .recalc = &followparent_recalc, -}; - -static struct clk uart3_fck = { - .name ="uart3_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &per_48m_fck, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_UART3_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk uart4_fck = { - .name ="uart4_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &per_48m_fck, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3630_EN_UART4_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk uart4_fck_am35xx = { - .name ="uart4_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &per_48m_fck, - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP3430_EN_UART4_SHIFT , - .clkdm_name ="core_l4_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpt2_fck = { - .name ="gpt2_fck" , - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_GPT2_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430_CLKSEL_GPT2_MASK , - .clksel = omap343x_gpt_clksel, - .clkdm_name ="per_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt3_fck = { - .name ="gpt3_fck" , - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_GPT3_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430_CLKSEL_GPT3_MASK , - .clksel = omap343x_gpt_clksel, - .clkdm_name ="per_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt4_fck = { - .name ="gpt4_fck" , - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_GPT4_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430_CLKSEL_GPT4_MASK , - .clksel = omap343x_gpt_clksel, - .clkdm_name ="per_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt5_fck = { - .name ="gpt5_fck" , - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_GPT5_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430_CLKSEL_GPT5_MASK , - .clksel = omap343x_gpt_clksel, - .clkdm_name ="per_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt6_fck = { - .name ="gpt6_fck" , - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_GPT6_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430_CLKSEL_GPT6_MASK , - .clksel = omap343x_gpt_clksel, - .clkdm_name ="per_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt7_fck = { - .name ="gpt7_fck" , - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_GPT7_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430_CLKSEL_GPT7_MASK , - .clksel = omap343x_gpt_clksel, - .clkdm_name ="per_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt8_fck = { - .name ="gpt8_fck" , - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_GPT8_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430_CLKSEL_GPT8_MASK , - .clksel = omap343x_gpt_clksel, - .clkdm_name ="per_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt9_fck = { - .name ="gpt9_fck" , - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_GPT9_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP3430_CLKSEL_GPT9_MASK , - .clksel = omap343x_gpt_clksel, - .clkdm_name ="per_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -static struct clk per_32k_alwon_fck = { - .name ="per_32k_alwon_fck" , - .ops = &clkops_null, - .parent = &omap_32k_fck, - .recalc = &followparent_recalc, -}; - -static struct clk gpio6_dbck = { - .name ="gpio6_dbck" , - .ops = &clkops_omap2_dflt, - .parent = &per_32k_alwon_fck, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_GPIO6_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpio5_dbck = { - .name ="gpio5_dbck" , - .ops = &clkops_omap2_dflt, - .parent = &per_32k_alwon_fck, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_GPIO5_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpio4_dbck = { - .name ="gpio4_dbck" , - .ops = &clkops_omap2_dflt, - .parent = &per_32k_alwon_fck, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_GPIO4_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpio3_dbck = { - .name ="gpio3_dbck" , - .ops = &clkops_omap2_dflt, - .parent = &per_32k_alwon_fck, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_GPIO3_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpio2_dbck = { - .name ="gpio2_dbck" , - .ops = &clkops_omap2_dflt, - .parent = &per_32k_alwon_fck, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_GPIO2_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk wdt3_fck = { - .name ="wdt3_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &per_32k_alwon_fck, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_WDT3_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk per_l4_ick = { - .name ="per_l4_ick" , - .ops = &clkops_null, - .parent = &l4_ick, - .recalc = &followparent_recalc, -}; - -static struct clk gpio6_ick = { - .name ="gpio6_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_GPIO6_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpio5_ick = { - .name ="gpio5_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_GPIO5_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpio4_ick = { - .name ="gpio4_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_GPIO4_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpio3_ick = { - .name ="gpio3_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_GPIO3_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpio2_ick = { - .name ="gpio2_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_GPIO2_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk wdt3_ick = { - .name ="wdt3_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_WDT3_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk uart3_ick = { - .name ="uart3_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_UART3_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk uart4_ick = { - .name ="uart4_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3630_EN_UART4_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpt9_ick = { - .name ="gpt9_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_GPT9_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpt8_ick = { - .name ="gpt8_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_GPT8_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpt7_ick = { - .name ="gpt7_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_GPT7_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpt6_ick = { - .name ="gpt6_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_GPT6_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpt5_ick = { - .name ="gpt5_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_GPT5_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpt4_ick = { - .name ="gpt4_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_GPT4_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpt3_ick = { - .name ="gpt3_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_GPT3_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk gpt2_ick = { - .name ="gpt2_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_GPT2_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp2_ick = { - .name ="mcbsp2_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_MCBSP2_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp3_ick = { - .name ="mcbsp3_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_MCBSP3_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp4_ick = { - .name ="mcbsp4_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &per_l4_ick, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_ICLKEN ), - .enable_bit =OMAP3430_EN_MCBSP4_SHIFT , - .clkdm_name ="per_clkdm" , - .recalc = &followparent_recalc, -}; - -static const struct clksel mcbsp_234_clksel[] = { - { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, - { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, - { .parent =NULL } -}; - -static struct clk mcbsp2_fck = { - .name ="mcbsp2_fck" , - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_MCBSP2_SHIFT , - .clksel_reg =OMAP343X_CTRL_REGADDR (OMAP2_CONTROL_DEVCONF0 ), - .clksel_mask =OMAP2_MCBSP2_CLKS_MASK , - .clksel = mcbsp_234_clksel, - .clkdm_name ="per_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp3_fck = { - .name ="mcbsp3_fck" , - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_MCBSP3_SHIFT , - .clksel_reg =OMAP343X_CTRL_REGADDR (OMAP343X_CONTROL_DEVCONF1 ), - .clksel_mask =OMAP2_MCBSP3_CLKS_MASK , - .clksel = mcbsp_234_clksel, - .clkdm_name ="per_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp4_fck = { - .name ="mcbsp4_fck" , - .ops = &clkops_omap2_dflt_wait, - .init = &omap2_init_clksel_parent, - .enable_reg =OMAP_CM_REGADDR (OMAP3430_PER_MOD ,CM_FCLKEN ), - .enable_bit =OMAP3430_EN_MCBSP4_SHIFT , - .clksel_reg =OMAP343X_CTRL_REGADDR (OMAP343X_CONTROL_DEVCONF1 ), - .clksel_mask =OMAP2_MCBSP4_CLKS_MASK , - .clksel = mcbsp_234_clksel, - .clkdm_name ="per_clkdm" , - .recalc = &omap2_clksel_recalc, -}; - -/* EMU clocks */ - -/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ - -static const struct clksel_rate emu_src_sys_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_3XXX }, - { .div =0 }, -}; - -static const struct clksel_rate emu_src_core_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_3XXX }, - { .div =0 }, -}; - -static const struct clksel_rate emu_src_per_rates[] = { - { .div =1 , .val =2 , .flags =RATE_IN_3XXX }, - { .div =0 }, -}; - -static const struct clksel_rate emu_src_mpu_rates[] = { - { .div =1 , .val =3 , .flags =RATE_IN_3XXX }, - { .div =0 }, -}; - -static const struct clksel emu_src_clksel[] = { - { .parent = &sys_ck, .rates = emu_src_sys_rates }, - { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, - { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, - { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, - { .parent =NULL }, -}; - -/* -* Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only -* to switch the source of some of the EMU clocks. -* XXX Are there CLKEN bits for these EMU clks? -*/ -static struct clk emu_src_ck = { - .name ="emu_src_ck" , - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_EMU_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP3430_MUX_CTRL_MASK , - .clksel = emu_src_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate pclk_emu_rates[] = { - { .div =2 , .val =2 , .flags =RATE_IN_3XXX }, - { .div =3 , .val =3 , .flags =RATE_IN_3XXX }, - { .div =4 , .val =4 , .flags =RATE_IN_3XXX }, - { .div =6 , .val =6 , .flags =RATE_IN_3XXX }, - { .div =0 }, -}; - -static const struct clksel pclk_emu_clksel[] = { - { .parent = &emu_src_ck, .rates = pclk_emu_rates }, - { .parent =NULL }, -}; - -static struct clk pclk_fck = { - .name ="pclk_fck" , - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_EMU_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP3430_CLKSEL_PCLK_MASK , - .clksel = pclk_emu_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate pclkx2_emu_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_3XXX }, - { .div =2 , .val =2 , .flags =RATE_IN_3XXX }, - { .div =3 , .val =3 , .flags =RATE_IN_3XXX }, - { .div =0 }, -}; - -static const struct clksel pclkx2_emu_clksel[] = { - { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, - { .parent =NULL }, -}; - -static struct clk pclkx2_fck = { - .name ="pclkx2_fck" , - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_EMU_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP3430_CLKSEL_PCLKX2_MASK , - .clksel = pclkx2_emu_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel atclk_emu_clksel[] = { - { .parent = &emu_src_ck, .rates = div2_rates }, - { .parent =NULL }, -}; - -static struct clk atclk_fck = { - .name ="atclk_fck" , - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_EMU_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP3430_CLKSEL_ATCLK_MASK , - .clksel = atclk_emu_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk traceclk_src_fck = { - .name ="traceclk_src_fck" , - .ops = &clkops_null, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (OMAP3430_EMU_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP3430_TRACE_MUX_CTRL_MASK , - .clksel = emu_src_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate traceclk_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_3XXX },
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1.7.1
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PATCH 29/29 ARM: omap2: clk: Delete old OMAP clock data
In reply to Rajendra NayakNow that we have switched to using new common clk
data for OMAP2, delete the old one.
Signed-off-by Rajendra Nayak <[email protected]>
--- arch/arm/mach-omap2/clock2420_data.c | 2010 -------------------------------- arch/arm/mach-omap2/clock2430_data.c | 2114 ---------------------------------- 2 files changed, 0 insertions(+), 4124 deletions(-) delete mode 100644 arch/arm/mach-omap2/clock2420_data.c delete mode 100644 arch/arm/mach-omap2/clock2430_data.c
arch/arm/mach-omap2/clock2420_data.c deleted +0 -2010
@@ -1,2010 +0,0 @@ -/* -* OMAP2420 clock data -* -* Copyright (C) 2005-2009 Texas Instruments, Inc. -* Copyright (C) 2004-2011 Nokia Corporation -* -* Contacts: -* Richard Woodruff <[email protected]> -* Paul Walmsley -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License version 2 as -* published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/clk.h> -#include <linux/list.h> - -#include <plat/hardware.h> -#include <plat/clkdev_omap.h> - -#include "iomap.h" -#include "clock.h" -#include "clock2xxx.h" -#include "opp2xxx.h" -#include "cm2xxx_3xxx.h" -#include "prm2xxx_3xxx.h" -#include "prm-regbits-24xx.h" -#include "cm-regbits-24xx.h" -#include "sdrc.h" -#include "control.h" - -#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR - -/* -* 2420 clock tree. -* -* NOTE:In many cases here we are assigning a 'default' parent. In -* many cases the parent is selectable. The set parent calls will -* also switch sources. -* -* Several sources are given initial rates which may be wrong, this will -* be fixed up in the init func. -* -* Things are broadly separated below by clock domains. It is -* noteworthy that most peripherals have dependencies on multiple clock -* domains. Many get their interface clocks from the L4 domain, but get -* functional clocks from fixed sources or other core domain derived -* clocks. -*/ - -/* Base external input clocks */ -static struct clk func_32k_ck = { - .name ="func_32k_ck" , - .ops = &clkops_null, - .rate =32768 , -}; - -static struct clk secure_32k_ck = { - .name ="secure_32k_ck" , - .ops = &clkops_null, - .rate =32768 , -}; - -/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ -static struct clk osc_ck = {/* (*12, *13, 19.2, *26, 38.4)MHz */ - .name ="osc_ck" , - .ops = &clkops_oscck, - .clkdm_name ="wkup_clkdm" , - .recalc = &omap2_osc_clk_recalc, -}; - -/* Without modem likely 12MHz, with modem likely 13MHz */ -static struct clk sys_ck = {/* (*12, *13, 19.2, 26, 38.4)MHz */ - .name ="sys_ck" ,/* ~ ref_clk also */ - .ops = &clkops_null, - .parent = &osc_ck, - .recalc = &omap2xxx_sys_clk_recalc, -}; - -static struct clk alt_ck = {/* Typical 54M or 48M, may not exist */ - .name ="alt_ck" , - .ops = &clkops_null, - .rate =54000000 , -}; - -/* Optional external clock input for McBSP CLKS */ -static struct clk mcbsp_clks = { - .name ="mcbsp_clks" , - .ops = &clkops_null, -}; - -/* -* Analog domain root source clocks -*/ - -/* dpll_ck, is broken out in to special cases through clksel */ -/* REVISIT: Rate changes on dpll_ck trigger a full set change. ... -* deal with this -*/ - -static struct dpll_data dpll_dd = { - .mult_div1_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKSEL1 ), - .mult_mask =OMAP24XX_DPLL_MULT_MASK , - .div1_mask =OMAP24XX_DPLL_DIV_MASK , - .clk_bypass = &sys_ck, - .clk_ref = &sys_ck, - .control_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKEN ), - .enable_mask =OMAP24XX_EN_DPLL_MASK , - .max_multiplier =1023 , - .min_divider =1 , - .max_divider =16 , -}; - -/* -* XXX Cannot add round_rate here yet, as this is still a composite clock, -* not just a DPLL -*/ -static struct clk dpll_ck = { - .name ="dpll_ck" , - .ops = &clkops_omap2xxx_dpll_ops, - .parent = &sys_ck,/* Can be func_32k also */ - .dpll_data = &dpll_dd, - .clkdm_name ="wkup_clkdm" , - .recalc = &omap2_dpllcore_recalc, - .set_rate = &omap2_reprogram_dpllcore, -}; - -static struct clk apll96_ck = { - .name ="apll96_ck" , - .ops = &clkops_apll96, - .parent = &sys_ck, - .rate =96000000 , - .flags =ENABLE_ON_INIT , - .clkdm_name ="wkup_clkdm" , - .enable_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKEN ), - .enable_bit =OMAP24XX_EN_96M_PLL_SHIFT , -}; - -static struct clk apll54_ck = { - .name ="apll54_ck" , - .ops = &clkops_apll54, - .parent = &sys_ck, - .rate =54000000 , - .flags =ENABLE_ON_INIT , - .clkdm_name ="wkup_clkdm" , - .enable_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKEN ), - .enable_bit =OMAP24XX_EN_54M_PLL_SHIFT , -}; - -/* -* PRCM digital base sources -*/ - -/* func_54m_ck */ - -static const struct clksel_rate func_54m_apll54_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_24XX }, - { .div =0 }, -}; - -static const struct clksel_rate func_54m_alt_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_24XX }, - { .div =0 }, -}; - -static const struct clksel func_54m_clksel[] = { - { .parent = &apll54_ck, .rates = func_54m_apll54_rates, }, - { .parent = &alt_ck, .rates = func_54m_alt_rates, }, - { .parent =NULL }, -}; - -static struct clk func_54m_ck = { - .name ="func_54m_ck" , - .ops = &clkops_null, - .parent = &apll54_ck,/* can also be alt_clk */ - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP24XX_54M_SOURCE_MASK , - .clksel = func_54m_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk core_ck = { - .name ="core_ck" , - .ops = &clkops_null, - .parent = &dpll_ck,/* can also be 32k */ - .recalc = &followparent_recalc, -}; - -static struct clk func_96m_ck = { - .name ="func_96m_ck" , - .ops = &clkops_null, - .parent = &apll96_ck, - .recalc = &followparent_recalc, -}; - -/* func_48m_ck */ - -static const struct clksel_rate func_48m_apll96_rates[] = { - { .div =2 , .val =0 , .flags =RATE_IN_24XX }, - { .div =0 }, -}; - -static const struct clksel_rate func_48m_alt_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_24XX }, - { .div =0 }, -}; - -static const struct clksel func_48m_clksel[] = { - { .parent = &apll96_ck, .rates = func_48m_apll96_rates }, - { .parent = &alt_ck, .rates = func_48m_alt_rates }, - { .parent =NULL } -}; - -static struct clk func_48m_ck = { - .name ="func_48m_ck" , - .ops = &clkops_null, - .parent = &apll96_ck,/* 96M or Alt */ - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (PLL_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP24XX_48M_SOURCE_MASK , - .clksel = func_48m_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -static struct clk func_12m_ck = { - .name ="func_12m_ck" , - .ops = &clkops_null, - .parent = &func_48m_ck, - .fixed_div =4 , - .recalc = &omap_fixed_divisor_recalc, -}; - -/* Secure timer, only available in secure mode */ -static struct clk wdt1_osc_ck = { - .name ="ck_wdt1_osc" , - .ops = &clkops_null,/* RMK: missing? */ - .parent = &osc_ck, - .recalc = &followparent_recalc, -}; - -/* -* The common_clkout* clksel_rate structs are common to -* sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src. -* sys_clkout2_* are 2420-only, so the -* clksel_rate flags fields are inaccurate for those clocks. This is -* harmless since access to those clocks are gated by the struct clk -* flags fields, which mark them as 2420-only. -*/ -static const struct clksel_rate common_clkout_src_core_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_24XX }, - { .div =0 } -}; - -static const struct clksel_rate common_clkout_src_sys_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_24XX }, - { .div =0 } -}; - -static const struct clksel_rate common_clkout_src_96m_rates[] = { - { .div =1 , .val =2 , .flags =RATE_IN_24XX }, - { .div =0 } -}; - -static const struct clksel_rate common_clkout_src_54m_rates[] = { - { .div =1 , .val =3 , .flags =RATE_IN_24XX }, - { .div =0 } -}; - -static const struct clksel common_clkout_src_clksel[] = { - { .parent = &core_ck, .rates = common_clkout_src_core_rates }, - { .parent = &sys_ck, .rates = common_clkout_src_sys_rates }, - { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates }, - { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates }, - { .parent =NULL } -}; - -static struct clk sys_clkout_src = { - .name ="sys_clkout_src" , - .ops = &clkops_omap2_dflt, - .parent = &func_54m_ck, - .clkdm_name ="wkup_clkdm" , - .enable_reg =OMAP2420_PRCM_CLKOUT_CTRL , - .enable_bit =OMAP24XX_CLKOUT_EN_SHIFT , - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP2420_PRCM_CLKOUT_CTRL , - .clksel_mask =OMAP24XX_CLKOUT_SOURCE_MASK , - .clksel = common_clkout_src_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -static const struct clksel_rate common_clkout_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_24XX }, - { .div =2 , .val =1 , .flags =RATE_IN_24XX }, - { .div =4 , .val =2 , .flags =RATE_IN_24XX }, - { .div =8 , .val =3 , .flags =RATE_IN_24XX }, - { .div =16 , .val =4 , .flags =RATE_IN_24XX }, - { .div =0 }, -}; - -static const struct clksel sys_clkout_clksel[] = { - { .parent = &sys_clkout_src, .rates = common_clkout_rates }, - { .parent =NULL } -}; - -static struct clk sys_clkout = { - .name ="sys_clkout" , - .ops = &clkops_null, - .parent = &sys_clkout_src, - .clksel_reg =OMAP2420_PRCM_CLKOUT_CTRL , - .clksel_mask =OMAP24XX_CLKOUT_DIV_MASK , - .clksel = sys_clkout_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -/* In 2430, new in 2420 ES2 */ -static struct clk sys_clkout2_src = { - .name ="sys_clkout2_src" , - .ops = &clkops_omap2_dflt, - .parent = &func_54m_ck, - .clkdm_name ="wkup_clkdm" , - .enable_reg =OMAP2420_PRCM_CLKOUT_CTRL , - .enable_bit =OMAP2420_CLKOUT2_EN_SHIFT , - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP2420_PRCM_CLKOUT_CTRL , - .clksel_mask =OMAP2420_CLKOUT2_SOURCE_MASK , - .clksel = common_clkout_src_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -static const struct clksel sys_clkout2_clksel[] = { - { .parent = &sys_clkout2_src, .rates = common_clkout_rates }, - { .parent =NULL } -}; - -/* In 2430, new in 2420 ES2 */ -static struct clk sys_clkout2 = { - .name ="sys_clkout2" , - .ops = &clkops_null, - .parent = &sys_clkout2_src, - .clksel_reg =OMAP2420_PRCM_CLKOUT_CTRL , - .clksel_mask =OMAP2420_CLKOUT2_DIV_MASK , - .clksel = sys_clkout2_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -static struct clk emul_ck = { - .name ="emul_ck" , - .ops = &clkops_omap2_dflt, - .parent = &func_54m_ck, - .clkdm_name ="wkup_clkdm" , - .enable_reg =OMAP2420_PRCM_CLKEMUL_CTRL , - .enable_bit =OMAP24XX_EMULATION_EN_SHIFT , - .recalc = &followparent_recalc, - -}; - -/* -* MPU clock domain -* Clocks: -* MPU_FCLK, MPU_ICLK -* INT_M_FCLK, INT_M_I_CLK -* -* - Individual clocks are hardware managed. -* - Base divider comes from: CM_CLKSEL_MPU -* -*/ -static const struct clksel_rate mpu_core_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_24XX }, - { .div =2 , .val =2 , .flags =RATE_IN_24XX }, - { .div =4 , .val =4 , .flags =RATE_IN_242X }, - { .div =6 , .val =6 , .flags =RATE_IN_242X }, - { .div =8 , .val =8 , .flags =RATE_IN_242X }, - { .div =0 }, -}; - -static const struct clksel mpu_clksel[] = { - { .parent = &core_ck, .rates = mpu_core_rates }, - { .parent =NULL } -}; - -static struct clk mpu_ck = {/* Control cpu */ - .name ="mpu_ck" , - .ops = &clkops_null, - .parent = &core_ck, - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (MPU_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP24XX_CLKSEL_MPU_MASK , - .clksel = mpu_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* -* DSP (2420-UMA+IVA1) clock domain -* Clocks: -* 2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP -* -* Won't be too specific here. The core clock comes into this block -* it is divided then tee'ed. One branch goes directly to xyz enable -* controls. The other branch gets further divided by 2 then possibly -* routed into a synchronizer and out of clocks abc. -*/ -static const struct clksel_rate dsp_fck_core_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_24XX }, - { .div =2 , .val =2 , .flags =RATE_IN_24XX }, - { .div =3 , .val =3 , .flags =RATE_IN_24XX }, - { .div =4 , .val =4 , .flags =RATE_IN_24XX }, - { .div =6 , .val =6 , .flags =RATE_IN_242X }, - { .div =8 , .val =8 , .flags =RATE_IN_242X }, - { .div =12 , .val =12 , .flags =RATE_IN_242X }, - { .div =0 }, -}; - -static const struct clksel dsp_fck_clksel[] = { - { .parent = &core_ck, .rates = dsp_fck_core_rates }, - { .parent =NULL } -}; - -static struct clk dsp_fck = { - .name ="dsp_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_ck, - .clkdm_name ="dsp_clkdm" , - .enable_reg =OMAP_CM_REGADDR (OMAP24XX_DSP_MOD ,CM_FCLKEN ), - .enable_bit =OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (OMAP24XX_DSP_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP24XX_CLKSEL_DSP_MASK , - .clksel = dsp_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel dsp_ick_clksel[] = { - { .parent = &dsp_fck, .rates = dsp_ick_rates }, - { .parent =NULL } -}; - -static struct clk dsp_ick = { - .name ="dsp_ick" ,/* apparently ipi and isp */ - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &dsp_fck, - .clkdm_name ="dsp_clkdm" , - .enable_reg =OMAP_CM_REGADDR (OMAP24XX_DSP_MOD ,CM_ICLKEN ), - .enable_bit =OMAP2420_EN_DSP_IPI_SHIFT ,/* for ipi */ - .clksel_reg =OMAP_CM_REGADDR (OMAP24XX_DSP_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP24XX_CLKSEL_DSP_IF_MASK , - .clksel = dsp_ick_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* -* The IVA1 is an ARM7 core on the 2420 that has nothing to do with -* the C54x, but which is contained in the DSP powerdomain. Does not -* exist on later OMAPs. -*/ -static struct clk iva1_ifck = { - .name ="iva1_ifck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_ck, - .clkdm_name ="iva1_clkdm" , - .enable_reg =OMAP_CM_REGADDR (OMAP24XX_DSP_MOD ,CM_FCLKEN ), - .enable_bit =OMAP2420_EN_IVA_COP_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (OMAP24XX_DSP_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP2420_CLKSEL_IVA_MASK , - .clksel = dsp_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* IVA1 mpu/int/i/f clocks are /2 of parent */ -static struct clk iva1_mpu_int_ifck = { - .name ="iva1_mpu_int_ifck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &iva1_ifck, - .clkdm_name ="iva1_clkdm" , - .enable_reg =OMAP_CM_REGADDR (OMAP24XX_DSP_MOD ,CM_FCLKEN ), - .enable_bit =OMAP2420_EN_IVA_MPU_SHIFT , - .fixed_div =2 , - .recalc = &omap_fixed_divisor_recalc, -}; - -/* -* L3 clock domain -* L3 clocks are used for both interface and functional clocks to -* multiple entities. Some of these clocks are completely managed -* by hardware, and some others allow software control. Hardware -* managed ones general are based on directly CLK_REQ signals and -* various auto idle settings. The functional spec sets many of these -* as 'tie-high' for their enables. -* -* I-CLOCKS: -* L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA -* CAM, HS-USB. -* F-CLOCK -* SSI. -* -* GPMC memories and SDRC have timing and clock sensitive registers which -* may very well need notification when the clock changes. Currently for low -* operating points, these are taken care of in sleep.S. -*/ -static const struct clksel_rate core_l3_core_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_24XX }, - { .div =2 , .val =2 , .flags =RATE_IN_242X }, - { .div =4 , .val =4 , .flags =RATE_IN_24XX }, - { .div =6 , .val =6 , .flags =RATE_IN_24XX }, - { .div =8 , .val =8 , .flags =RATE_IN_242X }, - { .div =12 , .val =12 , .flags =RATE_IN_242X }, - { .div =16 , .val =16 , .flags =RATE_IN_242X }, - { .div =0 } -}; - -static const struct clksel core_l3_clksel[] = { - { .parent = &core_ck, .rates = core_l3_core_rates }, - { .parent =NULL } -}; - -static struct clk core_l3_ck = {/* Used for ick and fck, interconnect */ - .name ="core_l3_ck" , - .ops = &clkops_null, - .parent = &core_ck, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP24XX_CLKSEL_L3_MASK , - .clksel = core_l3_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* usb_l4_ick */ -static const struct clksel_rate usb_l4_ick_core_l3_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_24XX }, - { .div =2 , .val =2 , .flags =RATE_IN_24XX }, - { .div =4 , .val =4 , .flags =RATE_IN_24XX }, - { .div =0 } -}; - -static const struct clksel usb_l4_ick_clksel[] = { - { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates }, - { .parent =NULL }, -}; - -/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ -static struct clk usb_l4_ick = {/* FS-USB interface clock */ - .name ="usb_l4_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l3_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN2 ), - .enable_bit =OMAP24XX_EN_USB_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP24XX_CLKSEL_USB_MASK , - .clksel = usb_l4_ick_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* -* L4 clock management domain -* -* This domain contains lots of interface clocks from the L4 interface, some -* functional clocks. Fixed APLL functional source clocks are managed in -* this domain. -*/ -static const struct clksel_rate l4_core_l3_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_24XX }, - { .div =2 , .val =2 , .flags =RATE_IN_24XX }, - { .div =0 } -}; - -static const struct clksel l4_clksel[] = { - { .parent = &core_l3_ck, .rates = l4_core_l3_rates }, - { .parent =NULL } -}; - -static struct clk l4_ck = {/* used both as an ick and fck */ - .name ="l4_ck" , - .ops = &clkops_null, - .parent = &core_l3_ck, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP24XX_CLKSEL_L4_MASK , - .clksel = l4_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* -* SSI is in L3 management domain, its direct parent is core not l3, -* many core power domain entities are grouped into the L3 clock -* domain. -* SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK -* -* ssr = core/1/2/3/4/5, sst = 1/2 ssr. -*/ -static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_24XX }, - { .div =2 , .val =2 , .flags =RATE_IN_24XX }, - { .div =3 , .val =3 , .flags =RATE_IN_24XX }, - { .div =4 , .val =4 , .flags =RATE_IN_24XX }, - { .div =6 , .val =6 , .flags =RATE_IN_242X }, - { .div =8 , .val =8 , .flags =RATE_IN_242X }, - { .div =0 } -}; - -static const struct clksel ssi_ssr_sst_fck_clksel[] = { - { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates }, - { .parent =NULL } -}; - -static struct clk ssi_ssr_sst_fck = { - .name ="ssi_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_ck, - .clkdm_name ="core_l3_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,OMAP24XX_CM_FCLKEN2 ), - .enable_bit =OMAP24XX_EN_SSI_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP24XX_CLKSEL_SSI_MASK , - .clksel = ssi_ssr_sst_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* -* Presumably this is the same as SSI_ICLK. -* TRM contradicts itself on what clockdomain SSI_ICLK is in -*/ -static struct clk ssi_l4_ick = { - .name ="ssi_l4_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN2 ), - .enable_bit =OMAP24XX_EN_SSI_SHIFT , - .recalc = &followparent_recalc, -}; - - -/* -* GFX clock domain -* Clocks: -* GFX_FCLK, GFX_ICLK -* GFX_CG1(2d), GFX_CG2(3d) -* -* GFX_FCLK runs from L3, and is divided by (1,2,3,4) -* The 2d and 3d clocks run at a hardware determined -* divided value of fclk. -* -*/ - -/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */ -static const struct clksel gfx_fck_clksel[] = { - { .parent = &core_l3_ck, .rates = gfx_l3_rates }, - { .parent =NULL }, -}; - -static struct clk gfx_3d_fck = { - .name ="gfx_3d_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l3_ck, - .clkdm_name ="gfx_clkdm" , - .enable_reg =OMAP_CM_REGADDR (GFX_MOD ,CM_FCLKEN ), - .enable_bit =OMAP24XX_EN_3D_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (GFX_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP_CLKSEL_GFX_MASK , - .clksel = gfx_fck_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -static struct clk gfx_2d_fck = { - .name ="gfx_2d_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l3_ck, - .clkdm_name ="gfx_clkdm" , - .enable_reg =OMAP_CM_REGADDR (GFX_MOD ,CM_FCLKEN ), - .enable_bit =OMAP24XX_EN_2D_SHIFT , - .clksel_reg =OMAP_CM_REGADDR (GFX_MOD ,CM_CLKSEL ), - .clksel_mask =OMAP_CLKSEL_GFX_MASK , - .clksel = gfx_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -/* This interface clock does not have a CM_AUTOIDLE bit */ -static struct clk gfx_ick = { - .name ="gfx_ick" ,/* From l3 */ - .ops = &clkops_omap2_dflt_wait, - .parent = &core_l3_ck, - .clkdm_name ="gfx_clkdm" , - .enable_reg =OMAP_CM_REGADDR (GFX_MOD ,CM_ICLKEN ), - .enable_bit =OMAP_EN_GFX_SHIFT , - .recalc = &followparent_recalc, -}; - -/* -* DSS clock domain -* CLOCKs: -* DSS_L4_ICLK, DSS_L3_ICLK, -* DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK -* -* DSS is both initiator and target. -*/ -/* XXX Add RATE_NOT_VALIDATED */ - -static const struct clksel_rate dss1_fck_sys_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_24XX }, - { .div =0 } -}; - -static const struct clksel_rate dss1_fck_core_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_24XX }, - { .div =2 , .val =2 , .flags =RATE_IN_24XX }, - { .div =3 , .val =3 , .flags =RATE_IN_24XX }, - { .div =4 , .val =4 , .flags =RATE_IN_24XX }, - { .div =5 , .val =5 , .flags =RATE_IN_24XX }, - { .div =6 , .val =6 , .flags =RATE_IN_24XX }, - { .div =8 , .val =8 , .flags =RATE_IN_24XX }, - { .div =9 , .val =9 , .flags =RATE_IN_24XX }, - { .div =12 , .val =12 , .flags =RATE_IN_24XX }, - { .div =16 , .val =16 , .flags =RATE_IN_24XX }, - { .div =0 } -}; - -static const struct clksel dss1_fck_clksel[] = { - { .parent = &sys_ck, .rates = dss1_fck_sys_rates }, - { .parent = &core_ck, .rates = dss1_fck_core_rates }, - { .parent =NULL }, -}; - -static struct clk dss_ick = {/* Enables both L3,L4 ICLK's */ - .name ="dss_ick" , - .ops = &clkops_omap2_iclk_dflt, - .parent = &l4_ck,/* really both l3 and l4 */ - .clkdm_name ="dss_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_DSS1_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk dss1_fck = { - .name ="dss1_fck" , - .ops = &clkops_omap2_dflt, - .parent = &core_ck,/* Core or sys */ - .clkdm_name ="dss_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_DSS1_SHIFT , - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP24XX_CLKSEL_DSS1_MASK , - .clksel = dss1_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static const struct clksel_rate dss2_fck_sys_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_24XX }, - { .div =0 } -}; - -static const struct clksel_rate dss2_fck_48m_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_24XX }, - { .div =0 } -}; - -static const struct clksel dss2_fck_clksel[] = { - { .parent = &sys_ck, .rates = dss2_fck_sys_rates }, - { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates }, - { .parent =NULL } -}; - -static struct clk dss2_fck = {/* Alt clk used in power management */ - .name ="dss2_fck" , - .ops = &clkops_omap2_dflt, - .parent = &sys_ck,/* fixed at sys_ck or 48MHz */ - .clkdm_name ="dss_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_DSS2_SHIFT , - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP24XX_CLKSEL_DSS2_MASK , - .clksel = dss2_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk dss_54m_fck = {/* Alt clk used in power management */ - .name ="dss_54m_fck" ,/* 54m tv clk */ - .ops = &clkops_omap2_dflt_wait, - .parent = &func_54m_ck, - .clkdm_name ="dss_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_TV_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk wu_l4_ick = { - .name ="wu_l4_ick" , - .ops = &clkops_null, - .parent = &sys_ck, - .recalc = &followparent_recalc, -}; - -/* -* CORE power domain ICLK & FCLK defines. -* Many of the these can have more than one possible parent. Entries -* here will likely have an L4 interface parent, and may have multiple -* functional clock parents. -*/ -static const struct clksel_rate gpt_alt_rates[] = { - { .div =1 , .val =2 , .flags =RATE_IN_24XX }, - { .div =0 } -}; - -static const struct clksel omap24xx_gpt_clksel[] = { - { .parent = &func_32k_ck, .rates = gpt_32k_rates }, - { .parent = &sys_ck, .rates = gpt_sys_rates }, - { .parent = &alt_ck, .rates = gpt_alt_rates }, - { .parent =NULL }, -}; - -static struct clk gpt1_ick = { - .name ="gpt1_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wu_l4_ick, - .clkdm_name ="wkup_clkdm" , - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_ICLKEN ), - .enable_bit =OMAP24XX_EN_GPT1_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk gpt1_fck = { - .name ="gpt1_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_FCLKEN ), - .enable_bit =OMAP24XX_EN_GPT1_SHIFT , - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP24XX_CLKSEL_GPT1_MASK , - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, - .round_rate = &omap2_clksel_round_rate, - .set_rate = &omap2_clksel_set_rate -}; - -static struct clk gpt2_ick = { - .name ="gpt2_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT2_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk gpt2_fck = { - .name ="gpt2_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT2_SHIFT , - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL2 ), - .clksel_mask =OMAP24XX_CLKSEL_GPT2_MASK , - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt3_ick = { - .name ="gpt3_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT3_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk gpt3_fck = { - .name ="gpt3_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT3_SHIFT , - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL2 ), - .clksel_mask =OMAP24XX_CLKSEL_GPT3_MASK , - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt4_ick = { - .name ="gpt4_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT4_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk gpt4_fck = { - .name ="gpt4_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT4_SHIFT , - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL2 ), - .clksel_mask =OMAP24XX_CLKSEL_GPT4_MASK , - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt5_ick = { - .name ="gpt5_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT5_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk gpt5_fck = { - .name ="gpt5_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT5_SHIFT , - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL2 ), - .clksel_mask =OMAP24XX_CLKSEL_GPT5_MASK , - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt6_ick = { - .name ="gpt6_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT6_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk gpt6_fck = { - .name ="gpt6_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT6_SHIFT , - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL2 ), - .clksel_mask =OMAP24XX_CLKSEL_GPT6_MASK , - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt7_ick = { - .name ="gpt7_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT7_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk gpt7_fck = { - .name ="gpt7_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT7_SHIFT , - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL2 ), - .clksel_mask =OMAP24XX_CLKSEL_GPT7_MASK , - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt8_ick = { - .name ="gpt8_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT8_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk gpt8_fck = { - .name ="gpt8_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT8_SHIFT , - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL2 ), - .clksel_mask =OMAP24XX_CLKSEL_GPT8_MASK , - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt9_ick = { - .name ="gpt9_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT9_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk gpt9_fck = { - .name ="gpt9_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT9_SHIFT , - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL2 ), - .clksel_mask =OMAP24XX_CLKSEL_GPT9_MASK , - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt10_ick = { - .name ="gpt10_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT10_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk gpt10_fck = { - .name ="gpt10_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT10_SHIFT , - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL2 ), - .clksel_mask =OMAP24XX_CLKSEL_GPT10_MASK , - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt11_ick = { - .name ="gpt11_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT11_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk gpt11_fck = { - .name ="gpt11_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT11_SHIFT , - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL2 ), - .clksel_mask =OMAP24XX_CLKSEL_GPT11_MASK , - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk gpt12_ick = { - .name ="gpt12_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT12_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk gpt12_fck = { - .name ="gpt12_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &secure_32k_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_GPT12_SHIFT , - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL2 ), - .clksel_mask =OMAP24XX_CLKSEL_GPT12_MASK , - .clksel = omap24xx_gpt_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp1_ick = { - .name ="mcbsp1_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_MCBSP1_SHIFT , - .recalc = &followparent_recalc, -}; - -static const struct clksel_rate common_mcbsp_96m_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_24XX }, - { .div =0 } -}; - -static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_24XX }, - { .div =0 } -}; - -static const struct clksel mcbsp_fck_clksel[] = { - { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates }, - { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, - { .parent =NULL } -}; - -static struct clk mcbsp1_fck = { - .name ="mcbsp1_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .init = &omap2_init_clksel_parent, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_MCBSP1_SHIFT , - .clksel_reg =OMAP242X_CTRL_REGADDR (OMAP2_CONTROL_DEVCONF0 ), - .clksel_mask =OMAP2_MCBSP1_CLKS_MASK , - .clksel = mcbsp_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcbsp2_ick = { - .name ="mcbsp2_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_MCBSP2_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk mcbsp2_fck = { - .name ="mcbsp2_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .init = &omap2_init_clksel_parent, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_MCBSP2_SHIFT , - .clksel_reg =OMAP242X_CTRL_REGADDR (OMAP2_CONTROL_DEVCONF0 ), - .clksel_mask =OMAP2_MCBSP2_CLKS_MASK , - .clksel = mcbsp_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk mcspi1_ick = { - .name ="mcspi1_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_MCSPI1_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk mcspi1_fck = { - .name ="mcspi1_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_MCSPI1_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk mcspi2_ick = { - .name ="mcspi2_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_MCSPI2_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk mcspi2_fck = { - .name ="mcspi2_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_MCSPI2_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk uart1_ick = { - .name ="uart1_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_UART1_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk uart1_fck = { - .name ="uart1_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_UART1_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk uart2_ick = { - .name ="uart2_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_UART2_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk uart2_fck = { - .name ="uart2_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_UART2_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk uart3_ick = { - .name ="uart3_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN2 ), - .enable_bit =OMAP24XX_EN_UART3_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk uart3_fck = { - .name ="uart3_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,OMAP24XX_CM_FCLKEN2 ), - .enable_bit =OMAP24XX_EN_UART3_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk gpios_ick = { - .name ="gpios_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wu_l4_ick, - .clkdm_name ="wkup_clkdm" , - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_ICLKEN ), - .enable_bit =OMAP24XX_EN_GPIOS_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk gpios_fck = { - .name ="gpios_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name ="wkup_clkdm" , - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_FCLKEN ), - .enable_bit =OMAP24XX_EN_GPIOS_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk mpu_wdt_ick = { - .name ="mpu_wdt_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wu_l4_ick, - .clkdm_name ="wkup_clkdm" , - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_ICLKEN ), - .enable_bit =OMAP24XX_EN_MPU_WDT_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk mpu_wdt_fck = { - .name ="mpu_wdt_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name ="wkup_clkdm" , - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_FCLKEN ), - .enable_bit =OMAP24XX_EN_MPU_WDT_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk sync_32k_ick = { - .name ="sync_32k_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wu_l4_ick, - .clkdm_name ="wkup_clkdm" , - .flags =ENABLE_ON_INIT , - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_ICLKEN ), - .enable_bit =OMAP24XX_EN_32KSYNC_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk wdt1_ick = { - .name ="wdt1_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wu_l4_ick, - .clkdm_name ="wkup_clkdm" , - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_ICLKEN ), - .enable_bit =OMAP24XX_EN_WDT1_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk omapctrl_ick = { - .name ="omapctrl_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &wu_l4_ick, - .clkdm_name ="wkup_clkdm" , - .flags =ENABLE_ON_INIT , - .enable_reg =OMAP_CM_REGADDR (WKUP_MOD ,CM_ICLKEN ), - .enable_bit =OMAP24XX_EN_OMAPCTRL_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk cam_ick = { - .name ="cam_ick" , - .ops = &clkops_omap2_iclk_dflt, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_CAM_SHIFT , - .recalc = &followparent_recalc, -}; - -/* -* cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be -* split into two separate clocks, since the parent clocks are different -* and the clockdomains are also different. -*/ -static struct clk cam_fck = { - .name ="cam_fck" , - .ops = &clkops_omap2_dflt, - .parent = &func_96m_ck, - .clkdm_name ="core_l3_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_CAM_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk mailboxes_ick = { - .name ="mailboxes_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_MAILBOXES_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk wdt4_ick = { - .name ="wdt4_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_WDT4_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk wdt4_fck = { - .name ="wdt4_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_WDT4_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk wdt3_ick = { - .name ="wdt3_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP2420_EN_WDT3_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk wdt3_fck = { - .name ="wdt3_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_32k_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP2420_EN_WDT3_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk mspro_ick = { - .name ="mspro_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_MSPRO_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk mspro_fck = { - .name ="mspro_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_MSPRO_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk mmc_ick = { - .name ="mmc_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP2420_EN_MMC_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk mmc_fck = { - .name ="mmc_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP2420_EN_MMC_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk fac_ick = { - .name ="fac_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_FAC_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk fac_fck = { - .name ="fac_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_12m_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_FAC_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk eac_ick = { - .name ="eac_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP2420_EN_EAC_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk eac_fck = { - .name ="eac_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP2420_EN_EAC_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk hdq_ick = { - .name ="hdq_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP24XX_EN_HDQ_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk hdq_fck = { - .name ="hdq_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_12m_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP24XX_EN_HDQ_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk i2c2_ick = { - .name ="i2c2_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP2420_EN_I2C2_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk i2c2_fck = { - .name ="i2c2_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_12m_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP2420_EN_I2C2_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk i2c1_ick = { - .name ="i2c1_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP2420_EN_I2C1_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk i2c1_fck = { - .name ="i2c1_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_12m_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP2420_EN_I2C1_SHIFT , - .recalc = &followparent_recalc, -}; - -/* -* The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE -* accesses derived from this data. -*/ -static struct clk gpmc_fck = { - .name ="gpmc_fck" , - .ops = &clkops_omap2_iclk_idle_only, - .parent = &core_l3_ck, - .flags =ENABLE_ON_INIT , - .clkdm_name ="core_l3_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN3 ), - .enable_bit =OMAP24XX_AUTO_GPMC_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk sdma_fck = { - .name ="sdma_fck" , - .ops = &clkops_null,/* RMK: missing? */ - .parent = &core_l3_ck, - .recalc = &followparent_recalc, -}; - -/* -* The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE -* accesses derived from this data. -*/ -static struct clk sdma_ick = { - .name ="sdma_ick" , - .ops = &clkops_omap2_iclk_idle_only, - .parent = &core_l3_ck, - .clkdm_name ="core_l3_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN3 ), - .enable_bit =OMAP24XX_AUTO_SDMA_SHIFT , - .recalc = &followparent_recalc, -}; - -/* -* The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE -* accesses derived from this data. -*/ -static struct clk sdrc_ick = { - .name ="sdrc_ick" , - .ops = &clkops_omap2_iclk_idle_only, - .parent = &core_l3_ck, - .flags =ENABLE_ON_INIT , - .clkdm_name ="core_l3_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN3 ), - .enable_bit =OMAP24XX_AUTO_SDRC_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk vlynq_ick = { - .name ="vlynq_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &core_l3_ck, - .clkdm_name ="core_l3_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_ICLKEN1 ), - .enable_bit =OMAP2420_EN_VLYNQ_SHIFT , - .recalc = &followparent_recalc, -}; - -static const struct clksel_rate vlynq_fck_96m_rates[] = { - { .div =1 , .val =0 , .flags =RATE_IN_242X }, - { .div =0 } -}; - -static const struct clksel_rate vlynq_fck_core_rates[] = { - { .div =1 , .val =1 , .flags =RATE_IN_242X }, - { .div =2 , .val =2 , .flags =RATE_IN_242X }, - { .div =3 , .val =3 , .flags =RATE_IN_242X }, - { .div =4 , .val =4 , .flags =RATE_IN_242X }, - { .div =6 , .val =6 , .flags =RATE_IN_242X }, - { .div =8 , .val =8 , .flags =RATE_IN_242X }, - { .div =9 , .val =9 , .flags =RATE_IN_242X }, - { .div =12 , .val =12 , .flags =RATE_IN_242X }, - { .div =16 , .val =16 , .flags =RATE_IN_242X }, - { .div =18 , .val =18 , .flags =RATE_IN_242X }, - { .div =0 } -}; - -static const struct clksel vlynq_fck_clksel[] = { - { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates }, - { .parent = &core_ck, .rates = vlynq_fck_core_rates }, - { .parent =NULL } -}; - -static struct clk vlynq_fck = { - .name ="vlynq_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_96m_ck, - .clkdm_name ="core_l3_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_FCLKEN1 ), - .enable_bit =OMAP2420_EN_VLYNQ_SHIFT , - .init = &omap2_init_clksel_parent, - .clksel_reg =OMAP_CM_REGADDR (CORE_MOD ,CM_CLKSEL1 ), - .clksel_mask =OMAP2420_CLKSEL_VLYNQ_MASK , - .clksel = vlynq_fck_clksel, - .recalc = &omap2_clksel_recalc, -}; - -static struct clk des_ick = { - .name ="des_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,OMAP24XX_CM_ICLKEN4 ), - .enable_bit =OMAP24XX_EN_DES_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk sha_ick = { - .name ="sha_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,OMAP24XX_CM_ICLKEN4 ), - .enable_bit =OMAP24XX_EN_SHA_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk rng_ick = { - .name ="rng_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,OMAP24XX_CM_ICLKEN4 ), - .enable_bit =OMAP24XX_EN_RNG_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk aes_ick = { - .name ="aes_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,OMAP24XX_CM_ICLKEN4 ), - .enable_bit =OMAP24XX_EN_AES_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk pka_ick = { - .name ="pka_ick" , - .ops = &clkops_omap2_iclk_dflt_wait, - .parent = &l4_ck, - .clkdm_name ="core_l4_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,OMAP24XX_CM_ICLKEN4 ), - .enable_bit =OMAP24XX_EN_PKA_SHIFT , - .recalc = &followparent_recalc, -}; - -static struct clk usb_fck = { - .name ="usb_fck" , - .ops = &clkops_omap2_dflt_wait, - .parent = &func_48m_ck, - .clkdm_name ="core_l3_clkdm" , - .enable_reg =OMAP_CM_REGADDR (CORE_MOD ,OMAP24XX_CM_FCLKEN2 ), - .enable_bit =OMAP24XX_EN_USB_SHIFT , - .recalc = &followparent_recalc, -}; - -/* -* This clock is a composite clock which does entire set changes then -* forces a rebalance. It keys on the MPU speed, but it really could -* be any key speed part of a set in the rate table. -* -* to really change a set, you need memory table sets which get changed -* in sram, pre-notifiers & post notifiers, changing the top set, without -* having low level display recalc's won't work... this is why dpm notifiers -* work, isr's off, walk a list of clocks already _off_ and not messing with -* the bus. -* -* This clock should have no parent. It embodies the entire upper level -* active set. A parent will mess up some of the init also. -*/ -static struct clk virt_prcm_set = { - .name ="virt_prcm_set" , - .ops = &clkops_null, - .parent = &mpu_ck,/* Indexed by mpu speed, no parent */ - .recalc = &omap2_table_mpu_recalc,/* sets are keyed on mpu rate */ - .set_rate = &omap2_select_table_rate, - .round_rate = &omap2_round_to_table_rate, -}; - - -/* -* clkdev integration -*/ - -static struct omap_clk omap2420_clks[] = { -/* external root sources */ -CLK (NULL ,"func_32k_ck" , &func_32k_ck,CK_242X ), -CLK (NULL ,"secure_32k_ck" , &secure_32k_ck,CK_242X ), -CLK (NULL ,"osc_ck" , &osc_ck,CK_242X ), -CLK (NULL ,"sys_ck" , &sys_ck,CK_242X ), -CLK (NULL ,"alt_ck" , &alt_ck,CK_242X ), -CLK ("omap-mcbsp.1" ,"pad_fck" , &mcbsp_clks,CK_242X ), -CLK ("omap-mcbsp.2" ,"pad_fck" , &mcbsp_clks,CK_242X ), -CLK (NULL ,"mcbsp_clks" , &mcbsp_clks,CK_242X ), -/* internal analog sources */ -CLK (NULL ,"dpll_ck" , &dpll_ck,CK_242X ), -CLK (NULL ,"apll96_ck" , &apll96_ck,CK_242X ), -CLK (NULL ,"apll54_ck" , &apll54_ck,CK_242X ), -/* internal prcm root sources */ -CLK (NULL ,"func_54m_ck" , &func_54m_ck,CK_242X ), -CLK (NULL ,"core_ck" , &core_ck,CK_242X ), -CLK ("omap-mcbsp.1" ,"prcm_fck" , &func_96m_ck,CK_242X ), -CLK ("omap-mcbsp.2" ,"prcm_fck" , &func_96m_ck,CK_242X ), -CLK (NULL ,"func_96m_ck" , &func_96m_ck,CK_242X ), -CLK (NULL ,"func_48m_ck" , &func_48m_ck,CK_242X ), -CLK (NULL ,"func_12m_ck" , &func_12m_ck,CK_242X ), -CLK (NULL ,"ck_wdt1_osc" , &wdt1_osc_ck,CK_242X ), -CLK (NULL ,"sys_clkout_src" , &sys_clkout_src,CK_242X ), -CLK (NULL ,"sys_clkout" , &sys_clkout,CK_242X ), -CLK (NULL ,"sys_clkout2_src" , &sys_clkout2_src,CK_242X ), -CLK (NULL ,"sys_clkout2" , &sys_clkout2,CK_242X ), -CLK (NULL ,"emul_ck" , &emul_ck,CK_242X ), -/* mpu domain clocks */ -CLK (NULL ,"mpu_ck" , &mpu_ck,CK_242X ), -/* dsp domain clocks */ -CLK (NULL ,"dsp_fck" , &dsp_fck,CK_242X ), -CLK (NULL ,"dsp_ick" , &dsp_ick,CK_242X ), -CLK (NULL ,"iva1_ifck" , &iva1_ifck,CK_242X ), -CLK (NULL ,"iva1_mpu_int_ifck" , &iva1_mpu_int_ifck,CK_242X ), -/* GFX domain clocks */ -CLK (NULL ,"gfx_3d_fck" , &gfx_3d_fck,CK_242X ), -CLK (NULL ,"gfx_2d_fck" , &gfx_2d_fck,CK_242X ), -CLK (NULL ,"gfx_ick" , &gfx_ick,CK_242X ), -/* DSS domain clocks */ -CLK ("omapdss_dss" ,"ick" , &dss_ick,CK_242X ), -CLK (NULL ,"dss_ick" , &dss_ick,CK_242X ), -CLK (NULL ,"dss1_fck" , &dss1_fck,CK_242X ), -CLK (NULL ,"dss2_fck" , &dss2_fck,CK_242X ), -CLK (NULL ,"dss_54m_fck" , &dss_54m_fck,CK_242X ), -/* L3 domain clocks */ -CLK (NULL ,"core_l3_ck" , &core_l3_ck,CK_242X ), -CLK (NULL ,"ssi_fck" , &ssi_ssr_sst_fck,CK_242X ), -CLK (NULL ,"usb_l4_ick" , &usb_l4_ick,CK_242X ), -/* L4 domain clocks */ -CLK (NULL ,"l4_ck" , &l4_ck,CK_242X ), -CLK (NULL ,"ssi_l4_ick" , &ssi_l4_ick,CK_242X ), -CLK (NULL ,"wu_l4_ick" , &wu_l4_ick,CK_242X ), -/* virtual meta-group clock */ -CLK (NULL ,"virt_prcm_set" , &virt_prcm_set,CK_242X ), -/* general l4 interface ck, multi-parent functional clk */ -CLK (NULL ,"gpt1_ick" , &gpt1_ick,CK_242X ), -CLK (NULL ,"gpt1_fck" , &gpt1_fck,CK_242X ), -CLK (NULL ,"gpt2_ick" , &gpt2_ick,CK_242X ), -CLK (NULL ,"gpt2_fck" , &gpt2_fck,CK_242X ), -CLK (NULL ,"gpt3_ick" , &gpt3_ick,CK_242X ), -CLK (NULL ,"gpt3_fck" , &gpt3_fck,CK_242X ), -CLK (NULL ,"gpt4_ick" , &gpt4_ick,CK_242X ), -CLK (NULL ,"gpt4_fck" , &gpt4_fck,CK_242X ), -CLK (NULL ,"gpt5_ick" , &gpt5_ick,CK_242X ), -CLK (NULL ,"gpt5_fck" , &gpt5_fck,CK_242X ), -CLK (NULL ,"gpt6_ick" , &gpt6_ick,CK_242X ), -CLK (NULL ,"gpt6_fck" , &gpt6_fck,CK_242X ), -CLK (NULL ,"gpt7_ick" , &gpt7_ick,CK_242X ), -CLK (NULL ,"gpt7_fck" , &gpt7_fck,CK_242X ), -CLK (NULL ,"gpt8_ick" , &gpt8_ick,CK_242X ), -CLK (NULL ,"gpt8_fck" , &gpt8_fck,CK_242X ), -CLK (NULL ,"gpt9_ick" , &gpt9_ick,CK_242X ), -CLK (NULL ,"gpt9_fck" , &gpt9_fck,CK_242X ), -CLK (NULL ,"gpt10_ick" , &gpt10_ick,CK_242X ), -CLK (NULL ,"gpt10_fck" , &gpt10_fck,CK_242X ), -CLK (NULL ,"gpt11_ick" , &gpt11_ick,CK_242X ), -CLK (NULL ,"gpt11_fck" , &gpt11_fck,CK_242X ), -CLK (NULL ,"gpt12_ick" , &gpt12_ick,CK_242X ), -CLK (NULL ,"gpt12_fck" , &gpt12_fck,CK_242X ), -CLK ("omap-mcbsp.1" ,"ick" , &mcbsp1_ick,CK_242X ), -CLK (NULL ,"mcbsp1_ick" , &mcbsp1_ick,CK_242X ), -CLK (NULL ,"mcbsp1_fck" , &mcbsp1_fck,CK_242X ), -CLK ("omap-mcbsp.2" ,"ick" , &mcbsp2_ick,CK_242X ), -CLK (NULL ,"mcbsp2_ick" , &mcbsp2_ick,CK_242X ), -CLK (NULL ,"mcbsp2_fck" , &mcbsp2_fck,CK_242X ), -CLK ("omap2_mcspi.1" ,"ick" , &mcspi1_ick,CK_242X ), -CLK (NULL ,"mcspi1_ick" , &mcspi1_ick,CK_242X ), -CLK (NULL ,"mcspi1_fck" , &mcspi1_fck,CK_242X ), -CLK ("omap2_mcspi.2" ,"ick" , &mcspi2_ick,CK_242X ), -CLK (NULL ,"mcspi2_ick" , &mcspi2_ick,CK_242X ), -CLK (NULL ,"mcspi2_fck" , &mcspi2_fck,CK_242X ), -CLK (NULL ,"uart1_ick" , &uart1_ick,CK_242X ), -CLK (NULL ,"uart1_fck" , &uart1_fck,CK_242X ), -CLK (NULL ,"uart2_ick" , &uart2_ick,CK_242X ), -CLK (NULL ,"uart2_fck" , &uart2_fck,CK_242X ), -CLK (NULL ,"uart3_ick" , &uart3_ick,CK_242X ), -CLK (NULL ,"uart3_fck" , &uart3_fck,CK_242X ), -CLK (NULL ,"gpios_ick" , &gpios_ick,CK_242X ), -CLK (NULL ,"gpios_fck" , &gpios_fck,CK_242X ), -CLK ("omap_wdt" ,"ick" , &mpu_wdt_ick,CK_242X ), -CLK (NULL ,"mpu_wdt_ick" , &mpu_wdt_ick,CK_242X ), -CLK (NULL ,"mpu_wdt_fck" , &mpu_wdt_fck,CK_242X ), -CLK (NULL ,"sync_32k_ick" , &sync_32k_ick,CK_242X ), -CLK (NULL ,"wdt1_ick" , &wdt1_ick,CK_242X ), -CLK (NULL ,"omapctrl_ick" , &omapctrl_ick,CK_242X ), -CLK ("omap24xxcam" ,"fck" , &cam_fck,CK_242X ), -CLK (NULL ,"cam_fck" , &cam_fck,CK_242X ), -CLK ("omap24xxcam" ,"ick" , &cam_ick,CK_242X ), -CLK (NULL ,"cam_ick" , &cam_ick,CK_242X ), -CLK (NULL ,"mailboxes_ick" , &mailboxes_ick,CK_242X ), -CLK (NULL ,"wdt4_ick" , &wdt4_ick,CK_242X ), -CLK (NULL ,"wdt4_fck" , &wdt4_fck,CK_242X ), -CLK (NULL ,"wdt3_ick" , &wdt3_ick,CK_242X ), -CLK (NULL ,"wdt3_fck" , &wdt3_fck,CK_242X ), -CLK (NULL ,"mspro_ick" , &mspro_ick,CK_242X ), -CLK (NULL ,"mspro_fck" , &mspro_fck,CK_242X ), -CLK ("mmci-omap.0" ,"ick" , &mmc_ick,CK_242X ), -CLK (NULL ,"mmc_ick" , &mmc_ick,CK_242X ), -CLK ("mmci-omap.0" ,"fck" , &mmc_fck,CK_242X ), -CLK (NULL ,"mmc_fck" , &mmc_fck,CK_242X ), -CLK (NULL ,"fac_ick" , &fac_ick,CK_242X ), -CLK (NULL ,"fac_fck" , &fac_fck,CK_242X ), -CLK (NULL ,"eac_ick" , &eac_ick,CK_242X ), -CLK (NULL ,"eac_fck" , &eac_fck,CK_242X ), -CLK ("omap_hdq.0" ,"ick" , &hdq_ick,CK_242X ), -CLK (NULL ,"hdq_ick" , &hdq_ick,CK_242X ), -CLK ("omap_hdq.0" ,"fck" , &hdq_fck,CK_242X ), -CLK (NULL ,"hdq_fck" , &hdq_fck,CK_242X ), -CLK ("omap_i2c.1" ,"ick" , &i2c1_ick,CK_242X ), -CLK (NULL ,"i2c1_ick" , &i2c1_ick,CK_242X ), -CLK (NULL ,"i2c1_fck" , &i2c1_fck,CK_242X ), -CLK ("omap_i2c.2" ,"ick" , &i2c2_ick,CK_242X ), -CLK (NULL ,"i2c2_ick" , &i2c2_ick,CK_242X ), -CLK (NULL ,"i2c2_fck" , &i2c2_fck,CK_242X ), -CLK (NULL ,"gpmc_fck" , &gpmc_fck,CK_242X ), -CLK (NULL ,"sdma_fck" , &sdma_fck,CK_242X ), -CLK (NULL ,"sdma_ick" , &sdma_ick,CK_242X ), -CLK (NULL ,"sdrc_ick" , &sdrc_ick,CK_242X ), -CLK (NULL ,"vlynq_ick" , &vlynq_ick,CK_242X ), -CLK (NULL ,"vlynq_fck" , &vlynq_fck,CK_242X ), -CLK (NULL ,"des_ick" , &des_ick,CK_242X ), -CLK ("omap-sham" ,"ick" , &sha_ick,CK_242X ), -CLK (NULL ,"sha_ick" , &sha_ick,CK_242X ), -CLK ("omap_rng" ,"ick" , &rng_ick,CK_242X ), -CLK (NULL ,"rng_ick" , &rng_ick,CK_242X ), -CLK ("omap-aes" ,"ick" , &aes_ick,CK_242X ), -CLK (NULL ,"aes_ick" , &aes_ick,CK_242X ), -CLK (NULL ,"pka_ick" , &pka_ick,CK_242X ), -CLK (NULL ,"usb_fck" , &usb_fck,CK_242X ), -CLK ("musb-hdrc" ,"fck" , &osc_ck,CK_242X ), -CLK ("omap_timer.1" ,"32k_ck" , &func_32k_ck,CK_243X ), -CLK ("omap_timer.2" ,"32k_ck" , &func_32k_ck,CK_243X ), -CLK ("omap_timer.3" ,"32k_ck" , &func_32k_ck,CK_243X ), -CLK ("omap_timer.4" ,"32k_ck" , &func_32k_ck,CK_243X ), -CLK ("omap_timer.5" ,"32k_ck" , &func_32k_ck,CK_243X ), -CLK ("omap_timer.6" ,"32k_ck" , &func_32k_ck,CK_243X ), -CLK ("omap_timer.7" ,"32k_ck" , &func_32k_ck,CK_243X ), -CLK ("omap_timer.8" ,"32k_ck" , &func_32k_ck,CK_243X ), -CLK ("omap_timer.9" ,"32k_ck" , &func_32k_ck,CK_243X ), -CLK ("omap_timer.10" ,"32k_ck" , &func_32k_ck,CK_243X ), -CLK ("omap_timer.11" ,"32k_ck" , &func_32k_ck,CK_243X ), -CLK ("omap_timer.12" ,"32k_ck" , &func_32k_ck,CK_243X ), -CLK ("omap_timer.1" ,"sys_ck" , &sys_ck,CK_243X ), -CLK ("omap_timer.2" ,"sys_ck" , &sys_ck,CK_243X ), -CLK ("omap_timer.3" ,"sys_ck" , &sys_ck,CK_243X ), -CLK ("omap_timer.4" ,"sys_ck" , &sys_ck,CK_243X ), -CLK ("omap_timer.5" ,"sys_ck" , &sys_ck,CK_243X ), -CLK ("omap_timer.6" ,"sys_ck" , &sys_ck,CK_243X ), -CLK ("omap_timer.7" ,"sys_ck" , &sys_ck,CK_243X ), -CLK ("omap_timer.8" ,"sys_ck" , &sys_ck,CK_243X ), -CLK ("omap_timer.9" ,"sys_ck" , &sys_ck,CK_243X ), -CLK ("omap_timer.10" ,"sys_ck" , &sys_ck,CK_243X ), -CLK ("omap_timer.11" ,"sys_ck" , &sys_ck,CK_243X ), -CLK ("omap_timer.12" ,"sys_ck" , &sys_ck,CK_243X ), -CLK ("omap_timer.1" ,"alt_ck" , &alt_ck,CK_243X ), -CLK ("omap_timer.2" ,"alt_ck" , &alt_ck,CK_243X ), -CLK ("omap_timer.3" ,"alt_ck" , &alt_ck,CK_243X ), -CLK ("omap_timer.4" ,"alt_ck" , &alt_ck,CK_243X ), -CLK ("omap_timer.5" ,"alt_ck" , &alt_ck,CK_243X ), -CLK ("omap_timer.6" ,"alt_ck" , &alt_ck,CK_243X ), -CLK ("omap_timer.7" ,"alt_ck" , &alt_ck,CK_243X ), -CLK ("omap_timer.8" ,"alt_ck" , &alt_ck,CK_243X ), -CLK ("omap_timer.9" ,"alt_ck" , &alt_ck,CK_243X ), -CLK ("omap_timer.10" ,"alt_ck" , &alt_ck,CK_243X ), -CLK ("omap_timer.11" ,"alt_ck" , &alt_ck,CK_243X ), -CLK ("omap_timer.12" ,"alt_ck" , &alt_ck,CK_243X ), -}; - -/* -* init code -*/ - -int __init omap2420_clk_init (void ) -{ -const struct prcm_config *prcm; -struct omap_clk *c; -u32 clkrate; - - prcm_clksrc_ctrl =OMAP2420_PRCM_CLKSRC_CTRL ; - cm_idlest_pll =OMAP_CM_REGADDR (PLL_MOD ,CM_IDLEST ); - cpu_mask =RATE_IN_242X ; - rate_table = omap2420_rate_table; - -clk_init (&omap2_clk_functions); - -for (c = omap2420_clks; c < omap2420_clks +ARRAY_SIZE (omap2420_clks); - c++) -clk_preinit (c->lk.clk); - - osc_ck.rate =omap2_osc_clk_recalc (&osc_ck); -propagate_rate (&osc_ck); - sys_ck.rate =omap2xxx_sys_clk_recalc (&sys_ck); -propagate_rate (&sys_ck); - -for (c = omap2420_clks; c < omap2420_clks +ARRAY_SIZE (omap2420_clks); - c++) { -clkdev_add (&c->lk); -clk_register (c->lk.clk); -omap2_init_clk_clkdm (c->lk.clk); - } - -/* Disable autoidle on all clocks; let the PM code enable it later */ -omap_clk_disable_autoidle_all (); - -/* Check the MPU rate set by bootloader */ - clkrate =omap2xxx_clk_get_core_rate (&dpll_ck); -for (prcm = rate_table; prcm->mpu_speed; prcm++) { -if (!(prcm->flags & cpu_mask)) -continue ; -if (prcm->xtal_speed != sys_ck.rate) -continue ; -if (prcm->dpll_speed <= clkrate) -break ; - } - curr_prcm_set = prcm; - -recalculate_root_clocks (); - -pr_info ("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n" , - (sys_ck.rate /1000000 ), (sys_ck.rate /100000 ) %10 , - (dpll_ck.rate /1000000 ), (mpu_ck.rate /1000000 )) ; - -/* -* Only enable those clocks we will need, let the drivers -* enable other clocks as necessary -*/ -clk_enable_init_clocks (); - -/* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ - vclk =clk_get (NULL ,"virt_prcm_set" ); - sclk =clk_get (NULL ,"sys_ck" ); - dclk =clk_get (NULL ,"dpll_ck" ); - -return 0 ; -} -
arch/arm/mach-omap2/clock2430_data.c deleted +0 -2114
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1.7.1
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Paul Walmsley
maintainercover Move OMAP2+ over to use COMMON clock
In reply to Rajendra NayakQuoted 7 lines · Rajendra Nayak
OMAP3 has suspend broken in mainline, so I tested it on an older kernel (3.4-rc4 using my RFC series)
Idle and OFF mode however seem to be broken for a long time, I wasn;t able to get it working even on 3.4 major. See my logs '3630 Beagle-Xm broken idle/off on 3.4' if I am doing anything wrong. I have CPUidle enabled in the kernel config.
http://www.spinics.net/lists/arm-kernel/msg173688.html
- Paul
cover Move OMAP2+ over to use COMMON clock
Quoted 11 lines · Paul Walmsley
Quoted 7 lines · Rajendra Nayak
OMAP3 has suspend broken in mainline, so I tested it on an older kernel (3.4-rc4 using my RFC series)
Idle and OFF mode however seem to be broken for a long time, I wasn;t able to get it working even on 3.4 major. See my logs '3630 Beagle-Xm broken idle/off on 3.4' if I am doing anything wrong. I have CPUidle enabled in the kernel config.
Thanks Paul. I re-tested my branch [1] after applying the 32K sync timer fix [2] and using timer based wakeup [3] instead of UART. Both retention and off work fine on my 3630 Beagle-Xm on my CCF conversion branch.
Updated logs can be found here http://pastebin.com/u/rnayak
regards,
Rajendra
[1] git://github.com/rrnayak/linux.git clk-next-omap-3.5-rc2
[2] http://marc.info/?l=linux-omap&m=134000053229888&w=2
[3] http://marc.info/?l=linux-omap&m=134001387702336&w=2
Quoted 3 lines
- Paul
Paul Walmsley
maintainercover Move OMAP2+ over to use COMMON clock
In reply to Rajendra NayakHi Rajendra,
A CCF testing branch has been built here. The base is v3.6-rc5, plus the most recent version of the Common Clock Framework preparation patches that you posted to the list, "[PATCH v4 0/3] Prepare for OMAP2+ movement to Common Clk", but updated to take RMK's feedback into account. Then the 'clk-next-omap-3.6-rc3' branch from your repo at 'git://github.com/rrnayak/linux.git' was added. Then some patches to drop the old arch/arm/mach-omap2/clock*_data.c files were added.
This branch was then run through checkpatch.pl, and all of the parenthesis alignment warnings have been fixed. I don't know what to do about these crazy DECLARE_CLK_* macros; they have so many arguments that they are basically impossible to read. Mike and I discussed converting them into C99 structure initializers with named fields, but am not sure if it's a readability advantage; it's probably going to be "write-only data" either way. I've reflowed many of them to save diffstat but there are quite a few more to go.
The branch was then built with a set of testing Kconfigs. Here's what was
found: (these are still being investigated)
- The OMAP4-only testconfig and rmk's OMAP4430-SDP Kconfigs failed:
"undefined reference to `omap2_clkt_iclk_allow_idle'":
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/build/omap4_testconfig/
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/build/rmk_omap4430_sdp_oldconfig/
- RMK's OMAP3430-LDP Kconfig failed with a whole set of warnings:
The kernel built with omap2plus_defconfig was then booted on several OMAP2+ boards. Here's what was found:
- The kernel wouldn't boot on either the 3517EVM nor CM-T3517 boards. This turned out to be due to some missing AM35XX clkdev aliases, the lack of which cause the CCF code to panic. The patch that adds the OMAP3 data has been updated to fix that bug and an HSOTGUSB clkdev alias bug that was found by visual inspection.
- The 3730 Beagle XM issued a warning and stack trace upon boot. Debugging with Mike, this turned out to be due to a bug in the modified omap2_init_clksel_parent() function: it returned a register bitfield rather than an array index. The patch that modifies this function was then updated to fix the bug.
- The 2420 N800 seems to have some kind of MMC-related problem that prevents it from booting. Still looking into this:
Then the branch was PM-tested to determine whether it can suspend and serial-resume properly, and whether dynamic idle works. These tests didn't go so well:
- 3530ES3 Beagleboard here was able to enter retention-idle suspend, and leave it with serial wakeup, but the CORE powerdomain never entered a low-power state. Dynamic retention-idle with serial wakeup never resumed, and the test stopped there:
- 37xx EVM and 3730 Beagle XM fared better; they made it through the whole test program, but the CORE powerdomain also never entered a low-power state:
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/boot/37xxevm/37xxevm_log.txt
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/boot/3730beaglexm/3730beaglexm_log.txt
- 4430ES2 Panda never made past the first retention-idle suspend:
Could you please take a look and see if you can identify why the patches aren't passing the tests? I can't send these upstream until they pass the PM tests.
This testing branch can be found at the branch named "common_clk_testing_devel_3.7" of git://git.pwsan.com/linux-2.6
The testbed reports from this branch can be found here:
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/
And the baseline test reports from v3.6-rc5 can be found here:
http://www.pwsan.com/omap/testlogs/test_v3.6-rc5/20120908202511/
- Paul
cover Move OMAP2+ over to use COMMON clock
Quoted 85 lines · Paul Walmsley
Hi Rajendra,
A CCF testing branch has been built here. The base is v3.6-rc5, plus the most recent version of the Common Clock Framework preparation patches that you posted to the list, "[PATCH v4 0/3] Prepare for OMAP2+ movement to Common Clk", but updated to take RMK's feedback into account. Then the 'clk-next-omap-3.6-rc3' branch from your repo at '
git://github.com/rrnayak/linux.git' was added. Then some patches to drop the oldarch/arm/mach-omap2/clock*_data.cfiles were added.This branch was then run through checkpatch.pl, and all of the parenthesis alignment warnings have been fixed. I don't know what to do about these crazy DECLARE_CLK_* macros; they have so many arguments that they are basically impossible to read. Mike and I discussed converting them into C99 structure initializers with named fields, but am not sure if it's a readability advantage; it's probably going to be "write-only data" either way. I've reflowed many of them to save diffstat but there are quite a few more to go.
The branch was then built with a set of testing Kconfigs. Here's what was
found: (these are still being investigated)- The OMAP4-only testconfig and rmk's OMAP4430-SDP Kconfigs failed:
"undefined reference to `omap2_clkt_iclk_allow_idle'":http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/build/omap4_testconfig/
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/build/rmk_omap4430_sdp_oldconfig/- RMK's OMAP3430-LDP
Kconfigfailed with a whole set of warnings:The kernel built with
omap2plus_defconfigwas then booted on several OMAP2+ boards. Here's what was found:- The kernel wouldn't boot on either the 3517EVM nor CM-T3517 boards. This turned out to be due to some missing AM35XX clkdev aliases, the lack of which cause the CCF code to panic. The patch that adds the OMAP3 data has been updated to fix that bug and an HSOTGUSB clkdev alias bug that was found by visual inspection.
- The 3730 Beagle XM issued a warning and stack trace upon boot. Debugging with Mike, this turned out to be due to a bug in the modified
omap2_init_clksel_parent()function: it returned a register bitfield rather than an array index. The patch that modifies this function was then updated to fix the bug.- The 2420 N800 seems to have some kind of MMC-related problem that prevents it from booting. Still looking into this:
Then the branch was PM-tested to determine whether it can suspend and serial-resume properly, and whether dynamic idle works. These tests didn't go so well:
- 3530ES3 Beagleboard here was able to enter retention-idle suspend, and leave it with serial wakeup, but the CORE powerdomain never entered a low-power state. Dynamic retention-idle with serial wakeup never resumed, and the test stopped there:
- 37xx EVM and 3730 Beagle XM fared better; they made it through the whole test program, but the CORE powerdomain also never entered a low-power state:
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/boot/37xxevm/37xxevm_log.txt
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/boot/3730beaglexm/3730beaglexm_log.txt- 4430ES2 Panda never made past the first retention-idle suspend:
Could you please take a look and see if you can identify why the patches aren't passing the tests? I can't send these upstream until they pass the PM tests.
This testing branch can be found at the branch named "common_clk_testing_devel_3.7" of
git://git.pwsan.com/linux-2.6
Quoted 8 lines
The testbed reports from this branch can be found here:
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/And the baseline test reports from v3.6-rc5 can be found here:
http://www.pwsan.com/omap/testlogs/test_v3.6-rc5/20120908202511/
I tried this branch on BeagleBone platform and needs one small typo correction in hwmod data patch (submitted earlier, which you are going to queue it)
(quoted diff) +0 -0
b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index de7a3ab..767a77d 100644
arch/arm/mach-omap2/omap_hwmod_33xx_data.c +1 -1
@@ -1441,7 +1441,7 @@ static struct omap_hwmod am33xx_mmc2_hwmod = { .clkdm_name = "l3s_clkdm", .mpu_irqs = am33xx_mmc2_irqs, .sdma_reqs = am33xx_mmc2_edma_reqs, - .main_clk = "mmc2_fck", + .main_clk = "mmc_clk", .prcm = { .omap4 = { .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
With above change I boot tested it on BeagleBone platform and also verified the clock rates getting printed in debugfs.
Thanks,
Vaibhav
Quoted 9 lines
- Paul
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Paul Walmsley
maintainercover Move OMAP2+ over to use COMMON clock
Quoted 21 lines · Vaibhav Hiremath
I tried this branch on BeagleBone platform and needs one small typo correction in hwmod data patch (submitted earlier, which you are going to queue it)
arch/arm/mach-omap2/omap_hwmod_33xx_data.c +1
-1@@ -1441,7 +1441,7 @@ static struct omap_hwmod am33xx_mmc2_hwmod = { .clkdm_name = "l3s_clkdm", .mpu_irqs = am33xx_mmc2_irqs, .sdma_reqs = am33xx_mmc2_edma_reqs, - .main_clk = "mmc2_fck", + .main_clk = "mmc_clk", .prcm = { .omap4 = { .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
Quoted 2 lines
With above change I boot tested it on BeagleBone platform and also verified the clock rates getting printed in debugfs.
So does this mean we need to put together a patch to remove the existing mmc2_fck first from the OMAP clock data file? Looks like that would be the right thing to do, based on the AM33x PRCM data.
- Paul
cover Move OMAP2+ over to use COMMON clock
Quoted 23 lines · Paul Walmsley
Quoted 21 lines · Vaibhav Hiremath
I tried this branch on BeagleBone platform and needs one small typo correction in hwmod data patch (submitted earlier, which you are going to queue it)
arch/arm/mach-omap2/omap_hwmod_33xx_data.c +1
-1@@ -1441,7 +1441,7 @@ static struct omap_hwmod am33xx_mmc2_hwmod = { .clkdm_name = "l3s_clkdm", .mpu_irqs = am33xx_mmc2_irqs, .sdma_reqs = am33xx_mmc2_edma_reqs, - .main_clk = "mmc2_fck", + .main_clk = "mmc_clk", .prcm = { .omap4 = { .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
Quoted 7 lines
Quoted 2 lines
With above change I boot tested it on BeagleBone platform and also verified the clock rates getting printed in debugfs.
So does this mean we need to put together a patch to remove the existing
mmc2_fckfirst from the OMAP clock data file? Looks like that would be the right thing to do, based on the AM33x PRCM data.
Yes, that's correct and it has been already removed from clock data file while migrating to common clock framework.
Thanks,
Vaibhav
Quoted 3 lines
- Paul
Paul Walmsley
maintainercover Move OMAP2+ over to use COMMON clock
In reply to Paul WalmsleyQuoted 6 lines · Paul Walmsley
The branch was then built with a set of testing Kconfigs. Here's what was
found: (these are still being investigated)- The OMAP4-only testconfig and rmk's OMAP4430-SDP Kconfigs failed:
"undefined reference to `omap2_clkt_iclk_allow_idle'":
Quoted 6 lines
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/build/omap4_testconfig/
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/build/rmk_omap4430_sdp_oldconfig/- RMK's OMAP3430-LDP
Kconfigfailed with a whole set of warnings:
These build problems have been fixed and the branch updated. Current test logs at
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911134655/
- Paul
Paul Walmsley
maintainercover Move OMAP2+ over to use COMMON clock
In reply to Paul WalmsleyQuoted 2 lines · Paul Walmsley
The kernel built with
omap2plus_defconfigwas then booted on several OMAP2+ boards. Here's what was found:
[ ... ]
Quoted 4 lines
- The 2420 N800 seems to have some kind of MMC-related problem that prevents it from booting. Still looking into this:
This has been resolved. The APLL clocks have been missing rate recalculation functions for a long time. This wasn't a problem in the past because these were considered fixed rate clocks (at the locked frequency). But in the CCF conversion, the fixed rate was dropped. This caused the MMC functional clock to be set incorrectly to the sys_clk rate. This in turn caused the MMC driver's timing calculation code to return the wrong value, preventing meaningful MMC/SD access.
The problem was resolved by creating recalc_rate function pointers for the APLLs that return sys_ck if the APLL is bypassed, or the APLL rate if it's locked, for both 2420 and 2430.
- Paul
Paul Walmsley
maintainercover Move OMAP2+ over to use COMMON clock
Quoted 3 lines · Paul Walmsley
The problem was resolved by creating
recalc_ratefunction pointers for the APLLs that returnsys_ckif the APLL is bypassed, or the APLL rate if it's locked, for both 2420 and 2430.
One correction - the APLL recalc functions return a zero rate if stopped, not the bypass rate. This appears to be the case, from a close reading of the TRM.
- Paul
Paul Walmsley
maintainercover Move OMAP2+ over to use COMMON clock
In reply to Paul WalmsleyQuoted 9 lines · Paul Walmsley
Then the branch was PM-tested to determine whether it can suspend and serial-resume properly, and whether dynamic idle works. These tests didn't go so well:
- 3530ES3 Beagleboard here was able to enter retention-idle suspend, and leave it with serial wakeup, but the CORE powerdomain never entered a low-power state. Dynamic retention-idle with serial wakeup never resumed, and the test stopped there:
Quoted 8 lines
- 37xx EVM and 3730 Beagle XM fared better; they made it through the whole test program, but the CORE powerdomain also never entered a low-power state:
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/boot/37xxevm/37xxevm_log.txt
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/boot/3730beaglexm/3730beaglexm_log.txt
Thanks to debugging work by some TI LDC engineers, these two issues have been resolved. Some clockdomain associations had been removed that were necessary for the OMAP power management code to function correctly. The obvious ones have been restored to the clock data, and the branch updated.
- Paul
Tony Lindgren
maintainercover Move OMAP2+ over to use COMMON clock
Quoted 17 lines · Paul Walmsley
Quoted 15 lines · Paul Walmsley
Then the branch was PM-tested to determine whether it can suspend and serial-resume properly, and whether dynamic idle works. These tests didn't go so well:
- 3530ES3 Beagleboard here was able to enter retention-idle suspend, and leave it with serial wakeup, but the CORE powerdomain never entered a low-power state. Dynamic retention-idle with serial wakeup never resumed, and the test stopped there:
- 37xx EVM and 3730 Beagle XM fared better; they made it through the whole test program, but the CORE powerdomain also never entered a low-power state:
Quoted 7 lines
Quoted 2 lines
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/boot/37xxevm/37xxevm_log.txt
http://www.pwsan.com/omap/testlogs/common_clk_testing_devel_3.7/20120911000742/boot/3730beaglexm/3730beaglexm_log.txtThanks to debugging work by some TI LDC engineers, these two issues have been resolved. Some clockdomain associations had been removed that were necessary for the OMAP power management code to function correctly. The obvious ones have been restored to the clock data, and the branch updated.
That's good news. Does that mean we should try to merge these patches for v3.7 then? Or do we still have issues remaining?
Regards,
Tony
Paul Walmsley
maintainercover Move OMAP2+ over to use COMMON clock
Quoted 2 lines · Tony Lindgren
That's good news. Does that mean we should try to merge these patches for v3.7 then? Or do we still have issues remaining?
There are still problems with the OMAP4 CCF implementation. Power management is broken on some bootloaders that the original data works fine
with. It's still under debug.
- Paul