pinctrl: mvebu: pinctrl driver

---
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Sebastian Hesselbarth <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-08-11 12:56 UTC #1 lore raw

PATCH 1/11 pinctrl: mvebu: pinctrl driver core

This patch adds a pinctrl driver core for Marvell SoCs plus DT binding documentation. This core driver will be used by SoC family specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.

Signed-off-by Sebastian Hesselbarth <[email protected]>

---
 .../bindings/pinctrl/marvell,mvebu-pinctrl.txt     |   46 ++
 drivers/pinctrl/Kconfig                            |   10 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-mvebu.c                    |  758 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-mvebu.h                    |  175 +++++
 5 files changed, 990 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.c
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.h

Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt new file +46 -0

new file mode 100644
index 0000000..b3e5066
@@ -0,0 +1,46 @@
+* Marvell SoC pinctrl core driver for mpp
+
+The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
+(mpp) to a specific function. For each SoC family there is a SoC specific
+driver using this core driver.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+A Marvell SoC pin configuration node is a node of a group of pins which can
+be used for a specific device or function. Each node requires one or more
+mpp pins or group of pins and a mpp function common to all pins.
+
+Required properties for pinctrl driver:
+- compatible: "marvell,<soc>-pinctrl"
+  Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
+
+Required properties for pin configuration node:
+- marvell,pins: string array of mpp pins or group of pins to be muxed.
+- marvell,function: string representing to function to mux to for all
+    marvell,pins given in this pin configuration node. The function has to be
+    common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
+    valid pin/pin group names and available function names for each SoC.
+
+Examples:
+
+uart1: serial at 12100 {
+	compatible = "ns16550a";
+	reg = <0x12100 0x100>;
+	reg-shift = <2>;
+	interrupts = <7>;
+	clock-frequency = <166666667>;
+
+	pinctrl-0 = <&pmx_uart1_sw>;
+};
+
+pinctrl: pinctrl at d0200 {
+	compatible = "marvell,dove-pinctrl";
+	reg = <0xd0200 0x20>;
+
+	pmx_uart1_sw: pmx-uart1-sw {
+		marvell,pins = "mpp_uart1";
+		marvell,function = "uart1";
+	};
+};

drivers/pinctrl/Kconfig +10 -0

index 54e3588..b968335 100644
@@ -145,6 +145,16 @@ config PINCTRL_COH901
 	  COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
 	  ports of 8 GPIO pins each.
 
+config PINCTRL_MVEBU
+	bool "Marvell SoC pin controller drivers"
+	depends on ARCH_MVEBU
+	select PINMUX
+	select PINCONF
+	help
+	  Say yes here to support pinctrl driver on Marvell SoCs.
+	  This is only the driver core and additionally needs a SoC specific
+	  driver.
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index f40b1f8..007ed32 100644
@@ -29,5 +29,6 @@ obj-$(CONFIG_PINCTRL_TEGRA20)	+= pinctrl-tegra20.o
 obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
+obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-mvebu.c new file +758 -0

758 lines not on this page · raw message

drivers/pinctrl/pinctrl-mvebu.h new file +175 -0

175 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Linus Walleij

2012-08-20 09:09 UTC #2 lore raw

Re: [PATCH 01/11] pinctrl: mvebu: pinctrl driver core

Quoted 3 lines · Sebastian Hesselbarth

This patch adds a pinctrl driver core for Marvell SoCs plus DT binding documentation. This core driver will be used by SoC family specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.

Thanks for dealing with this, much appreaciated!

Are you taking this patch series through some Marvell tree or do you want me to carry it in the pinctrl tree?

(...)

Quoted 25 lines

+++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt

Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt new file +23 -0

@@ -0,0 +1,46 @@
+* Marvell SoC pinctrl core driver for mpp
+
+The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
+(mpp) to a specific function. For each SoC family there is a SoC specific
+driver using this core driver.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+A Marvell SoC pin configuration node is a node of a group of pins which can
+be used for a specific device or function. Each node requires one or more
+mpp pins or group of pins and a mpp function common to all pins.
+
+Required properties for pinctrl driver:
+- compatible: "marvell,<soc>-pinctrl"
+  Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
+
+Required properties for pin configuration node:
+- marvell,pins: string array of mpp pins or group of pins to be muxed.
+- marvell,function: string representing to function to mux to for all
+    marvell,pins given in this pin configuration node. The function has to be
+    common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for

Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt line 33

Quoted 10 lines

Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt new file +10 -0

+    valid pin/pin group names and available function names for each SoC.
+
+Examples:
+
+uart1: serial at 12100 {
+       compatible = "ns16550a";
+       reg = <0x12100 0x100>;
+       reg-shift = <2>;
+       interrupts = <7>;
+       clock-frequency = <166666667>;

It's got nothing to do with this patch, but getting a clock frequency out of the DT instead of getting it from the clk_get_rate(clk) and the clock tree seems absurd... (But maybe this platform does not even have a clk implementation?)

Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt line 46

Quoted 13 lines

Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt new file +13 -0

+
+       pinctrl-0 = <&pmx_uart1_sw>;
+};
+
+pinctrl: pinctrl at d0200 {
+       compatible = "marvell,dove-pinctrl";
+       reg = <0xd0200 0x20>;
+
+       pmx_uart1_sw: pmx-uart1-sw {
+               marvell,pins = "mpp_uart1";
+               marvell,function = "uart1";
+       };
+};

This looks very good.

(...)

Quoted 1 line

+#include <linux/pinctrl/consumer.h>

Why are you including this header?
(There are valid reasons, state them in a comment, e.g. /* to access pinctrl_gpio* in GPIO portions */)

Quoted 19 lines

drivers/pinctrl/pinctrl-mvebu.c new file +19 -0

+struct mvebu_pinctrl_function {
+       unsigned fid;
+       const char *name;
+       const char *setting;
+       const char **groups;
+       unsigned num_groups;
+};
+
+struct mvebu_pinctrl_group {
+       const char *name;
+       struct mvebu_mpp_ctrl *ctrl;
+       struct mvebu_mpp_ctrl_setting *settings;
+       unsigned num_settings;
+       unsigned gid;
+       unsigned *pins;
+       unsigned npins;
+};
+
+struct mvebu_pinctrl {

drivers/pinctrl/pinctrl-mvebu.c line 58

Quoted 10 lines

drivers/pinctrl/pinctrl-mvebu.c new file +10 -0

+       struct device *dev;
+       struct pinctrl_dev *pctldev;
+       struct pinctrl_desc desc;
+       void __iomem *base;
+       struct mvebu_pinctrl_group *groups;
+       unsigned num_groups;
+       struct mvebu_pinctrl_function *functions;
+       unsigned num_functions;
+       unsigned variant;
+};

There is some other "variant" field elsewhere that is a u8, is this correct? In this and the other case, should this "variant" rather be an enum?

Quoted 77 lines

drivers/pinctrl/pinctrl-mvebu.c new file +77 -0

+struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_pid(
+       struct mvebu_pinctrl *pctl, unsigned pid)
+{
+       unsigned n;
+       for (n = 0; n < pctl->num_groups; n++) {
+               if (pid >= pctl->groups[n].pins[0] &&
+                   pid < pctl->groups[n].pins[0] +
+                       pctl->groups[n].npins)
+                       return &pctl->groups[n];
+       }
+       return NULL;
+}
+
+struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_name(
+       struct mvebu_pinctrl *pctl, const char *name)
+{
+       unsigned n;
+       for (n = 0; n < pctl->num_groups; n++) {
+               if (strcmp(name, pctl->groups[n].name) == 0)
+                       return &pctl->groups[n];
+       }
+       return NULL;
+}
+
+struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_val(
+       struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
+       unsigned long config)
+{
+       unsigned n;
+       for (n = 0; n < grp->num_settings; n++) {
+               if (config == grp->settings[n].val) {
+                       if (!pctl->variant || (pctl->variant &
+                                              grp->settings[n].variant))
+                               return &grp->settings[n];
+               }
+       }
+       return NULL;
+}
+
+struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_name(
+       struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
+       const char *name)
+{
+       unsigned n;
+       for (n = 0; n < grp->num_settings; n++) {
+               if (strcmp(name, grp->settings[n].name) == 0) {
+                       if (!pctl->variant || (pctl->variant &
+                                              grp->settings[n].variant))
+                               return &grp->settings[n];
+               }
+       }
+       return NULL;
+}
+
+struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_gpio_setting(
+       struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp)
+{
+       unsigned n;
+       for (n = 0; n < grp->num_settings; n++) {
+               if (grp->settings[n].flags &
+                       (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+                       if (!pctl->variant || (pctl->variant &
+                                               grp->settings[n].variant))
+                               return &grp->settings[n];
+               }
+       }
+       return NULL;
+}
+
+struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name(
+       struct mvebu_pinctrl *pctl, const char *name)
+{
+       unsigned n;
+       for (n = 0; n < pctl->num_functions; n++) {
+               if (strcmp(name, pctl->functions[n].name) == 0)
+                       return &pctl->functions[n];
+       }

drivers/pinctrl/pinctrl-mvebu.c line 146

Quoted 10 lines

drivers/pinctrl/pinctrl-mvebu.c new file +10 -0

+       return NULL;
+}
+
+static int mvebu_common_mpp_get(struct mvebu_pinctrl *pctl,
+                               struct mvebu_pinctrl_group *grp,
+                               unsigned long *config)
+{
+       unsigned pin = grp->gid;
+       unsigned off = (pin / 8) * 4;
+       unsigned shift = (pin % 8) * 4;

Some magic numbers here. Either use relevant #define:s or put an inline comment that explains what is going on.

drivers/pinctrl/pinctrl-mvebu.c line 150

Quoted 4 lines

drivers/pinctrl/pinctrl-mvebu.c new file +4 -0

+
+       *config = readl(pctl->base + off);
+       *config >>= shift;
+       *config &= 0xf;

Here too...

Quoted 10 lines

drivers/pinctrl/pinctrl-mvebu.c new file +10 -0

+
+       return 0;
+}
+
+static int mvebu_common_mpp_set(struct mvebu_pinctrl *pctl,
+                               struct mvebu_pinctrl_group *grp,
+                               unsigned long config)
+{
+       unsigned pin = grp->gid;
+       unsigned off = (pin / 8) * 4;

drivers/pinctrl/pinctrl-mvebu.c line 170

Quoted 10 lines

drivers/pinctrl/pinctrl-mvebu.c new file +10 -0

+       unsigned shift = (pin % 8) * 4;
+       unsigned long reg;
+
+       reg = readl(pctl->base + off);
+       reg &= ~(0xf << shift);
+       reg |= (config << shift);
+       writel(reg, pctl->base + off);
+
+       return 0;
+}

Same comment as previous function.

(...)

drivers/pinctrl/pinctrl-mvebu.c line 465

Quoted 5 lines

drivers/pinctrl/pinctrl-mvebu.c new file +5 -0

+static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
+                               struct pinctrl_map *map, unsigned num_maps)
+{
+       kfree(map);
+}

Is it possible to use devm_* managed devm_kzalloc() for this map so you don't need to free it explicitly?

(Maybe not, just checking.)

The rest of this file is looking so good that I find nothing to comment on.

(...)

Quoted 1 line

drivers/pinctrl/pinctrl-mvebu.h +0 -0

(...)

Quoted 1 line

+/*

Kerneldoc begins with /** have you really tested to generate kerneldoc?

Quoted 17 lines

+ * struct mvebu_mpp_ctrl - describe a mpp control
+ * @name: name of the control group
+ * @pid: first pin id handled by this control
+ * @npins: number of pins controlled by this control
+ * @mpp_get: (optional) special function to get mpp setting
+ * @mpp_set: (optional) special function to set mpp setting
+ * @mpp_gpio_req: (optional) special function to request gpio
+ * @mpp_gpio_dir: (optional) special function to set gpio direction
+ *
+ * if optional mpp_get/_set functions are set these
+ * are used to get/set a specific mode. Otherwise it is
+ * assumed that the mpp control is based on 4-bit groups
+ * in subsequent registers.
+ *
+ * mpp_gpio_req/_dir functions can be used to allow pin settings
+ * with varying gpio pins.
+ */

drivers/pinctrl/pinctrl-mvebu.h line 37

Quoted 4 lines

drivers/pinctrl/pinctrl-mvebu.h +4 -0

+struct mvebu_mpp_ctrl {
+       const char *name;
+       u8 pid;
+       u8 npins;

So, there will never be > 256 pins on a Marvell platform?

Just checking...

drivers/pinctrl/pinctrl-mvebu.h line 45

Quoted 8 lines

drivers/pinctrl/pinctrl-mvebu.h +8 -0

+       unsigned *pins;
+       int (*mpp_get)(struct mvebu_mpp_ctrl *ctrl, unsigned long *config);
+       int (*mpp_set)(struct mvebu_mpp_ctrl *ctrl, unsigned long config);
+       int (*mpp_gpio_req)(struct mvebu_mpp_ctrl *ctrl, u8 pid);
+       int (*mpp_gpio_dir)(struct mvebu_mpp_ctrl *ctrl, u8 pid, bool input);
+};
+
+/*

/**

Quoted 2 lines

+ * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
+ * @val: ctrl setting value

It is not obvious to me what this means, it it possible to elaborate on how this member is defined and used?

Quoted 3 lines

+ * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
+ * @subname: (optional) additional ctrl setting name, e.g. rts, cts
+ * @variant: (optional) variant identifier mask

This thing again, there are lots of "variants" around here. Is it a candidate for an enum?

Quoted 1 line

+ * @flags: (private) flags to store gpi/gpo/gpio capabilities

Write something about the two available flags and what they mean maybe?

drivers/pinctrl/pinctrl-mvebu.h line 63

Quoted 12 lines

+ *
+ * ctrl setting name will be used to switch to this setting in
+ * DT description, e.g. marvell,function = "uart2". subname
+ * is only for debugging purposes.
+ * If name is one of "gpi", "gpo", "gpio" gpio capabilities are
+ * parsed during initialization.
+ */
drivers/pinctrl/pinctrl-mvebu.h +5 -0
+struct mvebu_mpp_ctrl_setting {
+       u8 val;
+       const char *name;
+       const char *subname;
+       u8 variant;

enum?

drivers/pinctrl/pinctrl-mvebu.h line 66

Quoted 3 lines

drivers/pinctrl/pinctrl-mvebu.h +3 -0

+       u8 flags;
+#define  MVEBU_SETTING_GPO     (1 << 0)
+#define  MVEBU_SETTING_GPI     (1 << 1)

So these are the possible flags I suspect. (Looking good.)

Quoted 15 lines

drivers/pinctrl/pinctrl-mvebu.h +15 -0

+};
+
+/*
+ * struct mvebu_mpp_mode - link ctrl and settings
+ * @pid: first pin id handled by this mode
+ * @settings: list of settings available for this mode
+ */
+struct mvebu_mpp_mode {
+       u8 pid;
+       struct mvebu_mpp_ctrl_setting *settings;
+};
+
+/*
+ * struct mvebu_pinctrl_soc_info -
+ *       SoC specific info passed to pinctrl-mvebu

drivers/pinctrl/pinctrl-mvebu.h line 91

Quoted 10 lines

drivers/pinctrl/pinctrl-mvebu.h +10 -0

+ * @variant: variant mask of soc_info
+ * @controls: list of available mvebu_mpp_ctrls
+ * @ncontrols: number of available mvebu_mpp_ctrls
+ * @modes: list of available mvebu_mpp_modes
+ * @nmodes: number of available mvebu_mpp_modes
+ * @gpioranges: list of pinctrl_gpio_ranges
+ * @ngpioranges: number of available pinctrl_gpio_ranges
+ */
+struct mvebu_pinctrl_soc_info {
+       u8 variant;

Why is this an u8 rather than an enum?

Quoted 7 lines

drivers/pinctrl/pinctrl-mvebu.h +7 -0

+       struct mvebu_mpp_ctrl *controls;
+       int ncontrols;
+       struct mvebu_mpp_mode *modes;
+       int nmodes;
+       struct pinctrl_gpio_range *gpioranges;
+       int ngpioranges;
+};

(...)

drivers/pinctrl/pinctrl-mvebu.h line 151

Quoted 7 lines

drivers/pinctrl/pinctrl-mvebu.h +7 -0

+#if defined(CONFIG_DEBUG_FS)
+#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask)         \
+       _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
+#else
+#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask)         \
+       _MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
+#endif

This looks a bit kludgy. Is the purpose to save memory if debugfs is not used?

This looks good overall.

Yours,
Linus Walleij

Sebastian Hesselbarth

author maintainer

2012-08-20 09:46 UTC #3 lore raw

Re: [PATCH 01/11] pinctrl: mvebu: pinctrl driver core

Quoted 2 lines · Linus Walleij

Are you taking this patch series through some Marvell tree or do you want me to carry it in the pinctrl tree?

Hi Linus,

I think it would be better to take it through the Marvell tree of Jason Cooper. It is only for Marvell SoCs anyway.

Quoted 11 lines

Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt line 33
Quoted 6 lines
Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt new file +6 -0
+uart1: serial at 12100 {
+       compatible = "ns16550a";
+       reg = <0x12100 0x100>;
+       reg-shift = <2>;
+       interrupts = <7>;
+       clock-frequency = <166666667>;
It's got nothing to do with this patch, but getting a clock frequency out of the DT instead of getting it from the clk_get_rate(clk) and the clock tree seems absurd... (But maybe this platform does not even have a clk implementation?)

It's of_serial's implementation. I patched that once for getting frequency out of "clocks" property but then I got busy with porting mach-dove and pinctrl.. Marvell SoCs do have a clk implementation and as soon as of_serial can handle "clocks" property it will be used for sure. I can remove "clock-frequency" from the example anyway as it is not really part of pinctrl binding documentation.

Quoted 6 lines

(...)
Quoted 1 line
+#include <linux/pinctrl/consumer.h>
Why are you including this header?
(There are valid reasons, state them in a comment, e.g. /* to access pinctrl_gpio* in GPIO portions */)

I guess it was a left-over from my experiments with default pinmux configuration until you pointed me to the correct way of having the pinctrl itself hog muxes.

I'll remove that include.

Quoted 7 lines

drivers/pinctrl/pinctrl-mvebu.c new file +7 -0

+struct mvebu_pinctrl {
+       struct device *dev;
+       struct pinctrl_dev *pctldev;
+       struct pinctrl_desc desc;
+       void __iomem *base;
+       struct mvebu_pinctrl_group *groups;
+       unsigned num_groups;

Quoted 8 lines

drivers/pinctrl/pinctrl-mvebu.c line 58
Quoted 4 lines
drivers/pinctrl/pinctrl-mvebu.c new file +4 -0
+       struct mvebu_pinctrl_function *functions;
+       unsigned num_functions;
+       unsigned variant;
+};
There is some other "variant" field elsewhere that is a u8, is this correct? In this and the other case, should this "variant" rather be an enum?

I'll review the variant types but inside pinctrl-mvebu variant is used as a bit mask to distinguish different variants. Anyway, they should always be the same size.

Quoted 10 lines

drivers/pinctrl/pinctrl-mvebu.c line 146

Quoted 7 lines

drivers/pinctrl/pinctrl-mvebu.c new file +7 -0

+static int mvebu_common_mpp_get(struct mvebu_pinctrl *pctl,
+                               struct mvebu_pinctrl_group *grp,
+                               unsigned long *config)
+{
+       unsigned pin = grp->gid;
+       unsigned off = (pin / 8) * 4;
+       unsigned shift = (pin % 8) * 4;

Some magic numbers here. Either use relevant #define:s or put an inline comment that explains what is going on.

Ok.

Quoted 11 lines

drivers/pinctrl/pinctrl-mvebu.c line 465
Quoted 6 lines
(quoted diff) +2 -0
+static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
+                               struct pinctrl_map *map, unsigned
num_maps)
drivers/pinctrl/pinctrl-mvebu.c new file +3 -0
+{
+       kfree(map);
+}
Is it possible to use devm_* managed devm_kzalloc() for this map so you don't need to free it explicitly?
(Maybe not, just checking.)

Hmm, I guess not as I thought I've read not to use devm_kfree when you allocate _and_ free stuff on runtime without removing the device itself, right?

Quoted 7 lines

Quoted 2 lines
drivers/pinctrl/pinctrl-mvebu.h +0 -0
(...)
Quoted 1 line
+/*
Kerneldoc begins with /** have you really tested to generate kerneldoc?

Nope, I wasn't even aware of that, sorry. I just copied it over from some other pinctrl include. I'll check for compatibility with kerneldoc.

Quoted 6 lines

drivers/pinctrl/pinctrl-mvebu.h line 37
Quoted 4 lines
drivers/pinctrl/pinctrl-mvebu.h +4 -0
+struct mvebu_mpp_ctrl {
+       const char *name;
+       u8 pid;
+       u8 npins;
So, there will never be > 256 pins on a Marvell platform?

Well, with all current platforms we are well below 100. I guess 256 max (muxable) pins will be enough.

Quoted 5 lines

Quoted 2 lines
+ * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
+ * @val: ctrl setting value
It is not obvious to me what this means, it it possible to elaborate on how this member is defined and used?

Well, I see if I can clarify the description but wrt the datasheet it _should_ be quite obvious.

Quoted 4 lines

Quoted 1 line
+ * @variant: (optional) variant identifier mask
This thing again, there are lots of "variants" around here. Is it a candidate for an enum?

As it is a mask, I don't think enum fits here.

Quoted 4 lines

Quoted 1 line
+ * @flags: (private) flags to store gpi/gpo/gpio capabilities
Write something about the two available flags and what they mean maybe?

Ok.

Quoted 4 lines

drivers/pinctrl/pinctrl-mvebu.h line 66
Quoted 2 lines
drivers/pinctrl/pinctrl-mvebu.h +2 -0
+#define  MVEBU_SETTING_GPO     (1 << 0)
+#define  MVEBU_SETTING_GPI     (1 << 1)
So these are the possible flags I suspect. (Looking good.)

Yes, some mpp pins on Marvell SoCs are out-only, while normally they are in-out. I haven't seen in-only yet but better to have the flags ready if someone stumbles upon one.

Quoted 10 lines

drivers/pinctrl/pinctrl-mvebu.h line 151
Quoted 7 lines
drivers/pinctrl/pinctrl-mvebu.h +7 -0
+#if defined(CONFIG_DEBUG_FS)
+#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask)         \
+       _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
+#else
+#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask)         \
+       _MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
+#endif
This looks a bit kludgy. Is the purpose to save memory if debugfs is not used?

Yes, that was the intention. Subnames are not used by pinctrl at all, other for debugfs files. Although, there are some pins that have two different settings for the same device name, e.g. sata(prsnt) and sata(act), I don't think it is a good idea to use the subname but have sata(prsnt) and sata-1(act) instead. Otherwise, you'll always have to look up the specific function for each pin. OTOH, I could check for "sata" and take the subname into account when it is given in marvell,function. But it will not help reducing the required pinmux descriptions in DT because you still have to distinguish both and there are only 2 out of ~50 groups that have them for Dove.

Quoted 1 line

This looks good overall.

Thanks!
In some internal review with Andrew I also added a spinlock to mvebu_pinconf_get/_set that will protect all calls to generic and specific _get/_set register accesses. Moreover, I replaced clk_get_sys in pinctrl-dove with the devm_ counterpart and removed the explicit clk_put.

Sebastian

Thomas Petazzoni

2012-08-20 12:51 UTC #4 lore raw

Re: [PATCH 01/11] pinctrl: mvebu: pinctrl driver core

Hello,

Le Mon, 20 Aug 2012 11:46:14 +0200,
Sebastian Hesselbarth <[email protected]> a ?crit :

Quoted 12 lines

Quoted 11 lines
Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt line 33
Quoted 6 lines
Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt new file +6 -0
+uart1: serial at 12100 {
+       compatible = "ns16550a";
+       reg = <0x12100 0x100>;
+       reg-shift = <2>;
+       interrupts = <7>;
+       clock-frequency = <166666667>;
It's got nothing to do with this patch, but getting a clock frequency out of the DT instead of getting it from the clk_get_rate(clk) and the clock tree seems absurd... (But maybe this platform does not even have a clk implementation?)

Quoted 7 lines

It's of_serial's implementation. I patched that once for getting frequency out of "clocks" property but then I got busy with porting mach-dove and pinctrl.. Marvell SoCs do have a clk implementation and as soon as of_serial can handle "clocks" property it will be used for sure. I can remove "clock-frequency" from the example anyway as it is not really part of pinctrl binding documentation.

We are also working on using the clk framework for the 370/XP support (my colleague Gr?gory in Cc has started working on this last week), and we also want to be able to get the serial clock-frequency from the clk framework instead of an explicit value in the DT node. But that's a separate topic :)

Quoted 8 lines

Quoted 4 lines
Is it possible to use devm_* managed devm_kzalloc() for this map so you don't need to free it explicitly?
(Maybe not, just checking.)
Hmm, I guess not as I thought I've read not to use devm_kfree when you allocate _and_ free stuff on runtime without removing the device itself, right?

It is also my understanding that devm_*() functions should be used to allocate things that should persist until the device is removed. But I might be wrong here.

Quoted 9 lines

Quoted 6 lines
drivers/pinctrl/pinctrl-mvebu.h line 37
Quoted 4 lines
drivers/pinctrl/pinctrl-mvebu.h new file +4 -0
+struct mvebu_mpp_ctrl {
+       const char *name;
+       u8 pid;
+       u8 npins;
So, there will never be > 256 pins on a Marvell platform?
Well, with all current platforms we are well below 100. I guess 256 max (muxable) pins will be enough.

Agreed, and this structure is completely internal to the kernel, so we can easily change it in the future if needed.

Quoted 8 lines

Quoted 5 lines
Quoted 2 lines
+ * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
+ * @val: ctrl setting value
It is not obvious to me what this means, it it possible to elaborate on how this member is defined and used?
Well, I see if I can clarify the description but wrt the datasheet it _should_ be quite obvious.

I think the setting/function/group/control terminology would benefit from an explanation, as it isn't very easy to figure out what all these words mean in the context of the pinctrl-mvebu driver.

Quoted 4 lines

In some internal review with Andrew I also added a spinlock to mvebu_pinconf_get/_set that will protect all calls to generic and specific _get/_set register accesses. Moreover, I replaced clk_get_sys in pinctrl-dove with the devm_ counterpart and removed the explicit clk_put.

Yes, I had seen this discussion, but I am not sure it is needed: it seems the pinctrl core calls all the pinconf_set/pinconf_get methods with the pinctrl_mutex held. When I wrote an initial pinctrl driver for 370/XP I had the same question as Andrew and my conclusion was that the locking done by the pinctrl subsystem core was sufficient.

Best regards,

Thomas

Signature · 4 lines

Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Linus Walleij

2012-08-20 14:18 UTC #5 lore raw

Re: [PATCH 01/11] pinctrl: mvebu: pinctrl driver core

In reply to Linus Walleij

Quoted 7 lines · Sebastian Hesselbarth

Quoted 2 lines · Linus Walleij
Are you taking this patch series through some Marvell tree or do you want me to carry it in the pinctrl tree?
I think it would be better to take it through the Marvell tree of Jason Cooper. It is only for Marvell SoCs anyway.

OK.

Quoted 7 lines

Quoted 3 lines
There is some other "variant" field elsewhere that is a u8, is this correct? In this and the other case, should this "variant" rather be an enum?
I'll review the variant types but inside pinctrl-mvebu variant is used as a bit mask to distinguish different variants. Anyway, they should always be the same size.

Aha bitmask, seems you can only have 8 different variants of the Marvell's then?

Quoted 8 lines

Quoted 4 lines
Is it possible to use devm_* managed devm_kzalloc() for this map so you don't need to free it explicitly?
(Maybe not, just checking.)
Hmm, I guess not as I thought I've read not to use devm_kfree when you allocate _and_ free stuff on runtime without removing the device itself, right?

You're right.

Quoted 4 lines

Quoted 1 line
So, there will never be > 256 pins on a Marvell platform?
Well, with all current platforms we are well below 100. I guess 256 max (muxable) pins will be enough.

OK.

Quoted 8 lines

Quoted 5 lines
Quoted 2 lines
+ * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
+ * @val: ctrl setting value
It is not obvious to me what this means, it it possible to elaborate on how this member is defined and used?
Well, I see if I can clarify the description but wrt the datasheet it _should_ be quite obvious.

I mainly worry about being able to read the code and figure out what's going on, if the datasheet is vital then pls include some link to it or so in the header of the file (but preferrably the code should speak for itself).

Quoted 6 lines

Quoted 4 lines
Quoted 1 line
+ * @variant: (optional) variant identifier mask
This thing again, there are lots of "variants" around here. Is it a candidate for an enum?
As it is a mask, I don't think enum fits here.

OK. No big deal anyway.

Quoted 4 lines

In some internal review with Andrew I also added a spinlock to mvebu_pinconf_get/_set that will protect all calls to generic and specific _get/_set register accesses. Moreover, I replaced clk_get_sys in pinctrl-dove with the devm_ counterpart and removed the explicit clk_put.

I had some separate comments on that clk thing... Anyway, looking forward to v2, this is progressing quickly I think.

Yours,
Linus Walleij

Sebastian Hesselbarth

author maintainer

2012-08-20 14:51 UTC #6 lore raw

Re: [PATCH 01/11] pinctrl: mvebu: pinctrl driver core

Quoted 6 lines · Linus Walleij

Quoted 3 lines
I'll review the variant types but inside pinctrl-mvebu variant is used as a bit mask to distinguish different variants. Anyway, they should always be the same size.
Aha bitmask, seems you can only have 8 different variants of the Marvell's then?

Only 8 different variants of one SoC! Currently, there are 5 for Kirkwood, none for Dove. I think there are two more Kirkwood's that never appeared in public, but it is still < 8.

Quoted 7 lines

Quoted 2 lines
Well, I see if I can clarify the description but wrt the datasheet it _should_ be quite obvious.
I mainly worry about being able to read the code and figure out what's going on, if the datasheet is vital then pls include some link to it or so in the header of the file (but preferrably the code should speak for itself).

Ok, I clarify whats meant by mvebu_*_ctrl/ctrl_setting/mode. I am not that happy with that names either, but honestly pinctrl core already took all names that I'd have chosen. Therefore, I chose some that do not interfere with pinctrl core as the meaning is different.

Sebastian

Andrew Lunn

maintainer

2012-08-25 08:22 UTC #7 lore raw

Re: [PATCH 01/11] pinctrl: mvebu: pinctrl driver core

Quoted 11 lines · Linus Walleij

Quoted 3 lines · Sebastian Hesselbarth
This patch adds a pinctrl driver core for Marvell SoCs plus DT binding documentation. This core driver will be used by SoC family specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.
Thanks for dealing with this, much appreaciated!
Are you taking this patch series through some Marvell tree or do you want me to carry it in the pinctrl tree?

Hi Linus

We can carry it thought the Marvell tree.

Andrew

Linus Walleij

2012-08-20 14:11 UTC #8 lore raw

Re: [PATCH 01/11] pinctrl: mvebu: pinctrl driver core

Quoted 3 lines · Sebastian Hesselbarth

This patch adds a pinctrl driver core for Marvell SoCs plus DT binding documentation. This core driver will be used by SoC family specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.

(...)

drivers/pinctrl/Kconfig config PINCTRL_COH901 · line 150

Quoted 3 lines

drivers/pinctrl/Kconfig +3 -0

+config PINCTRL_MVEBU
+       bool "Marvell SoC pin controller drivers"
+       depends on ARCH_MVEBU

So altering earlier statements I suspect this should be simply:

depends on PLAT_ORION

Yours,
Linus Walleij

Sebastian Hesselbarth

author maintainer

2012-08-11 12:56 UTC #9 lore raw

PATCH 2/11 pinctrl: mvebu: dove pinctrl driver

In reply to Linus Walleij

This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core.

Signed-off-by Sebastian Hesselbarth <[email protected]>

---
 .../bindings/pinctrl/marvell,dove-pinctrl.txt      |   71 +++
 arch/arm/Kconfig                                   |    1 +
 drivers/pinctrl/Kconfig                            |    9 +-
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-dove.c                     |  622 ++++++++++++++++++++
 5 files changed, 703 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-dove.c

Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt new file +71 -0

new file mode 100644
index 0000000..9e6eea2
@@ -0,0 +1,71 @@
+* Marvell Dove SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,dove-pinctrl"
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
+mpp1          1        gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
+mpp2          2        gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
+                       uart1(rts)
+mpp3          3        gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
+                       uart1(cts), lcd-spi(cs1)
+mpp4          4        gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
+mpp5          5        gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
+mpp6          6        gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
+mpp7          7        gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
+mpp8          8        gpio, pmu, watchdog(rstout)
+mpp9          9        gpio, pmu, pex1(clkreq)
+mpp10         10       gpio, pmu, ssp(sclk)
+mpp11         11       gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
+                       sdio1(ledctrl), pex0(clkreq)
+mpp12         12       gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
+mpp13         13       gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
+                       ssp(extclk)
+mpp14         14       gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
+mpp15         15       gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
+mpp16         16       gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
+mpp17         17       gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
+                       ac97-1(sysclko)
+mpp18         18       gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
+mpp19         19       gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
+mpp20         20       gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
+                       ac97(sysclko)
+mpp21         21       gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
+                       uart1(cts), ssp(sfrm)
+mpp22         22       gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
+                       lcd-spi(mosi), uart1(cts), ssp(txd)
+mpp23         23       gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
+                       lcd-spi(sck), ssp(sclk)
+mpp_camera    24-39    gpio, camera
+mpp_sdio0     40-45    gpio, sdio0
+mpp_sdio1     46-51    gpio, sdio1
+mpp_audio1    52-57    gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
+                       ssp/twsi
+mpp_spi0      58-61    gpio, spi0
+mpp_uart1     62-63    gpio, uart1
+mpp_nand      64-71    gpo, nand
+audio0        -        i2s, ac97
+twsi          -        none, opt1, opt2, opt3
+
+Notes:
+* group "mpp_audio1" allows the following functions and gpio pins:
+  - gpio          : gpio on pins 52-57
+  - i2s1/spdifo   : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
+  - i2s1          : audio1 i2s on pins 52-55, gpio on pins 56,57
+  - spdifo        : spdifo on pin 57, gpio on pins 52-55
+  - twsi          : twsi on pins 56,57, gpio on pins 52-55
+  - ssp/spdifo    : ssp on pins 52-55, spdifo on pin 57, no gpios
+  - ssp           : ssp on pins 52-55, gpio on pins 56,57
+  - ssp/twsi      : ssp on pins 52-55, twsi on pins 56,57, no gpios
+* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
+  audio0 pins.
+* group "twsi" internally muxes twsi controller to the dedicated or option pins.

arch/arm/Kconfig +1 -0

index e91c7cd..cd3d827 100644
@@ -584,6 +584,7 @@ config ARCH_DOVE
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
 	select PLAT_ORION
+	select PINCTRL
 	help
 	  Support for the Marvell Dove SoC 88AP510

drivers/pinctrl/Kconfig +8 -1

index b968335..e2427eb 100644
@@ -147,7 +147,7 @@ config PINCTRL_COH901
 
 config PINCTRL_MVEBU
 	bool "Marvell SoC pin controller drivers"
-	depends on ARCH_MVEBU
+	depends on ARCH_MVEBU || ARCH_DOVE
 	select PINMUX
 	select PINCONF
 	help

@@ -155,6 +155,13 @@ config PINCTRL_MVEBU
 	  This is only the driver core and additionally needs a SoC specific
 	  driver.
 
+config PINCTRL_DOVE
+	bool "Support for Marvell Dove SoCs"
+	depends on PINCTRL_MVEBU
+	help
+	  Say yes here to support pinctrl driver on Marvell Dove SoCs
+	  (88AP510).
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index 007ed32..d1327df 100644
@@ -30,5 +30,6 @@ obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
+obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-dove.c new file +622 -0

622 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Linus Walleij

2012-08-20 13:43 UTC #10 lore raw

Re: [PATCH 02/11] pinctrl: mvebu: dove pinctrl driver

On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth <[email protected]> wrote:

(...)

drivers/pinctrl/Kconfig config PINCTRL_COH901 · line 150

Quoted 7 lines

drivers/pinctrl/Kconfig +1 -1

@@ -147,7 +147,7 @@ config PINCTRL_COH901
 
 config PINCTRL_MVEBU
        bool "Marvell SoC pin controller drivers"
-       depends on ARCH_MVEBU
+       depends on ARCH_MVEBU || ARCH_DOVE

Hmmmm.

Shouldn't this thing rather be:

depends on PLAT_ORION

else you end up lining up all Marvell machines here...

drivers/pinctrl/Kconfig config PINCTRL_MVEBU · line 160

Quoted 10 lines

drivers/pinctrl/Kconfig +3 -0

        select PINMUX
        select PINCONF
        help

@@ -155,6 +155,13 @@ config PINCTRL_MVEBU
          This is only the driver core and additionally needs a SoC specific
          driver.
 
+config PINCTRL_DOVE
+       bool "Support for Marvell Dove SoCs"
+       depends on PINCTRL_MVEBU

Shouldn't this rather be:

depends on ARCH_DOVE
select PINCTRL_MVEBU

since you call down into the mvebu driver, it definatley needs to select that.

(...)

drivers/pinctrl/pinctrl-dove.c

Quoted 3 lines

drivers/pinctrl/pinctrl-dove.c +1 -0

 
+#define  DOVE_AU0_AC97_SEL             (1 << 16)

It is way cleaner to say:

#include <linux/bitops.h>

#define DOVE_AU0_AC97_SEL BIT(16)

(...)

Quoted 4 lines

drivers/pinctrl/pinctrl-dove.c +4 -0

+static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+                                unsigned long *config)
+{
+       unsigned off = (ctrl->pid / 8) * 4;

drivers/pinctrl/pinctrl-dove.c line 61

Quoted 10 lines

drivers/pinctrl/pinctrl-dove.c +10 -0

+       unsigned shift = (ctrl->pid % 8) * 4;
+       unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+       unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
+
+       if (pmu & (1 << ctrl->pid))
+               *config = 0x10;
+       else
+               *config = (mpp >> shift) & 0xf;
+       return 0;
+}

Same comments about the magic numbers as in the review of the first patch.

Quoted 8 lines

drivers/pinctrl/pinctrl-dove.c +8 -0

+static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+                                unsigned long config)
+{
+       unsigned off = (ctrl->pid / 8) * 4;
+       unsigned shift = (ctrl->pid % 8) * 4;
+       unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+       unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
+

drivers/pinctrl/pinctrl-dove.c line 80

Quoted 10 lines

drivers/pinctrl/pinctrl-dove.c +10 -0

+       if (config == 0x10)
+               writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
+       else {
+               writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
+               mpp &= ~(0xf << shift);
+               mpp |= config << shift;
+               writel(mpp, DOVE_MPP_VIRT_BASE + off);
+       }
+       return 0;
+}

Dito.

Quoted 8 lines

drivers/pinctrl/pinctrl-dove.c +8 -0

+static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+                             unsigned long *config)
+{
+       unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+       unsigned long mask;
+
+       if (ctrl->pid == 24)
+               mask = DOVE_CAM_GPIO_SEL;

drivers/pinctrl/pinctrl-dove.c line 99

Quoted 10 lines

drivers/pinctrl/pinctrl-dove.c +10 -0

+       else if (ctrl->pid == 40)
+               mask = DOVE_SD0_GPIO_SEL;
+       else if (ctrl->pid == 46)
+               mask = DOVE_SD1_GPIO_SEL;
+       else if (ctrl->pid == 58)
+               mask = DOVE_SPI_GPIO_SEL;
+       else if (ctrl->pid == 62)
+               mask = DOVE_UART1_GPIO_SEL;
+       else
+               return -EINVAL;

Magic numbers, atleast provide a comment on what is so special about these pins, and can you use a switch() statement instead?

(...)

Quoted 8 lines

drivers/pinctrl/pinctrl-dove.c +8 -0

+static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+                             unsigned long config)
+{
+       unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+       unsigned long mask;
+
+       if (ctrl->pid == 24)
+               mask = DOVE_CAM_GPIO_SEL;

drivers/pinctrl/pinctrl-dove.c line 123

Quoted 10 lines

drivers/pinctrl/pinctrl-dove.c +10 -0

+       else if (ctrl->pid == 40)
+               mask = DOVE_SD0_GPIO_SEL;
+       else if (ctrl->pid == 46)
+               mask = DOVE_SD1_GPIO_SEL;
+       else if (ctrl->pid == 58)
+               mask = DOVE_SPI_GPIO_SEL;
+       else if (ctrl->pid == 62)
+               mask = DOVE_UART1_GPIO_SEL;
+       else
+               return -EINVAL;

Dito.

(...)

Quoted 7 lines

drivers/pinctrl/pinctrl-dove.c +7 -0

+static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+                               unsigned long *config)
+{
+       unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+       unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
+       unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+       unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);

drivers/pinctrl/pinctrl-dove.c line 197

Quoted 10 lines

drivers/pinctrl/pinctrl-dove.c +10 -0

+
+       *config = 0;
+       if (mpp4 & DOVE_AU1_GPIO_SEL)
+               *config |= 0x8;
+       if (sspc1 & DOVE_SSP_ON_AU1)
+               *config |= 0x4;
+       if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN)
+               *config |= 0x2;
+       if (gcfg2 & DOVE_TWSI_OPTION3_GPIO)
+               *config |= 0x1;

More magic, but the flags make it clear what the set bits are all about, so OK.

But I would have:
#include <linux/bitops.h>

*config |= BIT(0);

etc.

drivers/pinctrl/pinctrl-dove.c line 205

Quoted 7 lines

drivers/pinctrl/pinctrl-dove.c +7 -0

+       /* SSP/TWSI only if I2S1 not set*/
+       if ((*config & 0x8) == 0)
+               *config &= ~(0x4 | 0x1);
+       /* TWSI only if SPDIFO not set*/
+       if ((*config & 0x2) == 0)
+               *config &= ~(0x1);
+       return 0;

And that applies to these.

Quoted 6 lines

drivers/pinctrl/pinctrl-dove.c +6 -0

+static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+                               unsigned long config)
+{
+       unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+       unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
+       unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);

drivers/pinctrl/pinctrl-dove.c line 223

Quoted 10 lines

drivers/pinctrl/pinctrl-dove.c +10 -0

+       unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+       if (config & 0x1)
+               gcfg2 |= DOVE_TWSI_OPTION3_GPIO;
+       if (config & 0x2)
+               gmpp |= DOVE_AU1_SPDIFO_GPIO_EN;
+       if (config & 0x4)
+               sspc1 |= DOVE_SSP_ON_AU1;
+       if (config & 0x8)
+               mpp4 |= DOVE_AU1_GPIO_SEL;

Dito.

Quoted 4 lines

drivers/pinctrl/pinctrl-dove.c +4 -0

+static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid)
+{
+       unsigned long config;
+

drivers/pinctrl/pinctrl-dove.c line 251

Quoted 10 lines

drivers/pinctrl/pinctrl-dove.c +10 -0

+       dove_audio1_ctrl_get(ctrl, &config);
+
+       switch (config) {
+       /* mode 0x00 i2s1/spdifo : no gpio */
+       /* mode 0x0c ssp/spdifo  : no gpio */
+       /* mode 0x0f ssp/twsi    : no gpio */
+       case 0x00:
+       case 0x0c:
+       case 0x0f:
+               return -ENOTSUPP;

Nice with the comments (also before the function), now I understand what's happening, this is pretty OK, I would have put the comments on the same line as the magic number but whatever.

However you could just delete these lines and let them fall through to -ENOTSUPP at the bottom.

Quoted 19 lines

drivers/pinctrl/pinctrl-dove.c +19 -0

+
+       /* mode 0x02 i2s1 : gpio[56:57] */
+       /* mode 0x0e ssp  : gpio[56:57] */
+       case 0x02:
+       case 0x0e:
+               if (pid >= 56)
+                       return 0;
+
+       /* mode 0x08 spdifo : gpio[52:55] */
+       /* mode 0x0b twsi   : gpio[52:55] */
+       case 0x08:
+       case 0x0b:
+               if (pid <= 55)
+                       return 0;
+
+       /* mode 0x0a/gpio : all gpio */
+       case 0x0a:
+               return 0;
+       }

drivers/pinctrl/pinctrl-dove.c line 280

Quoted 10 lines

drivers/pinctrl/pinctrl-dove.c +9 -0

+
+       return -ENOTSUPP;
+}
 
+/* mpp[52:57] has gpio pins capable of in and out */
+static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl *ctrl, u8 pid,
+                               bool input)
+{
+       return 0;
+}

So should this not return a -ENOTSUPP for
pin < 52 || pin > 57?

(...)

Quoted 4 lines

drivers/pinctrl/pinctrl-dove.c +4 -0

+static int __devinit dove_pinctrl_probe(struct platform_device *pdev)
+{
+       const struct of_device_id *match =
+               of_match_device(dove_pinctrl_of_match, &pdev->dev);

drivers/pinctrl/pinctrl-dove.c line 580

Quoted 10 lines

drivers/pinctrl/pinctrl-dove.c +10 -0

+       int ret;
+
+       if (match)
+               pdev->dev.platform_data = match->data;
+
+       /*
+        * General MPP Configuration Register is part of pdma registers.
+        * grab clk to make sure it is clocked.
+        */
+       pdma_clk = clk_get_sys("dove-pdma", NULL);

First there is something really weird with the name of this clock. Atleast call the variable holding the clk something apropriate like just "clk".

Second why are you fetching a sys clock instead of using the clkdev device binding in the clock tree so you could say:

clk = clk_get(&pdev->dev, NULL);

Quoted 1 line

+ clk_prepare_enable(pdma_clk);

Good!

Quoted 8 lines

drivers/pinctrl/pinctrl-dove.c +8 -0

+       ret = mvebu_pinctrl_probe(pdev);
+       if (!ret)
+               return 0;
+
+       clk_disable_unprepare(pdma_clk);
+       clk_put(pdma_clk);
+       return ret;
+}

drivers/pinctrl/pinctrl-dove.c line 604

Quoted 10 lines

drivers/pinctrl/pinctrl-dove.c +10 -0

+
+static int __devexit dove_pinctrl_remove(struct platform_device *pdev)
+{
+       int ret;
+
+       ret = mvebu_pinctrl_remove(pdev);
+       if (!IS_ERR(pdma_clk)) {
+               clk_disable_unprepare(pdma_clk);
+               clk_put(pdma_clk);
+       }

You don't need this (!IS_ERR()) clause, look in yout probe function:
you bail out if the clock is not found.

The rest looks good... atleast now, but I'm low on coffee FTM.

Yours,
Linus Walleij

Sebastian Hesselbarh

author maintainer

2012-08-20 14:43 UTC #11 lore raw

Re: [PATCH 02/11] pinctrl: mvebu: dove pinctrl driver

Quoted 15 lines · Linus Walleij

drivers/pinctrl/Kconfig config PINCTRL_COH901 · line 150
Quoted 4 lines
config PINCTRL_MVEBU
bool "Marvell SoC pin controller drivers"
drivers/pinctrl/Kconfig +1 -1
-       depends on ARCH_MVEBU
+       depends on ARCH_MVEBU || ARCH_DOVE
Hmmmm.
Shouldn't this thing rather be:
depends on PLAT_ORION
else you end up lining up all Marvell machines here... (...)
drivers/pinctrl/Kconfig config PINCTRL_MVEBU · line 160
Quoted 3 lines
drivers/pinctrl/Kconfig +3 -0
+config PINCTRL_DOVE
+       bool "Support for Marvell Dove SoCs"
+       depends on PINCTRL_MVEBU

Quoted 7 lines

Shouldn't this rather be:
depends on ARCH_DOVE
select PINCTRL_MVEBU
since you call down into the mvebu driver, it definatley needs to select that.

Yes, this is a bit difficult but PLAT_ORION is basically all existing Marvell SoCs of the Orion family. Armada 370/XP are two new SoCs _and_ the approach to combine all into one mach-mvebu. The pinctrl driver will only be made available to mach-mvebu as I am already close to have at least mach-dove ported over.

After the review of Andrew, I already changed the Kconfig to have the structure you are proposing.

Quoted 5 lines

Quoted 1 line
+#define DOVE_AU0_AC97_SEL (1<< 16)
It is way cleaner to say:
#include<linux/bitops.h>
#define DOVE_AU0_AC97_SEL BIT(16)

Ok.

Quoted 2 lines

Same comments about the magic numbers as in the review of the first patch.

I just agree with all of these comments and will work them in.

Quoted 13 lines

drivers/pinctrl/pinctrl-dove.c line 99

Quoted 12 lines

drivers/pinctrl/pinctrl-dove.c new file +12 -0

+       if (ctrl->pid == 24)
+               mask = DOVE_CAM_GPIO_SEL;
+       else if (ctrl->pid == 40)
+               mask = DOVE_SD0_GPIO_SEL;
+       else if (ctrl->pid == 46)
+               mask = DOVE_SD1_GPIO_SEL;
+       else if (ctrl->pid == 58)
+               mask = DOVE_SPI_GPIO_SEL;
+       else if (ctrl->pid == 62)
+               mask = DOVE_UART1_GPIO_SEL;
+       else
+               return -EINVAL;

Quoted 2 lines

Magic numbers, atleast provide a comment on what is so special about these pins, and can you use a switch() statement instead?

Sure.

Quoted 20 lines

Quoted 4 lines
drivers/pinctrl/pinctrl-dove.c new file +4 -0
+static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid)
+{
+       unsigned long config;
+
drivers/pinctrl/pinctrl-dove.c line 251
Quoted 10 lines
drivers/pinctrl/pinctrl-dove.c new file +10 -0
+       dove_audio1_ctrl_get(ctrl,&config);
+
+       switch (config) {
+       /* mode 0x00 i2s1/spdifo : no gpio */
+       /* mode 0x0c ssp/spdifo  : no gpio */
+       /* mode 0x0f ssp/twsi    : no gpio */
+       case 0x00:
+       case 0x0c:
+       case 0x0f:
+               return -ENOTSUPP;
Nice with the comments (also before the function), now I understand what's happening, this is pretty OK, I would have put the comments on the same line as the magic number but whatever.

Quoted 2 lines

However you could just delete these lines and let them fall through to -ENOTSUPP at the bottom.

Ok.

Quoted 9 lines

drivers/pinctrl/pinctrl-dove.c line 280
Quoted 6 lines
drivers/pinctrl/pinctrl-dove.c new file +6 -0
+/* mpp[52:57] has gpio pins capable of in and out */
+static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl *ctrl, u8 pid,
+                               bool input)
+{
+       return 0;
+}
So should this not return a -ENOTSUPP for
pin< 52 || pin> 57?

Well, as pinctrl-mvebu and pinctrl core are already checking for pin ranges, I think it's ok not to do it here again. But I don't have a strong opinion about that.

Quoted 6 lines

drivers/pinctrl/pinctrl-dove.c line 580

Quoted 5 lines

drivers/pinctrl/pinctrl-dove.c new file +5 -0

+       /*
+        * General MPP Configuration Register is part of pdma registers.
+        * grab clk to make sure it is clocked.
+        */
+       pdma_clk = clk_get_sys("dove-pdma", NULL);

Quoted 8 lines

First there is something really weird with the name of this clock. Atleast call the variable holding the clk something apropriate like just "clk".
Second why are you fetching a sys clock instead of using the clkdev device binding in the clock tree so you could say:
clk = clk_get(&pdev->dev, NULL);

pdma is the name of the clock gating control bit used in DS, IIRC it stands for Peripheral DMA. Moreover, as I already mentioned it is now using devm_clk_get. I think the time the pinctrl-dove driver patch was posted there was no clock binding in 3.6.

Quoted 4 lines

Quoted 4 lines
drivers/pinctrl/pinctrl-dove.c new file +4 -0
+static int __devexit dove_pinctrl_remove(struct platform_device *pdev)
+{
+       int ret;
+

Quoted 8 lines

drivers/pinctrl/pinctrl-dove.c line 604
Quoted 5 lines
drivers/pinctrl/pinctrl-dove.c new file +5 -0
+       ret = mvebu_pinctrl_remove(pdev);
+       if (!IS_ERR(pdma_clk)) {
+               clk_disable_unprepare(pdma_clk);
+               clk_put(pdma_clk);
+       }
You don't need this (!IS_ERR()) clause, look in yout probe function:
you bail out if the clock is not found.

Agree.

Sebastian

Thomas Petazzoni

2012-08-20 17:16 UTC #12 lore raw

Re: [PATCH 02/11] pinctrl: mvebu: dove pinctrl driver

Le Mon, 20 Aug 2012 15:43:11 +0200,
Linus Walleij <[email protected]> a ?crit :

Quoted 5 lines

drivers/pinctrl/Kconfig config PINCTRL_COH901 · line 150
Quoted 4 lines
config PINCTRL_MVEBU
bool "Marvell SoC pin controller drivers"
drivers/pinctrl/Kconfig +1 -1
-       depends on ARCH_MVEBU
+       depends on ARCH_MVEBU || ARCH_DOVE

Quoted 7 lines

Hmmmm.
Shouldn't this thing rather be:
depends on PLAT_ORION
else you end up lining up all Marvell machines here...

When we started working on this, ARCH_MVEBU was not a PLAT_ORION platform, because PLAT_ORION includes its own custom pinmux code, gpio code, etc, and what we're trying to achieve with Sebastian is to clean all this. Ultimately, our goal is to have all Orion, Kirkwood, Dove, Discovery and Armada 370/XP supported in mach-mvebu, and therefore plat-orion would most likely disappear.

In the mean time, a patch got accepted that separates PLAT_ORION for PLAT_ORION_LEGACY, and therefore MACH_MVEBU now selects PLAT_ORION to access things that are still useful (address decoding code) while all other platforms select PLAT_ORION_LEGACY to get the old pinmux code, old gpio code, etc. All this is very much a work in progress.

Best regards,

Thomas

Signature · 4 lines

Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Sebastian Hesselbarth

author maintainer

2012-08-11 12:56 UTC #13 lore raw

PATCH 3/11 pinctrl: mvebu: kirkwood pinctrl driver

This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core.

Signed-off-by Sebastian Hesselbarth <[email protected]>

---
 .../bindings/pinctrl/marvell,kirkwood-pinctrl.txt  |  279 ++++++++++++
 arch/arm/Kconfig                                   |    1 +
 drivers/pinctrl/Kconfig                            |    9 +-
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-kirkwood.c                 |  460 ++++++++++++++++++++
 5 files changed, 749 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-kirkwood.c

Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt new file +279 -0

new file mode 100644
index 0000000..361bccb
@@ -0,0 +1,279 @@
+* Marvell Kirkwood SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6180-pinctrl",
+              "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
+              "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
+
+This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Kirkwood 88f6180
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17         17       gpio, sdio(d3)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, mii(rxerr)
+mpp21         21       gpio, audio(spdifi)
+mpp22         22       gpio, audio(spdifo)
+mpp23         23       gpio, audio(rmclk)
+mpp24         24       gpio, audio(bclk)
+mpp25         25       gpio, audio(sdo)
+mpp26         26       gpio, audio(lrclk)
+mpp27         27       gpio, audio(mclk)
+mpp28         28       gpio, audio(sdi)
+mpp29         29       gpio, audio(extclk)
+
+* Marvell Kirkwood 88f6190
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0)
+mpp21         21       gpio, ge1(txd1), sata0(act)
+mpp22         22       gpio, ge1(txd2)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt)
+mpp24         24       gpio, ge1(rxd0)
+mpp25         25       gpio, ge1(rxd1)
+mpp26         26       gpio, ge1(rxd2)
+mpp27         27       gpio, ge1(rxd3)
+mpp28         28       gpio, ge1(col)
+mpp29         29       gpio, ge1(txclk)
+mpp30         30       gpio, ge1(rxclk)
+mpp31         31       gpio, ge1(rxclk)
+mpp32         32       gpio, ge1(txclko)
+mpp33         33       gpo, ge1(txclk)
+mpp34         34       gpio, ge1(txen)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr)
+
+* Marvell Kirkwood 88f6192
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33         33       gpo, ge1(txclk), tdm(drx)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+
+* Marvell Kirkwood 88f6281
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpio, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33         33       gpo, ge1(txclk), tdm(drx)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi)
+mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo)
+mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk)
+mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk)
+mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo)
+mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
+mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk)
+mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi)
+mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk)
+mpp45         45       gpio, ts(mp9), tdm(pclk)
+mpp46         46       gpio, ts(mp10), tdm(fs)
+mpp47         47       gpio, ts(mp11), tdm(drx)
+mpp48         48       gpio, ts(mp12), tdm(dtx)
+mpp49         49       gpio, ts(mp9), tdm(rx0ql), ptp(clk)
+
+* Marvell Kirkwood 88f6282
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync)
+mpp5          5        gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync)
+mpp6          6        sysrst(out), spi(mosi)
+mpp7          7        gpo, spi(cs), lcd(pwm)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
+                       mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
+                       sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), sata0(act)
+mpp12         12       gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda)
+mpp13         13       gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt),
+                       audio(spdifi), audio-1(sdi)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
+                       spi(cs)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act), lcd(extclk)
+mpp17         17       gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck)
+mpp18         18       gpo, nand(io0), pex(clkreq)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act), lcd(d0)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo), lcd(d1)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt), lcd(d2)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk), lcd(d3)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo),
+                       lcd(d4)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
+                       lcd(d5)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk),
+                       lcd(d6)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi),
+                       lcd(d7)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk),
+                       lcd(d8)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12)
+mpp33         33       gpo, ge1(txclk), tdm(drx), lcd(d13)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql),
+                       lcd(d15)
+mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda)
+mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck)
+mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18)
+mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19)
+mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20)
+mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
+mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22)
+mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23)
+mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk)
+mpp45         45       gpio, ts(mp9), tdm(pclk), lcd(e)
+mpp46         46       gpio, ts(mp10), tdm(fs), lcd(hsync)
+mpp47         47       gpio, ts(mp11), tdm(drx), lcd(vsync)
+mpp48         48       gpio, ts(mp12), tdm(dtx), lcd(d16)
+mpp49         49       gpo, tdm(rx0ql), pex(clkreq), lcd(d17)

arch/arm/Kconfig +1 -0

index cd3d827..361f513 100644
@@ -596,6 +596,7 @@ config ARCH_KIRKWOOD
 	select GENERIC_CLOCKEVENTS
 	select NEED_MACH_IO_H
 	select PLAT_ORION
+	select PINCTRL
 	help
 	  Support for the following Marvell Kirkwood series SoCs:
 	  88F6180, 88F6192 and 88F6281.

drivers/pinctrl/Kconfig +8 -1

index e2427eb..1f84090 100644
@@ -147,7 +147,7 @@ config PINCTRL_COH901
 
 config PINCTRL_MVEBU
 	bool "Marvell SoC pin controller drivers"
-	depends on ARCH_MVEBU || ARCH_DOVE
+	depends on ARCH_MVEBU || ARCH_DOVE || ARCH_KIRKWOOD
 	select PINMUX
 	select PINCONF
 	help

@@ -162,6 +162,13 @@ config PINCTRL_DOVE
 	  Say yes here to support pinctrl driver on Marvell Dove SoCs
 	  (88AP510).
 
+config PINCTRL_KIRKWOOD
+	bool "Support for Marvell Kirkwood SoCs"
+	depends on PINCTRL_MVEBU
+	help
+	  Say yes here to support pinctrl driver on Marvell Kirkwood SoCs
+	  (88f6180, 88f6190, 88f6192, 88f6281, 88f6282).
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index d1327df..3006294 100644
@@ -31,5 +31,6 @@ obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
+obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-kirkwood.c new file +460 -0

460 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Linus Walleij

2012-08-20 13:49 UTC #14 lore raw

Re: [PATCH 03/11] pinctrl: mvebu: kirkwood pinctrl driver

Quoted 3 lines · Sebastian Hesselbarth

This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core.

Thanks for working on Kirkwood. Love this platform.

arch/arm/Kconfig config ARCH_KIRKWOOD · line 599

Quoted 9 lines

arch/arm/Kconfig +1 -0

index cd3d827..361f513 100644
@@ -596,6 +596,7 @@ config ARCH_KIRKWOOD
        select GENERIC_CLOCKEVENTS
        select NEED_MACH_IO_H
        select PLAT_ORION
+       select PINCTRL

select PINCTRL_KIRKWOOD too I think.
Then it's just automatic.

drivers/pinctrl/Kconfig config PINCTRL_COH901 · line 150

Quoted 10 lines

drivers/pinctrl/Kconfig +1 -1

index e2427eb..1f84090 100644
@@ -147,7 +147,7 @@ config PINCTRL_COH901
 
 config PINCTRL_MVEBU
        bool "Marvell SoC pin controller drivers"
-       depends on ARCH_MVEBU || ARCH_DOVE
+       depends on ARCH_MVEBU || ARCH_DOVE || ARCH_KIRKWOOD

As stated elsewhere I think this should be
depends on PLAT_ORION

drivers/pinctrl/Kconfig config PINCTRL_DOVE · line 167

Quoted 3 lines

drivers/pinctrl/Kconfig +3 -0

+config PINCTRL_KIRKWOOD
+       bool "Support for Marvell Kirkwood SoCs"
+       depends on PINCTRL_MVEBU

depends on ARCH_KIRKWOOD
select PINCTRL_MVEBU

(...)

Quoted 6 lines

drivers/pinctrl/pinctrl-kirkwood.c +5 -0

+static struct mvebu_pinctrl_soc_info kirkwood_pinctrl_info;
+
+static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata = {
+       { .compatible = "marvell,88f6180-pinctrl",
+                                         .data = (void *)VARIANT_MV88F6180 },

drivers/pinctrl/pinctrl-kirkwood.c line 398

Quoted 10 lines

drivers/pinctrl/pinctrl-kirkwood.c +10 -0

+       { .compatible = "marvell,88f6190-pinctrl",
+                                         .data = (void *)VARIANT_MV88F6190 },
+       { .compatible = "marvell,88f6192-pinctrl",
+                                         .data = (void *)VARIANT_MV88F6192 },
+       { .compatible = "marvell,88f6281-pinctrl",
+                                         .data = (void *)VARIANT_MV88F6281 },
+       { .compatible = "marvell,88f6282-pinctrl",
+                                         .data = (void *)VARIANT_MV88F6282 },
+       { }
+};

I'm thinking this variant should maybe be an enum... unless it is strongly established somewhere in Orion/Marvell stuff.

Quoted 30 lines

drivers/pinctrl/pinctrl-kirkwood.c +30 -0

+static int __devinit kirkwood_pinctrl_probe(struct platform_device *pdev)
+{
+       struct mvebu_pinctrl_soc_info *soc = &kirkwood_pinctrl_info;
+       const struct of_device_id *match =
+               of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
+
+       if (match) {
+               soc->variant = (unsigned)match->data & 0xff;
+               switch (soc->variant) {
+               case VARIANT_MV88F6180:
+                       soc->controls = mv88f6180_mpp_controls;
+                       soc->ncontrols = ARRAY_SIZE(mv88f6180_mpp_controls);
+                       soc->modes = mv88f6xxx_mpp_modes;
+                       soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+                       soc->gpioranges = mv88f6180_gpio_ranges;
+                       soc->ngpioranges = ARRAY_SIZE(mv88f6180_gpio_ranges);
+                       break;
+               case VARIANT_MV88F6190:
+               case VARIANT_MV88F6192:
+                       soc->controls = mv88f619x_mpp_controls;
+                       soc->ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls);
+                       soc->modes = mv88f6xxx_mpp_modes;
+                       soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+                       soc->gpioranges = mv88f619x_gpio_ranges;
+                       soc->ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges);
+                       break;
+               case VARIANT_MV88F6281:
+               case VARIANT_MV88F6282:
+                       soc->controls = mv88f628x_mpp_controls;
+                       soc->ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls);

drivers/pinctrl/pinctrl-kirkwood.c line 439

Quoted 10 lines

drivers/pinctrl/pinctrl-kirkwood.c +10 -0

+                       soc->modes = mv88f6xxx_mpp_modes;
+                       soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+                       soc->gpioranges = mv88f628x_gpio_ranges;
+                       soc->ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges);
+                       break;
+               }
+               pdev->dev.platform_data = soc;
+       }
+       return mvebu_pinctrl_probe(pdev);
+}

This is looking real good, clean & nice.

No further comments on this driver.

Yours,
Linus Walleij

Ben Dooks

2012-08-27 13:43 UTC #15 lore raw

Re: [PATCH 03/11] pinctrl: mvebu: kirkwood pinctrl driver

Quoted 116 lines · Linus Walleij

Quoted 5 lines · Sebastian Hesselbarth
This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs
plus DT binding documentation. This driver will use the mvebu pinctrl
driver core.
Thanks for working on Kirkwood. Love this platform.
arch/arm/Kconfig config ARCH_KIRKWOOD · line 599
Quoted 9 lines
arch/arm/Kconfig +1 -0
index cd3d827..361f513 100644
@@ -596,6 +596,7 @@ config ARCH_KIRKWOOD
        select GENERIC_CLOCKEVENTS
        select NEED_MACH_IO_H
        select PLAT_ORION
+       select PINCTRL
select PINCTRL_KIRKWOOD too I think.
Then it's just automatic.
drivers/pinctrl/Kconfig config PINCTRL_COH901 · line 150
Quoted 10 lines
drivers/pinctrl/Kconfig +1 -1
index e2427eb..1f84090 100644
@@ -147,7 +147,7 @@ config PINCTRL_COH901
 
 config PINCTRL_MVEBU
        bool "Marvell SoC pin controller drivers"
-       depends on ARCH_MVEBU || ARCH_DOVE
+       depends on ARCH_MVEBU || ARCH_DOVE || ARCH_KIRKWOOD
As stated elsewhere I think this should be
depends on PLAT_ORION
drivers/pinctrl/Kconfig config PINCTRL_DOVE · line 167
Quoted 3 lines
drivers/pinctrl/Kconfig +3 -0
+config PINCTRL_KIRKWOOD
+       bool "Support for Marvell Kirkwood SoCs"
+       depends on PINCTRL_MVEBU
depends on ARCH_KIRKWOOD
select PINCTRL_MVEBU
(...)
Quoted 21 lines
drivers/pinctrl/pinctrl-kirkwood.c +3 -0
+static struct mvebu_pinctrl_soc_info kirkwood_pinctrl_info;
+
+static struct of_device_id kirkwood_pinctrl_of_match[] 
__devinitdata = {
drivers/pinctrl/pinctrl-kirkwood.c +2 -0
+       { .compatible = "marvell,88f6180-pinctrl",
+                                         .data = (void 
*)VARIANT_MV88F6180 },
drivers/pinctrl/pinctrl-kirkwood.c +2 -0
+       { .compatible = "marvell,88f6190-pinctrl",
+                                         .data = (void 
*)VARIANT_MV88F6190 },
drivers/pinctrl/pinctrl-kirkwood.c +2 -0
+       { .compatible = "marvell,88f6192-pinctrl",
+                                         .data = (void 
*)VARIANT_MV88F6192 },
drivers/pinctrl/pinctrl-kirkwood.c +2 -0
+       { .compatible = "marvell,88f6281-pinctrl",
+                                         .data = (void 
*)VARIANT_MV88F6281 },
drivers/pinctrl/pinctrl-kirkwood.c +2 -0
+       { .compatible = "marvell,88f6282-pinctrl",
+                                         .data = (void 
*)VARIANT_MV88F6282 },
drivers/pinctrl/pinctrl-kirkwood.c
Quoted 2 lines
drivers/pinctrl/pinctrl-kirkwood.c +2 -0
+       { }
+};
I'm thinking this variant should maybe be an enum... unless it is strongly established somewhere in Orion/Marvell stuff.
Quoted 43 lines
+static int __devinit kirkwood_pinctrl_probe(struct platform_device *pdev)
drivers/pinctrl/pinctrl-kirkwood.c +4 -0
+{
+       struct mvebu_pinctrl_soc_info *soc = &kirkwood_pinctrl_info;
+       const struct of_device_id *match =
+               of_match_device(kirkwood_pinctrl_of_match, 
&pdev->dev);
drivers/pinctrl/pinctrl-kirkwood.c +7 -0
+
+       if (match) {
+               soc->variant = (unsigned)match->data & 0xff;
+               switch (soc->variant) {
+               case VARIANT_MV88F6180:
+                       soc->controls = mv88f6180_mpp_controls;
+                       soc->ncontrols = 
ARRAY_SIZE(mv88f6180_mpp_controls);
drivers/pinctrl/pinctrl-kirkwood.c +2 -0
+                       soc->modes = mv88f6xxx_mpp_modes;
+                       soc->nmodes = 
ARRAY_SIZE(mv88f6xxx_mpp_modes);
drivers/pinctrl/pinctrl-kirkwood.c +2 -0
+                       soc->gpioranges = mv88f6180_gpio_ranges;
+                       soc->ngpioranges = 
ARRAY_SIZE(mv88f6180_gpio_ranges);
drivers/pinctrl/pinctrl-kirkwood.c +5 -0
+                       break;
+               case VARIANT_MV88F6190:
+               case VARIANT_MV88F6192:
+                       soc->controls = mv88f619x_mpp_controls;
+                       soc->ncontrols = 
ARRAY_SIZE(mv88f619x_mpp_controls);
drivers/pinctrl/pinctrl-kirkwood.c +2 -0
+                       soc->modes = mv88f6xxx_mpp_modes;
+                       soc->nmodes = 
ARRAY_SIZE(mv88f6xxx_mpp_modes);
drivers/pinctrl/pinctrl-kirkwood.c +2 -0
+                       soc->gpioranges = mv88f619x_gpio_ranges;
+                       soc->ngpioranges = 
ARRAY_SIZE(mv88f619x_gpio_ranges);
drivers/pinctrl/pinctrl-kirkwood.c +5 -0
+                       break;
+               case VARIANT_MV88F6281:
+               case VARIANT_MV88F6282:
+                       soc->controls = mv88f628x_mpp_controls;
+                       soc->ncontrols = 
ARRAY_SIZE(mv88f628x_mpp_controls);
drivers/pinctrl/pinctrl-kirkwood.c +2 -0
+                       soc->modes = mv88f6xxx_mpp_modes;
+                       soc->nmodes = 
ARRAY_SIZE(mv88f6xxx_mpp_modes);
+ soc->gpioranges = mv88f628x_gpio_ranges;

Quoted 8 lines

drivers/pinctrl/pinctrl-kirkwood.c line 439
Quoted 8 lines
+ soc->ngpioranges =
ARRAY_SIZE(mv88f628x_gpio_ranges);
drivers/pinctrl/pinctrl-kirkwood.c +6 -0
+                       break;
+               }
+               pdev->dev.platform_data = soc;
+       }
+       return mvebu_pinctrl_probe(pdev);
+}

Why not have structures defining the soc-> parameters and use that in the
of_match list?

Signature · 1 line

Ben

Sebastian Hesselbarth

author maintainer

2012-08-27 19:19 UTC #16 lore raw

Re: [PATCH 03/11] pinctrl: mvebu: kirkwood pinctrl driver

Quoted 62 lines · Ben Dooks

Quoted 61 lines · Linus Walleij
On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth <[email protected]> wrote:
(...)
Quoted 10 lines
drivers/pinctrl/pinctrl-kirkwood.c +3 -0
+static struct mvebu_pinctrl_soc_info kirkwood_pinctrl_info;
+
+static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata
= {
+ { .compatible = "marvell,88f6180-pinctrl",
+ .data = (void *)VARIANT_MV88F6180 },
+ { .compatible = "marvell,88f6190-pinctrl",
+ .data = (void *)VARIANT_MV88F6190 },
Quoted 8 lines
+ { .compatible = "marvell,88f6192-pinctrl",
+ .data = (void *)VARIANT_MV88F6192 },
+ { .compatible = "marvell,88f6281-pinctrl",
+ .data = (void *)VARIANT_MV88F6281 },
+ { .compatible = "marvell,88f6282-pinctrl",
+ .data = (void *)VARIANT_MV88F6282 },
+ { }
+};
I'm thinking this variant should maybe be an enum... unless it is strongly established somewhere in Orion/Marvell stuff.
Quoted 36 lines
+static int __devinit kirkwood_pinctrl_probe(struct platform_device *pdev)
drivers/pinctrl/pinctrl-kirkwood.c +34 -0
+{
+ struct mvebu_pinctrl_soc_info *soc = &kirkwood_pinctrl_info;
+ const struct of_device_id *match =
+ of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
+
+ if (match) {
+ soc->variant = (unsigned)match->data & 0xff;
+ switch (soc->variant) {
+ case VARIANT_MV88F6180:
+ soc->controls = mv88f6180_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv88f6180_mpp_controls);
+ soc->modes = mv88f6xxx_mpp_modes;
+ soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+ soc->gpioranges = mv88f6180_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv88f6180_gpio_ranges);
+ break;
+ case VARIANT_MV88F6190:
+ case VARIANT_MV88F6192:
+ soc->controls = mv88f619x_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls);
+ soc->modes = mv88f6xxx_mpp_modes;
+ soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+ soc->gpioranges = mv88f619x_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges);
+ break;
+ case VARIANT_MV88F6281:
+ case VARIANT_MV88F6282:
+ soc->controls = mv88f628x_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls);
+ soc->modes = mv88f6xxx_mpp_modes;
+ soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+ soc->gpioranges = mv88f628x_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges);
+ break;

Quoted 8 lines

Quoted 5 lines
Quoted 5 lines
+ }
+ pdev->dev.platform_data = soc;
+ }
+ return mvebu_pinctrl_probe(pdev);
+}
Why not have structures defining the soc-> parameters and use that in the of_match list?

Ben,

functionally it is equivalent and IMHO using soc structs doesn't improve readability here. I there any other good reason to have structs for each soc?

Sebastian

Stephen Warren

2012-08-27 20:02 UTC #17 lore raw

Re: [PATCH 03/11] pinctrl: mvebu: kirkwood pinctrl driver

Quoted 72 lines · Sebastian Hesselbarth

Quoted 62 lines · Ben Dooks
Quoted 61 lines · Linus Walleij
On Sat, Aug 11, 2012 at 2:56 PM, Sebastian Hesselbarth <[email protected]> wrote:
(...)
Quoted 10 lines
drivers/pinctrl/pinctrl-kirkwood.c +3 -0
+static struct mvebu_pinctrl_soc_info kirkwood_pinctrl_info;
+
+static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata
= {
+ { .compatible = "marvell,88f6180-pinctrl",
+ .data = (void *)VARIANT_MV88F6180 },
+ { .compatible = "marvell,88f6190-pinctrl",
+ .data = (void *)VARIANT_MV88F6190 },
Quoted 8 lines
+ { .compatible = "marvell,88f6192-pinctrl",
+ .data = (void *)VARIANT_MV88F6192 },
+ { .compatible = "marvell,88f6281-pinctrl",
+ .data = (void *)VARIANT_MV88F6281 },
+ { .compatible = "marvell,88f6282-pinctrl",
+ .data = (void *)VARIANT_MV88F6282 },
+ { }
+};
I'm thinking this variant should maybe be an enum... unless it is strongly established somewhere in Orion/Marvell stuff.
Quoted 36 lines
+static int __devinit kirkwood_pinctrl_probe(struct platform_device *pdev)
drivers/pinctrl/pinctrl-kirkwood.c +34 -0
+{
+ struct mvebu_pinctrl_soc_info *soc = &kirkwood_pinctrl_info;
+ const struct of_device_id *match =
+ of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
+
+ if (match) {
+ soc->variant = (unsigned)match->data & 0xff;
+ switch (soc->variant) {
+ case VARIANT_MV88F6180:
+ soc->controls = mv88f6180_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv88f6180_mpp_controls);
+ soc->modes = mv88f6xxx_mpp_modes;
+ soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+ soc->gpioranges = mv88f6180_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv88f6180_gpio_ranges);
+ break;
+ case VARIANT_MV88F6190:
+ case VARIANT_MV88F6192:
+ soc->controls = mv88f619x_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls);
+ soc->modes = mv88f6xxx_mpp_modes;
+ soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+ soc->gpioranges = mv88f619x_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges);
+ break;
+ case VARIANT_MV88F6281:
+ case VARIANT_MV88F6282:
+ soc->controls = mv88f628x_mpp_controls;
+ soc->ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls);
+ soc->modes = mv88f6xxx_mpp_modes;
+ soc->nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes);
+ soc->gpioranges = mv88f628x_gpio_ranges;
+ soc->ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges);
+ break;
Quoted 8 lines
Quoted 5 lines
Quoted 5 lines
+ }
+ pdev->dev.platform_data = soc;
+ }
+ return mvebu_pinctrl_probe(pdev);
+}
Why not have structures defining the soc-> parameters and use that in the of_match list?

Quoted 5 lines

Ben,
functionally it is equivalent and IMHO using soc structs doesn't improve readability here. I there any other good reason to have structs for each soc?

Well, it does change from 6 assignments down to one, and remove the need for a switch statement - i.e. all of the code quoted above becomes just roughly:

*soc = *match->data;

Sebastian Hesselbarth

author maintainer

2012-08-11 12:56 UTC #18 lore raw

PATCH 4/11 pinctrl: mvebu: add pinctrl driver for Armada 370

From: Thomas Petazzoni <[email protected]>

This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs.

---
 .../pinctrl/marvell,armada-370-pinctrl.txt         |   95 +++++
 drivers/pinctrl/Kconfig                            |    5 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-armada-370.c               |  421 ++++++++++++++++++++
 4 files changed, 522 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-armada-370.c

Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt new file +95 -0

new file mode 100644
index 0000000..01ef408
@@ -0,0 +1,95 @@
+* Marvell Armada 370 SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6710-pinctrl"
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, uart0(rxd)
+mpp1          1        gpo, uart0(txd)
+mpp2          2        gpio, i2c0(sck), uart0(txd)
+mpp3          3        gpio, i2c0(sda), uart0(rxd)
+mpp4          4        gpio, cpu_pd(vdd)
+mpp5          5        gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
+mpp6          6        gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
+mpp7          7        gpo, ge0(txd1), tdm(tdx), audio(lrclk)
+mpp8          8        gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
+mpp9          9        gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
+mpp10         10       gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
+mpp11         11       gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
+                       sata1(prsnt), spi1(cs1)
+mpp12         12       gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
+                       audio(spdifi)
+mpp13         13       gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
+                       audio(rmclk)
+mpp14         14       gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
+                       spi0(cs2)
+mpp15         15       gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
+                       spi0(cs3)
+mpp16         16       gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
+mpp17         17       gpo, ge(mdc)
+mpp18         18       gpio, ge(mdio)
+mpp19         19       gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
+mpp20         20       gpo, ge0(txd4), ge1(txd0)
+mpp21         21       gpo, ge0(txd5), ge1(txd1), uart1(txd)
+mpp22         22       gpo, ge0(txd6), ge1(txd2), uart0(rts)
+mpp23         23       gpo, ge0(txd7), ge1(txd3), spi1(mosi)
+mpp24         24       gpio, ge0(col), ge1(txctl), spi1(cs0)
+mpp25         25       gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
+mpp26         26       gpio, ge0(crs), ge1(rxd1), spi1(miso)
+mpp27         27       gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
+mpp28         28       gpio, ge0(rxd5), ge1(rxd3)
+mpp29         29       gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
+mpp30         30       gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
+mpp31         31       gpio, tclk, ge0(txerr)
+mpp32         32       gpio, spi0(cs0)
+mpp33         33       gpio, dev(bootcs), spi0(cs0)
+mpp34         34       gpo, dev(wen0), spi0(mosi)
+mpp35         35       gpo, dev(oen), spi0(sck)
+mpp36         36       gpo, dev(a1), spi0(miso)
+mpp37         37       gpo, dev(a0), sata0(prsnt)
+mpp38         38       gpio, dev(ready), uart1(cts), uart0(cts)
+mpp39         39       gpo, dev(ad0), audio(spdifo)
+mpp40         40       gpio, dev(ad1), uart1(rts), uart0(rts)
+mpp41         41       gpio, dev(ad2), uart1(rxd)
+mpp42         42       gpo, dev(ad3), uart1(txd)
+mpp43         43       gpo, dev(ad4), audio(bclk)
+mpp44         44       gpo, dev(ad5), audio(mclk)
+mpp45         45       gpo, dev(ad6), audio(lrclk)
+mpp46         46       gpo, dev(ad7), audio(sdo)
+mpp47         47       gpo, dev(ad8), sd0(clk), audio(spdifo)
+mpp48         48       gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
+                       spi0(cs1)
+mpp49         49       gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
+                       audio(spdifi)
+mpp50         50       gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
+                       audio(rmclk)
+mpp51         51       gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
+mpp52         52       gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
+mpp53         53       gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
+                       pcie(clkreq1)
+mpp54         54       gpo, dev(ad15), tdm(dtx)
+mpp55         55       gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
+                       sata0(prsnt)
+mpp56         56       gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
+                       pcie(clkreq0), spi1(cs1)
+mpp57         57       gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
+                       audio(sdo)
+mpp58         58       gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
+                       uart0(rts)
+mpp59         59       gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
+mpp60         60       gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
+                       audio(sdi)
+mpp61         61       gpo, dev(wen1), uart1(txd), audio(rclk)
+mpp62         62       gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
+                       audio(mclk), uart0(cts)
+mpp63         63       gpo, spi0(sck), tclk
+mpp64         64       gpio, spi0(miso), spi0-1(cs1)
+mpp65         65       gpio, spi0(mosi), spi0-1(cs2)

drivers/pinctrl/Kconfig +5 -0

index 1f84090..caa97cc 100644
@@ -169,6 +169,11 @@ config PINCTRL_KIRKWOOD
 	  Say yes here to support pinctrl driver on Marvell Kirkwood SoCs
 	  (88f6180, 88f6190, 88f6192, 88f6281, 88f6282).
 
+config PINCTRL_ARMADA_370
+	bool "Support for Marvell Armada 370 SoCs"
+	depends on PINCTRL_MVEBU
+	depends on MACH_ARMADA_370_XP
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index 3006294..e6d6667 100644
@@ -32,5 +32,6 @@ obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
 obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
+obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-armada-370.c new file +421 -0

421 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Linus Walleij

2012-08-20 14:25 UTC #19 lore raw

Re: [PATCH 04/11] pinctrl: mvebu: add pinctrl driver for Armada 370

Quoted 3 lines · Sebastian Hesselbarth

This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs.

Good!

drivers/pinctrl/Kconfig config PINCTRL_KIRKWOOD · line 175

Quoted 4 lines

drivers/pinctrl/Kconfig +4 -0

+config PINCTRL_ARMADA_370
+       bool "Support for Marvell Armada 370 SoCs"
+       depends on PINCTRL_MVEBU
+       depends on MACH_ARMADA_370_XP

select PINCTRL_MVEBU simply?

And then have the Armada Kconfig

select PINCTRL
select PINCTRL_ARMADA_370

This machine doesn't seem to depend in the MVEBU driver, I guess it's the same ARCH as something else, oh well. Still suspect the MVEBU driver should depend on PLAT_ORION until proven wrong.

(...)

drivers/pinctrl/pinctrl-armada-370.c line 389

Quoted 5 lines

drivers/pinctrl/pinctrl-armada-370.c new file +5 -0

+static int __devinit armada_370_pinctrl_probe(struct platform_device *pdev)
+{
+       struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info;
+
+       soc->variant = 0;

Shouldn't this be a #defined thing or something. "variant 0" doesn't tell me much.

No further comments, looking good.

Yours,
Linus Walleij

Sebastian Hesselbarth

author maintainer

2012-08-20 16:48 UTC #20 lore raw

Re: [PATCH 04/11] pinctrl: mvebu: add pinctrl driver for Armada 370

Quoted 11 lines · Linus Walleij

drivers/pinctrl/Kconfig config PINCTRL_KIRKWOOD · line 175
Quoted 4 lines
drivers/pinctrl/Kconfig +4 -0
+config PINCTRL_ARMADA_370
+       bool "Support for Marvell Armada 370 SoCs"
+       depends on PINCTRL_MVEBU
+       depends on MACH_ARMADA_370_XP
select PINCTRL_MVEBU simply?
And then have the Armada Kconfig
select PINCTRL
select PINCTRL_ARMADA_370

Linus, Thomas, Gregory,

this is really difficult here ;) I thought I could just add PINCTRL_DOVE to MACH_DOVE inside ARCH_MVEBU, PINCTRL_KIRKWOOD to MACH_KIRKWOOD, aso. But there is a common MACH_ARMADA_370_XP for both 370 and XP obviously.

If it is ok for you I will add both PINCTRL_ stubs to the Kconfig and you work it out if you ever have two distinct MACHs? Or it could remain selectable in pinctrl/Kconfig but that will then be different with the other stubs.

Sebastian

Thomas Petazzoni

2012-08-20 17:36 UTC #21 lore raw

Re: [PATCH 04/11] pinctrl: mvebu: add pinctrl driver for Armada 370

Le Mon, 20 Aug 2012 18:48:32 +0200,
Sebastian Hesselbarth <[email protected]> a ?crit :

Quoted 8 lines

this is really difficult here ;) I thought I could just add PINCTRL_DOVE to MACH_DOVE inside ARCH_MVEBU, PINCTRL_KIRKWOOD to MACH_KIRKWOOD, aso. But there is a common MACH_ARMADA_370_XP for both 370 and XP obviously.
If it is ok for you I will add both PINCTRL_ stubs to the Kconfig and you work it out if you ever have two distinct MACHs? Or it could remain selectable in pinctrl/Kconfig but that will then be different with the other stubs.

In order to keep the consistency with other SoC families, maybe we can split the 370 and XP options in two separate MACH_ARMADA_370 and MACH_ARMADA_XP. So, in the ideal world, once all Marvell EBU SoCs are converted to DT+mach-mvebu, we should have:

*) arch/arm/Kconfig defines MACH_MVEBU

*) arch/arm/mach-mvebu/Kconfig defines MACH_KIRKWOOD, MACH_DOVE,

    MACH_MX78X00, MACH_ARMADA_370, MACH_ARMADA_XP, MACH_ORION5X

Then, an user is free to build a single kernel image that supports all, or a selection of the supported Marvell EBU SoCs.

Would that be ok with you?

If that's fine with you, then I would prefer if we keep the single MACH_ARMADA_370_XP symbol for now, so that your pinctrl set of patches does not depend on something else. We would do the small Kconfig option refactoring as a follow-up set of patches. Thoughts?

Best regards,

Thomas

Signature · 4 lines

Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Sebastian Hesselbarth

author maintainer

2012-08-20 18:01 UTC #22 lore raw

Re: [PATCH 04/11] pinctrl: mvebu: add pinctrl driver for Armada 370

Quoted 7 lines · Thomas Petazzoni

In order to keep the consistency with other SoC families, maybe we can split the 370 and XP options in two separate MACH_ARMADA_370 and MACH_ARMADA_XP. So, in the ideal world, once all Marvell EBU SoCs are converted to DT+mach-mvebu, we should have:
*) arch/arm/Kconfig defines MACH_MVEBU

Quoted 7 lines

*) arch/arm/mach-mvebu/Kconfig defines MACH_KIRKWOOD, MACH_DOVE,
     MACH_MX78X00, MACH_ARMADA_370, MACH_ARMADA_XP, MACH_ORION5X
Then, an user is free to build a single kernel image that supports all, or a selection of the supported Marvell EBU SoCs.
Would that be ok with you?

Yes!

Quoted 4 lines

If that's fine with you, then I would prefer if we keep the single MACH_ARMADA_370_XP symbol for now, so that your pinctrl set of patches does not depend on something else. We would do the small Kconfig option refactoring as a follow-up set of patches. Thoughts?

Despite any objections, I will remove all arch/arm/*/Kconfig patches from pinctrl patch set.

Sebastian

Thomas Petazzoni

2012-08-20 18:51 UTC #23 lore raw

Re: [PATCH 04/11] pinctrl: mvebu: add pinctrl driver for Armada 370

Le Mon, 20 Aug 2012 20:01:51 +0200,
Sebastian Hesselbarth <[email protected]> a ?crit :

Quoted 7 lines

Quoted 4 lines
If that's fine with you, then I would prefer if we keep the single MACH_ARMADA_370_XP symbol for now, so that your pinctrl set of patches does not depend on something else. We would do the small Kconfig option refactoring as a follow-up set of patches. Thoughts?
Despite any objections, I will remove all arch/arm/*/Kconfig patches from pinctrl patch set.

Ok, fine with me, but we'll have to send separate patches for those, then.

Thanks!

Thomas

Signature · 4 lines

Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Gregory CLEMENT

2012-08-21 07:12 UTC #24 lore raw

Re: [PATCH 04/11] pinctrl: mvebu: add pinctrl driver for Armada 370

Quoted 17 lines · Thomas Petazzoni

Le Mon, 20 Aug 2012 18:48:32 +0200,
Sebastian Hesselbarth <[email protected]> a ?crit :
Quoted 8 lines
this is really difficult here ;) I thought I could just add PINCTRL_DOVE to MACH_DOVE inside ARCH_MVEBU, PINCTRL_KIRKWOOD to MACH_KIRKWOOD, aso. But there is a common MACH_ARMADA_370_XP for both 370 and XP obviously.
If it is ok for you I will add both PINCTRL_ stubs to the Kconfig and you work it out if you ever have two distinct MACHs? Or it could remain selectable in pinctrl/Kconfig but that will then be different with the other stubs.
In order to keep the consistency with other SoC families, maybe we can split the 370 and XP options in two separate MACH_ARMADA_370 and MACH_ARMADA_XP. So, in the ideal world, once all Marvell EBU SoCs are converted to DT+mach-mvebu, we should have:

Quoted 7 lines

*) arch/arm/Kconfig defines MACH_MVEBU
*) arch/arm/mach-mvebu/Kconfig defines MACH_KIRKWOOD, MACH_DOVE,
    MACH_MX78X00, MACH_ARMADA_370, MACH_ARMADA_XP, MACH_ORION5X
Then, an user is free to build a single kernel image that supports all, or a selection of the supported Marvell EBU SoCs.

I agree with Thomas

Quoted 3 lines

Thomas

Signature · 4 lines

Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Sebastian Hesselbarth

author maintainer

2012-08-11 12:56 UTC #25 lore raw

PATCH 5/11 pinctrl: mvebu: add pinctrl driver for Armada XP

From: Thomas Petazzoni <[email protected]>

This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs.

---
 .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt |  100 +++++
 drivers/pinctrl/Kconfig                            |    5 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-armada-xp.c                |  466 ++++++++++++++++++++
 4 files changed, 572 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-armada-xp.c

Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt new file +100 -0

new file mode 100644
index 0000000..bfa0a2e
@@ -0,0 +1,100 @@
+* Marvell Armada XP SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
+              "marvell,mv78460-pinctrl"
+
+This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Armada XP (all variants)
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, ge0(txclko), lcd(d0)
+mpp1          1        gpio, ge0(txd0), lcd(d1)
+mpp2          2        gpio, ge0(txd1), lcd(d2)
+mpp3          3        gpio, ge0(txd2), lcd(d3)
+mpp4          4        gpio, ge0(txd3), lcd(d4)
+mpp5          5        gpio, ge0(txctl), lcd(d5)
+mpp6          6        gpio, ge0(rxd0), lcd(d6)
+mpp7          7        gpio, ge0(rxd1), lcd(d7)
+mpp8          8        gpio, ge0(rxd2), lcd(d8)
+mpp9          9        gpio, ge0(rxd3), lcd(d9)
+mpp10         10       gpio, ge0(rxctl), lcd(d10)
+mpp11         11       gpio, ge0(rxclk), lcd(d11)
+mpp12         12       gpio, ge0(txd4), ge1(txd0), lcd(d12)
+mpp13         13       gpio, ge0(txd5), ge1(txd1), lcd(d13)
+mpp14         14       gpio, ge0(txd6), ge1(txd2), lcd(d15)
+mpp15         15       gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp16         16       gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp17         17       gpio, ge0(col), ge1(txctl), lcd(d17)
+mpp18         18       gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
+mpp19         19       gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
+mpp20         20       gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
+mpp21         21       gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
+mpp22         22       gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
+mpp23         23       gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
+mpp24         24       gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
+mpp25         25       gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
+mpp26         26       gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
+mpp27         27       gpio, lcd(e), tdm(dtx), ptp(trig)
+mpp28         28       gpio, lcd(pwm), tdm(drx), ptp(evreq)
+mpp29         29       gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
+mpp30         30       gpio, tdm(int1), sd0(clk)
+mpp31         31       gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
+mpp32         32       gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
+mpp33         33       gpio, tdm(int4), sd0(d1), mem(bat)
+mpp34         34       gpio, tdm(int5), sd0(d2), sata0(prsnt)
+mpp35         35       gpio, tdm(int6), sd0(d3), sata1(prsnt)
+mpp36         36       gpio, spi(mosi)
+mpp37         37       gpio, spi(miso)
+mpp38         38       gpio, spi(sck)
+mpp39         39       gpio, spi(cs0)
+mpp40         40       gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
+                       pcie(clkreq0)
+mpp41         41       gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
+                       pcie(clkreq1)
+mpp42         42       gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
+                       vdd(cpu0-pd)
+mpp43         43       gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
+                       vdd(cpu2-3-pd){1}
+mpp44         44       gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
+                       mem(bat)
+mpp45         45       gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
+mpp46         46       gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
+mpp47         47       gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
+                       ref(clkout)
+mpp48         48       gpio, tclk, dev(burst/last)
+
+* Marvell Armada XP (mv78260 and mv78460 only)
+
+name          pins     functions
+================================================================================
+mpp49         49       gpio, dev(we3)
+mpp50         50       gpio, dev(we2)
+mpp51         51       gpio, dev(ad16)
+mpp52         52       gpio, dev(ad17)
+mpp53         53       gpio, dev(ad18)
+mpp54         54       gpio, dev(ad19)
+mpp55         55       gpio, dev(ad20), vdd(cpu0-pd)
+mpp56         56       gpio, dev(ad21), vdd(cpu1-pd)
+mpp57         57       gpio, dev(ad22), vdd(cpu2-3-pd){1}
+mpp58         58       gpio, dev(ad23)
+mpp59         59       gpio, dev(ad24)
+mpp60         60       gpio, dev(ad25)
+mpp61         61       gpio, dev(ad26)
+mpp62         62       gpio, dev(ad27)
+mpp63         63       gpio, dev(ad28)
+mpp64         64       gpio, dev(ad29)
+mpp65         65       gpio, dev(ad30)
+mpp66         66       gpio, dev(ad31)
+
+Notes:
+* {1} vdd(cpu2-3-pd) only available on mv78460.

drivers/pinctrl/Kconfig +5 -0

index caa97cc..5502539 100644
@@ -174,6 +174,11 @@ config PINCTRL_ARMADA_370
 	depends on PINCTRL_MVEBU
 	depends on MACH_ARMADA_370_XP
 
+config PINCTRL_ARMADA_XP
+	bool "Support for Marvell Armada XP SoCs"
+	depends on PINCTRL_MVEBU
+	depends on MACH_ARMADA_370_XP
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index e6d6667..f2ea050 100644
@@ -33,5 +33,6 @@ obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
 obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
 obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
+obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-armada-xp.c new file +466 -0

466 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Linus Walleij

2012-08-20 14:26 UTC #26 lore raw

Re: [PATCH 05/11] pinctrl: mvebu: add pinctrl driver for Armada XP

Quoted 7 lines · Sebastian Hesselbarth

From: Thomas Petazzoni <[email protected]>
This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs.
Signed-off-by Thomas Petazzoni <[email protected]>

Same comments as on the previous driver, no further comments, and looking good.

Yours,
Linus Walleij

Sebastian Hesselbarth

author maintainer

2012-08-11 12:56 UTC #27 lore raw

PATCH 6/11 ARM: mvebu: add pinctrl device in DT for Armada 370/XP SoCs

From: Thomas Petazzoni <[email protected]>

The Armada 370 and XP SoCs have configurable muxing for a certain number of their pins, controlled through a pinctrl driver.

The 'compatible' property is defined in the SoC-specific .dtsi files, since the compatible string identifies the number of pins and other SoC-specific properties.

---
 arch/arm/boot/dts/armada-370-xp.dtsi |    7 +++++++
 1 file changed, 7 insertions(+)

arch/arm/boot/dts/armada-370-xp.dtsi +7 -0

index 6b6b932..7c72a70 100644
@@ -63,6 +63,13 @@
 			       reg = <0xd0020300 0x30>;
 			       interrupts = <37>, <38>, <39>, <40>;
 		};
+
+                pinctrl at d0018000 {
+                               reg = <0xd0018000 0x38>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               ranges;
+                };
 	};
 };

Signature · 1 line

1.7.10.4

Linus Walleij

Acked-by on v1 6/11

2012-08-20 14:27 UTC #28 lore raw

Re: [PATCH 06/11] ARM: mvebu: add pinctrl device in DT for Armada 370/XP SoCs

Quoted 10 lines · Sebastian Hesselbarth

From: Thomas Petazzoni <[email protected]>
The Armada 370 and XP SoCs have configurable muxing for a certain number of their pins, controlled through a pinctrl driver.
The 'compatible' property is defined in the SoC-specific .dtsi files, since the compatible string identifies the number of pins and other SoC-specific properties.
Signed-off-by Thomas Petazzoni <[email protected]>

FWIW:

Yours,
Linus Walleij

Sebastian Hesselbarth

author maintainer

2012-08-11 12:56 UTC #29 lore raw

PATCH 7/11 ARM: mvebu: Add pinctrl support to Armada XP SoCs

From: Thomas Petazzoni <[email protected]>

This commits adds the necessary device tree information to define the compatible property for the pinctrl driver instance of Armada XP SoCs.

Until now, the device tree representation considered the Armada XP as a single SoC. But in fact, there are three different SoCs in the Armada XP families, with different number of CPU cores, different number of Ethernet interfaces... and different number of muxable pins or functions. We therefore introduce three armada-xp-mv78xx0.dtsi for the three SoCs of the Armada XP family. The current armada-xp-db.dts evaluation board uses the MV78460 variant of the SoC.

---
 arch/arm/boot/dts/armada-xp-mv78230.dtsi |   27 +++++++++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78260.dtsi |   27 +++++++++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78460.dtsi |   27 +++++++++++++++++++++++++++
 3 files changed, 81 insertions(+)
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78230.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78260.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78460.dtsi

arch/arm/boot/dts/armada-xp-mv78230.dtsi new file +27 -0

new file mode 100644
index 0000000..69ad287
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78230 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP family SoC";
+	compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	soc {
+		pinctrl at d0018000 {
+			compatible = "marvell,mv78230-pinctrl";
+		};
+	};
+};

arch/arm/boot/dts/armada-xp-mv78260.dtsi new file +27 -0

new file mode 100644
index 0000000..0f38fa9
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78260 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP family SoC";
+	compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	soc {
+		pinctrl at d0018000 {
+			compatible = "marvell,mv78260-pinctrl";
+		};
+	};
+};

arch/arm/boot/dts/armada-xp-mv78460.dtsi new file +27 -0

new file mode 100644
index 0000000..9e61836
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78460 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP family SoC";
+	compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	soc {
+		pinctrl at d0018000 {
+			compatible = "marvell,mv78460-pinctrl";
+		};
+	};
+ };

Signature · 1 line

1.7.10.4

Linus Walleij

Acked-by on v1 7/11

2012-08-20 14:27 UTC #30 lore raw

Re: [PATCH 07/11] ARM: mvebu: Add pinctrl support to Armada XP SoCs

Quoted 13 lines · Sebastian Hesselbarth

From: Thomas Petazzoni <[email protected]>
This commits adds the necessary device tree information to define the compatible property for the pinctrl driver instance of Armada XP SoCs.
Until now, the device tree representation considered the Armada XP as a single SoC. But in fact, there are three different SoCs in the Armada XP families, with different number of CPU cores, different number of Ethernet interfaces... and different number of muxable pins or functions. We therefore introduce three armada-xp-mv78xx0.dtsi for the three SoCs of the Armada XP family. The current armada-xp-db.dts evaluation board uses the MV78460 variant of the SoC.

Quoted 1 line

Signed-off-by Thomas Petazzoni <[email protected]>

FWIW:

Yours,
Linus Walleij

Sebastian Hesselbarth

author maintainer

2012-08-11 12:56 UTC #31 lore raw

PATCH 8/11 ARM: mvebu: Add pinctrl support to Armada 370 SoC

From: Thomas Petazzoni <[email protected]>

This commits adds the necessary device tree information to define the compatible property for the pinctrl driver instance of Armada 370 SoC.

---
 arch/arm/boot/dts/armada-370.dtsi |    4 ++++
 1 file changed, 4 insertions(+)

arch/arm/boot/dts/armada-370.dtsi +4 -0

index 3228ccc..875fcd8 100644
@@ -31,5 +31,9 @@
 				compatible = "marvell,armada-370-xp-system-controller";
 				reg = <0xd0018200 0x100>;
 		};
+
+                pinctrl at d0018000 {
+			        compatible = "marvell,mv88f6710-pinctrl";
+	        };
 	};
 };

Signature · 1 line

1.7.10.4

Linus Walleij

Acked-by on v1 8/11

2012-08-20 14:28 UTC #32 lore raw

Re: [PATCH 08/11] ARM: mvebu: Add pinctrl support to Armada 370 SoC

Quoted 6 lines · Sebastian Hesselbarth

From: Thomas Petazzoni <[email protected]>
This commits adds the necessary device tree information to define the compatible property for the pinctrl driver instance of Armada 370 SoC.
Signed-off-by Thomas Petazzoni <[email protected]>

FWIW:

Yours,
Linus Walleij

Sebastian Hesselbarth

author maintainer

2012-08-11 12:56 UTC #33 lore raw

PATCH 9/11 ARM: mvebu: adjust Armada XP evaluation board DTS

From: Thomas Petazzoni <[email protected]>

The Armada XP evaluation board is based on the MV78460 Armava XP SoC. Now that we have separate .dtsi files for the three different SoCs of the Armada XP family, use the appropriate one as include for the Armada XP evaluation board .dts file.

---
 arch/arm/boot/dts/armada-xp-db.dts |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

arch/arm/boot/dts/armada-xp-db.dts +2 -2

index f97040d..b1fc728 100644
@@ -14,11 +14,11 @@
  */
 
 /dts-v1/;
-/include/ "armada-xp.dtsi"
+/include/ "armada-xp-mv78460.dtsi"
 
 / {
 	model = "Marvell Armada XP Evaluation Board";
-	compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
+	compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";

Signature · 1 line

1.7.10.4

Linus Walleij

Acked-by on v1 9/11

2012-08-20 14:28 UTC #34 lore raw

Re: [PATCH 09/11] ARM: mvebu: adjust Armada XP evaluation board DTS

Quoted 8 lines · Sebastian Hesselbarth

From: Thomas Petazzoni <[email protected]>
The Armada XP evaluation board is based on the MV78460 Armava XP SoC. Now that we have separate .dtsi files for the three different SoCs of the Armada XP family, use the appropriate one as include for the Armada XP evaluation board .dts file.
Signed-off-by Thomas Petazzoni <[email protected]>

FWIW:

Yours,
Linus Walleij

Sebastian Hesselbarth

author maintainer

2012-08-11 12:56 UTC #35 lore raw

PATCH 10/11 arm: mvebu: enable PINCTRL usage

From: Thomas Petazzoni <[email protected]>

Now that we have a proper pinctrl driver for Marvell EBU platforms, enable PINCTRL support in ARCH_MVEBU.

---
 arch/arm/Kconfig |    1 +
 1 file changed, 1 insertion(+)

arch/arm/Kconfig +1 -0

index 361f513..95317a9 100644
@@ -573,6 +573,7 @@ config ARCH_MVEBU
 	select GENERIC_IRQ_CHIP
 	select IRQ_DOMAIN
 	select COMMON_CLK
+	select PINCTRL
 	help
 	  Support for the Marvell SoC Family with device tree support

Signature · 1 line

1.7.10.4

Linus Walleij

2012-08-20 14:29 UTC #36 lore raw

Re: [PATCH 10/11] arm: mvebu: enable PINCTRL usage

Quoted 6 lines · Sebastian Hesselbarth

From: Thomas Petazzoni <[email protected]>
Now that we have a proper pinctrl driver for Marvell EBU platforms, enable PINCTRL support in ARCH_MVEBU.
Signed-off-by Thomas Petazzoni <[email protected]>

(...)

arch/arm/Kconfig config ARCH_MVEBU · line 578

Quoted 11 lines

arch/arm/Kconfig +1 -0

index 361f513..95317a9 100644
@@ -573,6 +573,7 @@ config ARCH_MVEBU
        select GENERIC_IRQ_CHIP
        select IRQ_DOMAIN
        select COMMON_CLK
+       select PINCTRL
        help
          Support for the Marvell SoC Family with device tree support

So this symbol collects all the DT-migrated platforms?

Probably OK but want to figure out if the PLAT_NOMADIK symbol is applicable.

Yours,
Linus Walleij

Sebastian Hesselbarth

author maintainer

2012-08-11 12:56 UTC #37 lore raw

PATCH 11/11 arm: mvebu: add pinctrl support in defconfig

From: Thomas Petazzoni <[email protected]>

---
 arch/arm/configs/mvebu_defconfig |    2 ++
 1 file changed, 2 insertions(+)

arch/arm/configs/mvebu_defconfig +2 -0

index 2e86b31..cb07e64 100644
@@ -21,6 +21,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_PINCTRL_ARMADA_370=y
+CONFIG_PINCTRL_ARMADA_XP=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set

Signature · 1 line

1.7.10.4

Linus Walleij

2012-08-20 14:31 UTC #38 lore raw

Re: [PATCH 11/11] arm: mvebu: add pinctrl support in defconfig

arch/arm/configs/mvebu_defconfig CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" · line 25

Quoted 10 lines · Sebastian Hesselbarth

arch/arm/configs/mvebu_defconfig +2 -0

index 2e86b31..cb07e64 100644
@@ -21,6 +21,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_PINCTRL_ARMADA_370=y
+CONFIG_PINCTRL_ARMADA_XP=y

If the system is not even booting without pinctrl you should (IMHO) select these from the machine's Kconfig entry insteaf.

If they boot fine without I'm fine with this ... the arch maintainer gets to choose anyway.

Yours,
Linus Walleij

Sebastian Hesselbarth

author maintainer

2012-08-20 14:54 UTC #39 lore raw

Re: [PATCH 11/11] arm: mvebu: add pinctrl support in defconfig

Quoted 7 lines · Linus Walleij

arch/arm/configs/mvebu_defconfig CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" · line 25
Quoted 2 lines · Sebastian Hesselbarth
arch/arm/configs/mvebu_defconfig +2 -0
+CONFIG_PINCTRL_ARMADA_370=y
+CONFIG_PINCTRL_ARMADA_XP=y
If the system is not even booting without pinctrl you should (IMHO) select these from the machine's Kconfig entry insteaf.

I don't have a strong opinion on this but I think most systems will boot just fine without pinctrl. The basic stuff is set up by u-boot. Anyway, I think we should enable pinctrl for each soc by default.

Sebastian

Thomas Petazzoni

2012-08-20 17:37 UTC #40 lore raw

Re: [PATCH 11/11] arm: mvebu: add pinctrl support in defconfig

Le Mon, 20 Aug 2012 16:54:27 +0200,
Sebastian Hesselbarth <[email protected]> a ?crit :

Quoted 9 lines · Linus Walleij

Quoted 7 lines
arch/arm/configs/mvebu_defconfig CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" · line 25
Quoted 2 lines · Sebastian Hesselbarth
arch/arm/configs/mvebu_defconfig +2 -0
+CONFIG_PINCTRL_ARMADA_370=y
+CONFIG_PINCTRL_ARMADA_XP=y
If the system is not even booting without pinctrl you should (IMHO) select these from the machine's Kconfig entry insteaf.

Quoted 4 lines

I don't have a strong opinion on this but I think most systems will boot just fine without pinctrl. The basic stuff is set up by u-boot. Anyway, I think we should enable pinctrl for each soc by default.

Yes, the system boots fine without the pinctrl support. So I don't think that MACH_ARMADA_370_XP should forcefully select the pinctrl code, but it's nice to have the default defconfig for this platform select the pinctrl support.

Best regards,

Thomas

Signature · 4 lines

Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Linus Walleij

2012-08-20 08:12 UTC #41 lore raw

Quoted 4 lines · Sebastian Hesselbarth

This patch set adds a core pinctrl driver for Marvell MVEBU SoCs and SoC specific stubs for Armada 370, Armada XP, Dove, and Kirkwood. The SoC specific stubs use the pinctrl-mvebu core driver that handles pinctrl API and register accesses for common pinctrl registers.

Nice! I'll now go in and review it.

Please add Stephen Warren <[email protected]> on CC for subsequent iterations.

Yours,
Linus Walleij

Sebastian Hesselbarth

author maintainer

2012-08-22 08:22 UTC #42 lore raw

v2 cover pinctrl: mvebu: pinctrl driver

As especially Dove has some pinctrl registers that do not match the common pinctrl register layout the core driver has been extended by some callbacks to allow uncommon Dove pinctrl registers.

DT binding documentation is added for all supported SoCs but as Dove and Kirkwood are not yet ready for full DT support, the pinctrl driver is only activated for Armada 370 and XP.

The driver has been tested on Dove, 88f6281 variant of Kirkwood, Armada 370, and XP.

Changelog:
v2:
- rebased on git://git.infradead.org/users/jcooper/linux.git boards-for-3.7
- removed arch/arm/*/Kconfig patches that enable PINCTRL_ on MACH_MVEBU (those will be sent as a different patch set)
- reworked patches wrt reviews from Andrew Lunn and Linus Walleij

Sebastian Hesselbarth (3):
pinctrl: mvebu: pinctrl driver core
pinctrl: mvebu: dove pinctrl driver
pinctrl: mvebu: kirkwood pinctrl driver

Thomas Petazzoni (6):
pinctrl: mvebu: add pinctrl driver for Armada 370
pinctrl: mvebu: add pinctrl driver for Armada XP
ARM: mvebu: add pinctrl device in DT for Armada 370/XP SoCs
ARM: mvebu: Add pinctrl support to Armada XP SoCs
ARM: mvebu: Add pinctrl support to Armada 370 SoC
ARM: mvebu: adjust Armada XP evaluation board DTS

 .../pinctrl/marvell,armada-370-pinctrl.txt         |   95 +++
 .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt |  100 +++
 .../bindings/pinctrl/marvell,dove-pinctrl.txt      |   72 ++
 .../bindings/pinctrl/marvell,kirkwood-pinctrl.txt  |  279 +++++++
 .../bindings/pinctrl/marvell,mvebu-pinctrl.txt     |   45 ++
 arch/arm/Kconfig                                   |    1 +
 arch/arm/boot/dts/armada-370-xp.dtsi               |    7 +
 arch/arm/boot/dts/armada-370.dtsi                  |    4 +
 arch/arm/boot/dts/armada-xp-db.dts                 |    4 +-
 arch/arm/boot/dts/armada-xp-mv78230.dtsi           |   27 +
 arch/arm/boot/dts/armada-xp-mv78260.dtsi           |   27 +
 arch/arm/boot/dts/armada-xp-mv78460.dtsi           |   27 +
 drivers/pinctrl/Kconfig                            |   22 +
 drivers/pinctrl/Makefile                           |    5 +
 drivers/pinctrl/pinctrl-armada-370.c               |  421 +++++++++++
 drivers/pinctrl/pinctrl-armada-xp.c                |  468 ++++++++++++
 drivers/pinctrl/pinctrl-dove.c                     |  622 ++++++++++++++++
 drivers/pinctrl/pinctrl-kirkwood.c                 |  462 ++++++++++++
 drivers/pinctrl/pinctrl-mvebu.c                    |  761 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-mvebu.h                    |  192 +++++
 20 files changed, 3639 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78230.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78260.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78460.dtsi
 create mode 100644 drivers/pinctrl/pinctrl-armada-370.c
 create mode 100644 drivers/pinctrl/pinctrl-armada-xp.c
 create mode 100644 drivers/pinctrl/pinctrl-dove.c
 create mode 100644 drivers/pinctrl/pinctrl-kirkwood.c
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.c
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.h

---
Cc: Thomas Petazzoni <[email protected]>
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-08-22 08:22 UTC #43 lore raw

PATCH v2 1/9 pinctrl: mvebu: pinctrl driver core

This patch adds a pinctrl driver core for Marvell SoCs plus DT binding documentation. This core driver will be used by SoC family specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.

Signed-off-by Sebastian Hesselbarth <[email protected]>

---
v2:
- restructured Kconfig to have a common PINCTRL_MVEBU that are selected by SoC specific drivers.
- cleaned pinctrl-mvebu and replaced 'magic numbers' by defines
- make use of of_iomap instead of get_resource/ioremap
- extended include documentation and checked with scripts/kernel-doc
- cleaned devicetree binding documentation

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 .../bindings/pinctrl/marvell,mvebu-pinctrl.txt     |   45 ++
 arch/arm/Kconfig                                   |    1 +
 drivers/pinctrl/Kconfig                            |    6 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-mvebu.c                    |  761 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-mvebu.h                    |  192 +++++
 6 files changed, 1006 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.c
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.h

Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt new file +45 -0

new file mode 100644
index 0000000..dc419e3
@@ -0,0 +1,45 @@
+* Marvell SoC pinctrl core driver for mpp
+
+The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
+(mpp) to a specific function. For each SoC family there is a SoC specific
+driver using this core driver.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+A Marvell SoC pin configuration node is a node of a group of pins which can
+be used for a specific device or function. Each node requires one or more
+mpp pins or group of pins and a mpp function common to all pins.
+
+Required properties for pinctrl driver:
+- compatible: "marvell,<soc>-pinctrl"
+  Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
+
+Required properties for pin configuration node:
+- marvell,pins: string array of mpp pins or group of pins to be muxed.
+- marvell,function: string representing a function to mux to for all
+    marvell,pins given in this pin configuration node. The function has to be
+    common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
+    valid pin/pin group names and available function names for each SoC.
+
+Examples:
+
+uart1: serial at 12100 {
+	compatible = "ns16550a";
+	reg = <0x12100 0x100>;
+	reg-shift = <2>;
+	interrupts = <7>;
+
+	pinctrl-0 = <&pmx_uart1_sw>;
+};
+
+pinctrl: pinctrl at d0200 {
+	compatible = "marvell,dove-pinctrl";
+	reg = <0xd0200 0x20>;
+
+	pmx_uart1_sw: pmx-uart1-sw {
+		marvell,pins = "mpp_uart1";
+		marvell,function = "uart1";
+	};
+};

arch/arm/Kconfig +1 -0

index a2b6f74..2eb3f6b 100644
@@ -574,6 +574,7 @@ config ARCH_MVEBU
 	select IRQ_DOMAIN
 	select COMMON_CLK
 	select PLAT_ORION
+	select PINCTRL
 	help
 	  Support for the Marvell SoC Family with device tree support

drivers/pinctrl/Kconfig +6 -0

index 54e3588..20bfdc3 100644
@@ -145,6 +145,12 @@ config PINCTRL_COH901
 	  COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
 	  ports of 8 GPIO pins each.
 
+config PINCTRL_MVEBU
+	bool
+	depends on ARCH_MVEBU
+	select PINMUX
+	select PINCONF
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index f40b1f8..007ed32 100644
@@ -29,5 +29,6 @@ obj-$(CONFIG_PINCTRL_TEGRA20)	+= pinctrl-tegra20.o
 obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
+obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-mvebu.c new file +761 -0

761 lines not on this page · raw message

drivers/pinctrl/pinctrl-mvebu.h new file +192 -0

192 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Stephen Warren

2012-08-22 20:43 UTC #44 lore raw

Re: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 5 lines · Sebastian Hesselbarth

This patch adds a pinctrl driver core for Marvell SoCs plus DT binding documentation. This core driver will be used by SoC family specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt

This, and all the other binding documents in this series, all look sane to me.

Quoted 9 lines

+++ b/drivers/pinctrl/pinctrl-mvebu.c

drivers/pinctrl/pinctrl-mvebu.c new file +5 -0

+static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 
 
+	of_property_for_each_string(np, "marvell,pins", prop, group) {
+		struct mvebu_pinctrl_group *grp =
+			mvebu_pinctrl_find_group_by_name(pctl, group);
+

drivers/pinctrl/pinctrl-mvebu.c line 457

Quoted 10 lines

drivers/pinctrl/pinctrl-mvebu.c new file +10 -0

+		if (!grp) {
+			dev_err(pctl->dev, "unknown pin %s", group);
+			continue;
+		}
+
+		if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, function)) {
+			dev_err(pctl->dev, "unsupported function %s on pin %s",
+				function, group);
+			continue;
+		}

The error-checking here isn't strictly necessary; the pinctrl core will error-check all the names if/when the map entries are used. So, you could probably get away with just assigning the pin/function names directly into (*map) and hence remove some code here. Still, it's not a big deal either way.

drivers/pinctrl/pinctrl-mvebu.c line 541

Quoted 4 lines

drivers/pinctrl/pinctrl-mvebu.c new file +3 -0

+static int __devinit mvebu_pinctrl_dt_parse_function(struct mvebu_pinctrl *pctl,
 
+static int __devinit mvebu_pinctrl_dt_parse(struct platform_device *pdev,
+					struct mvebu_pinctrl *pctl)

I don't understand what those two functions do, or a good chunk of probe(). It seems like they're setting up the ability to get/set pin configrations in addition to pin muxing, although if that's so, it seems odd that none of the binding documents specify any way of controlling pin configuration from device tree. Are you expecting drivers to call APIs such as pin_config_set() directly, rather than controlling pin config through DT?

Sebastian Hesselbarth

author maintainer

2012-08-23 09:45 UTC #45 lore raw

Re: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 17 lines · Stephen Warren

Quoted 16 lines · Sebastian Hesselbarth

+++ b/drivers/pinctrl/pinctrl-mvebu.c

drivers/pinctrl/pinctrl-mvebu.c new file +13 -0

+static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 
+	of_property_for_each_string(np, "marvell,pins", prop, group) {
+		struct mvebu_pinctrl_group *grp =
+			mvebu_pinctrl_find_group_by_name(pctl, group);
+
+		if (!grp) {
+			dev_err(pctl->dev, "unknown pin %s", group);
+			continue;
+		}
+
+		if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, function)) {
+			dev_err(pctl->dev, "unsupported function %s on pin %s",
+				function, group);

Quoted 8 lines

Review
Quoted 2 lines
(quoted diff) +2 -0
+			continue;
+		}
The error-checking here isn't strictly necessary; the pinctrl core will error-check all the names if/when the map entries are used. So, you could probably get away with just assigning the pin/function names directly into (*map) and hence remove some code here. Still, it's not a big deal either way.

Hi Stephen,

as these error checks are only performed once, I'd like to have them there as they give hints when someone uses wrong marvell,pins/function names in DT.

Quoted 14 lines

drivers/pinctrl/pinctrl-mvebu.c line 541
Quoted 6 lines
+static int __devinit mvebu_pinctrl_dt_parse_function(struct mvebu_pinctrl *pctl,
+static int __devinit mvebu_pinctrl_dt_parse(struct platform_device *pdev,
drivers/pinctrl/pinctrl-mvebu.c new file +1 -0
+					struct mvebu_pinctrl *pctl)
I don't understand what those two functions do, or a good chunk of probe(). It seems like they're setting up the ability to get/set pin configrations in addition to pin muxing, although if that's so, it seems odd that none of the binding documents specify any way of controlling pin configuration from device tree. Are you expecting drivers to call APIs such as pin_config_set() directly, rather than controlling pin config through DT?

probe() receives some structs from the SoC specific driver stubs that describe, e.g. how many muxable pins are available, which pingroup they belong to (marvell,pins), what valid register values are and how they are named (marvell,function). Although, all mvebu SoC share a good part of pinmux register layout, there are especially for dove some very different ways to mux pins. As mvebu pinctrl is a true mux-only driver, i.e. no pin drive strength or pin direction configuration, we decided not to have single pins controlable but only pingroups even if they comprise only a single pin.

dt_parse() and dt_parse_function() build up structs that get used later on in mvebu_pinmux_ops that require indexed functions. I can join them with dt_node_to_map() but that would require incremental kzalloc for the corresponding array. Or I could (functionally) leave dt_parse() to allocate the array and only join dt_parse_function() with dt_node_to_map().

There is an example of how to use pinctrl in marvell.mvebu-pinctrl.txt:

uart1: serial at 12100 {
	compatible = "ns16550a";
	reg = <0x12100 0x100>;
	reg-shift = <2>;
	interrupts = <7>;

	pinctrl-0 = <&pmx_uart1_sw>;
};

pinctrl: pinctrl at d0200 {
	compatible = "marvell,dove-pinctrl";
	reg = <0xd0200 0x20>;

	pmx_uart1_sw: pmx-uart1-sw {
		marvell,pins = "mpp_uart1";
		marvell,function = "uart1";
	};
};

In my understanding this will allow uart1 to switch the pingroup "mpp_uart1" to the function "uart1". The pinctrl core driver is taking care of translating mpp_uart1
to the corresponding pingroup and mvebu core driver of translating uart1 into the required
register values to set the requested function. Is it so odd, that we use names instead
of direct register values in DT? I agree, that maybe picking an example for dove that is a little bit different in pingroup naming isn't the best choice but it still gives
you an idea how to use it.

Consider this (virtual) example:
Muxing some SATA functions to pins 24 and 37 would require to set register values
to 0x3 on pin 24 and 0x6 on pin 37. The proposed driver still allows us to have a DT
description of

pmx_sata_example: pmx-sata-example {
	marvell,pins = "mpp24", "mpp37";
	marvell,function = "sata";
};

because the SoC specific driver passes function "sata" on pins 24 and 37 with the
corresponding register values. These are fed by the mvebu core driver that builds
up all required pins, pingroups, and pinmux functions.

Sebastian

Stephen Warren

2012-08-23 17:54 UTC #46 lore raw

Re: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 58 lines · Sebastian Hesselbarth

Quoted 17 lines · Stephen Warren
Quoted 16 lines · Sebastian Hesselbarth
+++ b/drivers/pinctrl/pinctrl-mvebu.c
drivers/pinctrl/pinctrl-mvebu.c new file +13 -0
+static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 
+	of_property_for_each_string(np, "marvell,pins", prop, group) {
+		struct mvebu_pinctrl_group *grp =
+			mvebu_pinctrl_find_group_by_name(pctl, group);
+
+		if (!grp) {
+			dev_err(pctl->dev, "unknown pin %s", group);
+			continue;
+		}
+
+		if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, function)) {
+			dev_err(pctl->dev, "unsupported function %s on pin %s",
+				function, group);
Quoted 8 lines
Review
Quoted 2 lines
(quoted diff) +2 -0
+			continue;
+		}
The error-checking here isn't strictly necessary; the pinctrl core will error-check all the names if/when the map entries are used. So, you could probably get away with just assigning the pin/function names directly into (*map) and hence remove some code here. Still, it's not a big deal either way.
Hi Stephen,
as these error checks are only performed once, I'd like to have them there as they give hints when someone uses wrong marvell,pins/function names in DT.
Quoted 14 lines
drivers/pinctrl/pinctrl-mvebu.c line 541
Quoted 6 lines
+static int __devinit mvebu_pinctrl_dt_parse_function(struct mvebu_pinctrl *pctl,
+static int __devinit mvebu_pinctrl_dt_parse(struct platform_device *pdev,
drivers/pinctrl/pinctrl-mvebu.c new file +1 -0
+					struct mvebu_pinctrl *pctl)
I don't understand what those two functions do, or a good chunk of probe(). It seems like they're setting up the ability to get/set pin configrations in addition to pin muxing, although if that's so, it seems odd that none of the binding documents specify any way of controlling pin configuration from device tree. Are you expecting drivers to call APIs such as pin_config_set() directly, rather than controlling pin config through DT?
probe() receives some structs from the SoC specific driver stubs that describe, e.g. how many muxable pins are available, which pingroup they belong to (marvell,pins), what valid register values are and how they are named (marvell,function). Although, all mvebu SoC share a good part of pinmux register layout, there are especially for dove some very different ways to mux pins. As mvebu pinctrl is a true mux-only driver, i.e. no pin drive strength or pin direction configuration, we decided not to have single pins controlable but only pingroups even if they comprise only a single pin.

Quoted 5 lines

dt_parse() and dt_parse_function() build up structs that get used later on in mvebu_pinmux_ops that require indexed functions. I can join them with dt_node_to_map() but that would require incremental kzalloc for the corresponding array. Or I could (functionally) leave dt_parse() to allocate the array and only join dt_parse_function() with dt_node_to_map().

So everything you said makes sense, in that the core driver is parameterizable and receives data from a SoC-variant-specific driver indicating which pins/groups/functions are available. I'm still not sure though why the translation of the pin/group/function structures passed to probe into other data structures requires accessing the DT at all; the set of available pins/groups/functions isn't configured through DT, and doesn't need to be limited to only those options actually used in DT, so can't you just process all the data that's passed to probe without interaction with the DT?

Sebastian Hesselbarth

author maintainer

2012-08-23 20:31 UTC #47 lore raw

Re: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 6 lines · Stephen Warren

Quoted 5 lines
dt_parse() and dt_parse_function() build up structs that get used later on in mvebu_pinmux_ops that require indexed functions. I can join them with dt_node_to_map() but that would require incremental kzalloc for the corresponding array. Or I could (functionally) leave dt_parse() to allocate the array and only join dt_parse_function() with dt_node_to_map().

Quoted 9 lines

So everything you said makes sense, in that the core driver is parameterizable and receives data from a SoC-variant-specific driver indicating which pins/groups/functions are available. I'm still not sure though why the translation of the pin/group/function structures passed to probe into other data structures requires accessing the DT at all; the set of available pins/groups/functions isn't configured through DT, and doesn't need to be limited to only those options actually used in DT, so can't you just process all the data that's passed to probe without interaction with the DT?

Hmm, maybe I still don't quite understand the terminology of pinctrl/pinmux core completely. What exactly should mvebu_pinmux_get_funcs_count return if not the number of DT node children?

I thought that a "function" in the terminology of pinctrl/pinmux core is a list of pingroups and corresponding values to actually set it to e.g. uart1. In pinctrl-mvebu this would be one marvell,function assigned to one or more marvell,pins.

If the above is correct, I still need to access DT in probe() at least to count the number of children passed to allocate an array for mvebu_pinmux_ops callbacks that get indexed by "fid" (pctl->functions).

Sebastian

Stephen Warren

2012-08-23 21:26 UTC #48 lore raw

Re: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 19 lines · Sebastian Hesselbarth

Quoted 8 lines · Stephen Warren
Quoted 7 lines
dt_parse() and dt_parse_function() build up structs that get used later on
in mvebu_pinmux_ops that require indexed functions. I can join them with dt_node_to_map() but that would require incremental kzalloc for the corresponding array. Or I could (functionally) leave dt_parse() to allocate
the array and only join dt_parse_function() with dt_node_to_map().
Quoted 9 lines
So everything you said makes sense, in that the core driver is parameterizable and receives data from a SoC-variant-specific driver indicating which pins/groups/functions are available. I'm still not sure though why the translation of the pin/group/function structures passed to probe into other data structures requires accessing the DT at all; the set of available pins/groups/functions isn't configured through DT, and doesn't need to be limited to only those options actually used in DT, so can't you just process all the data that's passed to probe without interaction with the DT?

Quoted 3 lines

Hmm, maybe I still don't quite understand the terminology of pinctrl/pinmux core completely. What exactly should mvebu_pinmux_get_funcs_count return if not the number of DT node children?

In HW, you have:

* A number of pins

* In some cases, multiple pins are controlled by a single register field, so there are groups of pins, whose pins all get mux'd at once.

* In some cases, SW chooses to control multiple pins at once even if the HW allows otherwise, and these are also represented as groups.

* A (mux) function represents what options (signals, modules, ...) are available to be mux'd onto any given pin or group of pins.

If all of your pins/groups can support 4 different mux choices 0..3 (even though the interpretation of values 0..3 may differ per pin/group) you may simply have functions 0, 1, 2, 3 exposed by your driver.

Alternatively, you may define a function for each logical HW module (e.g. UART1, UART2, SPI1, SPI2, MMC1...) that exists in your SoC, or even per each separate subset of signals (e.g. UART1 RX/TX, UART 1 RTS/CTS, UART 2 RX/TX/RTS/CTS, ...).

In a driver where the set of pins, groups, and functions known to the driver is defined as static data in the driver itself (which I believe covers your driver; IIRC I saw all those tables in the patch), then you'd simply count up all the defined function names/IDs available, and return that from pinmux_ops.get_functions_count(). In this case, the number of functions is entirely static, being defined by the SoC HW design, and hence DT content has absolutely no impact on it. For reference, this is how the Tegra pinctrl drivers work.

In a driver where the set of pins, groups, and functions known to the driver is not hard-coded into the driver itself, but instead derived from DT content (which is useful for a driver that works for say 10 different similar SoCs, each with slightly different sets of actual pins/groups/functions, but where you don't want to hard-code all the tables into the driver), then you may need to parse DT to extract the definitions of those pins/groups/functions. Then, there's the question of how to represent the set of known pins/groups/function in DT; do you have explicit tables for this, or reverse engineer the tables based on whichever pins/groups/function just happen to be used by the board you're running on, in which cases the reverse-engineered lists will probably not include all options the HW could support, given one particular DT file. Anyway, as I said, I don't think this approach applies to your driver anyway since IIRC I did see all the data tables in the patch.

As you may have guessed, I strongly prefer the hard-coded static table based approach, or at least separating the definition of known pins/groups/functions from the configuration nodes that define which particular mux settings to actually use.

Puting this all a little more simply, the pinctrl core wants to generate a list of all known functions. It is a single global/unified list. It first calls pinmux_ops.get_functions_count() to find out how many functions there are in the list, then pinmux_ops.get_function_name() for each one to find its name, then pinmux_ops.get_function_groups() to find out which groups allow that function to be mux'd onto them.

Sebastian Hesselbarth

author maintainer

2012-08-23 23:01 UTC #49 lore raw

Re: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 11 lines · Stephen Warren

As you may have guessed, I strongly prefer the hard-coded static table based approach, or at least separating the definition of known pins/groups/functions from the configuration nodes that define which particular mux settings to actually use.
Puting this all a little more simply, the pinctrl core wants to generate a list of all known functions. It is a single global/unified list. It first calls pinmux_ops.get_functions_count() to find out how many functions there are in the list, then pinmux_ops.get_function_name() for each one to find its name, then pinmux_ops.get_function_groups() to find out which groups allow that function to be mux'd onto them.

Ok, now this becomes a little bit more clear to me.

Consider uart1 on dove is muxable to:
mpp2 uart1(rts), mpp3 uart1(cts), mpp21 uart1(rts), mpp22 uart1(cts), and finally mpp_uart1(rx and tx).

So possible, valid combinations for uart1 would be:
(a) mpp_uart1;
(b) mpp_uart1, mpp2, mpp3;
(c) mpp_uart1, mpp21, mpp22;
(d) mpp_uart1, mpp2, mpp22;
(e) mpp_uart1, mpp21, mpp3;

Now what we currently do is, use DT to setup all known functions with e.g. marvell,pins = "mpp_uart1", "mpp2", "mpp22" and marvell,function = "uart1". This requires to count all pinctrl DT node children to count the known functions that can ever be muxed to. It will never allow to mux uart1 to sw flow control during run-time when there was no DT child node for it.

But you are proposing to scan the list passed from SoC specific driver for all possible marvell,function ("uart1", "uart2", "sdio0", ...) and build up lists of pingroups that can be used with this specific marvell,function; or even build up lists of pingroups that allow uart1(rts), and another one for uart1(cts), ...?

Sebastian

Stephen Warren

2012-08-24 03:34 UTC #50 lore raw

Re: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 26 lines · Sebastian Hesselbarth

Quoted 11 lines · Stephen Warren
As you may have guessed, I strongly prefer the hard-coded static table based approach, or at least separating the definition of known pins/groups/functions from the configuration nodes that define which particular mux settings to actually use.
Puting this all a little more simply, the pinctrl core wants to generate a list of all known functions. It is a single global/unified list. It first calls pinmux_ops.get_functions_count() to find out how many functions there are in the list, then pinmux_ops.get_function_name() for each one to find its name, then pinmux_ops.get_function_groups() to find out which groups allow that function to be mux'd onto them.
Ok, now this becomes a little bit more clear to me.
Consider uart1 on dove is muxable to:
mpp2 uart1(rts), mpp3 uart1(cts), mpp21 uart1(rts), mpp22 uart1(cts), and finally mpp_uart1(rx and tx).
So possible, valid combinations for uart1 would be:
(a) mpp_uart1;
(b) mpp_uart1, mpp2, mpp3;
(c) mpp_uart1, mpp21, mpp22;
(d) mpp_uart1, mpp2, mpp22;
(e) mpp_uart1, mpp21, mpp3;

Quoted 5 lines

Now what we currently do is, use DT to setup all known functions with e.g. marvell,pins = "mpp_uart1", "mpp2", "mpp22" and marvell,function = "uart1". This requires to count all pinctrl DT node children to count the known functions that can ever be muxed to. It will never allow to mux uart1 to sw flow control during run-time when there was no DT child node for it.

In the example above, there is a single function named "uart1". If this was all the HW supported, I'd expect the driver's pinmux_ops.get_functions_count() to return 1, pinmux_ops.get_function_name(0) to return "uart1", and pinmux_ops.get_function_name(n>0) to return an error.

In practice, I assume there are many other options that can be muxed onto mpp2/3/21/22/uart1, so they'd be included in the list as well.

Quoted 8 lines

But you are proposing to scan the list passed from SoC specific driver for all
possible marvell,function ("uart1", "uart2", "sdio0", ...) and build up lists
of pingroups that can be used with this specific marvell,function; or even build
up lists of pingroups that allow uart1(rts), and another one for uart1(cts), ...?

I don't expect any scanning, no. I'd expect that tables provided by the SoC-specific drivers to be:

* A table of pins
* A table of groups
* A table of functions

No scanning involved.

Sebastian Hesselbarth

author maintainer

2012-08-25 15:53 UTC #51 lore raw

Re: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 17 lines · Stephen Warren

Quoted 7 lines · Sebastian Hesselbarth
So possible, valid combinations for uart1 would be:
(a) mpp_uart1;
(b) mpp_uart1, mpp2, mpp3;
(c) mpp_uart1, mpp21, mpp22;
(d) mpp_uart1, mpp2, mpp22;
(e) mpp_uart1, mpp21, mpp3;
[...]
In the example above, there is a single function named "uart1". If this was all the HW supported, I'd expect the driver's pinmux_ops.get_functions_count() to return 1, pinmux_ops.get_function_name(0) to return "uart1", and pinmux_ops.get_function_name(n>0) to return an error.
In practice, I assume there are many other options that can be muxed onto mpp2/3/21/22/uart1, so they'd be included in the list as well.

Quoted 8 lines

I don't expect any scanning, no. I'd expect that tables provided by the SoC-specific drivers to be:
* A table of pins
* A table of groups
* A table of functions
No scanning involved.

Stephen,

now I do understand but in the current driver we pass pingroups associated with the available functions, i.e. "mpp2" with "uart1", "uart2", "sdio0", aso. IMHO for the above three functions it would be better to have functions associated with the corresponding groups, i.e. "uart1" with "mpp_uart1", "mpp2", "mpp3", aso.

That would require some larger rework of the driver and therefore I just wanted to make sure, that I hit your expectations/explanations.

Sebastian

Stephen Warren

2012-08-27 04:33 UTC #52 lore raw

Re: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 29 lines · Sebastian Hesselbarth

Quoted 17 lines · Stephen Warren
Quoted 7 lines · Sebastian Hesselbarth
So possible, valid combinations for uart1 would be:
(a) mpp_uart1;
(b) mpp_uart1, mpp2, mpp3;
(c) mpp_uart1, mpp21, mpp22;
(d) mpp_uart1, mpp2, mpp22;
(e) mpp_uart1, mpp21, mpp3;
[...]
In the example above, there is a single function named "uart1". If this was all the HW supported, I'd expect the driver's pinmux_ops.get_functions_count() to return 1, pinmux_ops.get_function_name(0) to return "uart1", and pinmux_ops.get_function_name(n>0) to return an error.
In practice, I assume there are many other options that can be muxed onto mpp2/3/21/22/uart1, so they'd be included in the list as well.
Quoted 8 lines
I don't expect any scanning, no. I'd expect that tables provided by the SoC-specific drivers to be:
* A table of pins
* A table of groups
* A table of functions
No scanning involved.
Stephen,

Quoted 7 lines

now I do understand but in the current driver we pass pingroups associated with the available functions, i.e. "mpp2" with "uart1", "uart2", "sdio0", aso.
IMHO for the above three functions it would be better to have functions associated
with the corresponding groups, i.e. "uart1" with "mpp_uart1", "mpp2", "mpp3", aso.

The pinctrl subsystem does expect a list of functions, and for each function, a list of the groups where it can be selected. I admit that when I think about this, it's slightly backward, since HW typically has a list of pins/groups, and for each, a certain set of functions can be selected. Oh well...

Linus Walleij

2012-09-02 07:30 UTC #53 lore raw

Re: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 10 lines · Stephen Warren

Quoted 8 lines · Sebastian Hesselbarth
now I do understand but in the current driver we pass pingroups associated with the available functions, i.e. "mpp2" with "uart1", "uart2", "sdio0", aso.
IMHO for the above three functions it would be better to have functions associated
with the corresponding groups, i.e. "uart1" with "mpp_uart1", "mpp2", "mpp3", aso.

Quoted 5 lines

The pinctrl subsystem does expect a list of functions, and for each function, a list of the groups where it can be selected. I admit that when I think about this, it's slightly backward, since HW typically has a list of pins/groups, and for each, a certain set of functions can be selected. Oh well...

I agree that this is how we engineered it, would it create big hassles for you to fix up the driver so it's the other way around Sebastian?

I understand that the driver is perfectly working as it is, but from a subsystem maintainer point of view it is annoying if one driver turns the concepts around and it gets hard to maintain.

Yours,
Linus Walleij

Sebastian Hesselbarth

author maintainer

2012-09-02 08:27 UTC #54 lore raw

Re: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 7 lines · Linus Walleij

Quoted 5 lines · Stephen Warren
The pinctrl subsystem does expect a list of functions, and for each function, a list of the groups where it can be selected. I admit that when I think about this, it's slightly backward, since HW typically has a list of pins/groups, and for each, a certain set of functions can be selected. Oh well...

Quoted 6 lines

I agree that this is how we engineered it, would it create big hassles for you to fix up the driver so it's the other way around Sebastian?
I understand that the driver is perfectly working as it is, but from a subsystem maintainer point of view it is annoying if one driver turns the concepts around and it gets hard to maintain.

Stephen, Linus, Jason,

there is a v3 of the patch under internal review right now.

I know Stephen will not like it, but I decided not to have the list of functions passed statically from the SoC specific part but generate it out of pingroups during probe().

As soon as I have confirmation that it still works on the other SoCs, I will send the updated patches for public review.

Maybe Jason can also comment on what branch he wants to have it based on, as we all agreed to get it through the Marvell tree.

Sebastian

Linus Walleij

2012-09-03 09:32 UTC #55 lore raw

Re: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 1 line · Sebastian Hesselbarth

there is a v3 of the patch under internal review right now.

OK I'll review as you send it out. Will look through the v2 patches to see if I missed some comment.

Quoted 3 lines

I know Stephen will not like it, but I decided not to have the list of functions passed statically from the SoC specific part but generate it out of pingroups during probe().

Well, Tony's driver does even nastier things so we need to agree to disagree on this point. I for one can live with it.

Yours,
Linus Walleij

Jason Cooper

2012-09-03 19:47 UTC #56 lore raw

Re: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 2 lines · Sebastian Hesselbarth

Maybe Jason can also comment on what branch he wants to have it based on, as we all agreed to get it through the Marvell tree.

Please base against:

git://git.infradead.org/users/jcooper/linux.git boards-for-v3.7-v2

thx,

Jason.

Jason Cooper

2012-09-09 19:56 UTC #57 lore raw

Re: [PATCH v2 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 1 line · Sebastian Hesselbarth

there is a v3 of the patch under internal review right now.

Sebastian,

What is the status of v3? I'd like to get it (and gpio, which depends on this work) in for v3.7, but it's getting close...

thx,

Jason.

Sebastian Hesselbarth

author maintainer

2012-08-22 08:22 UTC #58 lore raw

PATCH v2 2/9 pinctrl: mvebu: dove pinctrl driver

This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core.

Signed-off-by Sebastian Hesselbarth <[email protected]>

---
v2:
- restructured pinctrl/Kconfig to hide pinctrl driver as it will be always selected by arch/arm/mach-mvebu/Kconfig
- cleaned pinctrl-dove and replaced 'magic numbers' by defines
- use devm_clk_get for (now optional) pdma clock and add to required properties in devicetree binding documentation

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 .../bindings/pinctrl/marvell,dove-pinctrl.txt      |   72 +++
 drivers/pinctrl/Kconfig                            |    4 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-dove.c                     |  622 ++++++++++++++++++++
 4 files changed, 699 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-dove.c

Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt new file +72 -0

new file mode 100644
index 0000000..a648aaa
@@ -0,0 +1,72 @@
+* Marvell Dove SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,dove-pinctrl"
+- clocks: (optional) phandle of pdma clock
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
+mpp1          1        gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
+mpp2          2        gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
+                       uart1(rts)
+mpp3          3        gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
+                       uart1(cts), lcd-spi(cs1)
+mpp4          4        gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
+mpp5          5        gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
+mpp6          6        gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
+mpp7          7        gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
+mpp8          8        gpio, pmu, watchdog(rstout)
+mpp9          9        gpio, pmu, pex1(clkreq)
+mpp10         10       gpio, pmu, ssp(sclk)
+mpp11         11       gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
+                       sdio1(ledctrl), pex0(clkreq)
+mpp12         12       gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
+mpp13         13       gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
+                       ssp(extclk)
+mpp14         14       gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
+mpp15         15       gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
+mpp16         16       gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
+mpp17         17       gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
+                       ac97-1(sysclko)
+mpp18         18       gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
+mpp19         19       gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
+mpp20         20       gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
+                       ac97(sysclko)
+mpp21         21       gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
+                       uart1(cts), ssp(sfrm)
+mpp22         22       gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
+                       lcd-spi(mosi), uart1(cts), ssp(txd)
+mpp23         23       gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
+                       lcd-spi(sck), ssp(sclk)
+mpp_camera    24-39    gpio, camera
+mpp_sdio0     40-45    gpio, sdio0
+mpp_sdio1     46-51    gpio, sdio1
+mpp_audio1    52-57    gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
+                       ssp/twsi
+mpp_spi0      58-61    gpio, spi0
+mpp_uart1     62-63    gpio, uart1
+mpp_nand      64-71    gpo, nand
+audio0        -        i2s, ac97
+twsi          -        none, opt1, opt2, opt3
+
+Notes:
+* group "mpp_audio1" allows the following functions and gpio pins:
+  - gpio          : gpio on pins 52-57
+  - i2s1/spdifo   : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
+  - i2s1          : audio1 i2s on pins 52-55, gpio on pins 56,57
+  - spdifo        : spdifo on pin 57, gpio on pins 52-55
+  - twsi          : twsi on pins 56,57, gpio on pins 52-55
+  - ssp/spdifo    : ssp on pins 52-55, spdifo on pin 57, no gpios
+  - ssp           : ssp on pins 52-55, gpio on pins 56,57
+  - ssp/twsi      : ssp on pins 52-55, twsi on pins 56,57, no gpios
+* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
+  audio0 pins.
+* group "twsi" internally muxes twsi controller to the dedicated or option pins.

drivers/pinctrl/Kconfig +4 -0

index 20bfdc3..f15eba4 100644
@@ -151,6 +151,10 @@ config PINCTRL_MVEBU
 	select PINMUX
 	select PINCONF
 
+config PINCTRL_DOVE
+	bool
+	select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index 007ed32..d1327df 100644
@@ -30,5 +30,6 @@ obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
+obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-dove.c new file +622 -0

622 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-08-22 08:22 UTC #59 lore raw

PATCH v2 3/9 pinctrl: mvebu: kirkwood pinctrl driver

This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core.

Signed-off-by Sebastian Hesselbarth <[email protected]>

---
v2:
- restructured pinctrl/Kconfig to hide pinctrl driver as it will be always selected by arch/arm/mach-mvebu/Kconfig
- use enum for kirkwood variants instead of defines

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 .../bindings/pinctrl/marvell,kirkwood-pinctrl.txt  |  279 ++++++++++++
 drivers/pinctrl/Kconfig                            |    4 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-kirkwood.c                 |  462 ++++++++++++++++++++
 4 files changed, 746 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-kirkwood.c

Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt new file +279 -0

new file mode 100644
index 0000000..361bccb
@@ -0,0 +1,279 @@
+* Marvell Kirkwood SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6180-pinctrl",
+              "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
+              "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
+
+This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Kirkwood 88f6180
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17         17       gpio, sdio(d3)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, mii(rxerr)
+mpp21         21       gpio, audio(spdifi)
+mpp22         22       gpio, audio(spdifo)
+mpp23         23       gpio, audio(rmclk)
+mpp24         24       gpio, audio(bclk)
+mpp25         25       gpio, audio(sdo)
+mpp26         26       gpio, audio(lrclk)
+mpp27         27       gpio, audio(mclk)
+mpp28         28       gpio, audio(sdi)
+mpp29         29       gpio, audio(extclk)
+
+* Marvell Kirkwood 88f6190
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0)
+mpp21         21       gpio, ge1(txd1), sata0(act)
+mpp22         22       gpio, ge1(txd2)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt)
+mpp24         24       gpio, ge1(rxd0)
+mpp25         25       gpio, ge1(rxd1)
+mpp26         26       gpio, ge1(rxd2)
+mpp27         27       gpio, ge1(rxd3)
+mpp28         28       gpio, ge1(col)
+mpp29         29       gpio, ge1(txclk)
+mpp30         30       gpio, ge1(rxclk)
+mpp31         31       gpio, ge1(rxclk)
+mpp32         32       gpio, ge1(txclko)
+mpp33         33       gpo, ge1(txclk)
+mpp34         34       gpio, ge1(txen)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr)
+
+* Marvell Kirkwood 88f6192
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33         33       gpo, ge1(txclk), tdm(drx)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+
+* Marvell Kirkwood 88f6281
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpio, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33         33       gpo, ge1(txclk), tdm(drx)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi)
+mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo)
+mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk)
+mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk)
+mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo)
+mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
+mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk)
+mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi)
+mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk)
+mpp45         45       gpio, ts(mp9), tdm(pclk)
+mpp46         46       gpio, ts(mp10), tdm(fs)
+mpp47         47       gpio, ts(mp11), tdm(drx)
+mpp48         48       gpio, ts(mp12), tdm(dtx)
+mpp49         49       gpio, ts(mp9), tdm(rx0ql), ptp(clk)
+
+* Marvell Kirkwood 88f6282
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync)
+mpp5          5        gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync)
+mpp6          6        sysrst(out), spi(mosi)
+mpp7          7        gpo, spi(cs), lcd(pwm)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
+                       mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
+                       sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), sata0(act)
+mpp12         12       gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda)
+mpp13         13       gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt),
+                       audio(spdifi), audio-1(sdi)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
+                       spi(cs)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act), lcd(extclk)
+mpp17         17       gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck)
+mpp18         18       gpo, nand(io0), pex(clkreq)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act), lcd(d0)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo), lcd(d1)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt), lcd(d2)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk), lcd(d3)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo),
+                       lcd(d4)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
+                       lcd(d5)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk),
+                       lcd(d6)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi),
+                       lcd(d7)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk),
+                       lcd(d8)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12)
+mpp33         33       gpo, ge1(txclk), tdm(drx), lcd(d13)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql),
+                       lcd(d15)
+mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda)
+mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck)
+mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18)
+mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19)
+mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20)
+mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
+mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22)
+mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23)
+mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk)
+mpp45         45       gpio, ts(mp9), tdm(pclk), lcd(e)
+mpp46         46       gpio, ts(mp10), tdm(fs), lcd(hsync)
+mpp47         47       gpio, ts(mp11), tdm(drx), lcd(vsync)
+mpp48         48       gpio, ts(mp12), tdm(dtx), lcd(d16)
+mpp49         49       gpo, tdm(rx0ql), pex(clkreq), lcd(d17)

drivers/pinctrl/Kconfig +4 -0

index f15eba4..31c0bba 100644
@@ -155,6 +155,10 @@ config PINCTRL_DOVE
 	bool
 	select PINCTRL_MVEBU
 
+config PINCTRL_KIRKWOOD
+	bool
+	select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index d1327df..3006294 100644
@@ -31,5 +31,6 @@ obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
+obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-kirkwood.c new file +462 -0

462 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-08-22 08:22 UTC #60 lore raw

PATCH v2 4/9 pinctrl: mvebu: add pinctrl driver for Armada 370

From: Thomas Petazzoni <[email protected]>

This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs.

---
v2:
- removed arch/arm/*/Kconfig changes and added note about variant = 0

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 .../pinctrl/marvell,armada-370-pinctrl.txt         |   95 +++++
 drivers/pinctrl/Kconfig                            |    4 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-armada-370.c               |  421 ++++++++++++++++++++
 4 files changed, 521 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-armada-370.c

Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt new file +95 -0

new file mode 100644
index 0000000..01ef408
@@ -0,0 +1,95 @@
+* Marvell Armada 370 SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6710-pinctrl"
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, uart0(rxd)
+mpp1          1        gpo, uart0(txd)
+mpp2          2        gpio, i2c0(sck), uart0(txd)
+mpp3          3        gpio, i2c0(sda), uart0(rxd)
+mpp4          4        gpio, cpu_pd(vdd)
+mpp5          5        gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
+mpp6          6        gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
+mpp7          7        gpo, ge0(txd1), tdm(tdx), audio(lrclk)
+mpp8          8        gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
+mpp9          9        gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
+mpp10         10       gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
+mpp11         11       gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
+                       sata1(prsnt), spi1(cs1)
+mpp12         12       gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
+                       audio(spdifi)
+mpp13         13       gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
+                       audio(rmclk)
+mpp14         14       gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
+                       spi0(cs2)
+mpp15         15       gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
+                       spi0(cs3)
+mpp16         16       gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
+mpp17         17       gpo, ge(mdc)
+mpp18         18       gpio, ge(mdio)
+mpp19         19       gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
+mpp20         20       gpo, ge0(txd4), ge1(txd0)
+mpp21         21       gpo, ge0(txd5), ge1(txd1), uart1(txd)
+mpp22         22       gpo, ge0(txd6), ge1(txd2), uart0(rts)
+mpp23         23       gpo, ge0(txd7), ge1(txd3), spi1(mosi)
+mpp24         24       gpio, ge0(col), ge1(txctl), spi1(cs0)
+mpp25         25       gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
+mpp26         26       gpio, ge0(crs), ge1(rxd1), spi1(miso)
+mpp27         27       gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
+mpp28         28       gpio, ge0(rxd5), ge1(rxd3)
+mpp29         29       gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
+mpp30         30       gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
+mpp31         31       gpio, tclk, ge0(txerr)
+mpp32         32       gpio, spi0(cs0)
+mpp33         33       gpio, dev(bootcs), spi0(cs0)
+mpp34         34       gpo, dev(wen0), spi0(mosi)
+mpp35         35       gpo, dev(oen), spi0(sck)
+mpp36         36       gpo, dev(a1), spi0(miso)
+mpp37         37       gpo, dev(a0), sata0(prsnt)
+mpp38         38       gpio, dev(ready), uart1(cts), uart0(cts)
+mpp39         39       gpo, dev(ad0), audio(spdifo)
+mpp40         40       gpio, dev(ad1), uart1(rts), uart0(rts)
+mpp41         41       gpio, dev(ad2), uart1(rxd)
+mpp42         42       gpo, dev(ad3), uart1(txd)
+mpp43         43       gpo, dev(ad4), audio(bclk)
+mpp44         44       gpo, dev(ad5), audio(mclk)
+mpp45         45       gpo, dev(ad6), audio(lrclk)
+mpp46         46       gpo, dev(ad7), audio(sdo)
+mpp47         47       gpo, dev(ad8), sd0(clk), audio(spdifo)
+mpp48         48       gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
+                       spi0(cs1)
+mpp49         49       gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
+                       audio(spdifi)
+mpp50         50       gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
+                       audio(rmclk)
+mpp51         51       gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
+mpp52         52       gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
+mpp53         53       gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
+                       pcie(clkreq1)
+mpp54         54       gpo, dev(ad15), tdm(dtx)
+mpp55         55       gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
+                       sata0(prsnt)
+mpp56         56       gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
+                       pcie(clkreq0), spi1(cs1)
+mpp57         57       gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
+                       audio(sdo)
+mpp58         58       gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
+                       uart0(rts)
+mpp59         59       gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
+mpp60         60       gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
+                       audio(sdi)
+mpp61         61       gpo, dev(wen1), uart1(txd), audio(rclk)
+mpp62         62       gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
+                       audio(mclk), uart0(cts)
+mpp63         63       gpo, spi0(sck), tclk
+mpp64         64       gpio, spi0(miso), spi0-1(cs1)
+mpp65         65       gpio, spi0(mosi), spi0-1(cs2)

drivers/pinctrl/Kconfig +4 -0

index 31c0bba..e16b8b0 100644
@@ -159,6 +159,10 @@ config PINCTRL_KIRKWOOD
 	bool
 	select PINCTRL_MVEBU
 
+config PINCTRL_ARMADA_370
+	bool
+	select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index 3006294..e6d6667 100644
@@ -32,5 +32,6 @@ obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
 obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
+obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-armada-370.c new file +421 -0

421 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-08-22 08:22 UTC #61 lore raw

PATCH v2 5/9 pinctrl: mvebu: add pinctrl driver for Armada XP

From: Thomas Petazzoni <[email protected]>

This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs.

---
v2: replaced variant with enum and used bitops.h

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt |  100 +++++
 drivers/pinctrl/Kconfig                            |    4 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-armada-xp.c                |  468 ++++++++++++++++++++
 4 files changed, 573 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-armada-xp.c

Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt new file +100 -0

new file mode 100644
index 0000000..bfa0a2e
@@ -0,0 +1,100 @@
+* Marvell Armada XP SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
+              "marvell,mv78460-pinctrl"
+
+This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Armada XP (all variants)
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, ge0(txclko), lcd(d0)
+mpp1          1        gpio, ge0(txd0), lcd(d1)
+mpp2          2        gpio, ge0(txd1), lcd(d2)
+mpp3          3        gpio, ge0(txd2), lcd(d3)
+mpp4          4        gpio, ge0(txd3), lcd(d4)
+mpp5          5        gpio, ge0(txctl), lcd(d5)
+mpp6          6        gpio, ge0(rxd0), lcd(d6)
+mpp7          7        gpio, ge0(rxd1), lcd(d7)
+mpp8          8        gpio, ge0(rxd2), lcd(d8)
+mpp9          9        gpio, ge0(rxd3), lcd(d9)
+mpp10         10       gpio, ge0(rxctl), lcd(d10)
+mpp11         11       gpio, ge0(rxclk), lcd(d11)
+mpp12         12       gpio, ge0(txd4), ge1(txd0), lcd(d12)
+mpp13         13       gpio, ge0(txd5), ge1(txd1), lcd(d13)
+mpp14         14       gpio, ge0(txd6), ge1(txd2), lcd(d15)
+mpp15         15       gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp16         16       gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp17         17       gpio, ge0(col), ge1(txctl), lcd(d17)
+mpp18         18       gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
+mpp19         19       gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
+mpp20         20       gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
+mpp21         21       gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
+mpp22         22       gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
+mpp23         23       gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
+mpp24         24       gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
+mpp25         25       gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
+mpp26         26       gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
+mpp27         27       gpio, lcd(e), tdm(dtx), ptp(trig)
+mpp28         28       gpio, lcd(pwm), tdm(drx), ptp(evreq)
+mpp29         29       gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
+mpp30         30       gpio, tdm(int1), sd0(clk)
+mpp31         31       gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
+mpp32         32       gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
+mpp33         33       gpio, tdm(int4), sd0(d1), mem(bat)
+mpp34         34       gpio, tdm(int5), sd0(d2), sata0(prsnt)
+mpp35         35       gpio, tdm(int6), sd0(d3), sata1(prsnt)
+mpp36         36       gpio, spi(mosi)
+mpp37         37       gpio, spi(miso)
+mpp38         38       gpio, spi(sck)
+mpp39         39       gpio, spi(cs0)
+mpp40         40       gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
+                       pcie(clkreq0)
+mpp41         41       gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
+                       pcie(clkreq1)
+mpp42         42       gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
+                       vdd(cpu0-pd)
+mpp43         43       gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
+                       vdd(cpu2-3-pd){1}
+mpp44         44       gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
+                       mem(bat)
+mpp45         45       gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
+mpp46         46       gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
+mpp47         47       gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
+                       ref(clkout)
+mpp48         48       gpio, tclk, dev(burst/last)
+
+* Marvell Armada XP (mv78260 and mv78460 only)
+
+name          pins     functions
+================================================================================
+mpp49         49       gpio, dev(we3)
+mpp50         50       gpio, dev(we2)
+mpp51         51       gpio, dev(ad16)
+mpp52         52       gpio, dev(ad17)
+mpp53         53       gpio, dev(ad18)
+mpp54         54       gpio, dev(ad19)
+mpp55         55       gpio, dev(ad20), vdd(cpu0-pd)
+mpp56         56       gpio, dev(ad21), vdd(cpu1-pd)
+mpp57         57       gpio, dev(ad22), vdd(cpu2-3-pd){1}
+mpp58         58       gpio, dev(ad23)
+mpp59         59       gpio, dev(ad24)
+mpp60         60       gpio, dev(ad25)
+mpp61         61       gpio, dev(ad26)
+mpp62         62       gpio, dev(ad27)
+mpp63         63       gpio, dev(ad28)
+mpp64         64       gpio, dev(ad29)
+mpp65         65       gpio, dev(ad30)
+mpp66         66       gpio, dev(ad31)
+
+Notes:
+* {1} vdd(cpu2-3-pd) only available on mv78460.

drivers/pinctrl/Kconfig +4 -0

index e16b8b0..a754144 100644
@@ -163,6 +163,10 @@ config PINCTRL_ARMADA_370
 	bool
 	select PINCTRL_MVEBU
 
+config PINCTRL_ARMADA_XP
+	bool
+	select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index e6d6667..f2ea050 100644
@@ -33,5 +33,6 @@ obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
 obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
 obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
+obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-armada-xp.c new file +468 -0

468 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-08-22 08:22 UTC #62 lore raw

PATCH v2 6/9 ARM: mvebu: add pinctrl device in DT for Armada 370/XP SoCs

From: Thomas Petazzoni <[email protected]>

The Armada 370 and XP SoCs have configurable muxing for a certain number of their pins, controlled through a pinctrl driver.

The 'compatible' property is defined in the SoC-specific .dtsi files, since the compatible string identifies the number of pins and other SoC-specific properties.

---
 arch/arm/boot/dts/armada-370-xp.dtsi |    7 +++++++
 1 file changed, 7 insertions(+)

arch/arm/boot/dts/armada-370-xp.dtsi +7 -0

index 16cc82c..54a944a 100644
@@ -68,6 +68,13 @@
 			compatible = "marvell,armada-addr-decoding-controller";
 			reg = <0xd0020000 0x258>;
 		};
+
+                pinctrl at d0018000 {
+                               reg = <0xd0018000 0x38>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               ranges;
+                };
 	};
 };

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-08-22 08:22 UTC #63 lore raw

PATCH v2 7/9 ARM: mvebu: Add pinctrl support to Armada XP SoCs

From: Thomas Petazzoni <[email protected]>

This commits adds the necessary device tree information to define the compatible property for the pinctrl driver instance of Armada XP SoCs.

---
 arch/arm/boot/dts/armada-xp-mv78230.dtsi |   27 +++++++++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78260.dtsi |   27 +++++++++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78460.dtsi |   27 +++++++++++++++++++++++++++
 3 files changed, 81 insertions(+)
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78230.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78260.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78460.dtsi

arch/arm/boot/dts/armada-xp-mv78230.dtsi new file +27 -0

new file mode 100644
index 0000000..69ad287
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78230 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP family SoC";
+	compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	soc {
+		pinctrl at d0018000 {
+			compatible = "marvell,mv78230-pinctrl";
+		};
+	};
+};

arch/arm/boot/dts/armada-xp-mv78260.dtsi new file +27 -0

new file mode 100644
index 0000000..0f38fa9
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78260 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP family SoC";
+	compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	soc {
+		pinctrl at d0018000 {
+			compatible = "marvell,mv78260-pinctrl";
+		};
+	};
+};

arch/arm/boot/dts/armada-xp-mv78460.dtsi new file +27 -0

new file mode 100644
index 0000000..9e61836
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78460 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP family SoC";
+	compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	soc {
+		pinctrl at d0018000 {
+			compatible = "marvell,mv78460-pinctrl";
+		};
+	};
+ };

Signature · 1 line

1.7.10.4

Stephen Warren

2012-08-22 20:45 UTC #64 lore raw

Re: [PATCH v2 7/9] ARM: mvebu: Add pinctrl support to Armada XP SoCs

Quoted 12 lines · Sebastian Hesselbarth

This commits adds the necessary device tree information to define the compatible property for the pinctrl driver instance of Armada XP SoCs.
Until now, the device tree representation considered the Armada XP as a single SoC. But in fact, there are three different SoCs in the Armada XP families, with different number of CPU cores, different number of Ethernet interfaces... and different number of muxable pins or functions. We therefore introduce three armada-xp-mv78xx0.dtsi for the three SoCs of the Armada XP family. The current armada-xp-db.dts evaluation board uses the MV78460 variant of the SoC.

arch/arm/boot/dts/armada-xp-mv78230.dtsi line 20

Quoted 6 lines

arch/arm/boot/dts/armada-xp-mv78230.dtsi +5 -0

 
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP family SoC";
+	compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";

Since each of these files is specifically for a different SoC, I'd expect them all to say something different in the model property?

Quoted 9 lines

arch/arm/boot/dts/armada-xp-mv78260.dtsi +2 -0

 
+	model = "Marvell Armada XP family SoC";
+	compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";

arch/arm/boot/dts/armada-xp-mv78460.dtsi +2 -0

 
+	model = "Marvell Armada XP family SoC";
+	compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";

Sebastian Hesselbarth

author maintainer

2012-08-22 08:22 UTC #65 lore raw

PATCH v2 8/9 ARM: mvebu: Add pinctrl support to Armada 370 SoC

From: Thomas Petazzoni <[email protected]>

This commits adds the necessary device tree information to define the compatible property for the pinctrl driver instance of Armada 370 SoC.

---
 arch/arm/boot/dts/armada-370.dtsi |    4 ++++
 1 file changed, 4 insertions(+)

arch/arm/boot/dts/armada-370.dtsi +4 -0

index 3228ccc..875fcd8 100644
@@ -31,5 +31,9 @@
 				compatible = "marvell,armada-370-xp-system-controller";
 				reg = <0xd0018200 0x100>;
 		};
+
+                pinctrl at d0018000 {
+			        compatible = "marvell,mv88f6710-pinctrl";
+	        };
 	};
 };

Signature · 1 line

1.7.10.4

Stephen Warren

2012-08-22 20:46 UTC #66 lore raw

Re: [PATCH v2 8/9] ARM: mvebu: Add pinctrl support to Armada 370 SoC

arch/arm/boot/dts/armada-370.dtsi line 37

Quoted 9 lines · Sebastian Hesselbarth

This commits adds the necessary device tree information to define the compatible property for the pinctrl driver instance of Armada 370 SoC.
arch/arm/boot/dts/armada-370.dtsi +4 -0
 
+
+                pinctrl at d0018000 {
+			        compatible = "marvell,mv88f6710-pinctrl";
+	        };

The indentation here is a mix of spaces and TABs.

Sebastian Hesselbarth

author maintainer

2012-08-22 08:22 UTC #67 lore raw

PATCH v2 9/9 ARM: mvebu: adjust Armada XP evaluation board DTS

From: Thomas Petazzoni <[email protected]>

---
 arch/arm/boot/dts/armada-xp-db.dts |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

arch/arm/boot/dts/armada-xp-db.dts +2 -2

index f97040d..b1fc728 100644
@@ -14,11 +14,11 @@
  */
 
 /dts-v1/;
-/include/ "armada-xp.dtsi"
+/include/ "armada-xp-mv78460.dtsi"
 
 / {
 	model = "Marvell Armada XP Evaluation Board";
-	compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
+	compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-09-10 08:39 UTC #68 lore raw

v3 cover pinctrl: mvebu: pinctrl driver

As especially Dove has some pinctrl registers that do not match the common pinctrl register layout the core driver has been extended by some callbacks to allow uncommon Dove pinctrl registers.

DT binding documentation is added for all supported SoCs but as Dove and Kirkwood are not yet ready for full DT support, the pinctrl driver is only activated for Armada 370 and XP.

The driver has been tested on Dove, 88f6281 variant of Kirkwood, Armada 370, and XP.

v3:
- parse functions from SoC specific pin groups instead of DT node
- move kirkwood variants to DT match data
- respect Armada XP variant in DTs
- cleaned whitespaces in DTs
- rebased to jcooper/boards-for-v3.7-v2

Sebastian Hesselbarth (3):
pinctrl: mvebu: pinctrl driver core
pinctrl: mvebu: dove pinctrl driver
pinctrl: mvebu: kirkwood pinctrl driver

 .../pinctrl/marvell,armada-370-pinctrl.txt         |   95 +++
 .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt |  100 +++
 .../bindings/pinctrl/marvell,dove-pinctrl.txt      |   72 ++
 .../bindings/pinctrl/marvell,kirkwood-pinctrl.txt  |  279 ++++++++
 .../bindings/pinctrl/marvell,mvebu-pinctrl.txt     |   45 ++
 arch/arm/Kconfig                                   |    1 +
 arch/arm/boot/dts/armada-370-xp.dtsi               |    7 +
 arch/arm/boot/dts/armada-370.dtsi                  |    4 +
 arch/arm/boot/dts/armada-xp-db.dts                 |    4 +-
 arch/arm/boot/dts/armada-xp-mv78230.dtsi           |   27 +
 arch/arm/boot/dts/armada-xp-mv78260.dtsi           |   27 +
 arch/arm/boot/dts/armada-xp-mv78460.dtsi           |   27 +
 drivers/pinctrl/Kconfig                            |   22 +
 drivers/pinctrl/Makefile                           |    5 +
 drivers/pinctrl/pinctrl-armada-370.c               |  421 ++++++++++++
 drivers/pinctrl/pinctrl-armada-xp.c                |  468 +++++++++++++
 drivers/pinctrl/pinctrl-dove.c                     |  622 +++++++++++++++++
 drivers/pinctrl/pinctrl-kirkwood.c                 |  473 +++++++++++++
 drivers/pinctrl/pinctrl-mvebu.c                    |  705 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-mvebu.h                    |  192 ++++++
 20 files changed, 3594 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78230.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78260.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78460.dtsi
 create mode 100644 drivers/pinctrl/pinctrl-armada-370.c
 create mode 100644 drivers/pinctrl/pinctrl-armada-xp.c
 create mode 100644 drivers/pinctrl/pinctrl-dove.c
 create mode 100644 drivers/pinctrl/pinctrl-kirkwood.c
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.c
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.h

---
Cc: Sebastian Hesselbarth <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Rob Landley <[email protected]>
Cc: Russell King <[email protected]>
Cc: Lior Amsalem <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Gregory CLEMENT <[email protected]>
Cc: Ben Dooks <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: devicetree-discuss at lists.ozlabs.org
Cc: linux-doc at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-09-10 08:39 UTC #69 lore raw

PATCH v3 1/9 pinctrl: mvebu: pinctrl driver core

This patch adds a pinctrl driver core for Marvell SoCs plus DT binding documentation. This core driver will be used by SoC family specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.

Signed-off-by Sebastian Hesselbarth <[email protected]>

v3:
- list of functions is now built out of pin groups passed to core driver instead of parsing DT node.

Cc Sebastian Hesselbarth <[email protected]>

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Jason Cooper <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 .../bindings/pinctrl/marvell,mvebu-pinctrl.txt     |   45 ++
 arch/arm/Kconfig                                   |    1 +
 drivers/pinctrl/Kconfig                            |    6 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-mvebu.c                    |  705 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-mvebu.h                    |  192 ++++++
 6 files changed, 950 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.c
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.h

Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt new file +45 -0

new file mode 100644
index 0000000..dc419e3
@@ -0,0 +1,45 @@
+* Marvell SoC pinctrl core driver for mpp
+
+The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
+(mpp) to a specific function. For each SoC family there is a SoC specific
+driver using this core driver.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+A Marvell SoC pin configuration node is a node of a group of pins which can
+be used for a specific device or function. Each node requires one or more
+mpp pins or group of pins and a mpp function common to all pins.
+
+Required properties for pinctrl driver:
+- compatible: "marvell,<soc>-pinctrl"
+  Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
+
+Required properties for pin configuration node:
+- marvell,pins: string array of mpp pins or group of pins to be muxed.
+- marvell,function: string representing a function to mux to for all
+    marvell,pins given in this pin configuration node. The function has to be
+    common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
+    valid pin/pin group names and available function names for each SoC.
+
+Examples:
+
+uart1: serial at 12100 {
+	compatible = "ns16550a";
+	reg = <0x12100 0x100>;
+	reg-shift = <2>;
+	interrupts = <7>;
+
+	pinctrl-0 = <&pmx_uart1_sw>;
+};
+
+pinctrl: pinctrl at d0200 {
+	compatible = "marvell,dove-pinctrl";
+	reg = <0xd0200 0x20>;
+
+	pmx_uart1_sw: pmx-uart1-sw {
+		marvell,pins = "mpp_uart1";
+		marvell,function = "uart1";
+	};
+};

arch/arm/Kconfig +1 -0

index a2b6f74..2eb3f6b 100644
@@ -574,6 +574,7 @@ config ARCH_MVEBU
 	select IRQ_DOMAIN
 	select COMMON_CLK
 	select PLAT_ORION
+	select PINCTRL
 	help
 	  Support for the Marvell SoC Family with device tree support

drivers/pinctrl/Kconfig +6 -0

index 54e3588..20bfdc3 100644
@@ -145,6 +145,12 @@ config PINCTRL_COH901
 	  COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
 	  ports of 8 GPIO pins each.
 
+config PINCTRL_MVEBU
+	bool
+	depends on ARCH_MVEBU
+	select PINMUX
+	select PINCONF
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index f40b1f8..007ed32 100644
@@ -29,5 +29,6 @@ obj-$(CONFIG_PINCTRL_TEGRA20)	+= pinctrl-tegra20.o
 obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
+obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-mvebu.c new file +705 -0

705 lines not on this page · raw message

drivers/pinctrl/pinctrl-mvebu.h new file +192 -0

192 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Linus Walleij

Acked-by on v3 1/9

2012-09-10 15:39 UTC #70 lore raw

Re: [PATCH v3 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 15 lines · Sebastian Hesselbarth

This patch adds a pinctrl driver core for Marvell SoCs plus DT binding documentation. This core driver will be used by SoC family specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.
Signed-off-by Sebastian Hesselbarth <[email protected]>
Signed-off-by Thomas Petazzoni <[email protected]>
---
v2:
- restructured Kconfig to have a common PINCTRL_MVEBU that are selected by SoC specific drivers.
- cleaned pinctrl-mvebu and replaced 'magic numbers' by defines
- make use of of_iomap instead of get_resource/ioremap
- extended include documentation and checked with scripts/kernel-doc
- cleaned devicetree binding documentation

Quoted 3 lines

v3:
- list of functions is now built out of pin groups passed to core driver instead of parsing DT node.

Looks good to me.

Yours,
Linus Walleij

Thomas Petazzoni

2012-09-11 14:44 UTC #71 lore raw

Re: [PATCH v3 1/9] pinctrl: mvebu: pinctrl driver core

In reply to Stephen Warren

Hello Sebastian,

Sorry for getting back to you so late about this patch set. I have been very busy with other things.

Le Mon, 10 Sep 2012 10:39:38 +0200,
Sebastian Hesselbarth <[email protected]> a ?crit :

Quoted 3 lines

v3:
- list of functions is now built out of pin groups passed to core driver instead of parsing DT node.

Even though I have gone through your discussion with Stephen Warren on this, I don't get what you have done exactly, and I'm even more puzzled by the following piece of code:

Quoted 28 lines

drivers/pinctrl/pinctrl-mvebu.c new file +28 -0

+static int __devinit _add_function(const char **funcs, const char *name)
+{
+	int n = 0;
+
+	while (funcs[n]) {
+		/* function already there */
+		if (strcmp(funcs[n], name) == 0)
+			return -EEXIST;
+		n++;
+	}
+	funcs[n] = name;
+	return 0;
+}
+
+static int __devinit mvebu_pinctrl_build_functions(struct platform_device *pdev,
+						   struct mvebu_pinctrl *pctl)
+{
+	const char **prefunc = kzalloc(sizeof(char *), GFP_KERNEL);
+	int num = 0;
+	int n, s;
+
+	for (n = 0; n < pctl->num_groups; n++) {
+		struct mvebu_pinctrl_group *grp = &pctl->groups[n];
+		for (s = 0; s < grp->num_settings; s++) {
+			/* skip unsupported settings on this variant */
+			if (pctl->variant &&
+			    !(pctl->variant & grp->settings[s].variant))
+				continue;

drivers/pinctrl/pinctrl-mvebu.c line 521

Quoted 10 lines

drivers/pinctrl/pinctrl-mvebu.c new file +10 -0

+
+			/* check for unique functions */
+			if (_add_function(prefunc, grp->settings[s].name))
+				continue;
+
+			num++;
+		}
+	}
+	return 0;
+}

What is this supposed to do? It allocates an array prefunc, whose reference is only stored in a local variable, and anywhere else, so basically it does nothing except leaking memory unless I got it wrong.

Moreover, this array has only one entry, while the loop accesses several entries, which probably explains the crash I'm seeing at boot time:

Unable to handle kernel paging request at virtual address ff74edca
pgd = ef290000
[ff74edca] *pgd=00000000
Internal error: Oops: 15 [#1] ARM
Modules linked in:
CPU: 0    Not tainted  (3.6.0-rc1-00021-g1dd75c4-dirty #336)
PC is at strcmp+0x0/0x30
LR is at mvebu_pinctrl_build_functions.isra.1+0x78/0xd0
pc : [<c011b600>]    lr : [<c021fbf8>]    psr: a0000013

sp : ef02de80 ip : 00000000 fp : c02a7e28
r10: 000002a0 r9 : ef0e4924 r8 : 00000018
r7 : ef2742d0 r6 : ef0cb2b0 r5 : 00000020 r4 : 00000002 r3 : ff74edca r2 : ef0e4920 r1 : c02a7e28 r0 : ff74edca
Flags: NzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c53c7d Table: 2f290059 DAC: 00000015 Process swapper (pid: 1, stack limit = 0xef02c268)

Stack: (0xef02de80 to 0xef02e000)

de80: ef0879c8 ef0e4900 00000043 00000043 ef2742d0 c054dd68 00000002 c057486c
dea0: 00000000 ef0879c8 ef0cb748 c02200f0 ef086348 c054c948 c055b550 c0576230
dec0: c054c6e0 ef0879c8 00000000 c054c6e0 c03008a0 c02f5c88 00000000 c014ed28
dee0: c014ed14 c014da3c ef0879c8 c054c6e0 ef0879fc 00000000 c02e91e0 c014dd30
df00: c054c6e0 c014dca4 00000000 c014c5e0 ef00554c ef0266f0 c054c6e0 c0551708
df20: ef274340 c014d380 c02a7da0 c055bf40 c054c6e0 ef02c000 c055bf40 00000000
df40: c02e91e0 c014e1e0 00000000 c02fdb4c ef02c000 c055bf40 00000000 c02e91e0
df60: c02f5c88 c00085c0 c02d1768 00000006 00000044 c02f5c88 00000044 00000006
df80: 00000006 c02e91e0 c1857e15 00000000 00000000 c02fdb4c 00000006 c02fdb2c
dfa0: c055bf40 c02e91e0 c03008a0 00000044 00000000 c02e9838 00000006 00000006
dfc0: c02e91e0 c030066c c030066c c030066c c000a04c 00000013 00000000 00000000
dfe0: 00000000 c02e98cc 00000000 00000000 c02e986c c000a04c be8ff7c8 e8dfff5e
[<c011b600>] (strcmp+0x0/0x30) from [<c021fbf8>] (mvebu_pinctrl_build_functions.isra.1+0x78/0xd0) [<c021fbf8>] (mvebu_pinctrl_build_functions.isra.1+0x78/0xd0) from [<c02200f0>] (mvebu_pinctrl_probe+0x4a0/0x564) [<c02200f0>] (mvebu_pinctrl_probe+0x4a0/0x564) from [<c014ed28>] (platform_drv_probe+0x14/0x18) [<c014ed28>] (platform_drv_probe+0x14/0x18) from [<c014da3c>] (really_probe+0x60/0x1e4) [<c014da3c>] (really_probe+0x60/0x1e4) from [<c014dd30>] (__driver_attach+0x8c/0x90) [<c014dd30>] (__driver_attach+0x8c/0x90) from [<c014c5e0>] (bus_for_each_dev+0x50/0x7c) [<c014c5e0>] (bus_for_each_dev+0x50/0x7c) from [<c014d380>] (bus_add_driver+0x168/0x22c) [<c014d380>] (bus_add_driver+0x168/0x22c) from [<c014e1e0>] (driver_register+0x78/0x144) [<c014e1e0>] (driver_register+0x78/0x144) from [<c00085c0>] (do_one_initcall+0x34/0x174) [<c00085c0>] (do_one_initcall+0x34/0x174) from [<c02e9838>] (do_basic_setup+0x90/0xc4) [<c02e9838>] (do_basic_setup+0x90/0xc4) from [<c02e98cc>] (kernel_init+0x60/0xf4)
[<c02e98cc>] (kernel_init+0x60/0xf4) from [<c000a04c>] (kernel_thread_exit+0x0/0x8)

Code: e3530000 e4c23001 1afffffb e12fff1e (e4d03001) 
---[ end trace a80e01be2a5f5b89 ]---
Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b

I'd like to fix that myself, but I really don't understand what the "functions" word mean now in this v3, as compared to v1/v2 of this patch set. Could you enlighten me on this?

Thanks!

Thomas

Signature · 4 lines

Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Stephen Warren

2012-09-11 22:17 UTC #72 lore raw

Re: [PATCH v3 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 50 lines · Thomas Petazzoni

Hello Sebastian,
Sorry for getting back to you so late about this patch set. I have been very busy with other things.
Le Mon, 10 Sep 2012 10:39:38 +0200,
Sebastian Hesselbarth <[email protected]> a ?crit :
Quoted 3 lines
v3:
- list of functions is now built out of pin groups passed to core driver instead of parsing DT node.
Even though I have gone through your discussion with Stephen Warren on this, I don't get what you have done exactly, and I'm even more puzzled by the following piece of code:
Quoted 34 lines
drivers/pinctrl/pinctrl-mvebu.c new file +34 -0
+static int __devinit _add_function(const char **funcs, const char *name)
+{
+	int n = 0;
+
+	while (funcs[n]) {
+		/* function already there */
+		if (strcmp(funcs[n], name) == 0)
+			return -EEXIST;
+		n++;
+	}
+	funcs[n] = name;
+	return 0;
+}
+
+static int __devinit mvebu_pinctrl_build_functions(struct platform_device *pdev,
+						   struct mvebu_pinctrl *pctl)
+{
+	const char **prefunc = kzalloc(sizeof(char *), GFP_KERNEL);
+	int num = 0;
+	int n, s;
+
+	for (n = 0; n < pctl->num_groups; n++) {
+		struct mvebu_pinctrl_group *grp = &pctl->groups[n];
+		for (s = 0; s < grp->num_settings; s++) {
+			/* skip unsupported settings on this variant */
+			if (pctl->variant &&
+			    !(pctl->variant & grp->settings[s].variant))
+				continue;
+
+			/* check for unique functions */
+			if (_add_function(prefunc, grp->settings[s].name))
+				continue;
+
+			num++;

Quoted 8 lines

drivers/pinctrl/pinctrl-mvebu.c line 162
Quoted 4 lines
drivers/pinctrl/pinctrl-mvebu.c new file +4 -0
+		}
+	}
+	return 0;
+}
What is this supposed to do? It allocates an array prefunc, whose reference is only stored in a local variable, and anywhere else, so basically it does nothing except leaking memory unless I got it wrong.

I imagine this is related to the way that the SoC-specific drivers provide their configuration to the generic core driver. I'm not sure the data structures used for this purpose are the best design.

The pinctrl core expects lists of:

* Pins

* Groups of pins (each being a name and an array of pins in the group)

* Functions that can be muxed onto the groups (each function being a global entity rather than something with a pin or group, and each function being a name, and an array of groups where the function can be selected).

However, the drivers in this patch seem to invert the data-structures a little - in other words, instead of defining a global list of functions, they define a list of groups, and for each group, list the functions that can be selected on to it.

In turn, that probably requires the core mvebu driver to invert these data-structures at run-time in order to provide the data the pinctrl core needs. I think it'd be better to just have each SoC-specific driver store the data tables in the same format that the pinctrl core needs it, so that the mvebu pinctrl core won't have to process the data-structures at all.

In particular, the following data structure is what I'm talking about:

+static struct mvebu_mpp_mode dove_mpp_modes[] = {
+ MPP_MODE(0,
+ MPP_FUNCTION(0x00, "gpio", NULL),
+ MPP_FUNCTION(0x02, "uart2", "rts"),
+ MPP_FUNCTION(0x03, "sdio0", "cd"),
+ MPP_FUNCTION(0x0f, "lcd0", "pwm"),
+ MPP_FUNCTION(0x10, "pmu", NULL)),

it's defining the functions within the context of a particular group ("mode" in the drivers terminology, I think...) rather than defining functions and groups as separate top-level tables.

Linus Walleij

2012-09-12 06:04 UTC #73 lore raw

Re: [PATCH v3 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 11 lines · Stephen Warren

the drivers in this patch seem to invert the data-structures a little - in other words, instead of defining a global list of functions, they define a list of groups, and for each group, list the functions that can be selected on to it.
In turn, that probably requires the core mvebu driver to invert these data-structures at run-time in order to provide the data the pinctrl core needs. I think it'd be better to just have each SoC-specific driver store the data tables in the same format that the pinctrl core needs it, so that the mvebu pinctrl core won't have to process the data-structures at all.

I sort of agree, not a blocker from my side but it'll surely make the code easier to maintain.

Else I think the culprit function needs some commenting to be readable, and writing in plaintext what can be explained by simpler code is not good...

Yours,
Linus Walleij

Thomas Petazzoni

2012-09-12 06:54 UTC #74 lore raw

Re: [PATCH v3 1/9] pinctrl: mvebu: pinctrl driver core

Le Tue, 11 Sep 2012 16:17:13 -0600,
Stephen Warren <[email protected]> a ?crit :

Quoted 9 lines

(quoted diff) +7 -0

+static struct mvebu_mpp_mode dove_mpp_modes[] = {
+	MPP_MODE(0,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart2", "rts"),
+		MPP_FUNCTION(0x03, "sdio0", "cd"),
+		MPP_FUNCTION(0x0f, "lcd0", "pwm"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),

Quoted 3 lines

it's defining the functions within the context of a particular group ("mode" in the drivers terminology, I think...) rather than defining functions and groups as separate top-level tables.

This data structure really reflects what the datasheet says. Typically, for SoCs where each pin is independently muxable (AT91, i.MX23/28, Marvell, and probably many more), the datasheet has a big array, with one line per pin, and then several columns which tell for a given pin, what is "function 0", "function 1", "function 2", "function 3", etc.

So the data structure that Sebastian has implemented in the mvebu driver immediately reflects this. In fact, the pinctrl table code for Armada 370 and Armada XP was semi-automatically generated from CSV data of the pinmux functions, directly coming from the datasheets. Having to create a global list of all possible functions seems useless and painful, since the functions only make sense in the context of one particular pin.

Could you be more specific as to what representation you're looking after? You're proposing to "define functions and groups as separate top-level tables", but then how to you map which functions are available for which group, and what is the number of that function is this group (which we need to actually configure the mapping). I'd really like to see (with a short code example) what is your view of how pinmux should be handled for SoCs having independently muxable pins.

I really don't understand how a global list of functions make sense:
the functions make sense on a per-group basis, and this is how the hardwaredatasheet defines them. If we could keep this representation, it would really be useful.

Thanks!

Thomas

Signature · 4 lines

Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Linus Walleij

2012-09-12 15:50 UTC #75 lore raw

Re: [PATCH v3 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 5 lines · Thomas Petazzoni

This data structure really reflects what the datasheet says. Typically, for SoCs where each pin is independently muxable (AT91, i.MX23/28, Marvell, and probably many more), the datasheet has a big array, with one line per pin, and then several columns which tell for a given pin, what is "function 0", "function 1", "function 2", "function 3", etc.

This is a valid reason to keep it as is in my book. Readability along with a datasheet is important, most important is that it has a good structure for those maintaining the driver.

Is this datasheet available so I can get the picture?

Yours,
Linus Walleij

Thomas Petazzoni

2012-09-12 16:01 UTC #76 lore raw

Re: [PATCH v3 1/9] pinctrl: mvebu: pinctrl driver core

Le Wed, 12 Sep 2012 17:50:48 +0200,
Linus Walleij <[email protected]> a ?crit :

Quoted 5 lines

This is a valid reason to keep it as is in my book. Readability along with a datasheet is important, most important is that it has a good structure for those maintaining the driver.
Is this datasheet available so I can get the picture?

All publicly available datasheets for Marvell ARM SoCs are referenced in Documentation/arm/Marvell/README.

See for example
http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6281_OpenSource.pdf,
which is the hardware datasheet for the 88F6281 Marvell SoC (Kirkwood family). Table 26 on page 53 of the PDF is a good example. It lists all the pins, on per row, and then has columns for each function identifier (from 0x0 to 0x7). Then each cell says when pin X is muxed in function Y, it provides this functionality.

So clearly, this representation is a list of pins, and for each pin, a list of possible functions that this pin can take.

Best regards,

Thomas

Signature · 4 lines

Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Linus Walleij

2012-09-12 16:17 UTC #77 lore raw

Re: [PATCH v3 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 10 lines · Thomas Petazzoni

See for example
http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6281_OpenSource.pdf,
which is the hardware datasheet for the 88F6281 Marvell SoC (Kirkwood family). Table 26 on page 53 of the PDF is a good example. It lists all the pins, on per row, and then has columns for each function identifier (from 0x0 to 0x7). Then each cell says when pin X is muxed in function Y, it provides this functionality.
So clearly, this representation is a list of pins, and for each pin, a list of possible functions that this pin can take.

OK the ux500 datasheet looks more or less the same. What I did was to define the groups that made sense for each column (our columns are named a,b,c), so you can see the result in drivers/pinctrl/pinctrl-nomadik-db8500.c

In your case I would have defined groups like this:

#define PIN_MPP18 18
#define PIN_MPP19 19
(...)

static const struct pinctrl_pin_desc nmk_db8500_pins[] = {
        PINCTRL_PIN(PIN_MPP18, "MPP[18]"),
        PINCTRL_PIN(PIN_MPP19, "MPP[19]"),

(...)
};
static const unsigned mpp_1_pins[] = { PIN_MPP18, PIN_MPP19);

Then I'd register this as a group, then map the groups to functions.

But maybe this is just stupid in your case, you'd have to tell. (Maybe it's my driver that sucks, I don't know.)

Linus Walleij

Yours,
Linus Walleij

Stephen Warren

2012-09-12 21:10 UTC #78 lore raw

Re: [PATCH v3 1/9] pinctrl: mvebu: pinctrl driver core

Quoted 22 lines · Thomas Petazzoni

Le Tue, 11 Sep 2012 16:17:13 -0600,
Stephen Warren <[email protected]> a ?crit :
Quoted 9 lines
(quoted diff) +7 -0
+static struct mvebu_mpp_mode dove_mpp_modes[] = {
+	MPP_MODE(0,
+		MPP_FUNCTION(0x00, "gpio", NULL),
+		MPP_FUNCTION(0x02, "uart2", "rts"),
+		MPP_FUNCTION(0x03, "sdio0", "cd"),
+		MPP_FUNCTION(0x0f, "lcd0", "pwm"),
+		MPP_FUNCTION(0x10, "pmu", NULL)),
Quoted 3 lines
it's defining the functions within the context of a particular group ("mode" in the drivers terminology, I think...) rather than defining functions and groups as separate top-level tables.
This data structure really reflects what the datasheet says. Typically, for SoCs where each pin is independently muxable (AT91, i.MX23/28, Marvell, and probably many more), the datasheet has a big array, with one line per pin, and then several columns which tell for a given pin, what is "function 0", "function 1", "function 2", "function 3", etc.

Quoted 4 lines

So the data structure that Sebastian has implemented in the mvebu driver immediately reflects this. In fact, the pinctrl table code for Armada 370 and Armada XP was semi-automatically generated from CSV data of the pinmux functions, directly coming from the datasheets.

OK, that seems like a reasonable explanation.

Still, doing data manipulation at run-time when it could easily be done by the script that converts your CSV into the driver tables seem inefficient at least. I agree with LinusW that it's not a big deal though.

Quoted 4 lines

Having to
create a global list of all possible functions seems useless and painful, since the functions only make sense in the context of one particular pin.

Surely some of your functions can be selected onto 1 of n pins? If that's true, then the functions don't only exist within the context of a single pin.

Note that some pinctrl driver authors have decided to create functions based on just the mux register values (e.g. mux0, mux1, mux2, mux3 for a 2-bit field) rather than semantically (e.g. uart1, uart2, i2c1, i2c2), in which case, all functions are global and available on any pin. I actually somewhat wonder if I shouldn't have done that for Tegra.

Quoted 4 lines

Could you be more specific as to what representation you're looking after? You're proposing to "define functions and groups as separate top-level tables", but then how to you map which functions are available for which group,

The definition of a function is a function name (struct pinmux_ops.get_function_name) and a list of groups onto which it can be selected (struct pinmux_ops.get_function_groups).

The pinctrl core leaves it up to individual drivers how to represent how to actually program a given group with a given function. ...

Quoted 4 lines

and what is the number of that function is
this group (which we need to actually configure the mapping). I'd really like to see (with a short code example) what is your view of how pinmux should be handled for SoCs having independently muxable pins.

As an example, see drivers/pinctrl/pinctrl-tegra20.c variable
tegra20_groups[] where each group definition contains additional information beyond the basic information that the pinctrl core requires (which is just struct pinctrl_ops get_group_name get_group_pins) - i.e. the global function ID that is selected by each of the 4 values you can write into that pin's/group's register.

Incidentally, I see that tegra20_groups[] is almost exactly equivalent to the data-structure we're talking about here; the difference is that the Tegra driver additionally has pre-generated arrays like xio_groups[] (the list of groups where function xio can be selected) in order to short-circuit the run-time calculations that your driver is doing.

(I don't believe any of this discussion is affected by whether the HW muxes at a per-pin level or per-pin-group level; Tegra30 muxes per-pin and the driver uses the exact same data-structures as Tegra20 which muxes per-group).

Sebastian Hesselbarth

author maintainer

2012-09-10 08:39 UTC #79 lore raw

PATCH v3 2/9 pinctrl: mvebu: dove pinctrl driver

This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core.

Signed-off-by Sebastian Hesselbarth <[email protected]>

Cc Sebastian Hesselbarth <[email protected]>

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Jason Cooper <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 .../bindings/pinctrl/marvell,dove-pinctrl.txt      |   72 +++
 drivers/pinctrl/Kconfig                            |    4 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-dove.c                     |  622 ++++++++++++++++++++
 4 files changed, 699 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-dove.c

Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt new file +72 -0

new file mode 100644
index 0000000..a648aaa
@@ -0,0 +1,72 @@
+* Marvell Dove SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,dove-pinctrl"
+- clocks: (optional) phandle of pdma clock
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
+mpp1          1        gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
+mpp2          2        gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
+                       uart1(rts)
+mpp3          3        gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
+                       uart1(cts), lcd-spi(cs1)
+mpp4          4        gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
+mpp5          5        gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
+mpp6          6        gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
+mpp7          7        gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
+mpp8          8        gpio, pmu, watchdog(rstout)
+mpp9          9        gpio, pmu, pex1(clkreq)
+mpp10         10       gpio, pmu, ssp(sclk)
+mpp11         11       gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
+                       sdio1(ledctrl), pex0(clkreq)
+mpp12         12       gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
+mpp13         13       gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
+                       ssp(extclk)
+mpp14         14       gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
+mpp15         15       gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
+mpp16         16       gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
+mpp17         17       gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
+                       ac97-1(sysclko)
+mpp18         18       gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
+mpp19         19       gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
+mpp20         20       gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
+                       ac97(sysclko)
+mpp21         21       gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
+                       uart1(cts), ssp(sfrm)
+mpp22         22       gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
+                       lcd-spi(mosi), uart1(cts), ssp(txd)
+mpp23         23       gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
+                       lcd-spi(sck), ssp(sclk)
+mpp_camera    24-39    gpio, camera
+mpp_sdio0     40-45    gpio, sdio0
+mpp_sdio1     46-51    gpio, sdio1
+mpp_audio1    52-57    gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
+                       ssp/twsi
+mpp_spi0      58-61    gpio, spi0
+mpp_uart1     62-63    gpio, uart1
+mpp_nand      64-71    gpo, nand
+audio0        -        i2s, ac97
+twsi          -        none, opt1, opt2, opt3
+
+Notes:
+* group "mpp_audio1" allows the following functions and gpio pins:
+  - gpio          : gpio on pins 52-57
+  - i2s1/spdifo   : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
+  - i2s1          : audio1 i2s on pins 52-55, gpio on pins 56,57
+  - spdifo        : spdifo on pin 57, gpio on pins 52-55
+  - twsi          : twsi on pins 56,57, gpio on pins 52-55
+  - ssp/spdifo    : ssp on pins 52-55, spdifo on pin 57, no gpios
+  - ssp           : ssp on pins 52-55, gpio on pins 56,57
+  - ssp/twsi      : ssp on pins 52-55, twsi on pins 56,57, no gpios
+* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
+  audio0 pins.
+* group "twsi" internally muxes twsi controller to the dedicated or option pins.

drivers/pinctrl/Kconfig +4 -0

index 20bfdc3..f15eba4 100644
@@ -151,6 +151,10 @@ config PINCTRL_MVEBU
 	select PINMUX
 	select PINCONF
 
+config PINCTRL_DOVE
+	bool
+	select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index 007ed32..d1327df 100644
@@ -30,5 +30,6 @@ obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
+obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-dove.c new file +622 -0

622 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Linus Walleij

Acked-by on v3 2/9

2012-09-10 15:40 UTC #80 lore raw

Re: [PATCH v3 2/9] pinctrl: mvebu: dove pinctrl driver

Quoted 4 lines · Sebastian Hesselbarth

This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core.

Quoted 8 lines

Signed-off-by Sebastian Hesselbarth <[email protected]>
---
v2:
- restructured pinctrl/Kconfig to hide pinctrl driver as it will be always selected by arch/arm/mach-mvebu/Kconfig
- cleaned pinctrl-dove and replaced 'magic numbers' by defines
- use devm_clk_get for (now optional) pdma clock and add to required properties in devicetree binding documentation

Nice work!

Yours,
Linus Walleij

Stephen Warren

2012-09-11 22:18 UTC #81 lore raw

Re: [PATCH v3 2/9] pinctrl: mvebu: dove pinctrl driver

Quoted 21 lines · Sebastian Hesselbarth

This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core.

drivers/pinctrl/pinctrl-dove.c +15 -0

 
+static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+			      unsigned long *config)
+{
+	unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+	unsigned long mask;
+
+	switch (ctrl->pid) {
+	case 24: /* mpp_camera */
+		mask = DOVE_CAM_GPIO_SEL;
+		break;
+	case 40: /* mpp_sdio0 */
+		mask = DOVE_SD0_GPIO_SEL;
+		break;
+	case 46: /* mpp_sdio1 */
+		mask = DOVE_SD1_GPIO_SEL;

drivers/pinctrl/pinctrl-dove.c line 113

Quoted 10 lines

drivers/pinctrl/pinctrl-dove.c +10 -0

+		break;
+	case 58: /* mpp_spi0 */
+		mask = DOVE_SPI_GPIO_SEL;
+		break;
+	case 62: /* mpp_uart1 */
+		mask = DOVE_UART1_GPIO_SEL;
+		break;
+	default:
+		return -EINVAL;
+	}

Wouldn't it be better to use #defines instead of the constants in the case statements, and also share those #defines with:

drivers/pinctrl/pinctrl-dove.c line 339

Quoted 2 lines

drivers/pinctrl/pinctrl-dove.c +2 -0

+static struct mvebu_mpp_ctrl dove_mpp_controls[] = {
+	MPP_FUNC_CTRL(0, 0, "mpp0", dove_pmu_mpp_ctrl),

                      ^^^^

drivers/pinctrl/pinctrl-dove.c line 368

Quoted 2 lines

drivers/pinctrl/pinctrl-dove.c +2 -0
+static struct mvebu_mpp_mode dove_mpp_modes[] = {
+	MPP_MODE(0,

^^

Sebastian Hesselbarth

author maintainer

2012-09-10 08:39 UTC #82 lore raw

PATCH v3 3/9 pinctrl: mvebu: kirkwood pinctrl driver

This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core.

Signed-off-by Sebastian Hesselbarth <[email protected]>

---
v2:
- restructured pinctrl/Kconfig to hide pinctrl driver as it will be always selected by arch/arm/mach-mvebu/Kconfig
- use enum for kirkwood variants instead of defines

v3:
- moved variant specific data to DT match struct

Cc Sebastian Hesselbarth <[email protected]>

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Jason Cooper <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 .../bindings/pinctrl/marvell,kirkwood-pinctrl.txt  |  279 ++++++++++++
 drivers/pinctrl/Kconfig                            |    4 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-kirkwood.c                 |  473 ++++++++++++++++++++
 4 files changed, 757 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-kirkwood.c

Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt new file +279 -0

new file mode 100644
index 0000000..361bccb
@@ -0,0 +1,279 @@
+* Marvell Kirkwood SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6180-pinctrl",
+              "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
+              "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
+
+This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Kirkwood 88f6180
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17         17       gpio, sdio(d3)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, mii(rxerr)
+mpp21         21       gpio, audio(spdifi)
+mpp22         22       gpio, audio(spdifo)
+mpp23         23       gpio, audio(rmclk)
+mpp24         24       gpio, audio(bclk)
+mpp25         25       gpio, audio(sdo)
+mpp26         26       gpio, audio(lrclk)
+mpp27         27       gpio, audio(mclk)
+mpp28         28       gpio, audio(sdi)
+mpp29         29       gpio, audio(extclk)
+
+* Marvell Kirkwood 88f6190
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0)
+mpp21         21       gpio, ge1(txd1), sata0(act)
+mpp22         22       gpio, ge1(txd2)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt)
+mpp24         24       gpio, ge1(rxd0)
+mpp25         25       gpio, ge1(rxd1)
+mpp26         26       gpio, ge1(rxd2)
+mpp27         27       gpio, ge1(rxd3)
+mpp28         28       gpio, ge1(col)
+mpp29         29       gpio, ge1(txclk)
+mpp30         30       gpio, ge1(rxclk)
+mpp31         31       gpio, ge1(rxclk)
+mpp32         32       gpio, ge1(txclko)
+mpp33         33       gpo, ge1(txclk)
+mpp34         34       gpio, ge1(txen)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr)
+
+* Marvell Kirkwood 88f6192
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33         33       gpo, ge1(txclk), tdm(drx)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+
+* Marvell Kirkwood 88f6281
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpio, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33         33       gpo, ge1(txclk), tdm(drx)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi)
+mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo)
+mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk)
+mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk)
+mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo)
+mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
+mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk)
+mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi)
+mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk)
+mpp45         45       gpio, ts(mp9), tdm(pclk)
+mpp46         46       gpio, ts(mp10), tdm(fs)
+mpp47         47       gpio, ts(mp11), tdm(drx)
+mpp48         48       gpio, ts(mp12), tdm(dtx)
+mpp49         49       gpio, ts(mp9), tdm(rx0ql), ptp(clk)
+
+* Marvell Kirkwood 88f6282
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync)
+mpp5          5        gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync)
+mpp6          6        sysrst(out), spi(mosi)
+mpp7          7        gpo, spi(cs), lcd(pwm)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
+                       mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
+                       sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), sata0(act)
+mpp12         12       gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda)
+mpp13         13       gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt),
+                       audio(spdifi), audio-1(sdi)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
+                       spi(cs)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act), lcd(extclk)
+mpp17         17       gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck)
+mpp18         18       gpo, nand(io0), pex(clkreq)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act), lcd(d0)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo), lcd(d1)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt), lcd(d2)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk), lcd(d3)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo),
+                       lcd(d4)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
+                       lcd(d5)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk),
+                       lcd(d6)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi),
+                       lcd(d7)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk),
+                       lcd(d8)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12)
+mpp33         33       gpo, ge1(txclk), tdm(drx), lcd(d13)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql),
+                       lcd(d15)
+mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda)
+mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck)
+mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18)
+mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19)
+mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20)
+mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
+mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22)
+mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23)
+mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk)
+mpp45         45       gpio, ts(mp9), tdm(pclk), lcd(e)
+mpp46         46       gpio, ts(mp10), tdm(fs), lcd(hsync)
+mpp47         47       gpio, ts(mp11), tdm(drx), lcd(vsync)
+mpp48         48       gpio, ts(mp12), tdm(dtx), lcd(d16)
+mpp49         49       gpo, tdm(rx0ql), pex(clkreq), lcd(d17)

drivers/pinctrl/Kconfig +4 -0

index f15eba4..31c0bba 100644
@@ -155,6 +155,10 @@ config PINCTRL_DOVE
 	bool
 	select PINCTRL_MVEBU
 
+config PINCTRL_KIRKWOOD
+	bool
+	select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index d1327df..3006294 100644
@@ -31,5 +31,6 @@ obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
+obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-kirkwood.c new file +473 -0

473 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Linus Walleij

Acked-by on v3 3/9

2012-09-10 15:42 UTC #83 lore raw

Re: [PATCH v3 3/9] pinctrl: mvebu: kirkwood pinctrl driver

Quoted 5 lines · Sebastian Hesselbarth

This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core.
Signed-off-by Sebastian Hesselbarth <[email protected]>

Quoted 8 lines

---
v2:
- restructured pinctrl/Kconfig to hide pinctrl driver as it will be always selected by arch/arm/mach-mvebu/Kconfig
- use enum for kirkwood variants instead of defines
v3:
- moved variant specific data to DT match struct

Lookin' good.

Yours,
Linus Walleij

Sebastian Hesselbarth

author maintainer

2012-09-10 08:39 UTC #84 lore raw

PATCH v3 4/9 pinctrl: mvebu: add pinctrl driver for Armada 370

From: Thomas Petazzoni <[email protected]>

This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs.

---
v2:
- removed arch/arm/*/Kconfig changes and added note about variant = 0

Cc Sebastian Hesselbarth <[email protected]>

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Jason Cooper <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 .../pinctrl/marvell,armada-370-pinctrl.txt         |   95 +++++
 drivers/pinctrl/Kconfig                            |    4 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-armada-370.c               |  421 ++++++++++++++++++++
 4 files changed, 521 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-armada-370.c

Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt new file +95 -0

new file mode 100644
index 0000000..01ef408
@@ -0,0 +1,95 @@
+* Marvell Armada 370 SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6710-pinctrl"
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, uart0(rxd)
+mpp1          1        gpo, uart0(txd)
+mpp2          2        gpio, i2c0(sck), uart0(txd)
+mpp3          3        gpio, i2c0(sda), uart0(rxd)
+mpp4          4        gpio, cpu_pd(vdd)
+mpp5          5        gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
+mpp6          6        gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
+mpp7          7        gpo, ge0(txd1), tdm(tdx), audio(lrclk)
+mpp8          8        gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
+mpp9          9        gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
+mpp10         10       gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
+mpp11         11       gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
+                       sata1(prsnt), spi1(cs1)
+mpp12         12       gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
+                       audio(spdifi)
+mpp13         13       gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
+                       audio(rmclk)
+mpp14         14       gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
+                       spi0(cs2)
+mpp15         15       gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
+                       spi0(cs3)
+mpp16         16       gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
+mpp17         17       gpo, ge(mdc)
+mpp18         18       gpio, ge(mdio)
+mpp19         19       gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
+mpp20         20       gpo, ge0(txd4), ge1(txd0)
+mpp21         21       gpo, ge0(txd5), ge1(txd1), uart1(txd)
+mpp22         22       gpo, ge0(txd6), ge1(txd2), uart0(rts)
+mpp23         23       gpo, ge0(txd7), ge1(txd3), spi1(mosi)
+mpp24         24       gpio, ge0(col), ge1(txctl), spi1(cs0)
+mpp25         25       gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
+mpp26         26       gpio, ge0(crs), ge1(rxd1), spi1(miso)
+mpp27         27       gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
+mpp28         28       gpio, ge0(rxd5), ge1(rxd3)
+mpp29         29       gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
+mpp30         30       gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
+mpp31         31       gpio, tclk, ge0(txerr)
+mpp32         32       gpio, spi0(cs0)
+mpp33         33       gpio, dev(bootcs), spi0(cs0)
+mpp34         34       gpo, dev(wen0), spi0(mosi)
+mpp35         35       gpo, dev(oen), spi0(sck)
+mpp36         36       gpo, dev(a1), spi0(miso)
+mpp37         37       gpo, dev(a0), sata0(prsnt)
+mpp38         38       gpio, dev(ready), uart1(cts), uart0(cts)
+mpp39         39       gpo, dev(ad0), audio(spdifo)
+mpp40         40       gpio, dev(ad1), uart1(rts), uart0(rts)
+mpp41         41       gpio, dev(ad2), uart1(rxd)
+mpp42         42       gpo, dev(ad3), uart1(txd)
+mpp43         43       gpo, dev(ad4), audio(bclk)
+mpp44         44       gpo, dev(ad5), audio(mclk)
+mpp45         45       gpo, dev(ad6), audio(lrclk)
+mpp46         46       gpo, dev(ad7), audio(sdo)
+mpp47         47       gpo, dev(ad8), sd0(clk), audio(spdifo)
+mpp48         48       gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
+                       spi0(cs1)
+mpp49         49       gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
+                       audio(spdifi)
+mpp50         50       gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
+                       audio(rmclk)
+mpp51         51       gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
+mpp52         52       gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
+mpp53         53       gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
+                       pcie(clkreq1)
+mpp54         54       gpo, dev(ad15), tdm(dtx)
+mpp55         55       gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
+                       sata0(prsnt)
+mpp56         56       gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
+                       pcie(clkreq0), spi1(cs1)
+mpp57         57       gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
+                       audio(sdo)
+mpp58         58       gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
+                       uart0(rts)
+mpp59         59       gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
+mpp60         60       gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
+                       audio(sdi)
+mpp61         61       gpo, dev(wen1), uart1(txd), audio(rclk)
+mpp62         62       gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
+                       audio(mclk), uart0(cts)
+mpp63         63       gpo, spi0(sck), tclk
+mpp64         64       gpio, spi0(miso), spi0-1(cs1)
+mpp65         65       gpio, spi0(mosi), spi0-1(cs2)

drivers/pinctrl/Kconfig +4 -0

index 31c0bba..e16b8b0 100644
@@ -159,6 +159,10 @@ config PINCTRL_KIRKWOOD
 	bool
 	select PINCTRL_MVEBU
 
+config PINCTRL_ARMADA_370
+	bool
+	select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index 3006294..e6d6667 100644
@@ -32,5 +32,6 @@ obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
 obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
+obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-armada-370.c new file +421 -0

421 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Linus Walleij

Acked-by on v3 4/9

2012-09-10 15:43 UTC #85 lore raw

Re: [PATCH v3 4/9] pinctrl: mvebu: add pinctrl driver for Armada 370

Quoted 10 lines · Sebastian Hesselbarth

From: Thomas Petazzoni <[email protected]>
This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs.
Signed-off-by Thomas Petazzoni <[email protected]>
---
v2:
- removed arch/arm/*/Kconfig changes and added note about variant = 0

Yours,
Linus Walleij

Sebastian Hesselbarth

author maintainer

2012-09-10 08:39 UTC #86 lore raw

PATCH v3 5/9 pinctrl: mvebu: add pinctrl driver for Armada XP

From: Thomas Petazzoni <[email protected]>

This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs.

---
v2: replaced variant with enum and used bitops.h

Cc Sebastian Hesselbarth <[email protected]>

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Jason Cooper <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt |  100 +++++
 drivers/pinctrl/Kconfig                            |    4 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-armada-xp.c                |  468 ++++++++++++++++++++
 4 files changed, 573 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-armada-xp.c

Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt new file +100 -0

new file mode 100644
index 0000000..bfa0a2e
@@ -0,0 +1,100 @@
+* Marvell Armada XP SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
+              "marvell,mv78460-pinctrl"
+
+This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Armada XP (all variants)
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, ge0(txclko), lcd(d0)
+mpp1          1        gpio, ge0(txd0), lcd(d1)
+mpp2          2        gpio, ge0(txd1), lcd(d2)
+mpp3          3        gpio, ge0(txd2), lcd(d3)
+mpp4          4        gpio, ge0(txd3), lcd(d4)
+mpp5          5        gpio, ge0(txctl), lcd(d5)
+mpp6          6        gpio, ge0(rxd0), lcd(d6)
+mpp7          7        gpio, ge0(rxd1), lcd(d7)
+mpp8          8        gpio, ge0(rxd2), lcd(d8)
+mpp9          9        gpio, ge0(rxd3), lcd(d9)
+mpp10         10       gpio, ge0(rxctl), lcd(d10)
+mpp11         11       gpio, ge0(rxclk), lcd(d11)
+mpp12         12       gpio, ge0(txd4), ge1(txd0), lcd(d12)
+mpp13         13       gpio, ge0(txd5), ge1(txd1), lcd(d13)
+mpp14         14       gpio, ge0(txd6), ge1(txd2), lcd(d15)
+mpp15         15       gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp16         16       gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp17         17       gpio, ge0(col), ge1(txctl), lcd(d17)
+mpp18         18       gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
+mpp19         19       gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
+mpp20         20       gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
+mpp21         21       gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
+mpp22         22       gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
+mpp23         23       gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
+mpp24         24       gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
+mpp25         25       gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
+mpp26         26       gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
+mpp27         27       gpio, lcd(e), tdm(dtx), ptp(trig)
+mpp28         28       gpio, lcd(pwm), tdm(drx), ptp(evreq)
+mpp29         29       gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
+mpp30         30       gpio, tdm(int1), sd0(clk)
+mpp31         31       gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
+mpp32         32       gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
+mpp33         33       gpio, tdm(int4), sd0(d1), mem(bat)
+mpp34         34       gpio, tdm(int5), sd0(d2), sata0(prsnt)
+mpp35         35       gpio, tdm(int6), sd0(d3), sata1(prsnt)
+mpp36         36       gpio, spi(mosi)
+mpp37         37       gpio, spi(miso)
+mpp38         38       gpio, spi(sck)
+mpp39         39       gpio, spi(cs0)
+mpp40         40       gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
+                       pcie(clkreq0)
+mpp41         41       gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
+                       pcie(clkreq1)
+mpp42         42       gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
+                       vdd(cpu0-pd)
+mpp43         43       gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
+                       vdd(cpu2-3-pd){1}
+mpp44         44       gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
+                       mem(bat)
+mpp45         45       gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
+mpp46         46       gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
+mpp47         47       gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
+                       ref(clkout)
+mpp48         48       gpio, tclk, dev(burst/last)
+
+* Marvell Armada XP (mv78260 and mv78460 only)
+
+name          pins     functions
+================================================================================
+mpp49         49       gpio, dev(we3)
+mpp50         50       gpio, dev(we2)
+mpp51         51       gpio, dev(ad16)
+mpp52         52       gpio, dev(ad17)
+mpp53         53       gpio, dev(ad18)
+mpp54         54       gpio, dev(ad19)
+mpp55         55       gpio, dev(ad20), vdd(cpu0-pd)
+mpp56         56       gpio, dev(ad21), vdd(cpu1-pd)
+mpp57         57       gpio, dev(ad22), vdd(cpu2-3-pd){1}
+mpp58         58       gpio, dev(ad23)
+mpp59         59       gpio, dev(ad24)
+mpp60         60       gpio, dev(ad25)
+mpp61         61       gpio, dev(ad26)
+mpp62         62       gpio, dev(ad27)
+mpp63         63       gpio, dev(ad28)
+mpp64         64       gpio, dev(ad29)
+mpp65         65       gpio, dev(ad30)
+mpp66         66       gpio, dev(ad31)
+
+Notes:
+* {1} vdd(cpu2-3-pd) only available on mv78460.

drivers/pinctrl/Kconfig +4 -0

index e16b8b0..a754144 100644
@@ -163,6 +163,10 @@ config PINCTRL_ARMADA_370
 	bool
 	select PINCTRL_MVEBU
 
+config PINCTRL_ARMADA_XP
+	bool
+	select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index e6d6667..f2ea050 100644
@@ -33,5 +33,6 @@ obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
 obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
 obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
+obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-armada-xp.c new file +468 -0

468 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Linus Walleij

Acked-by on v3 5/9

2012-09-10 15:43 UTC #87 lore raw

Re: [PATCH v3 5/9] pinctrl: mvebu: add pinctrl driver for Armada XP

Quoted 9 lines · Sebastian Hesselbarth

From: Thomas Petazzoni <[email protected]>
This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs.
Signed-off-by Thomas Petazzoni <[email protected]>
---
v2: replaced variant with enum and used bitops.h

Yours,
Linus Walleij

Sebastian Hesselbarth

author maintainer

2012-09-10 08:39 UTC #88 lore raw

PATCH v3 6/9 ARM: mvebu: add pinctrl device in DT for Armada 370/XP SoCs

From: Thomas Petazzoni <[email protected]>

The Armada 370 and XP SoCs have configurable muxing for a certain number of their pins, controlled through a pinctrl driver.

The 'compatible' property is defined in the SoC-specific .dtsi files, since the compatible string identifies the number of pins and other SoC-specific properties.

---
v3:
- cleaned whitespaces

Cc Sebastian Hesselbarth <[email protected]>

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Jason Cooper <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 arch/arm/boot/dts/armada-370-xp.dtsi |    7 +++++++
 1 file changed, 7 insertions(+)

arch/arm/boot/dts/armada-370-xp.dtsi +7 -0

index 16cc82c..ff1c7a6 100644
@@ -68,6 +68,13 @@
 			compatible = "marvell,armada-addr-decoding-controller";
 			reg = <0xd0020000 0x258>;
 		};
+
+		pinctrl at d0018000 {
+			reg = <0xd0018000 0x38>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+		};
 	};
 };

Signature · 1 line

1.7.10.4

Stephen Warren

2012-09-11 22:23 UTC #89 lore raw

Re: [PATCH v3 6/9] ARM: mvebu: add pinctrl device in DT for Armada 370/XP SoCs

Quoted 4 lines · Sebastian Hesselbarth

From: Thomas Petazzoni <[email protected]>
The Armada 370 and XP SoCs have configurable muxing for a certain number of their pins, controlled through a pinctrl driver.

Hmmm. I'd be tempted just to put the entire node definition there; putting in a .dtsi file just to share the reg property doesn't seem especially useful.

arch/arm/boot/dts/armada-370-xp.dtsi

Quoted 7 lines

The 'compatible' property is defined in the SoC-specific .dtsi files, since the compatible string identifies the number of pins and other SoC-specific properties.
arch/arm/boot/dts/armada-370-xp.dtsi +1 -0
 
+		pinctrl at d0018000 {

If this is the only pinctrl instance, you'd typically name the node just "pinctrl", since the "@d0018000" isn't needed to get unique node names.

arch/arm/boot/dts/armada-370-xp.dtsi line 76

Quoted 4 lines

arch/arm/boot/dts/armada-370-xp.dtsi +4 -0

+			reg = <0xd0018000 0x38>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;

What is "ranges" for; this isn't a memory-mapped bus, right?

Quoted 3 lines

arch/arm/boot/dts/armada-370-xp.dtsi +1 -0
+		};
 	};
 };

Thomas Petazzoni

2012-09-12 06:56 UTC #90 lore raw

Re: [PATCH v3 6/9] ARM: mvebu: add pinctrl device in DT for Armada 370/XP SoCs

Le Tue, 11 Sep 2012 16:23:19 -0600,
Stephen Warren <[email protected]> a ?crit :

Quoted 9 lines · Sebastian Hesselbarth

Quoted 4 lines
From: Thomas Petazzoni <[email protected]>
The Armada 370 and XP SoCs have configurable muxing for a certain number of their pins, controlled through a pinctrl driver.
Hmmm. I'd be tempted just to put the entire node definition there; putting in a .dtsi file just to share the reg property doesn't seem especially useful.

When you say "here" you're mentioning the SoC-specific .dtsi files (i.e the ones in PATCH 7/9 and PATCH 8/9), correct?

Quoted 10 lines

arch/arm/boot/dts/armada-370-xp.dtsi
Quoted 7 lines
The 'compatible' property is defined in the SoC-specific .dtsi files, since the compatible string identifies the number of pins and other SoC-specific properties.
arch/arm/boot/dts/armada-370-xp.dtsi +1 -0
 
+		pinctrl at d0018000 {
If this is the only pinctrl instance, you'd typically name the node just "pinctrl", since the "@d0018000" isn't needed to get unique node names.

Ack.

Quoted 6 lines

arch/arm/boot/dts/armada-370-xp.dtsi line 76
Quoted 4 lines
arch/arm/boot/dts/armada-370-xp.dtsi +4 -0
+			reg = <0xd0018000 0x38>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
What is "ranges" for; this isn't a memory-mapped bus, right?

Ack.

Best regards,

Thomas

Signature · 4 lines

Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Stephen Warren

2012-09-12 20:57 UTC #91 lore raw

Re: [PATCH v3 6/9] ARM: mvebu: add pinctrl device in DT for Armada 370/XP SoCs

Quoted 6 lines · Thomas Petazzoni

Le Tue, 11 Sep 2012 16:23:19 -0600,
Stephen Warren <[email protected]> a ?crit :
Quoted 3 lines · Sebastian Hesselbarth
Quoted 2 lines
From: Thomas Petazzoni <[email protected]>

Quoted 8 lines

Quoted 6 lines
Quoted 2 lines
The Armada 370 and XP SoCs have configurable muxing for a certain number of their pins, controlled through a pinctrl driver.
Hmmm. I'd be tempted just to put the entire node definition there; putting in a .dtsi file just to share the reg property doesn't seem especially useful.
When you say "here" you're mentioning the SoC-specific .dtsi files (i.e

(s/here/there I assume).

Quoted 1 line

the ones in PATCH 7/9 and PATCH 8/9), correct?

Yes, I believe so.

Sebastian Hesselbarth

author maintainer

2012-09-10 08:39 UTC #92 lore raw

PATCH v3 7/9 ARM: mvebu: Add pinctrl support to Armada XP SoCs

From: Thomas Petazzoni <[email protected]>

This commits adds the necessary device tree information to define the compatible property for the pinctrl driver instance of Armada XP SoCs.

---
v3:
- put specific variant into DT "model"

Cc Sebastian Hesselbarth <[email protected]>

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Jason Cooper <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 arch/arm/boot/dts/armada-xp-mv78230.dtsi |   27 +++++++++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78260.dtsi |   27 +++++++++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78460.dtsi |   27 +++++++++++++++++++++++++++
 3 files changed, 81 insertions(+)
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78230.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78260.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78460.dtsi

arch/arm/boot/dts/armada-xp-mv78230.dtsi new file +27 -0

new file mode 100644
index 0000000..8bdcd43
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78230 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP MV78230 SoC";
+	compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	soc {
+		pinctrl at d0018000 {
+			compatible = "marvell,mv78230-pinctrl";
+		};
+	};
+};

arch/arm/boot/dts/armada-xp-mv78260.dtsi new file +27 -0

new file mode 100644
index 0000000..e5c108b
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78260 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP MV78260 SoC";
+	compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	soc {
+		pinctrl at d0018000 {
+			compatible = "marvell,mv78260-pinctrl";
+		};
+	};
+};

arch/arm/boot/dts/armada-xp-mv78460.dtsi new file +27 -0

new file mode 100644
index 0000000..22e7fdd
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78460 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP MV78460 SoC";
+	compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	soc {
+		pinctrl at d0018000 {
+			compatible = "marvell,mv78460-pinctrl";
+		};
+	};
+ };

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-09-10 08:39 UTC #93 lore raw

PATCH v3 8/9 ARM: mvebu: Add pinctrl support to Armada 370 SoC

From: Thomas Petazzoni <[email protected]>

This commits adds the necessary device tree information to define the compatible property for the pinctrl driver instance of Armada 370 SoC.

---
v3:
- cleaned whitespaces

Cc Sebastian Hesselbarth <[email protected]>

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Jason Cooper <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 arch/arm/boot/dts/armada-370.dtsi |    4 ++++
 1 file changed, 4 insertions(+)

arch/arm/boot/dts/armada-370.dtsi +4 -0

index 3228ccc..b71ab9b 100644
@@ -31,5 +31,9 @@
 				compatible = "marvell,armada-370-xp-system-controller";
 				reg = <0xd0018200 0x100>;
 		};
+
+		pinctrl at d0018000 {
+			compatible = "marvell,mv88f6710-pinctrl";
+		};
 	};
 };

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-09-10 08:39 UTC #94 lore raw

PATCH v3 9/9 ARM: mvebu: adjust Armada XP evaluation board DTS

From: Thomas Petazzoni <[email protected]>

---
 arch/arm/boot/dts/armada-xp-db.dts |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

arch/arm/boot/dts/armada-xp-db.dts +2 -2

index f97040d..b1fc728 100644
@@ -14,11 +14,11 @@
  */
 
 /dts-v1/;
-/include/ "armada-xp.dtsi"
+/include/ "armada-xp-mv78460.dtsi"
 
 / {
 	model = "Marvell Armada XP Evaluation Board";
-	compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
+	compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";

Signature · 1 line

1.7.10.4

Linus Walleij

2012-09-10 15:45 UTC #95 lore raw

Quoted 4 lines · Sebastian Hesselbarth

This patch set adds a core pinctrl driver for Marvell MVEBU SoCs and SoC specific stubs for Armada 370, Armada XP, Dove, and Kirkwood. The SoC specific stubs use the pinctrl-mvebu core driver that handles pinctrl API and register accesses for common pinctrl registers.

This all looks good now, will this be pushed through some ARM SoC tree along with Marvell changes or do you want me to take it all through the pinctrl tree?

Yours,
Linus Walleij

Sebastian Hesselbarth

author maintainer

2012-09-10 15:57 UTC #96 lore raw

Quoted 3 lines · Linus Walleij

This all looks good now, will this be pushed through some ARM SoC tree along with Marvell changes or do you want me to take it all through the pinctrl tree?

Linus,

thanks for review and ACKs. Jason Cooper will take it through Marvell tree.

Sebastian

Thomas Petazzoni

2012-09-11 14:20 UTC #97 lore raw

pinctrl: mvebu: minor fixes

Sebastian,

Here are two minor fixes for the pinctrl-mvebu.c driver. The v3 of the driver still doesn't work for me on Armada 370/XP. I'm investigating, but I'm not sure to understand some of the changes you've made in the v3.

Best regards,

Thomas

Thomas Petazzoni

2012-09-11 14:20 UTC #98 lore raw

PATCH 1/2 pinctrl: mvebu: mark internal functions as static

---
 drivers/pinctrl/pinctrl-mvebu.c |   10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

drivers/pinctrl/pinctrl-mvebu.c +5 -5

index 52b1da1..ed1fc3b 100644
@@ -59,7 +59,7 @@ struct mvebu_pinctrl {
 	u8 variant;
 };
 
-struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_pid(
+static struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_pid(
 	struct mvebu_pinctrl *pctl, unsigned pid)
 {
 	unsigned n;

@@ -72,7 +72,7 @@ struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_pid(
 	return NULL;
 }
 
-struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_name(
+static struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_name(
 	struct mvebu_pinctrl *pctl, const char *name)
 {
 	unsigned n;

@@ -83,7 +83,7 @@ struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_name(
 	return NULL;
 }
 
-struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_val(
+static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_val(
 	struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
 	unsigned long config)
 {

@@ -98,7 +98,7 @@ struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_val(
 	return NULL;
 }
 
-struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_name(
+static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_name(
 	struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
 	const char *name)
 {

@@ -113,7 +113,7 @@ struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_name(
 	return NULL;
 }
 
-struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_gpio_setting(
+static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_gpio_setting(
 	struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp)
 {
 	unsigned n;

Signature · 1 line

1.7.9.5

Linus Walleij

2012-09-11 17:54 UTC #99 lore raw

PATCH 1/2 pinctrl: mvebu: mark internal functions as static

Quoted 4 lines · Thomas Petazzoni

Signed-off-by Thomas Petazzoni <[email protected]>
---
 drivers/pinctrl/pinctrl-mvebu.c |   10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

Yours,
Linus Walleij

Thomas Petazzoni

2012-09-11 14:20 UTC #100 lore raw

PATCH 2/2 pinctrl: mvebu: remove dead code

---
 drivers/pinctrl/pinctrl-mvebu.c |   13 -------------
 1 file changed, 13 deletions(-)

drivers/pinctrl/pinctrl-mvebu.c +0 ~~-13~~

index ed1fc3b..720e547 100644
@@ -128,19 +128,6 @@ static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_gpio_setting(
 	return NULL;
 }
 
-#if 0
-struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name(
-	struct mvebu_pinctrl *pctl, const char *name)
-{
-	unsigned n;
-	for (n = 0; n < pctl->num_functions; n++) {
-		if (strcmp(name, pctl->functions[n].name) == 0)
-			return &pctl->functions[n];
-	}
-	return NULL;
-}
-#endif
-
 /*
  * Common mpp pin configuration registers on MVEBU are
  * registers of eight 4-bit values for each mpp setting.

Signature · 1 line

1.7.9.5

Linus Walleij

2012-09-11 17:55 UTC #101 lore raw

PATCH 2/2 pinctrl: mvebu: remove dead code

drivers/pinctrl/pinctrl-mvebu.c static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_gpio_setting( · line 142

Quoted 12 lines · Thomas Petazzoni

drivers/pinctrl/pinctrl-mvebu.c +0 ~~-12~~

-#if 0
-struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name(
-       struct mvebu_pinctrl *pctl, const char *name)
-{
-       unsigned n;
-       for (n = 0; n < pctl->num_functions; n++) {
-               if (strcmp(name, pctl->functions[n].name) == 0)
-                       return &pctl->functions[n];
-       }
-       return NULL;
-}
-#endif

Grrr how could I miss this...?

Yours,
Linus Walleij

Sebastian Hesselbarth

author maintainer

2012-09-11 15:31 UTC #102 lore raw

pinctrl: mvebu: minor fixes

Quoted 4 lines · Thomas Petazzoni

Here are two minor fixes for the pinctrl-mvebu.c driver. The v3 of the driver still doesn't work for me on Armada 370/XP. I'm investigating, but I'm not sure to understand some of the changes you've made in the v3.

Thomas,

thanks for this one! After reviewing the offending code, I realized that it must
be an old(er) version of the pinctrl core. I ll dig out the correct version and report
on list accordingly.

Sebastian

Thomas Petazzoni

2012-09-11 15:35 UTC #103 lore raw

pinctrl: mvebu: minor fixes

Le Tue, 11 Sep 2012 17:31:56 +0200,
Sebastian Hesselbarth <[email protected]> a ?crit :

Quoted 5 lines

thanks for this one! After reviewing the offending code, I realized that it must
be an old(er) version of the pinctrl core. I ll dig out the correct version and report
on list accordingly.

Ok, great. The version you had sent looked really strange/unfinished to me, so happy to know there's a more finalized version somewhere :-)

I'll test it as soon as you post it, to validate that it works OK on Armada 370/XP.

That said, I'm still interested by a short human-readable summary of the changes you've done in terms of how the 'functions' are handled compared to the original version of the driver.

Thanks!

Thomas

Signature · 4 lines

Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Thomas Petazzoni

2012-09-11 15:37 UTC #104 lore raw

arm: mvebu: improve Kconfig options handling for pinctrl

Sebastian, Andrew, Jason, Gr?gory,

As was mentionned during the review of the pinctrl driver, it would be better to have the Armada 370 and XP pinctrl drivers being select-ed by their respective Kconfig options. This was unfortunately not possible due to the fact that both of those SoCs were handled by the same Kconfig option.

This small patch set splits the Armada 370 and XP Kconfig option into three options (one hidden common option, two visible options), and then uses those two options to select the appropriate pinctrl driver.

Sebastian, would you mind carrying them in your pinctrl patch set? Or has your patch set already been merged by Jason, in which case Jason could handle those two patches as well? Please let me know what solution you chose and if I need to rebase this on a specific branch. For now, it's based on top of the v3 of the pinctrl-mvebu driver.

Thanks,

Thomas

Thomas Petazzoni

2012-09-11 15:37 UTC #105 lore raw

PATCH 1/2 arm: mvebu: split Kconfig options for Armada 370 and XP

Until now, all the code for Armada 370 and XP was common, so we had a single Kconfig option to support all boards using both SoCs. With the addition of pinctrl drivers, this situation has changed: those two SoCs are radically different in terms of pinctrl, so they have two separate drivers. Since pinctrl drivers are typically select-ed from the SoC Kconfig option, it makes sense to split the 370/XP option into two separate options: one for Armada 370 and another for Armada XP.

We keep an hidden option selected by both ARMADA_370 and ARMADA_XP in order to easily compile common code.

A followup patch actually makes use of this split to select the appropriate pinctrl drivers.

---
 arch/arm/mach-mvebu/Kconfig |   16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

arch/arm/mach-mvebu/Kconfig +13 -3

index caa2c5e..b0924b1 100644
@@ -3,13 +3,23 @@ if ARCH_MVEBU
 menu "Marvell SOC with device tree"
 
 config MACH_ARMADA_370_XP
-	bool "Marvell Armada 370 and Aramada XP boards"
+	bool
 	select ARMADA_370_XP_TIMER
 	select CPU_V7
+
+config MACH_ARMADA_370
+	bool "Marvell Armada 370 boads"
+	select MACH_ARMADA_370_XP
 	help
+	  Say 'Y' here if you want your kernel to support boards based
+	  on the Marvell Armada XP SoC with device tree.
 
-	  Say 'Y' here if you want your kernel to support boards based on
-	  Marvell Armada 370 or Armada XP with device tree.
+config MACH_ARMADA_XP
+	bool "Marvell Armada XP boards"
+	select MACH_ARMADA_370_XP
+	help
+	  Say 'Y' here if you want your kernel to support boards based
+	  on the Marvell Armada XP SoC with device tree.
 
 endmenu

Signature · 1 line

1.7.9.5

Sebastian Hesselbarth

author maintainer

2012-09-11 17:35 UTC #106 lore raw

PATCH 1/2 arm: mvebu: split Kconfig options for Armada 370 and XP

arch/arm/mach-mvebu/Kconfig if ARCH_MVEBU · line 11

Quoted 7 lines · Thomas Petazzoni

A followup patch actually makes use of this split to select the appropriate pinctrl drivers.
[...]
arch/arm/mach-mvebu/Kconfig +2 -0
+config MACH_ARMADA_370
+	bool "Marvell Armada 370 boads"

typo: boards

arch/arm/mach-mvebu/Kconfig if ARCH_MVEBU · line 15

Quoted 4 lines

arch/arm/mach-mvebu/Kconfig +3 -0

+	select MACH_ARMADA_370_XP
  	help
+	  Say 'Y' here if you want your kernel to support boards based
+	  on the Marvell Armada XP SoC with device tree.

typo: Armada 370

arch/arm/mach-mvebu/Kconfig if ARCH_MVEBU · line 24

Quoted 11 lines

arch/arm/mach-mvebu/Kconfig +6 -2

-	  Say 'Y' here if you want your kernel to support boards based on
-	  Marvell Armada 370 or Armada XP with device tree.
+config MACH_ARMADA_XP
+	bool "Marvell Armada XP boards"
+	select MACH_ARMADA_370_XP
+	help
+	  Say 'Y' here if you want your kernel to support boards based
+	  on the Marvell Armada XP SoC with device tree.
 
  endmenu

Sebastian

Thomas Petazzoni

2012-09-11 15:37 UTC #107 lore raw

PATCH 2/2 arm: mvebu: select the pinctrl drivers for Armada 370 and Armada XP platforms

---
 arch/arm/mach-mvebu/Kconfig |    2 ++
 1 file changed, 2 insertions(+)

arch/arm/mach-mvebu/Kconfig +2 -0

index b0924b1..0da722e 100644
@@ -10,6 +10,7 @@ config MACH_ARMADA_370_XP
 config MACH_ARMADA_370
 	bool "Marvell Armada 370 boads"
 	select MACH_ARMADA_370_XP
+	select PINCTRL_ARMADA_370
 	help
 	  Say 'Y' here if you want your kernel to support boards based
 	  on the Marvell Armada XP SoC with device tree.

@@ -17,6 +18,7 @@ config MACH_ARMADA_370
 config MACH_ARMADA_XP
 	bool "Marvell Armada XP boards"
 	select MACH_ARMADA_370_XP
+	select PINCTRL_ARMADA_XP
 	help
 	  Say 'Y' here if you want your kernel to support boards based
 	  on the Marvell Armada XP SoC with device tree.

Signature · 1 line

1.7.9.5

Sebastian Hesselbarth

author maintainer

2012-09-11 17:40 UTC #108 lore raw

PATCH 2/2 arm: mvebu: select the pinctrl drivers for Armada 370 and Armada XP platforms

Quoted 13 lines · Thomas Petazzoni

arch/arm/mach-mvebu/Kconfig +1 -0

index b0924b1..0da722e 100644
@@ -10,6 +10,7 @@ config MACH_ARMADA_370_XP
  config MACH_ARMADA_370
  	bool "Marvell Armada 370 boads"
  	select MACH_ARMADA_370_XP
+	select PINCTRL_ARMADA_370
  	help
  	  Say 'Y' here if you want your kernel to support boards based
  	  on the Marvell Armada XP SoC with device tree.

arch/arm/mach-mvebu/Kconfig config MACH_ARMADA_370 · line 24

Quoted 7 lines

arch/arm/mach-mvebu/Kconfig +1 -0

@@ -17,6 +18,7 @@ config MACH_ARMADA_370
  config MACH_ARMADA_XP
  	bool "Marvell Armada XP boards"
  	select MACH_ARMADA_370_XP
+	select PINCTRL_ARMADA_XP
  	help
  	  Say 'Y' here if you want your kernel to support boards based
  	  on the Marvell Armada XP SoC with device tree.

Using PINCTRL_MVEBU on any mvebu SoC requires to "select PINCTRL" in arch/arm/Kconfig for ARCH_MVEBU, too.

Sebastian

Thomas Petazzoni

2012-09-12 10:48 UTC #109 lore raw

PATCH 2/2 arm: mvebu: select the pinctrl drivers for Armada 370 and Armada XP platforms

Le Tue, 11 Sep 2012 19:40:40 +0200,
Sebastian Hesselbarth <[email protected]> a ?crit :

Quoted 2 lines

Using PINCTRL_MVEBU on any mvebu SoC requires to "select PINCTRL" in arch/arm/Kconfig for ARCH_MVEBU, too.

This is already done by your PATCH 1/9 from the v3 of your patchset:

arch/arm/Kconfig +1 -0

index a2b6f74..2eb3f6b 100644
@@ -574,6 +574,7 @@ config ARCH_MVEBU
 	select IRQ_DOMAIN
 	select COMMON_CLK
 	select PLAT_ORION
+	select PINCTRL
 	help
 	  Support for the Marvell SoC Family with device tree support

Best regards,

Thomas

Signature · 4 lines

Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Gregory CLEMENT

2012-09-11 16:17 UTC #110 lore raw

arm: mvebu: improve Kconfig options handling for pinctrl

Quoted 12 lines · Thomas Petazzoni

Sebastian, Andrew, Jason, Gr?gory,
As was mentionned during the review of the pinctrl driver, it would be better to have the Armada 370 and XP pinctrl drivers being select-ed by their respective Kconfig options. This was unfortunately not possible due to the fact that both of those SoCs were handled by the same Kconfig option.
This small patch set splits the Armada 370 and XP Kconfig option into three options (one hidden common option, two visible options), and then uses those two options to select the appropriate pinctrl driver.

Quoted 7 lines

Sebastian, would you mind carrying them in your pinctrl patch set? Or has your patch set already been merged by Jason, in which case Jason could handle those two patches as well? Please let me know what solution you chose and if I need to rebase this on a specific branch. For now, it's based on top of the v3 of the pinctrl-mvebu driver.

I have tested the series for both board. It's OK for me you can add my Acked-by.

Shouldn't we update the defconfig in the same time?

With the current defconfig MACH_ARMADA_370_XP is selected but not visible and MACH_ARMADA_370 or MACH_ARMADA_XP are visible but not selected.

Quoted 4 lines

Thanks,
Thomas

Signature · 4 lines

Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Sebastian Hesselbarth

author maintainer

2012-09-11 17:32 UTC #111 lore raw

arm: mvebu: improve Kconfig options handling for pinctrl

Quoted 10 lines · Thomas Petazzoni

This small patch set splits the Armada 370 and XP Kconfig option into three options (one hidden common option, two visible options), and then uses those two options to select the appropriate pinctrl driver.
Sebastian, would you mind carrying them in your pinctrl patch set? Or has your patch set already been merged by Jason, in which case Jason could handle those two patches as well? Please let me know what solution you chose and if I need to rebase this on a specific branch. For now, it's based on top of the v3 of the pinctrl-mvebu driver.

Thomas,

as the linux-arm-kernel is already on this discussion, I'll not remove it on this one. But with future RFC patches we should be more careful who the patch is sent to.

I'd like to have pinctrl-mvebu patch set separated from this Kconfig patch set. Not because it doesn't fit but because I don't want to respin the pinctrl patch. Posting v3 without in-depth review of my own was a mistake. A final v4 will get offending patches right.

For this patch set I will comment on the single patch emails.

Sebastian

Thomas Petazzoni

2012-09-12 10:47 UTC #112 lore raw

arm: mvebu: improve Kconfig options handling for pinctrl

Hello,

Le Tue, 11 Sep 2012 19:32:44 +0200,
Sebastian Hesselbarth <[email protected]> a ?crit :

Quoted 3 lines

as the linux-arm-kernel is already on this discussion, I'll not remove it on this one. But with future RFC patches we should be more careful who the patch is sent to.

Since I wasn't sure you would take those patches, I thought sending to LAKML and other parties was a good idea.

Quoted 4 lines

I'd like to have pinctrl-mvebu patch set separated from this Kconfig patch set. Not because it doesn't fit but because I don't want to respin the pinctrl patch. Posting v3 without in-depth review of my own was a mistake. A final v4 will get offending patches right.

Well, in the end, you have to resend a new v4, so why not include those patches? Without those patches, the pinctrl stuff is not usable on 370/XP, which is not so nice.

Quoted 1 line

For this patch set I will comment on the single patch emails.

Thanks!

Thomas

Signature · 4 lines

Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Sebastian Hesselbarth

author maintainer

2012-09-13 15:41 UTC #113 lore raw

v4 cover pinctrl: mvebu: pinctrl driver

As especially Dove has some pinctrl registers that do not match the common pinctrl register layout the core driver has been extended by some callbacks to allow uncommon Dove pinctrl registers.

DT binding documentation is added for all supported SoCs but as Dove and Kirkwood are not yet ready for full DT support, the pinctrl driver is only activated for Armada 370 and XP.

The driver of latest patch v4 has been tested on Dove, Armada 370, Armada XP, and 88f6281 variant of Kirkwood.

v4:
- fix bogus v3 patch set with respect to pinctrl-mvebu, and pinctrl-kirkwood (my deep appologies to all reviewers that wasted their time with reviewing v3)
- mark internal functions in pinctrl-mvebu as static
- split up Kconfig of Armada 370 and XP
- enable pinctrl drivers for Armada 370 and XP

Sebastian Hesselbarth (3):
pinctrl: mvebu: pinctrl driver core
pinctrl: mvebu: dove pinctrl driver
pinctrl: mvebu: kirkwood pinctrl driver

Thomas Petazzoni (7):
pinctrl: mvebu: add pinctrl driver for Armada 370
pinctrl: mvebu: add pinctrl driver for Armada XP
ARM: mvebu: Add pinctrl support to Armada XP SoCs
ARM: mvebu: Add pinctrl support to Armada 370 SoC
ARM: mvebu: adjust Armada XP evaluation board DTS
arm: mvebu: split Kconfig options for Armada 370 and XP
arm: mvebu: select the pinctrl drivers for Armada 370 and Armada XP
platforms

 .../pinctrl/marvell,armada-370-pinctrl.txt         |   95 +++
 .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt |  100 +++
 .../bindings/pinctrl/marvell,dove-pinctrl.txt      |   72 ++
 .../bindings/pinctrl/marvell,kirkwood-pinctrl.txt  |  279 ++++++++
 .../bindings/pinctrl/marvell,mvebu-pinctrl.txt     |   46 ++
 arch/arm/Kconfig                                   |    1 +
 arch/arm/boot/dts/armada-370.dtsi                  |    7 +
 arch/arm/boot/dts/armada-xp-db.dts                 |    4 +-
 arch/arm/boot/dts/armada-xp-mv78230.dtsi           |   30 +
 arch/arm/boot/dts/armada-xp-mv78260.dtsi           |   30 +
 arch/arm/boot/dts/armada-xp-mv78460.dtsi           |   30 +
 arch/arm/mach-mvebu/Kconfig                        |   18 +-
 drivers/pinctrl/Kconfig                            |   22 +
 drivers/pinctrl/Makefile                           |    5 +
 drivers/pinctrl/pinctrl-armada-370.c               |  421 +++++++++++
 drivers/pinctrl/pinctrl-armada-xp.c                |  468 ++++++++++++
 drivers/pinctrl/pinctrl-dove.c                     |  620 ++++++++++++++++
 drivers/pinctrl/pinctrl-kirkwood.c                 |  472 ++++++++++++
 drivers/pinctrl/pinctrl-mvebu.c                    |  754 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-mvebu.h                    |  192 +++++
 20 files changed, 3661 insertions(+), 5 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78230.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78260.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78460.dtsi
 create mode 100644 drivers/pinctrl/pinctrl-armada-370.c
 create mode 100644 drivers/pinctrl/pinctrl-armada-xp.c
 create mode 100644 drivers/pinctrl/pinctrl-dove.c
 create mode 100644 drivers/pinctrl/pinctrl-kirkwood.c
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.c
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.h

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-09-13 15:41 UTC #114 lore raw

PATCH v4 1/10 pinctrl: mvebu: pinctrl driver core

This patch adds a pinctrl driver core for Marvell SoCs plus DT binding documentation. This core driver will be used by SoC family specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.

Signed-off-by Sebastian Hesselbarth <[email protected]>

v3:
- list of functions is now built out of pin groups passed to core driver instead of parsing DT node.

v4:
- fix bogus v3 patch set
- mark internal functions as static
- add a note to devicetree documentation for "default" pinctrl-name
- use function name instead of DT node name for DT mapping

Cc Sebastian Hesselbarth <[email protected]>

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Jason Cooper <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 .../bindings/pinctrl/marvell,mvebu-pinctrl.txt     |   46 ++
 arch/arm/Kconfig                                   |    1 +
 drivers/pinctrl/Kconfig                            |    6 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-mvebu.c                    |  754 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-mvebu.h                    |  192 +++++
 6 files changed, 1000 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.c
 create mode 100644 drivers/pinctrl/pinctrl-mvebu.h

Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt new file +46 -0

new file mode 100644
index 0000000..0a26c3a
@@ -0,0 +1,46 @@
+* Marvell SoC pinctrl core driver for mpp
+
+The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
+(mpp) to a specific function. For each SoC family there is a SoC specific
+driver using this core driver.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+A Marvell SoC pin configuration node is a node of a group of pins which can
+be used for a specific device or function. Each node requires one or more
+mpp pins or group of pins and a mpp function common to all pins.
+
+Required properties for pinctrl driver:
+- compatible: "marvell,<soc>-pinctrl"
+  Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
+
+Required properties for pin configuration node:
+- marvell,pins: string array of mpp pins or group of pins to be muxed.
+- marvell,function: string representing a function to mux to for all
+    marvell,pins given in this pin configuration node. The function has to be
+    common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
+    valid pin/pin group names and available function names for each SoC.
+
+Examples:
+
+uart1: serial at 12100 {
+	compatible = "ns16550a";
+	reg = <0x12100 0x100>;
+	reg-shift = <2>;
+	interrupts = <7>;
+
+	pinctrl-0 = <&pmx_uart1_sw>;
+	pinctrl-names = "default";
+};
+
+pinctrl: pinctrl at d0200 {
+	compatible = "marvell,dove-pinctrl";
+	reg = <0xd0200 0x20>;
+
+	pmx_uart1_sw: pmx-uart1-sw {
+		marvell,pins = "mpp_uart1";
+		marvell,function = "uart1";
+	};
+};

arch/arm/Kconfig +1 -0

index a2b6f74..2eb3f6b 100644
@@ -574,6 +574,7 @@ config ARCH_MVEBU
 	select IRQ_DOMAIN
 	select COMMON_CLK
 	select PLAT_ORION
+	select PINCTRL
 	help
 	  Support for the Marvell SoC Family with device tree support

drivers/pinctrl/Kconfig +6 -0

index 54e3588..20bfdc3 100644
@@ -145,6 +145,12 @@ config PINCTRL_COH901
 	  COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
 	  ports of 8 GPIO pins each.
 
+config PINCTRL_MVEBU
+	bool
+	depends on ARCH_MVEBU
+	select PINMUX
+	select PINCONF
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index f40b1f8..007ed32 100644
@@ -29,5 +29,6 @@ obj-$(CONFIG_PINCTRL_TEGRA20)	+= pinctrl-tegra20.o
 obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
+obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-mvebu.c new file +754 -0

754 lines not on this page · raw message

drivers/pinctrl/pinctrl-mvebu.h new file +192 -0

192 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-09-13 15:41 UTC #115 lore raw

PATCH v4 2/10 pinctrl: mvebu: dove pinctrl driver

This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core.

Signed-off-by Sebastian Hesselbarth <[email protected]>

In reply to Russell King - ARM Linux

v4:
- choose more precise twsi option names
- assume match on DT node

Cc Sebastian Hesselbarth <[email protected]>

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Jason Cooper <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 .../bindings/pinctrl/marvell,dove-pinctrl.txt      |   72 +++
 drivers/pinctrl/Kconfig                            |    4 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-dove.c                     |  620 ++++++++++++++++++++
 4 files changed, 697 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-dove.c

Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt new file +72 -0

new file mode 100644
index 0000000..a648aaa
@@ -0,0 +1,72 @@
+* Marvell Dove SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,dove-pinctrl"
+- clocks: (optional) phandle of pdma clock
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
+mpp1          1        gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
+mpp2          2        gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
+                       uart1(rts)
+mpp3          3        gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
+                       uart1(cts), lcd-spi(cs1)
+mpp4          4        gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
+mpp5          5        gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
+mpp6          6        gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
+mpp7          7        gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
+mpp8          8        gpio, pmu, watchdog(rstout)
+mpp9          9        gpio, pmu, pex1(clkreq)
+mpp10         10       gpio, pmu, ssp(sclk)
+mpp11         11       gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
+                       sdio1(ledctrl), pex0(clkreq)
+mpp12         12       gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
+mpp13         13       gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
+                       ssp(extclk)
+mpp14         14       gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
+mpp15         15       gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
+mpp16         16       gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
+mpp17         17       gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
+                       ac97-1(sysclko)
+mpp18         18       gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
+mpp19         19       gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
+mpp20         20       gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
+                       ac97(sysclko)
+mpp21         21       gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
+                       uart1(cts), ssp(sfrm)
+mpp22         22       gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
+                       lcd-spi(mosi), uart1(cts), ssp(txd)
+mpp23         23       gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
+                       lcd-spi(sck), ssp(sclk)
+mpp_camera    24-39    gpio, camera
+mpp_sdio0     40-45    gpio, sdio0
+mpp_sdio1     46-51    gpio, sdio1
+mpp_audio1    52-57    gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
+                       ssp/twsi
+mpp_spi0      58-61    gpio, spi0
+mpp_uart1     62-63    gpio, uart1
+mpp_nand      64-71    gpo, nand
+audio0        -        i2s, ac97
+twsi          -        none, opt1, opt2, opt3
+
+Notes:
+* group "mpp_audio1" allows the following functions and gpio pins:
+  - gpio          : gpio on pins 52-57
+  - i2s1/spdifo   : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
+  - i2s1          : audio1 i2s on pins 52-55, gpio on pins 56,57
+  - spdifo        : spdifo on pin 57, gpio on pins 52-55
+  - twsi          : twsi on pins 56,57, gpio on pins 52-55
+  - ssp/spdifo    : ssp on pins 52-55, spdifo on pin 57, no gpios
+  - ssp           : ssp on pins 52-55, gpio on pins 56,57
+  - ssp/twsi      : ssp on pins 52-55, twsi on pins 56,57, no gpios
+* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
+  audio0 pins.
+* group "twsi" internally muxes twsi controller to the dedicated or option pins.

drivers/pinctrl/Kconfig +4 -0

index 20bfdc3..f15eba4 100644
@@ -151,6 +151,10 @@ config PINCTRL_MVEBU
 	select PINMUX
 	select PINCONF
 
+config PINCTRL_DOVE
+	bool
+	select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index 007ed32..d1327df 100644
@@ -30,5 +30,6 @@ obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
+obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-dove.c new file +620 -0

620 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Russell King - ARM Linux

2013-06-18 11:36 UTC #116 lore raw

Re: [PATCH v4 02/10] pinctrl: mvebu: dove pinctrl driver

Quoted 6 lines · Sebastian Hesselbarth

drivers/pinctrl/pinctrl-dove.c new file +6 -0

+#define DOVE_GLOBAL_CONFIG_1		(DOVE_SB_REGS_VIRT_BASE | 0xe802C)
+#define  DOVE_TWSI_ENABLE_OPTION1	BIT(7)
+#define DOVE_GLOBAL_CONFIG_2		(DOVE_SB_REGS_VIRT_BASE | 0xe8030)
+#define  DOVE_TWSI_ENABLE_OPTION2	BIT(20)
+#define  DOVE_TWSI_ENABLE_OPTION3	BIT(21)
+#define  DOVE_TWSI_OPTION3_GPIO		BIT(22)

...

Quoted 16 lines

drivers/pinctrl/pinctrl-dove.c new file +16 -0

+static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+				unsigned long config)
+{
+	unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
+	unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+	gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1;
+	gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION2);
+
+	switch (config) {
+	case 1:
+		gcfg1 |= DOVE_TWSI_ENABLE_OPTION1;
+		break;
+	case 2:
+		gcfg2 |= DOVE_TWSI_ENABLE_OPTION2;
+		break;

drivers/pinctrl/pinctrl-dove.c line 336

Quoted 10 lines

drivers/pinctrl/pinctrl-dove.c new file +10 -0

+	case 3:
+		gcfg2 |= DOVE_TWSI_ENABLE_OPTION3;
+		break;
+	}
+
+	writel(gcfg1, DOVE_GLOBAL_CONFIG_1);
+	writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
+
+	return 0;
+}

So, I've just been thinking about the LCD clocking on the Armada 510, and found that there's dividers for the internal LCD clocks in the global config 1/2 registers. So I grepped the kernel source for references to these, expecting to find something in drivers/clk, but found the above.

Now, the reason that I'm replying to this is that we're again falling into the same trap that we did with SA1100 devices. Back in those days, there wasn't so much of a problem because the kernel was basically single threaded when it came to code like the above on such platforms. There was no kernel preemption.

However, todays kernel is sometimes SMP, commonly with kernel preemption enabled, maybe even RT. This makes things like the above sequence a problem where a multifunction register is read, modified and then written back.

Consider two threads doing this, and a preemption event happening in the middle of this sequence to another thread also doing a read-modify-write of the same register. Which one wins depends on the preemption sequence, but ultimately one loses out.

Any access to such registers needs careful thought, and protection in some manner.

Maybe what we need is something like this:

static DEFINE_SPINLOCK(io_lock);
static void modifyl(u32 new, u32 mask, void __iomem *reg)

{
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&io_lock, flags);
	val = readl(reg) & ~mask;
	val |= new | mask;
	writel(val, reg);
	spin_unlock_irqrestore(&io_lock, flags);
}

in order to provide arbitrated access to these kinds of multifunction registers in a safe, platform agnostic way.

Comments?

Sebastian Hesselbarth

author maintainer

2013-06-18 12:01 UTC #117 lore raw

Re: [PATCH v4 02/10] pinctrl: mvebu: dove pinctrl driver

Quoted 8 lines · Russell King - ARM Linux

Quoted 6 lines · Sebastian Hesselbarth

drivers/pinctrl/pinctrl-dove.c new file +6 -0

+#define DOVE_GLOBAL_CONFIG_1		(DOVE_SB_REGS_VIRT_BASE | 0xe802C)
+#define  DOVE_TWSI_ENABLE_OPTION1	BIT(7)
+#define DOVE_GLOBAL_CONFIG_2		(DOVE_SB_REGS_VIRT_BASE | 0xe8030)
+#define  DOVE_TWSI_ENABLE_OPTION2	BIT(20)
+#define  DOVE_TWSI_ENABLE_OPTION3	BIT(21)
+#define  DOVE_TWSI_OPTION3_GPIO		BIT(22)

...

Russell,

the above absolute addresses already made me think of cleaning up dove pinctrl a while ago. I also had in mind that below function exclusively request ownership of global config registers.

Quoted 24 lines

drivers/pinctrl/pinctrl-dove.c new file +24 -0

+static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+				unsigned long config)
+{
+	unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
+	unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+	gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1;
+	gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION2);
+
+	switch (config) {
+	case 1:
+		gcfg1 |= DOVE_TWSI_ENABLE_OPTION1;
+		break;
+	case 2:
+		gcfg2 |= DOVE_TWSI_ENABLE_OPTION2;
+		break;
+	case 3:
+		gcfg2 |= DOVE_TWSI_ENABLE_OPTION3;
+		break;
+	}
+
+	writel(gcfg1, DOVE_GLOBAL_CONFIG_1);
+	writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
+

Quoted 8 lines

Review
Quoted 2 lines
(quoted diff) +2 -0
+	return 0;
+}
So, I've just been thinking about the LCD clocking on the Armada 510, and found that there's dividers for the internal LCD clocks in the global config 1/2 registers. So I grepped the kernel source for references to these, expecting to find something in drivers/clk, but found the above.

We have no peripheral clock handling for Dove, yet. Just core clocks and clock gates are implemented. And I guess they are DT only anyway.

Quoted 9 lines

However, todays kernel is sometimes SMP, commonly with kernel preemption enabled, maybe even RT. This makes things like the above sequence a problem where a multifunction register is read, modified and then written back.
Consider two threads doing this, and a preemption event happening in the middle of this sequence to another thread also doing a read-modify-write of the same register. Which one wins depends on the preemption sequence, but ultimately one loses out.

Yeah, sure. We have the same issue with watchdog driver messing with timer registers. There I exported a function to _clrset TIMER_CTRL register safely. Just went into irqchip (tip for-next).

Quoted 18 lines

Any access to such registers needs careful thought, and protection in some manner.
Maybe what we need is something like this:
static DEFINE_SPINLOCK(io_lock);
static void modifyl(u32 new, u32 mask, void __iomem *reg)
{
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&io_lock, flags);
	val = readl(reg) & ~mask;
	val |= new | mask;
	writel(val, reg);
	spin_unlock_irqrestore(&io_lock, flags);
}

Quoted 2 lines

in order to provide arbitrated access to these kinds of multifunction registers in a safe, platform agnostic way.

I am fine with a generic modify function with a single lock. Most cases should be fine with a single lock even for non-related register accesses, e.g. watchdog will access TIMER_CTRL only once to enable itself. If you think you need a special lock because you have a lot of writes to shared registers, you can still have your own modify lock.

Sebastian

Linus Walleij

2013-06-18 15:02 UTC #118 lore raw

Re: [PATCH v4 02/10] pinctrl: mvebu: dove pinctrl driver

Quoted 15 lines · Russell King - ARM Linux

Maybe what we need is something like this:
static DEFINE_SPINLOCK(io_lock);
static void modifyl(u32 new, u32 mask, void __iomem *reg)
{
        unsigned long flags;
        u32 val;

        spin_lock_irqsave(&io_lock, flags);
        val = readl(reg) & ~mask;
        val |= new | mask;
        writel(val, reg);
        spin_unlock_irqrestore(&io_lock, flags);
}

Quoted 2 lines

in order to provide arbitrated access to these kinds of multifunction registers in a safe, platform agnostic way.

Nowadays I would do the above with regmap_update_bits().

Mutual exclusion for read-modify-write of individual bits in a register is one of those cases where doing a regmap over a memory-mapped register range makes a lot of sense. (drivers/mfd/syscon.c being a nice example)

Yours,
Linus Walleij

Russell King - ARM Linux

2013-06-18 15:11 UTC #119 lore raw

Re: [PATCH v4 02/10] pinctrl: mvebu: dove pinctrl driver

Quoted 6 lines · Linus Walleij

Nowadays I would do the above with regmap_update_bits().
Mutual exclusion for read-modify-write of individual bits in a register is one of those cases where doing a regmap over a memory-mapped register range makes a lot of sense. (drivers/mfd/syscon.c being a nice example)

So, for that solution we need to have some kind of global regmap per register or somesuch. Then you run into regmap needing a struct device - well, with a shared register, which struct device do you use, or do you have to invent one?

That sounds more heavy-weight than is really necessary.

Linus Walleij

2013-06-18 15:23 UTC #120 lore raw

Re: [PATCH v4 02/10] pinctrl: mvebu: dove pinctrl driver

Quoted 8 lines · Russell King - ARM Linux

Quoted 6 lines · Linus Walleij
Nowadays I would do the above with regmap_update_bits().
Mutual exclusion for read-modify-write of individual bits in a register is one of those cases where doing a regmap over a memory-mapped register range makes a lot of sense. (drivers/mfd/syscon.c being a nice example)

Quoted 4 lines

So, for that solution we need to have some kind of global regmap per register or somesuch. Then you run into regmap needing a struct device - well, with a shared register, which struct device do you use, or do you have to invent one?

Usually, like for syscon, you create an MFD hub which carry the regmap.

Quoted 1 line

That sounds more heavy-weight than is really necessary.

May be so, especially if there is just one register to protect. The usefulness of MM-regmap increase with the set of registers needing to be protected.

Yours,
Linus Walleij

Mark Brown

2013-06-18 18:33 UTC #121 lore raw

Re: [PATCH v4 02/10] pinctrl: mvebu: dove pinctrl driver

In reply to Russell King - ARM Linux

Quoted 8 lines · Russell King - ARM Linux

Quoted 6 lines · Linus Walleij
Nowadays I would do the above with regmap_update_bits().
Mutual exclusion for read-modify-write of individual bits in a register is one of those cases where doing a regmap over a memory-mapped register range makes a lot of sense. (drivers/mfd/syscon.c being a nice example)

Quoted 6 lines

So, for that solution we need to have some kind of global regmap per register or somesuch. Then you run into regmap needing a struct device - well, with a shared register, which struct device do you use, or do you have to invent one?
That sounds more heavy-weight than is really necessary.

Yes, regmap is far too heavyweight for a lot of these things - it shouldn't really go in performance critical at the CPU level paths, it's designed around things where I/O costs are considerable and worth avoiding.

I do think that this is a very good idea - with the I2C/SPI drivers I
was reviewing prior to regmap there were always just far too many simple
bugs with read/modify/write cycles so factoring out the code really
helped with review.
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Sebastian Hesselbarth

author maintainer

2012-09-13 15:41 UTC #122 lore raw

PATCH v4 3/10 pinctrl: mvebu: kirkwood pinctrl driver

In reply to Arnd Bergmann

This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core.

Signed-off-by Sebastian Hesselbarth <[email protected]>

---
v2:
- restructured pinctrl/Kconfig to hide pinctrl driver as it will be always selected by arch/arm/mach-mvebu/Kconfig
- use enum for kirkwood variants instead of defines

v3:
- moved variant specific data to DT match struct

v4:
- fix bogus v3 patch set

Cc Sebastian Hesselbarth <[email protected]>

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Jason Cooper <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 .../bindings/pinctrl/marvell,kirkwood-pinctrl.txt  |  279 ++++++++++++
 drivers/pinctrl/Kconfig                            |    4 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-kirkwood.c                 |  472 ++++++++++++++++++++
 4 files changed, 756 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-kirkwood.c

Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt new file +279 -0

new file mode 100644
index 0000000..361bccb
@@ -0,0 +1,279 @@
+* Marvell Kirkwood SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6180-pinctrl",
+              "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
+              "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
+
+This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Kirkwood 88f6180
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17         17       gpio, sdio(d3)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, mii(rxerr)
+mpp21         21       gpio, audio(spdifi)
+mpp22         22       gpio, audio(spdifo)
+mpp23         23       gpio, audio(rmclk)
+mpp24         24       gpio, audio(bclk)
+mpp25         25       gpio, audio(sdo)
+mpp26         26       gpio, audio(lrclk)
+mpp27         27       gpio, audio(mclk)
+mpp28         28       gpio, audio(sdi)
+mpp29         29       gpio, audio(extclk)
+
+* Marvell Kirkwood 88f6190
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0)
+mpp21         21       gpio, ge1(txd1), sata0(act)
+mpp22         22       gpio, ge1(txd2)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt)
+mpp24         24       gpio, ge1(rxd0)
+mpp25         25       gpio, ge1(rxd1)
+mpp26         26       gpio, ge1(rxd2)
+mpp27         27       gpio, ge1(rxd3)
+mpp28         28       gpio, ge1(col)
+mpp29         29       gpio, ge1(txclk)
+mpp30         30       gpio, ge1(rxclk)
+mpp31         31       gpio, ge1(rxclk)
+mpp32         32       gpio, ge1(txclko)
+mpp33         33       gpo, ge1(txclk)
+mpp34         34       gpio, ge1(txen)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr)
+
+* Marvell Kirkwood 88f6192
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33         33       gpo, ge1(txclk), tdm(drx)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+
+* Marvell Kirkwood 88f6281
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpio, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33         33       gpo, ge1(txclk), tdm(drx)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi)
+mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo)
+mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk)
+mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk)
+mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo)
+mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
+mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk)
+mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi)
+mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk)
+mpp45         45       gpio, ts(mp9), tdm(pclk)
+mpp46         46       gpio, ts(mp10), tdm(fs)
+mpp47         47       gpio, ts(mp11), tdm(drx)
+mpp48         48       gpio, ts(mp12), tdm(dtx)
+mpp49         49       gpio, ts(mp9), tdm(rx0ql), ptp(clk)
+
+* Marvell Kirkwood 88f6282
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync)
+mpp5          5        gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync)
+mpp6          6        sysrst(out), spi(mosi)
+mpp7          7        gpo, spi(cs), lcd(pwm)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
+                       mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
+                       sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), sata0(act)
+mpp12         12       gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda)
+mpp13         13       gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt),
+                       audio(spdifi), audio-1(sdi)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
+                       spi(cs)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act), lcd(extclk)
+mpp17         17       gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck)
+mpp18         18       gpo, nand(io0), pex(clkreq)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act), lcd(d0)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo), lcd(d1)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt), lcd(d2)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk), lcd(d3)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo),
+                       lcd(d4)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
+                       lcd(d5)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk),
+                       lcd(d6)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi),
+                       lcd(d7)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk),
+                       lcd(d8)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12)
+mpp33         33       gpo, ge1(txclk), tdm(drx), lcd(d13)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql),
+                       lcd(d15)
+mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda)
+mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck)
+mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18)
+mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19)
+mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20)
+mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
+mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22)
+mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23)
+mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk)
+mpp45         45       gpio, ts(mp9), tdm(pclk), lcd(e)
+mpp46         46       gpio, ts(mp10), tdm(fs), lcd(hsync)
+mpp47         47       gpio, ts(mp11), tdm(drx), lcd(vsync)
+mpp48         48       gpio, ts(mp12), tdm(dtx), lcd(d16)
+mpp49         49       gpo, tdm(rx0ql), pex(clkreq), lcd(d17)

drivers/pinctrl/Kconfig +4 -0

index f15eba4..31c0bba 100644
@@ -155,6 +155,10 @@ config PINCTRL_DOVE
 	bool
 	select PINCTRL_MVEBU
 
+config PINCTRL_KIRKWOOD
+	bool
+	select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index d1327df..3006294 100644
@@ -31,5 +31,6 @@ obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
+obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-kirkwood.c new file +472 -0

472 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Andrew Lunn

maintainer

2012-09-16 07:46 UTC #123 lore raw

Re: [PATCH v4 03/10] pinctrl: mvebu: kirkwood pinctrl driver

Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt line 11

Quoted 13 lines

+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt

Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt new file +11 -0

@@ -0,0 +1,279 @@
+* Marvell Kirkwood SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6180-pinctrl",
+              "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
+              "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
+
+This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628

Hi Sebastian

The current MPP code determines for itself what chip it is running on. It can then check if a pin configuration is valid for the current run time environment.

Here you are suggesting we have to put into the DT what chip we expect to be on.

What is the advantage of this, over getting the information from the device itself?

If i wanted to mass convert all existing kirkwood DT boards over to use pinctrl, im stuck at the very first step. I've no idea what chip they use, it was not relevant before.

Thanks
Andrew

Sebastian Hesselbarth

author maintainer

2012-09-16 09:09 UTC #124 lore raw

Re: [PATCH v4 03/10] pinctrl: mvebu: kirkwood pinctrl driver

Quoted 11 lines · Andrew Lunn

Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
Quoted 6 lines
Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt new file +6 -0
+Required properties:
+- compatible: "marvell,88f6180-pinctrl",
+              "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
+              "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
+
+This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628
The current MPP code determines for itself what chip it is running on. It can then check if a pin configuration is valid for the current run time environment.

Quoted 5 lines

Here you are suggesting we have to put into the DT what chip we expect to be on.
What is the advantage of this, over getting the information from the device itself?

Hi Andrew,

there is no advantage over determining the variant on run time except that it is statically and (normally) known at boot time. I understand that mass converting kirkwood to pinctrl would require to know all the different variants.

If there are no objections from the others, I agree to determine the variant from the existing kirkwood_id(). I was just unsure if it is ok to use platform-specific code with DT here.

Any ideas how to get kirkwood_id() linked into pinctrl-kirkwood with the get-rid-of-arch-includes policy?

Sebastian

Linus Walleij

2012-09-17 08:45 UTC #125 lore raw

Re: [PATCH v4 03/10] pinctrl: mvebu: kirkwood pinctrl driver

Quoted 8 lines · Sebastian Hesselbarth

Quoted 5 lines · Andrew Lunn
Here you are suggesting we have to put into the DT what chip we expect to be on.
What is the advantage of this, over getting the information from the device itself?

Quoted 6 lines

If there are no objections from the others, I agree to determine the variant from the existing kirkwood_id(). I was just unsure if it is ok to use platform-specific code with DT here.
Any ideas how to get kirkwood_id() linked into pinctrl-kirkwood with the get-rid-of-arch-includes policy?

You found the weak spot between two consolidation tracks.

Getting rid of a broadcast autodetect functions from say <mach/foo-id-probe.h> is nominally done by passing the data to the driver as platform data instead, and only using these functions in the mach-foo folder when populating platform data, and thus it can be made into a local header, say mach-foo/foo-id-probe.h

So the machine/arch code reads these registers to populate the platform data and device drivers only look at the platform data, which has some enum or bool indicating what hardware it's running on, cool.

But according to the other consolidation track, platform data should go into device tree bindings.

So the conclusion is that the DT must contain the data about the platform, so it's not auto-probed by the kernel. (I.e. the kernel reads no registers to figure out what hardware this is, that stuff comes from the device tree.)

DT purists will say that the boot loader should ask the chipset what it is with the same register writes and populate the DT accordingly, instead of loading a precompiled blob. Some may even ponder the crazy concept of amending the DT in the kernel at early boot.

But in practice someone will give up, encode the stuff in the static device tree and autoprobing of the platform goes out the window.

Yours,
Linus Walleij

Arnd Bergmann

2012-09-20 15:30 UTC #126 lore raw

Re: [PATCH v4 03/10] pinctrl: mvebu: kirkwood pinctrl driver

Quoted 28 lines · Linus Walleij

You found the weak spot between two consolidation tracks.
Getting rid of a broadcast autodetect functions from say <mach/foo-id-probe.h> is nominally done by passing the data to the driver as platform data instead, and only using these functions in the mach-foo folder when populating platform data, and thus it can be made into a local header, say mach-foo/foo-id-probe.h
So the machine/arch code reads these registers to populate the platform data and device drivers only look at the platform data, which has some enum or bool indicating what hardware it's running on, cool.
But according to the other consolidation track, platform data should go into device tree bindings.
So the conclusion is that the DT must contain the data about the platform, so it's not auto-probed by the kernel. (I.e. the kernel reads no registers to figure out what hardware this is, that stuff comes from the device tree.)
DT purists will say that the boot loader should ask the chipset what it is with the same register writes and populate the DT accordingly, instead of loading a precompiled blob. Some may even ponder the crazy concept of amending the DT in the kernel at early boot.

Quoted 3 lines

But in practice someone will give up, encode the stuff in the static device tree and autoprobing of the platform goes out the window.

In general, I would prefer probing hardware by asking the hardware itself rather than duplicating the information in the device tree. We do this whenever we can, e.g. on PCI or USB, but we cannot normally do the same on embedded buses like AHB, I2C or SPI, so we have to use the device tree to provide some or all of the information.

A corner case is the one where you have different versions of the same IP block (e.g. the pinctrl) and the kernel cannot find out which one it is by looking at registers inside it or on the parent bus, but only by looking at other hardware (CPU core revision, or PCI device ID of the root complex). We have a precedent of at91 doing this, but I don't like it too much because that still means having to change the driver again if you get a new SoC with the same IP block but a different version register, or if the block gets reused in something (e.g. by a different vendor) that doesn't even have the other block that's used for identification. To avoid that, I'd prefer using separate "compatible" values, at least if the hardware is already described in separate .dtsi files.

Arnd

Andrew Lunn

maintainer

2012-09-20 18:34 UTC #127 lore raw

Re: [PATCH v4 03/10] pinctrl: mvebu: kirkwood pinctrl driver

Quoted 39 lines · Arnd Bergmann

Quoted 28 lines · Linus Walleij
You found the weak spot between two consolidation tracks.
Getting rid of a broadcast autodetect functions from say <mach/foo-id-probe.h> is nominally done by passing the data to the driver as platform data instead, and only using these functions in the mach-foo folder when populating platform data, and thus it can be made into a local header, say mach-foo/foo-id-probe.h
So the machine/arch code reads these registers to populate the platform data and device drivers only look at the platform data, which has some enum or bool indicating what hardware it's running on, cool.
But according to the other consolidation track, platform data should go into device tree bindings.
So the conclusion is that the DT must contain the data about the platform, so it's not auto-probed by the kernel. (I.e. the kernel reads no registers to figure out what hardware this is, that stuff comes from the device tree.)
DT purists will say that the boot loader should ask the chipset what it is with the same register writes and populate the DT accordingly, instead of loading a precompiled blob. Some may even ponder the crazy concept of amending the DT in the kernel at early boot.
Quoted 3 lines
But in practice someone will give up, encode the stuff in the static device tree and autoprobing of the platform goes out the window.
In general, I would prefer probing hardware by asking the hardware itself rather than duplicating the information in the device tree. We do this whenever we can, e.g. on PCI or USB, but we cannot normally do the same on embedded buses like AHB, I2C or SPI, so we have to use the device tree to provide some or all of the information.

Quoted 5 lines

A corner case is the one where you have different versions of the same IP block (e.g. the pinctrl) and the kernel cannot find out which one it is by looking at registers inside it or on the parent bus, but only by looking at other hardware (CPU core revision, or PCI device ID of the root complex).

Hi Arnd

Even if we did look at the PCIe device IDs, we would still have one odd-ball case to deal with. We have had an initial port to a Marvell 98DX4122 contributed. This chip is a Marvell Ethernet chip, with an embedded Kirkwood SoC. The SoC is missing SATA, RTC, SDIO, I2S, TDM, and TS which other kirkwoods have. So it will need a different pinctrl table. However, looking at the PCIe device ID, it identifies itself as a normal MV88F6281. So we would have to deal with this in DT with a different compatibility string.

Andrew

Linus Walleij

2012-09-20 19:28 UTC #128 lore raw

Re: [PATCH v4 03/10] pinctrl: mvebu: kirkwood pinctrl driver

Quoted 5 lines · Arnd Bergmann

A corner case is the one where you have different versions of the same IP block (e.g. the pinctrl) and the kernel cannot find out which one it is by looking at registers inside it or on the parent bus, but only by looking at other hardware (CPU core revision, or PCI device ID of the root complex).

So this is the case I'm thinking of. We have e.g. differens small flags through platform data depending on cpu_is_ux* in the ux500.

Currently we modify platform data in the board files, just as we switch some cache handling etc as we know this or that ASIC has different sized cache.

Quoted 4 lines

We have a precedent of at91 doing this, but I don't
like it too much because that still means having to change the driver again if you get a new SoC with the same IP block but a different version register,

I don't like that either.

Quoted 3 lines

To avoid that, I'd prefer using separate "compatible" values, at least if the hardware is already described in separate .dtsi files.

So what I'm after is whether in this case statically encoding this onto the .dtsi files is the right thing to do, or whether the boot loader or kernel should runtime-modify the device tree, patching in the ASIC-specific info, just like device tree files can override properties from include files.

Or if this is a bad idea.

Nobody is doing that right now AFAICT, but it is surely possible....

Yours,
Linus Walleij

Thomas Petazzoni

2012-09-20 19:36 UTC #129 lore raw

Re: [PATCH v4 03/10] pinctrl: mvebu: kirkwood pinctrl driver

Dear Linus Walleij,

Quoted 9 lines · Linus Walleij

So what I'm after is whether in this case statically encoding this onto the .dtsi files is the right thing to do, or whether the boot loader or kernel should runtime-modify the device tree, patching in the ASIC-specific info, just like device tree files can override properties from include files.
Or if this is a bad idea.
Nobody is doing that right now AFAICT, but it is surely possible....

If I understand correctly, we would like drivers to be able to read some common "system" registers to figure out which SoC variant we are running on. Such feature should normally be provided by code in arch/arm/mach-*/ and called by drivers, but we are trying to eliminate all dependencies of driver code on architecture code, correct?

So, wouldn't we need a small, architecture-independent, infrastructure, through which architecture-specific code could "register" at boot time which SoC we are running on, and drivers could query this information from the common infrastructure?

Of course, the major problem is to figure out what is the good representation for this SoC identifier. Do we need a big list of SoCs like we had machine IDs? A simple string? Or maybe there is just no good way, and the whole idea is moot.

Best regards,

Thomas

Signature · 4 lines

Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Andrew Lunn

maintainer

2012-09-20 19:51 UTC #130 lore raw

Re: [PATCH v4 03/10] pinctrl: mvebu: kirkwood pinctrl driver

Quoted 9 lines

So, wouldn't we need a small, architecture-independent, infrastructure, through which architecture-specific code could "register" at boot time which SoC we are running on, and drivers could query this information from the common infrastructure?
Of course, the major problem is to figure out what is the good representation for this SoC identifier. Do we need a big list of SoCs like we had machine IDs? A simple string? Or maybe there is just no good way, and the whole idea is moot.

I did think about stuffing it inside the cpuinfo structures:

$ cat /proc/cpuinfo 
Processor       : Feroceon 88FR131 rev 1 (v5l)
BogoMIPS        : 1196.85
Features        : swp half thumb fastmult edsp 
CPU implementer : 0x56
CPU architecture: 5TE
CPU variant     : 0x2
CPU part        : 0x131
CPU revision    : 1

Hardware : BUBBA3 Kirkwood based miniserver
Revision : 0000
Serial : 0000000000000000

I could imaging a
SoC : MV88F6281

It would probably need a bit of string parsing by any consumer, which is not so good.

Andrew

Ben Dooks

2012-09-21 10:56 UTC #131 lore raw

Re: [PATCH v4 03/10] pinctrl: mvebu: kirkwood pinctrl driver

Quoted 25 lines · Thomas Petazzoni

Dear Linus Walleij,
Quoted 9 lines · Linus Walleij
So what I'm after is whether in this case statically encoding this onto the .dtsi files is the right thing to do, or whether the boot loader or kernel should runtime-modify the device tree, patching in the ASIC-specific info, just like device tree files can override properties from include files.
Or if this is a bad idea.
Nobody is doing that right now AFAICT, but it is surely possible....
If I understand correctly, we would like drivers to be able to read some common "system" registers to figure out which SoC variant we are running on. Such feature should normally be provided by code in arch/arm/mach-*/ and called by drivers, but we are trying to eliminate all dependencies of driver code on architecture code, correct?
So, wouldn't we need a small, architecture-independent, infrastructure, through which architecture-specific code could "register" at boot time which SoC we are running on, and drivers could query this information from the common infrastructure?

Quoted 4 lines

Of course, the major problem is to figure out what is the good representation for this SoC identifier. Do we need a big list of SoCs like we had machine IDs? A simple string? Or maybe there is just no good way, and the whole idea is moot.

I think this is a bad idea, it means you can't try and re-use an older kernel on an newer SoC design which may be broadly compatible without changing the kernel source to add these flag checks.

I also don't like information hidden away that the user cannot see. Having the device specifically named allows us to see from sysfs exactly what we are dealing with.

Signature · 2 lines

Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

Linus Walleij

2012-09-21 18:14 UTC #132 lore raw

Re: [PATCH v4 03/10] pinctrl: mvebu: kirkwood pinctrl driver

Quoted 5 lines · Thomas Petazzoni

If I understand correctly, we would like drivers to be able to read some common "system" registers to figure out which SoC variant we are running on. Such feature should normally be provided by code in arch/arm/mach-*/ and called by drivers, but we are trying to eliminate all dependencies of driver code on architecture code, correct?

So what I think is that any such mechanism would defy the idea with device tree providing all platform configuration, including the ASIC/SoC variant.

The only not-so-unelegant idea I have is for the machine to go in and fiddle with the device tree, e.g. add some info into the tree somewhere stating into the nodes which ASIC variant it is. Maybe even modify the compatible value at runtime.

But it somehow feels like cracking an egg with a sledgehammer.

I think we need to meditate on this.

Yours,
Linus Walleij

Jason Cooper

2012-09-16 12:40 UTC #133 lore raw

Re: [PATCH v4 03/10] pinctrl: mvebu: kirkwood pinctrl driver

In reply to Andrew Lunn

Quoted 20 lines · Andrew Lunn

Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt line 11
Quoted 13 lines
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt new file +11 -0
@@ -0,0 +1,279 @@
+* Marvell Kirkwood SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6180-pinctrl",
+              "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
+              "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
+
+This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628
Hi Sebastian
The current MPP code determines for itself what chip it is running on. It can then check if a pin configuration is valid for the current run time environment.

Quoted 5 lines

Here you are suggesting we have to put into the DT what chip we expect to be on.
What is the advantage of this, over getting the information from the device itself?

The DT should describe the hardware as accurately as possible. We can't always assume Linux will be the only thing the DT is handed off to.

Quoted 3 lines

If i wanted to mass convert all existing kirkwood DT boards over to use pinctrl, im stuck at the very first step. I've no idea what chip they use, it was not relevant before.

Let's try to do the DT correctly, and create a migration path for kirkwood to work first, then migrate to using the DT fully.

thx,

Jason.

Nicolas Pitre

2012-09-17 01:55 UTC #134 lore raw

Re: [PATCH v4 03/10] pinctrl: mvebu: kirkwood pinctrl driver

Quoted 30 lines · Jason Cooper

Quoted 20 lines · Andrew Lunn
Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt line 11
Quoted 13 lines
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt new file +11 -0
@@ -0,0 +1,279 @@
+* Marvell Kirkwood SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6180-pinctrl",
+              "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
+              "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
+
+This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628
Hi Sebastian
The current MPP code determines for itself what chip it is running on. It can then check if a pin configuration is valid for the current run time environment.
Quoted 5 lines
Here you are suggesting we have to put into the DT what chip we expect to be on.
What is the advantage of this, over getting the information from the device itself?
The DT should describe the hardware as accurately as possible. We can't always assume Linux will be the only thing the DT is handed off to.

Quoted 6 lines

Quoted 3 lines
If i wanted to mass convert all existing kirkwood DT boards over to use pinctrl, im stuck at the very first step. I've no idea what chip they use, it was not relevant before.
Let's try to do the DT correctly, and create a migration path for kirkwood to work first, then migrate to using the DT fully.

Beware beware.

The DT should of course describe the hardware as accurately as possible. That doesn't necessarily mean it should describe the hardware as _extensively_ as possible.

And that doesn't mean that all the information found in the DT has to be consumed by the kernel either.

Any information that can be *probed* at run time has no benefit being stuffed in a DT. That's true whether it is Linux or another operating system. The more that can be probed at run time the better.

Nicolas

Sebastian Hesselbarth

author maintainer

2012-09-17 06:36 UTC #135 lore raw

Re: [PATCH v4 03/10] pinctrl: mvebu: kirkwood pinctrl driver

Quoted 29 lines · Nicolas Pitre

Quoted 19 lines · Jason Cooper
Quoted 9 lines · Andrew Lunn
Quoted 9 lines
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt new file +7 -0
@@ -0,0 +1,279 @@
+* Marvell Kirkwood SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6180-pinctrl",
Quoted 8 lines
Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
Quoted 4 lines
Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt new file +4 -0
+              "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
+              "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
+
+This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628
...
If i wanted to mass convert all existing kirkwood DT boards over to use pinctrl, im stuck at the very first step. I've no idea what chip they use, it was not relevant before.
Quoted 2 lines
Let's try to do the DT correctly, and create a migration path for kirkwood to work first, then migrate to using the DT fully.
Beware beware.
The DT should of course describe the hardware as accurately as possible. That doesn't necessarily mean it should describe the hardware as _extensively_ as possible.

Quoted 6 lines

And that doesn't mean that all the information found in the DT has to be consumed by the kernel either.
Any information that can be *probed* at run time has no benefit being stuffed in a DT. That's true whether it is Linux or another operating system. The more that can be probed at run time the better.

I had a closer look at how kirkwood probes its id. I mentionend kirkwood_id() earlier but in fact it is kirkwood_pcie_id(). I assume pcie registers are shut down with pcie clk gated? That would require to have pcie running at least at boot-time on all boards.

While it is still possible to grab the id and power down pcie later, I still think that using five different compatible strings is better here. Of course, there is some effort to obtain the kirkwood SoC variant for all boards.

Sebastian

Andrew Lunn

maintainer

2012-09-17 08:32 UTC #136 lore raw

Re: [PATCH v4 03/10] pinctrl: mvebu: kirkwood pinctrl driver

Quoted 8 lines

I had a closer look at how kirkwood probes its id. I mentionend kirkwood_id() earlier but in fact it is kirkwood_pcie_id(). I assume pcie registers are shut down with pcie clk gated? That would require to have pcie running at least at boot-time on all boards.
While it is still possible to grab the id and power down pcie later, I still think that using five different compatible strings is better here. Of course, there is some effort to obtain the kirkwood SoC variant for all boards.

Hi Sebastian

I did the monkey work last night for converting all existing kirkwood DT boards over to pinctrl. I noticed that in all the DT descriptions, they all declare themselves as 88f6281. This is probably cut/paste from the first board we ever had. For these boards, i doubt it will be a problem, finding out what chip is really used, as there are active maintainers. The problem comes with old style devices which we want to convert. But if we do the monkey work for older boards, we are going to have to find testers anyway and they can tell us what SoC is used.

Having said that, not probing the hardware, having it configurable is a source of errors. We already probe the hardware in order to display:

Kirkwood: MV88F6282-Rev-A0, TCLK=200000000.

so we just need to cache this and make it available to anybody who wants it.

I'm surprised we don't have the infrastructure of this already. We have info about the CPU, e.g.

cat /proc/cpuinfo
Processor : Feroceon 88FR131 rev 1 (v5l)
BogoMIPS : 1587.60
Features : swp half thumb fastmult edsp
CPU implementer : 0x56
CPU architecture: 5TE
CPU variant : 0x2
CPU part : 0x131
CPU revision : 1

Hardware : Marvell Kirkwood (Flattened Device Tree)
Revision : 0000
Serial : 0000000000000000

but don't seem to have anything about the SoC the CPU is embedded in.

AT91 has at91_get_soc_type(struct at91_socinfo *c) which is what we would need for Kirkwood. However, interestingly, its never used outside of arch/arm/mach-at91/setup.c!

davinci has a global structure davinci_soc_info which gpio/gpio-davinci.c uses.

So we would not be the only architecture making such information available. We just need to make sure we do it such that its multi-arch kernel compatible.

Andrew

Andrew Lunn

maintainer Tested-by on v4 3/10

2012-09-18 18:59 UTC #137 lore raw

Re: [PATCH v4 03/10] pinctrl: mvebu: kirkwood pinctrl driver

Quoted 11 lines · Sebastian Hesselbarth

This patch adds a SoC specific pinctrl driver for Marvell Kirkwood SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core.
Signed-off-by Sebastian Hesselbarth <[email protected]>
---
v2:
- restructured pinctrl/Kconfig to hide pinctrl driver as it will be always selected by arch/arm/mach-mvebu/Kconfig
- use enum for kirkwood variants instead of defines

Quoted 5 lines

v3:
- moved variant specific data to DT match struct
v4:
- fix bogus v3 patch set

Since Linus Walleij thinks that autoprobing is not going to happen,

Tested-by Andrew Lunn <[email protected]>

However, i still think it would be nice to have auto probing.

Andrew

Quoted 818 lines

Cc Sebastian Hesselbarth <[email protected]>

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Jason Cooper <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 .../bindings/pinctrl/marvell,kirkwood-pinctrl.txt  |  279 ++++++++++++
 drivers/pinctrl/Kconfig                            |    4 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-kirkwood.c                 |  472 ++++++++++++++++++++
 4 files changed, 756 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-kirkwood.c

Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt new file +279 -0

new file mode 100644
index 0000000..361bccb
@@ -0,0 +1,279 @@
+* Marvell Kirkwood SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6180-pinctrl",
+              "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
+              "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
+
+This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Kirkwood 88f6180
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17         17       gpio, sdio(d3)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, mii(rxerr)
+mpp21         21       gpio, audio(spdifi)
+mpp22         22       gpio, audio(spdifo)
+mpp23         23       gpio, audio(rmclk)
+mpp24         24       gpio, audio(bclk)
+mpp25         25       gpio, audio(sdo)
+mpp26         26       gpio, audio(lrclk)
+mpp27         27       gpio, audio(mclk)
+mpp28         28       gpio, audio(sdi)
+mpp29         29       gpio, audio(extclk)
+
+* Marvell Kirkwood 88f6190
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0)
+mpp21         21       gpio, ge1(txd1), sata0(act)
+mpp22         22       gpio, ge1(txd2)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt)
+mpp24         24       gpio, ge1(rxd0)
+mpp25         25       gpio, ge1(rxd1)
+mpp26         26       gpio, ge1(rxd2)
+mpp27         27       gpio, ge1(rxd3)
+mpp28         28       gpio, ge1(col)
+mpp29         29       gpio, ge1(txclk)
+mpp30         30       gpio, ge1(rxclk)
+mpp31         31       gpio, ge1(rxclk)
+mpp32         32       gpio, ge1(txclko)
+mpp33         33       gpo, ge1(txclk)
+mpp34         34       gpio, ge1(txen)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr)
+
+* Marvell Kirkwood 88f6192
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33         33       gpo, ge1(txclk), tdm(drx)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+
+* Marvell Kirkwood 88f6281
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpio, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33         33       gpo, ge1(txclk), tdm(drx)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi)
+mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo)
+mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk)
+mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk)
+mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo)
+mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
+mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk)
+mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi)
+mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk)
+mpp45         45       gpio, ts(mp9), tdm(pclk)
+mpp46         46       gpio, ts(mp10), tdm(fs)
+mpp47         47       gpio, ts(mp11), tdm(drx)
+mpp48         48       gpio, ts(mp12), tdm(dtx)
+mpp49         49       gpio, ts(mp9), tdm(rx0ql), ptp(clk)
+
+* Marvell Kirkwood 88f6282
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync)
+mpp5          5        gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync)
+mpp6          6        sysrst(out), spi(mosi)
+mpp7          7        gpo, spi(cs), lcd(pwm)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
+                       mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
+                       sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), sata0(act)
+mpp12         12       gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda)
+mpp13         13       gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt),
+                       audio(spdifi), audio-1(sdi)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
+                       spi(cs)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act), lcd(extclk)
+mpp17         17       gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck)
+mpp18         18       gpo, nand(io0), pex(clkreq)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act), lcd(d0)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo), lcd(d1)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt), lcd(d2)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk), lcd(d3)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo),
+                       lcd(d4)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
+                       lcd(d5)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk),
+                       lcd(d6)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi),
+                       lcd(d7)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk),
+                       lcd(d8)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12)
+mpp33         33       gpo, ge1(txclk), tdm(drx), lcd(d13)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql),
+                       lcd(d15)
+mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda)
+mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck)
+mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18)
+mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19)
+mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20)
+mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
+mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22)
+mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23)
+mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk)
+mpp45         45       gpio, ts(mp9), tdm(pclk), lcd(e)
+mpp46         46       gpio, ts(mp10), tdm(fs), lcd(hsync)
+mpp47         47       gpio, ts(mp11), tdm(drx), lcd(vsync)
+mpp48         48       gpio, ts(mp12), tdm(dtx), lcd(d16)
+mpp49         49       gpo, tdm(rx0ql), pex(clkreq), lcd(d17)

drivers/pinctrl/Kconfig +4 -0

index f15eba4..31c0bba 100644
@@ -155,6 +155,10 @@ config PINCTRL_DOVE
 	bool
 	select PINCTRL_MVEBU
 
+config PINCTRL_KIRKWOOD
+	bool
+	select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index d1327df..3006294 100644
@@ -31,5 +31,6 @@ obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
+obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-kirkwood.c new file +472 -0

new file mode 100644
index 0000000..9a74ef6
@@ -0,0 +1,472 @@
+/*
+ * Marvell Kirkwood pinctrl driver based on mvebu pinctrl core
+ *
+ * Author: Sebastian Hesselbarth <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+#define V(f6180, f6190, f6192, f6281, f6282)		\
+	((f6180 << 0) | (f6190 << 1) | (f6192 << 2) |	\
+	 (f6281 << 3) | (f6282 << 4))
+
+enum kirkwood_variant {
+	VARIANT_MV88F6180 = V(1, 0, 0, 0, 0),
+	VARIANT_MV88F6190 = V(0, 1, 0, 0, 0),
+	VARIANT_MV88F6192 = V(0, 0, 1, 0, 0),
+	VARIANT_MV88F6281 = V(0, 0, 0, 1, 0),
+	VARIANT_MV88F6282 = V(0, 0, 0, 0, 1),
+};
+
+static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = {
+	MPP_MODE(0,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io2",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "spi", "cs",       V(1, 1, 1, 1, 1))),
+	MPP_MODE(1,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io3",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "spi", "mosi",     V(1, 1, 1, 1, 1))),
+	MPP_MODE(2,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io4",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "spi", "sck",      V(1, 1, 1, 1, 1))),
+	MPP_MODE(3,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io5",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "spi", "miso",     V(1, 1, 1, 1, 1))),
+	MPP_MODE(4,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io6",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "uart0", "rxd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "hsync",    V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xd, "ptp", "clk",      V(1, 1, 1, 1, 0))),
+	MPP_MODE(5,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io7",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "uart0", "txd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "ptp", "trig",     V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "vsync",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(6,
+		MPP_VAR_FUNCTION(0x0, "sysrst", "out",   V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "spi", "mosi",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "ptp", "trig",     V(1, 1, 1, 1, 0))),
+	MPP_MODE(7,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "pex", "rsto",     V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0x2, "spi", "cs",       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ptp", "trig",     V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "pwm",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(8,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "twsi0", "sda",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "uart0", "rts",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart1", "rts",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "mii-1", "rxerr",  V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata1", "prsnt",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xc, "ptp", "clk",      V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0xd, "mii", "col",      V(1, 1, 1, 1, 1))),
+	MPP_MODE(9,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "twsi0", "sck",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "uart0", "cts",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart1", "cts",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata0", "prsnt",  V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xc, "ptp", "evreq",    V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0xd, "mii", "crs",      V(1, 1, 1, 1, 1))),
+	MPP_MODE(10,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "spi", "sck",      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0X3, "uart0", "txd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xc, "ptp", "trig",     V(1, 1, 1, 1, 0))),
+	MPP_MODE(11,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "spi", "miso",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart0", "rxd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "ptp-1", "evreq",  V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0xc, "ptp-2", "trig",   V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0xd, "ptp", "clk",      V(1, 1, 1, 1, 0)),
+		MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1))),
+	MPP_MODE(12,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 0, 1)),
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 0)),
+		MPP_VAR_FUNCTION(0x1, "sdio", "clk",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xa, "audio", "spdifo", V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xb, "spi", "mosi",     V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xd, "twsi1", "sda",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(13,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "sdio", "cmd",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart1", "txd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xa, "audio", "rmclk",  V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "pwm",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(14,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "sdio", "d0",      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart1", "rxd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "sata1", "prsnt",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xa, "audio", "spdifi", V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xb, "audio-1", "sdi",  V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xd, "mii", "col",      V(1, 1, 1, 1, 1))),
+	MPP_MODE(15,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "sdio", "d1",      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "uart0", "rts",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart1", "txd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "sata0", "act",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "spi", "cs",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(16,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "sdio", "d2",      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "uart0", "cts",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "uart1", "rxd",    V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "sata1", "act",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "extclk",   V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xd, "mii", "crs",      V(1, 1, 1, 1, 1))),
+	MPP_MODE(17,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "sdio", "d3",      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "sata0", "prsnt",  V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xa, "sata1", "act",    V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xd, "twsi1", "sck",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(18,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io0",     V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "pex", "clkreq",   V(0, 0, 0, 0, 1))),
+	MPP_MODE(19,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "nand", "io1",     V(1, 1, 1, 1, 1))),
+	MPP_MODE(20,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp0",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txd0",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d0",       V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xc, "mii", "rxerr",    V(1, 0, 0, 0, 0))),
+	MPP_MODE(21,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp1",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txd1",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d1",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(22,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp2",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txd2",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "rmclk",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata1", "prsnt",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d2",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(23,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp3",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txd3",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "rmclk",  V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "bclk",   V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata0", "prsnt",  V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d3",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(24,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp4",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxd0",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "bclk",   V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "sdo",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d4",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(25,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp5",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxd1",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "sdo",    V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "lrclk",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d5",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(26,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp6",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxd2",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "lrclk",  V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "mclk",   V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d6",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(27,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp7",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxd3",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "mclk",   V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "sdi",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d7",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(28,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp8",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "int",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "col",      V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "sdi",    V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d8",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(29,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp9",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "rst",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txclk",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 0, 0)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d9",       V(0, 0, 0, 0, 1))),
+	MPP_MODE(30,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp10",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "pclk",     V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxctl",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d10",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(31,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp11",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "fs",       V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxclk",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d11",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(32,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp12",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "drx",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txclko",   V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d12",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(33,
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "dtx",      V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txctl",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d13",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(34,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1",  V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "txen",     V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d14",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(35,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql",    V(0, 0, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x3, "ge1", "rxerr",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d15",      V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xc, "mii", "rxerr",    V(0, 1, 1, 1, 1))),
+	MPP_MODE(36,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp0",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1",  V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "twsi1", "sda",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(37,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp1",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql",    V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "twsi1", "sck",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(38,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp2",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql",    V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "rmclk",  V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d18",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(39,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp3",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0",  V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "bclk",   V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d19",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(40,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp4",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck",  V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "sdo",    V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d20",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(41,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp5",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "lrclk",  V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d21",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(42,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp6",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "mclk",   V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d22",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(43,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp7",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "int",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "sdi",    V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d23",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(44,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp8",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "rst",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "clk",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(45,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp9",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "pclk",     V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "e",        V(0, 0, 0, 0, 1))),
+	MPP_MODE(46,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp10",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "fs",       V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "hsync",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(47,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp11",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "drx",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "vsync",    V(0, 0, 0, 0, 1))),
+	MPP_MODE(48,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp12",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "dtx",      V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d16",      V(0, 0, 0, 0, 1))),
+	MPP_MODE(49,
+		MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 0)),
+		MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0x1, "ts", "mp9",       V(0, 0, 0, 1, 0)),
+		MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql",    V(0, 0, 0, 1, 1)),
+		MPP_VAR_FUNCTION(0x5, "ptp", "clk",      V(0, 0, 0, 1, 0)),
+		MPP_VAR_FUNCTION(0xa, "pex", "clkreq",   V(0, 0, 0, 0, 1)),
+		MPP_VAR_FUNCTION(0xb, "lcd", "d17",      V(0, 0, 0, 0, 1))),
+};
+
+static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = {
+	MPP_REG_CTRL(0, 29),
+};
+
+static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0, 0, 0, 30),
+};
+
+static struct mvebu_mpp_ctrl mv88f619x_mpp_controls[] = {
+	MPP_REG_CTRL(0, 35),
+};
+
+static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,  0,  0, 32),
+	MPP_GPIO_RANGE(1, 32, 32,  4),
+};
+
+static struct mvebu_mpp_ctrl mv88f628x_mpp_controls[] = {
+	MPP_REG_CTRL(0, 49),
+};
+
+static struct pinctrl_gpio_range mv88f628x_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,  0,  0, 32),
+	MPP_GPIO_RANGE(1, 32, 32, 18),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f6180_info = {
+	.variant = VARIANT_MV88F6180,
+	.controls = mv88f6180_mpp_controls,
+	.ncontrols = ARRAY_SIZE(mv88f6180_mpp_controls),
+	.modes = mv88f6xxx_mpp_modes,
+	.nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
+	.gpioranges = mv88f6180_gpio_ranges,
+	.ngpioranges = ARRAY_SIZE(mv88f6180_gpio_ranges),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f6190_info = {
+	.variant = VARIANT_MV88F6190,
+	.controls = mv88f619x_mpp_controls,
+	.ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls),
+	.modes = mv88f6xxx_mpp_modes,
+	.nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
+	.gpioranges = mv88f619x_gpio_ranges,
+	.ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f6192_info = {
+	.variant = VARIANT_MV88F6192,
+	.controls = mv88f619x_mpp_controls,
+	.ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls),
+	.modes = mv88f6xxx_mpp_modes,
+	.nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
+	.gpioranges = mv88f619x_gpio_ranges,
+	.ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f6281_info = {
+	.variant = VARIANT_MV88F6281,
+	.controls = mv88f628x_mpp_controls,
+	.ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls),
+	.modes = mv88f6xxx_mpp_modes,
+	.nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
+	.gpioranges = mv88f628x_gpio_ranges,
+	.ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f6282_info = {
+	.variant = VARIANT_MV88F6282,
+	.controls = mv88f628x_mpp_controls,
+	.ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls),
+	.modes = mv88f6xxx_mpp_modes,
+	.nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
+	.gpioranges = mv88f628x_gpio_ranges,
+	.ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges),
+};
+
+static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata = {
+	{ .compatible = "marvell,88f6180-pinctrl", .data = &mv88f6180_info },
+	{ .compatible = "marvell,88f6190-pinctrl", .data = &mv88f6190_info },
+	{ .compatible = "marvell,88f6192-pinctrl", .data = &mv88f6192_info },
+	{ .compatible = "marvell,88f6281-pinctrl", .data = &mv88f6281_info },
+	{ .compatible = "marvell,88f6282-pinctrl", .data = &mv88f6282_info },
+	{ }
+};
+
+static int __devinit kirkwood_pinctrl_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match =
+		of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
+	pdev->dev.platform_data = match->data;
+	return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit kirkwood_pinctrl_remove(struct platform_device *pdev)
+{
+	return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver kirkwood_pinctrl_driver = {
+	.driver = {
+		.name = "kirkwood-pinctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(kirkwood_pinctrl_of_match),
+	},
+	.probe = kirkwood_pinctrl_probe,
+	.remove = __devexit_p(kirkwood_pinctrl_remove),
+};
+
+module_platform_driver(kirkwood_pinctrl_driver);
+
+MODULE_AUTHOR("Sebastian Hesselbarth <[email protected]>");
+MODULE_DESCRIPTION("Marvell Kirkwood pinctrl driver");
+MODULE_LICENSE("GPL v2");

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-09-13 15:41 UTC #138 lore raw

PATCH v4 4/10 pinctrl: mvebu: add pinctrl driver for Armada 370

From: Thomas Petazzoni <[email protected]>

This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs.

---
v2:
- removed arch/arm/*/Kconfig changes and added note about variant = 0

Cc Sebastian Hesselbarth <[email protected]>

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Jason Cooper <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 .../pinctrl/marvell,armada-370-pinctrl.txt         |   95 +++++
 drivers/pinctrl/Kconfig                            |    4 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-armada-370.c               |  421 ++++++++++++++++++++
 4 files changed, 521 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-armada-370.c

Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt new file +95 -0

new file mode 100644
index 0000000..01ef408
@@ -0,0 +1,95 @@
+* Marvell Armada 370 SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6710-pinctrl"
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, uart0(rxd)
+mpp1          1        gpo, uart0(txd)
+mpp2          2        gpio, i2c0(sck), uart0(txd)
+mpp3          3        gpio, i2c0(sda), uart0(rxd)
+mpp4          4        gpio, cpu_pd(vdd)
+mpp5          5        gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
+mpp6          6        gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
+mpp7          7        gpo, ge0(txd1), tdm(tdx), audio(lrclk)
+mpp8          8        gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
+mpp9          9        gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
+mpp10         10       gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
+mpp11         11       gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
+                       sata1(prsnt), spi1(cs1)
+mpp12         12       gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
+                       audio(spdifi)
+mpp13         13       gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
+                       audio(rmclk)
+mpp14         14       gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
+                       spi0(cs2)
+mpp15         15       gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
+                       spi0(cs3)
+mpp16         16       gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
+mpp17         17       gpo, ge(mdc)
+mpp18         18       gpio, ge(mdio)
+mpp19         19       gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
+mpp20         20       gpo, ge0(txd4), ge1(txd0)
+mpp21         21       gpo, ge0(txd5), ge1(txd1), uart1(txd)
+mpp22         22       gpo, ge0(txd6), ge1(txd2), uart0(rts)
+mpp23         23       gpo, ge0(txd7), ge1(txd3), spi1(mosi)
+mpp24         24       gpio, ge0(col), ge1(txctl), spi1(cs0)
+mpp25         25       gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
+mpp26         26       gpio, ge0(crs), ge1(rxd1), spi1(miso)
+mpp27         27       gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
+mpp28         28       gpio, ge0(rxd5), ge1(rxd3)
+mpp29         29       gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
+mpp30         30       gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
+mpp31         31       gpio, tclk, ge0(txerr)
+mpp32         32       gpio, spi0(cs0)
+mpp33         33       gpio, dev(bootcs), spi0(cs0)
+mpp34         34       gpo, dev(wen0), spi0(mosi)
+mpp35         35       gpo, dev(oen), spi0(sck)
+mpp36         36       gpo, dev(a1), spi0(miso)
+mpp37         37       gpo, dev(a0), sata0(prsnt)
+mpp38         38       gpio, dev(ready), uart1(cts), uart0(cts)
+mpp39         39       gpo, dev(ad0), audio(spdifo)
+mpp40         40       gpio, dev(ad1), uart1(rts), uart0(rts)
+mpp41         41       gpio, dev(ad2), uart1(rxd)
+mpp42         42       gpo, dev(ad3), uart1(txd)
+mpp43         43       gpo, dev(ad4), audio(bclk)
+mpp44         44       gpo, dev(ad5), audio(mclk)
+mpp45         45       gpo, dev(ad6), audio(lrclk)
+mpp46         46       gpo, dev(ad7), audio(sdo)
+mpp47         47       gpo, dev(ad8), sd0(clk), audio(spdifo)
+mpp48         48       gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
+                       spi0(cs1)
+mpp49         49       gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
+                       audio(spdifi)
+mpp50         50       gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
+                       audio(rmclk)
+mpp51         51       gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
+mpp52         52       gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
+mpp53         53       gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
+                       pcie(clkreq1)
+mpp54         54       gpo, dev(ad15), tdm(dtx)
+mpp55         55       gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
+                       sata0(prsnt)
+mpp56         56       gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
+                       pcie(clkreq0), spi1(cs1)
+mpp57         57       gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
+                       audio(sdo)
+mpp58         58       gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
+                       uart0(rts)
+mpp59         59       gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
+mpp60         60       gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
+                       audio(sdi)
+mpp61         61       gpo, dev(wen1), uart1(txd), audio(rclk)
+mpp62         62       gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
+                       audio(mclk), uart0(cts)
+mpp63         63       gpo, spi0(sck), tclk
+mpp64         64       gpio, spi0(miso), spi0-1(cs1)
+mpp65         65       gpio, spi0(mosi), spi0-1(cs2)

drivers/pinctrl/Kconfig +4 -0

index 31c0bba..e16b8b0 100644
@@ -159,6 +159,10 @@ config PINCTRL_KIRKWOOD
 	bool
 	select PINCTRL_MVEBU
 
+config PINCTRL_ARMADA_370
+	bool
+	select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index 3006294..e6d6667 100644
@@ -32,5 +32,6 @@ obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
 obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
+obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-armada-370.c new file +421 -0

421 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-09-13 15:41 UTC #139 lore raw

PATCH v4 5/10 pinctrl: mvebu: add pinctrl driver for Armada XP

From: Thomas Petazzoni <[email protected]>

This pinctrl driver is not a full-blown pinctrl driver from scratch:
it relies on the common pinctrl-mvebu driver, which is used for all Marvell EBU SoCs.

---
v2:
- replaced variant with enum and used bitops.h

Cc Sebastian Hesselbarth <[email protected]>

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Jason Cooper <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt |  100 +++++
 drivers/pinctrl/Kconfig                            |    4 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-armada-xp.c                |  468 ++++++++++++++++++++
 4 files changed, 573 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
 create mode 100644 drivers/pinctrl/pinctrl-armada-xp.c

Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt new file +100 -0

new file mode 100644
index 0000000..bfa0a2e
@@ -0,0 +1,100 @@
+* Marvell Armada XP SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
+              "marvell,mv78460-pinctrl"
+
+This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Armada XP (all variants)
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, ge0(txclko), lcd(d0)
+mpp1          1        gpio, ge0(txd0), lcd(d1)
+mpp2          2        gpio, ge0(txd1), lcd(d2)
+mpp3          3        gpio, ge0(txd2), lcd(d3)
+mpp4          4        gpio, ge0(txd3), lcd(d4)
+mpp5          5        gpio, ge0(txctl), lcd(d5)
+mpp6          6        gpio, ge0(rxd0), lcd(d6)
+mpp7          7        gpio, ge0(rxd1), lcd(d7)
+mpp8          8        gpio, ge0(rxd2), lcd(d8)
+mpp9          9        gpio, ge0(rxd3), lcd(d9)
+mpp10         10       gpio, ge0(rxctl), lcd(d10)
+mpp11         11       gpio, ge0(rxclk), lcd(d11)
+mpp12         12       gpio, ge0(txd4), ge1(txd0), lcd(d12)
+mpp13         13       gpio, ge0(txd5), ge1(txd1), lcd(d13)
+mpp14         14       gpio, ge0(txd6), ge1(txd2), lcd(d15)
+mpp15         15       gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp16         16       gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp17         17       gpio, ge0(col), ge1(txctl), lcd(d17)
+mpp18         18       gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
+mpp19         19       gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
+mpp20         20       gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
+mpp21         21       gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
+mpp22         22       gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
+mpp23         23       gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
+mpp24         24       gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
+mpp25         25       gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
+mpp26         26       gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
+mpp27         27       gpio, lcd(e), tdm(dtx), ptp(trig)
+mpp28         28       gpio, lcd(pwm), tdm(drx), ptp(evreq)
+mpp29         29       gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
+mpp30         30       gpio, tdm(int1), sd0(clk)
+mpp31         31       gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
+mpp32         32       gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
+mpp33         33       gpio, tdm(int4), sd0(d1), mem(bat)
+mpp34         34       gpio, tdm(int5), sd0(d2), sata0(prsnt)
+mpp35         35       gpio, tdm(int6), sd0(d3), sata1(prsnt)
+mpp36         36       gpio, spi(mosi)
+mpp37         37       gpio, spi(miso)
+mpp38         38       gpio, spi(sck)
+mpp39         39       gpio, spi(cs0)
+mpp40         40       gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
+                       pcie(clkreq0)
+mpp41         41       gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
+                       pcie(clkreq1)
+mpp42         42       gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
+                       vdd(cpu0-pd)
+mpp43         43       gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
+                       vdd(cpu2-3-pd){1}
+mpp44         44       gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
+                       mem(bat)
+mpp45         45       gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
+mpp46         46       gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
+mpp47         47       gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
+                       ref(clkout)
+mpp48         48       gpio, tclk, dev(burst/last)
+
+* Marvell Armada XP (mv78260 and mv78460 only)
+
+name          pins     functions
+================================================================================
+mpp49         49       gpio, dev(we3)
+mpp50         50       gpio, dev(we2)
+mpp51         51       gpio, dev(ad16)
+mpp52         52       gpio, dev(ad17)
+mpp53         53       gpio, dev(ad18)
+mpp54         54       gpio, dev(ad19)
+mpp55         55       gpio, dev(ad20), vdd(cpu0-pd)
+mpp56         56       gpio, dev(ad21), vdd(cpu1-pd)
+mpp57         57       gpio, dev(ad22), vdd(cpu2-3-pd){1}
+mpp58         58       gpio, dev(ad23)
+mpp59         59       gpio, dev(ad24)
+mpp60         60       gpio, dev(ad25)
+mpp61         61       gpio, dev(ad26)
+mpp62         62       gpio, dev(ad27)
+mpp63         63       gpio, dev(ad28)
+mpp64         64       gpio, dev(ad29)
+mpp65         65       gpio, dev(ad30)
+mpp66         66       gpio, dev(ad31)
+
+Notes:
+* {1} vdd(cpu2-3-pd) only available on mv78460.

drivers/pinctrl/Kconfig +4 -0

index e16b8b0..a754144 100644
@@ -163,6 +163,10 @@ config PINCTRL_ARMADA_370
 	bool
 	select PINCTRL_MVEBU
 
+config PINCTRL_ARMADA_XP
+	bool
+	select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu

drivers/pinctrl/Makefile +1 -0

index e6d6667..f2ea050 100644
@@ -33,5 +33,6 @@ obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o
 obj-$(CONFIG_PINCTRL_DOVE)	+= pinctrl-dove.o
 obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
 obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
+obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
 
 obj-$(CONFIG_PLAT_SPEAR)	+= spear/

drivers/pinctrl/pinctrl-armada-xp.c new file +468 -0

468 lines not on this page · raw message

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-09-13 15:41 UTC #140 lore raw

PATCH v4 6/10 ARM: mvebu: Add pinctrl support to Armada XP SoCs

From: Thomas Petazzoni <[email protected]>

This commits adds the necessary device tree information to define the compatible property for the pinctrl driver instance of Armada XP SoCs.

---
v3:
- put specific variant into DT "model"

v4:
- adjust pinctrl DT node of Armada XP SoC

Cc Sebastian Hesselbarth <[email protected]>

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Jason Cooper <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 arch/arm/boot/dts/armada-xp-mv78230.dtsi |   28 ++++++++++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78260.dtsi |   28 ++++++++++++++++++++++++++++
 arch/arm/boot/dts/armada-xp-mv78460.dtsi |   28 ++++++++++++++++++++++++++++
 3 files changed, 84 insertions(+)
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78230.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78260.dtsi
 create mode 100644 arch/arm/boot/dts/armada-xp-mv78460.dtsi

arch/arm/boot/dts/armada-xp-mv78230.dtsi new file +28 -0

new file mode 100644
index 0000000..38ede3d
@@ -0,0 +1,28 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78230 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP MV78230 SoC";
+	compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	soc {
+		pinctrl {
+			compatible = "marvell,mv78230-pinctrl";
+			reg = <0xd0018000 0x38>;
+		};
+	};
+};

arch/arm/boot/dts/armada-xp-mv78260.dtsi new file +28 -0

new file mode 100644
index 0000000..b2eafcd
@@ -0,0 +1,28 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78260 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP MV78260 SoC";
+	compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	soc {
+		pinctrl {
+			compatible = "marvell,mv78260-pinctrl";
+			reg = <0xd0018000 0x38>;
+		};
+	};
+};

arch/arm/boot/dts/armada-xp-mv78460.dtsi new file +28 -0

new file mode 100644
index 0000000..cf8624d
@@ -0,0 +1,28 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78460 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+	model = "Marvell Armada XP MV78460 SoC";
+	compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
+
+	soc {
+		pinctrl {
+			compatible = "marvell,mv78460-pinctrl";
+			reg = <0xd0018000 0x38>;
+		};
+	};
+ };

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-09-13 15:41 UTC #141 lore raw

PATCH v4 7/10 ARM: mvebu: Add pinctrl support to Armada 370 SoC

From: Thomas Petazzoni <[email protected]>

This commits adds the necessary device tree information to define the compatible property for the pinctrl driver instance of Armada 370 SoC.

---
v3:
- cleaned whitespaces

v4:
- adjust pinctrl DT node of Armada 370 SoC

Cc Sebastian Hesselbarth <[email protected]>

Cc Thomas Petazzoni <[email protected]>

Cc Grant Likely <[email protected]>

Cc Rob Herring <[email protected]>

Cc Rob Landley <[email protected]>

Cc Russell King <[email protected]>

Cc Lior Amsalem <[email protected]>

Cc Andrew Lunn <[email protected]>

Cc Jason Cooper <[email protected]>

Cc Gregory CLEMENT <[email protected]>

Cc Ben Dooks <[email protected]>

Cc Linus Walleij <[email protected]>

Cc Stephen Warren <[email protected]>

Cc devicetree-discuss at lists.ozlabs.org

Cc linux-doc at vger.kernel.org

Cc linux-kernel at vger.kernel.org

Cc linux-arm-kernel at lists.infradead.org

---
 arch/arm/boot/dts/armada-370.dtsi |    5 +++++
 1 file changed, 5 insertions(+)

arch/arm/boot/dts/armada-370.dtsi +5 -0

index 3228ccc..2bfb904 100644
@@ -31,5 +31,10 @@
 				compatible = "marvell,armada-370-xp-system-controller";
 				reg = <0xd0018200 0x100>;
 		};
+
+		pinctrl {
+			compatible = "marvell,mv88f6710-pinctrl";
+			reg = <0xd0018000 0x38>;
+		};
 	};
 };

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-09-13 15:41 UTC #142 lore raw

PATCH v4 8/10 ARM: mvebu: adjust Armada XP evaluation board DTS

From: Thomas Petazzoni <[email protected]>

---
 arch/arm/boot/dts/armada-xp-db.dts |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

arch/arm/boot/dts/armada-xp-db.dts +2 -2

index f97040d..b1fc728 100644
@@ -14,11 +14,11 @@
  */
 
 /dts-v1/;
-/include/ "armada-xp.dtsi"
+/include/ "armada-xp-mv78460.dtsi"
 
 / {
 	model = "Marvell Armada XP Evaluation Board";
-	compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
+	compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-09-13 15:41 UTC #143 lore raw

PATCH v4 9/10 arm: mvebu: split Kconfig options for Armada 370 and XP

From: Thomas Petazzoni <[email protected]>

We keep an hidden option selected by both ARMADA_370 and ARMADA_XP in order to easily compile common code.

A followup patch actually makes use of this split to select the appropriate pinctrl drivers.

Acked-by Gregory Clement <[email protected]>

---
 arch/arm/mach-mvebu/Kconfig |   16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

arch/arm/mach-mvebu/Kconfig +13 -3

index caa2c5e..5540a8b 100644
@@ -3,13 +3,23 @@ if ARCH_MVEBU
 menu "Marvell SOC with device tree"
 
 config MACH_ARMADA_370_XP
-	bool "Marvell Armada 370 and Aramada XP boards"
+	bool
 	select ARMADA_370_XP_TIMER
 	select CPU_V7
+
+config MACH_ARMADA_370
+	bool "Marvell Armada 370 boards"
+	select MACH_ARMADA_370_XP
 	help
+	  Say 'Y' here if you want your kernel to support boards based
+	  on the Marvell Armada 370 SoC with device tree.
 
-	  Say 'Y' here if you want your kernel to support boards based on
-	  Marvell Armada 370 or Armada XP with device tree.
+config MACH_ARMADA_XP
+	bool "Marvell Armada XP boards"
+	select MACH_ARMADA_370_XP
+	help
+	  Say 'Y' here if you want your kernel to support boards based
+	  on the Marvell Armada XP SoC with device tree.
 
 endmenu

Signature · 1 line

1.7.10.4

Sebastian Hesselbarth

author maintainer

2012-09-13 15:41 UTC #144 lore raw

PATCH v4 10/10 arm: mvebu: select the pinctrl drivers for Armada 370 and Armada XP platforms

From: Thomas Petazzoni <[email protected]>

This patch actually enables pinctrl drivers for Armada 370 and XP.

---
 arch/arm/mach-mvebu/Kconfig |    2 ++
 1 file changed, 2 insertions(+)

arch/arm/mach-mvebu/Kconfig +2 -0

index 5540a8b..a601a0b 100644
@@ -10,6 +10,7 @@ config MACH_ARMADA_370_XP
 config MACH_ARMADA_370
 	bool "Marvell Armada 370 boards"
 	select MACH_ARMADA_370_XP
+	select PINCTRL_ARMADA_370
 	help
 	  Say 'Y' here if you want your kernel to support boards based
 	  on the Marvell Armada 370 SoC with device tree.

@@ -17,6 +18,7 @@ config MACH_ARMADA_370
 config MACH_ARMADA_XP
 	bool "Marvell Armada XP boards"
 	select MACH_ARMADA_370_XP
+	select PINCTRL_ARMADA_XP
 	help
 	  Say 'Y' here if you want your kernel to support boards based
 	  on the Marvell Armada XP SoC with device tree.

Signature · 1 line

1.7.10.4

Thomas Petazzoni

Acked-by Tested-by on the v4 series

2012-09-13 15:48 UTC #145 lore raw

Dear Sebastian Hesselbarth,

Quoted 9 lines · Sebastian Hesselbarth

This patch set adds a core pinctrl driver for Marvell MVEBU SoCs and SoC specific stubs for Armada 370, Armada XP, Dove, and Kirkwood. The SoC specific stubs use the pinctrl-mvebu core driver that handles pinctrl API and register accesses for common pinctrl registers.
As especially Dove has some pinctrl registers that do not match the common pinctrl register layout the core driver has been extended by some callbacks to allow uncommon Dove pinctrl registers.

Quoted 6 lines

DT binding documentation is added for all supported SoCs but as Dove and Kirkwood are not yet ready for full DT support, the pinctrl driver is only activated for Armada 370 and XP.
The driver of latest patch v4 has been tested on Dove, Armada 370, Armada XP, and 88f6281 variant of Kirkwood.

I confirm the testing of this v4 of the patch set on Armada 370 and Armada XP, so for the whole series:

Acked-by Thomas Petazzoni <[email protected]>

Tested-by Thomas Petazzoni <[email protected]>

Thanks!

Thomas

Signature · 4 lines

Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Stephen Warren

Reviewed-by on the v4 series

2012-09-14 16:41 UTC #146 lore raw

Quoted 9 lines · Sebastian Hesselbarth

This patch set adds a core pinctrl driver for Marvell MVEBU SoCs and SoC specific stubs for Armada 370, Armada XP, Dove, and Kirkwood. The SoC specific stubs use the pinctrl-mvebu core driver that handles pinctrl API and register accesses for common pinctrl registers.
As especially Dove has some pinctrl registers that do not match the common pinctrl register layout the core driver has been extended by some callbacks to allow uncommon Dove pinctrl registers.

Quoted 6 lines

DT binding documentation is added for all supported SoCs but as Dove and Kirkwood are not yet ready for full DT support, the pinctrl driver is only activated for Armada 370 and XP.
The driver of latest patch v4 has been tested on Dove, Armada 370, Armada XP, and 88f6281 variant of Kirkwood.

The series,

Reviewed-by Stephen Warren <[email protected]>

(Mainly the DT bindings and .dts file edits)

In past versions of this series, we were had discussions about the best way to represent the data tables in the SoC-specific pinctrl drivers. I haven't actually looked at the current state in this patchset, but since this is an internal implementation detail and doesn't affect the DT bindings at all, I figure it's not a big deal right now; if it is ever a problem, it can be fixed without affecting anything outside the driver, so I won't worry about it:-)

Linus Walleij

2012-09-20 08:13 UTC #147 lore raw