Skip to contentSkip to conversation

drivers/gpu/drm/i915/intel_ringbuffer.c:1405:24: error: 'I915_GEM_SCRATCH_INDEX' undeclared

PATCH In review Fengguang Wu 3 participants 3 messages Oct 3, 2012 – Oct 4, 2012 Kernel janitors

lore
Share & tools
lore

Fengguang Wu

author
#0 lore raw

PATCH 15/18 drivers/gpu/drm/i915/intel_ringbuffer.c:1405:24: error: 'I915_GEM_SCRATCH_INDEX' undeclared

Hi Jesse,

FYI, kernel build failed on

tree:   git://people.freedesktop.org/~danvet/drm-intel.git drm-intel-fixes
head:   2cb47a9c6d49f2961dcf57f69ff968e65d48e876
commit: 307daa1b856699f1d4acc3972374017c3e99d331 [15/18] drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op
config: x86_64-allyesconfig

All error/warnings:

drivers/gpu/drm/i915/intel_ringbuffer.c: In function 'gen6_ring_flush':
drivers/gpu/drm/i915/intel_ringbuffer.c:1405:24: error: 'I915_GEM_SCRATCH_INDEX' undeclared (first use in this function) drivers/gpu/drm/i915/intel_ringbuffer.c:1405:24: note: each undeclared identifier is reported only once for each function it appears in drivers/gpu/drm/i915/intel_ringbuffer.c: In function 'blt_ring_flush':
drivers/gpu/drm/i915/intel_ringbuffer.c:1453:24: error: 'I915_GEM_SCRATCH_INDEX' undeclared (first use in this function)

vim +1405 drivers/gpu/drm/i915/intel_ringbuffer.c

307daa1b (Jesse Barnes 2012-10-02  1399) 	 * Post-Sync Operation field is a value of 1h or 3h."
307daa1b (Jesse Barnes 2012-10-02  1400) 	 */
71a77e07 (Chris Wilson 2011-02-02  1401) 	if (invalidate & I915_GEM_GPU_DOMAINS)
307daa1b (Jesse Barnes 2012-10-02  1402) 		cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
307daa1b (Jesse Barnes 2012-10-02  1403) 			MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
71a77e07 (Chris Wilson 2011-02-02  1404) 	intel_ring_emit(ring, cmd);
307daa1b (Jesse Barnes 2012-10-02 @1405) 	intel_ring_emit(ring, I915_GEM_SCRATCH_INDEX << 3);
b72f3acb (Chris Wilson 2011-01-04  1406) 	intel_ring_emit(ring, 0);
71a77e07 (Chris Wilson 2011-02-02  1407) 	intel_ring_emit(ring, MI_NOOP);
b72f3acb (Chris Wilson 2011-01-04  1408) 	intel_ring_advance(ring);

---
0-DAY kernel build testing backend Open Source Technology Centre
Fengguang Wu, Yuanhan Liu Intel Corporation

#1 lore raw
Quoted 8 lines · Fengguang Wu

Hi Jesse,

FYI, kernel build failed on

tree:   git://people.freedesktop.org/~danvet/drm-intel.git drm-intel-fixes
head:   2cb47a9c6d49f2961dcf57f69ff968e65d48e876
commit: 307daa1b856699f1d4acc3972374017c3e99d331 [15/18] drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op
config: x86_64-allyesconfig

Thanks for the report, should be fixed now - somehow I've failed to notice that my .config has gone awry.
-Daniel

Quoted 25 lines

All error/warnings:

drivers/gpu/drm/i915/intel_ringbuffer.c: In function 'gen6_ring_flush':
drivers/gpu/drm/i915/intel_ringbuffer.c:1405:24: error: 'I915_GEM_SCRATCH_INDEX' undeclared (first use in this function) drivers/gpu/drm/i915/intel_ringbuffer.c:1405:24: note: each undeclared identifier is reported only once for each function it appears in drivers/gpu/drm/i915/intel_ringbuffer.c: In function 'blt_ring_flush':
drivers/gpu/drm/i915/intel_ringbuffer.c:1453:24: error: 'I915_GEM_SCRATCH_INDEX' undeclared (first use in this function)

vim +1405 drivers/gpu/drm/i915/intel_ringbuffer.c

307daa1b (Jesse Barnes 2012-10-02  1399) 	 * Post-Sync Operation field is a value of 1h or 3h."
307daa1b (Jesse Barnes 2012-10-02  1400) 	 */
71a77e07 (Chris Wilson 2011-02-02  1401) 	if (invalidate & I915_GEM_GPU_DOMAINS)
307daa1b (Jesse Barnes 2012-10-02  1402) 		cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
307daa1b (Jesse Barnes 2012-10-02  1403) 			MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
71a77e07 (Chris Wilson 2011-02-02  1404) 	intel_ring_emit(ring, cmd);
307daa1b (Jesse Barnes 2012-10-02 @1405) 	intel_ring_emit(ring, I915_GEM_SCRATCH_INDEX << 3);
b72f3acb (Chris Wilson 2011-01-04  1406) 	intel_ring_emit(ring, 0);
71a77e07 (Chris Wilson 2011-02-02  1407) 	intel_ring_emit(ring, MI_NOOP);
b72f3acb (Chris Wilson 2011-01-04  1408) 	intel_ring_advance(ring);

---
0-DAY kernel build testing backend Open Source Technology Centre
Fengguang Wu, Yuanhan Liu Intel Corporation

Signature · 3 lines
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
#2 lore raw
Quoted 5 lines · On Wed, 3 Oct 2012 17:12:18 +0200 Daniel Vetter <[email protected]> wrote:
Quoted 4 lines · Fengguang Wu

Hi Jesse,

FYI, kernel build failed on

Quoted 7 lines
Quoted 4 lines
tree:   git://people.freedesktop.org/~danvet/drm-intel.git drm-intel-fixes
head:   2cb47a9c6d49f2961dcf57f69ff968e65d48e876
commit: 307daa1b856699f1d4acc3972374017c3e99d331 [15/18] drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op
config: x86_64-allyesconfig

Thanks for the report, should be fixed now - somehow I've failed to notice that my .config has gone awry.

No, this is because this patch depends on the earlier patch to add the GEM_SCRATCH_INDEX to i915_drv.h, which wasn't included in this series. Did you pull it in from the earlier series? Or fix it up some other way that caused the breakage you saw?

Jesse